1 /* 2 * Copyright (c) 2014-2020 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #include <linux/mod_devicetable.h> 31 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/ioport.h> 35 #include <linux/list.h> 36 #include <linux/compiler.h> 37 #include <linux/errno.h> 38 #include <linux/kobject.h> 39 #include <linux/atomic.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <bus/pci/pcivar.h> 49 #include <bus/pci/pcireg.h> 50 51 #define PCI_ANY_ID (~0u) 52 53 struct pci_bus; 54 struct device_node; 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 unsigned long driver_data; 64 }; 65 66 typedef unsigned short pci_dev_flags_t; 67 68 #define PCI_DEV_FLAGS_NEEDS_RESUME (1 << 11) 69 70 struct pci_dev { 71 struct pci_bus *bus; /* bus device is nailed to */ 72 struct device dev; 73 74 uint32_t devfn; 75 uint16_t vendor; /* vendor ID */ 76 uint16_t device; /* device ID */ 77 uint16_t subsystem_vendor; 78 uint16_t subsystem_device; 79 80 uint8_t revision; /* revision ID */ 81 82 unsigned int irq; /* handle with care */ 83 void *pci_dev_data; 84 85 unsigned int no_64bit_msi:1; 86 pci_dev_flags_t dev_flags; 87 88 /* DragonFly-specific data */ 89 int _irq_type; 90 struct resource *_irqr; 91 int _irqrid; 92 }; 93 94 struct pci_bus { 95 struct pci_dev *self; /* handle to pdev self */ 96 struct device *dev; /* handle to dev */ 97 98 unsigned char number; /* bus addr number */ 99 }; 100 101 struct pci_driver { 102 const char *name; 103 const struct pci_device_id *id_table; 104 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 105 void (*remove)(struct pci_dev *dev); 106 }; 107 108 #define PCI_DMA_BIDIRECTIONAL 0 109 110 /* extracted from radeon/si.c radeon/cik.c */ 111 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 112 #define PCI_EXP_LNKCTL2 48 113 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 114 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 115 #define PCI_EXP_DEVSTA_TRPND 0x0020 116 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 117 118 static inline int 119 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 120 { 121 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 122 return 0; 123 } 124 125 static inline int 126 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 127 { 128 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 129 return 0; 130 } 131 132 static inline int 133 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 134 { 135 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 136 return 0; 137 } 138 139 static inline int 140 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 141 { 142 pci_write_config(pdev->dev.bsddev, where, val, 1); 143 return 0; 144 } 145 146 static inline int 147 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 148 { 149 pci_write_config(pdev->dev.bsddev, where, val, 2); 150 return 0; 151 } 152 153 static inline int 154 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 155 { 156 pci_write_config(pdev->dev.bsddev, where, val, 4); 157 return 0; 158 } 159 160 /* extracted from drm/radeon/evergreen.c */ 161 static inline int 162 pcie_get_readrq(struct pci_dev *pdev) 163 { 164 u16 ctl; 165 int err, cap; 166 167 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 168 169 cap += PCIER_DEVCTRL; 170 171 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 172 173 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 174 } 175 176 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 177 static inline int 178 pcie_set_readrq(struct pci_dev *pdev, int rq) 179 { 180 u16 ctl; 181 int err, cap; 182 183 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 184 return -EINVAL; 185 186 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 187 if (err) 188 return (-1); 189 190 cap += PCIER_DEVCTRL; 191 192 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 193 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 194 ctl |= ((ffs(rq) - 8) << 12); 195 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 196 return 0; 197 } 198 199 static inline struct pci_dev * 200 pci_dev_get(struct pci_dev *dev) 201 { 202 /* Linux increments a reference count here */ 203 return dev; 204 } 205 206 static inline struct pci_dev * 207 pci_dev_put(struct pci_dev *dev) 208 { 209 /* Linux decrements a reference count here */ 210 return dev; 211 } 212 213 214 static inline int 215 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 216 { 217 return -EIO; 218 } 219 220 static inline int 221 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 222 { 223 return -EIO; 224 } 225 226 typedef int pci_power_t; 227 228 #define PCI_D0 0 229 #define PCI_D1 1 230 #define PCI_D2 2 231 #define PCI_D3hot 3 232 #define PCI_D3cold 4 233 234 #include <asm/pci.h> 235 236 static inline struct resource_list_entry* 237 _pci_get_rle(struct pci_dev *pdev, int bar) 238 { 239 struct pci_devinfo *dinfo; 240 device_t dev = pdev->dev.bsddev; 241 struct resource_list_entry *rle; 242 243 dinfo = device_get_ivars(dev); 244 245 /* Some child devices don't have registered resources, they 246 * are only present in the parent */ 247 if (dinfo == NULL) 248 dev = device_get_parent(dev); 249 dinfo = device_get_ivars(dev); 250 if (dinfo == NULL) 251 return NULL; 252 253 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 254 if (rle == NULL) { 255 rle = resource_list_find(&dinfo->resources, 256 SYS_RES_IOPORT, PCIR_BAR(bar)); 257 } 258 259 return rle; 260 } 261 262 /* 263 * Returns the first address (memory address or I/O port number) 264 * associated with one of the PCI I/O regions.The region is selected by 265 * the integer bar (the base address register), ranging from 0–5 (inclusive). 266 * The return value can be used by ioremap() 267 */ 268 static inline phys_addr_t 269 pci_resource_start(struct pci_dev *pdev, int bar) 270 { 271 struct resource *res; 272 int rid; 273 274 rid = PCIR_BAR(bar); 275 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 276 if (res == NULL) { 277 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 278 return -1; 279 } 280 281 return rman_get_start(res); 282 } 283 284 static inline phys_addr_t 285 pci_resource_len(struct pci_dev *pdev, int bar) 286 { 287 struct resource_list_entry *rle; 288 289 rle = _pci_get_rle(pdev, bar); 290 if (rle == NULL) 291 return -1; 292 293 return rman_get_size(rle->res); 294 } 295 296 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 297 { 298 resource_size_t base, size; 299 300 base = pci_resource_start(dev, bar); 301 size = pci_resource_len(dev, bar); 302 303 if (base == 0) 304 return NULL; 305 306 if (maxlen && size > maxlen) 307 size = maxlen; 308 309 return ioremap(base, size); 310 } 311 312 static inline int 313 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 314 { 315 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 316 317 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 318 return 0; 319 } 320 321 static inline int 322 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 323 { 324 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 325 326 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 327 return 0; 328 } 329 330 static inline const char * 331 pci_name(struct pci_dev *pdev) 332 { 333 return device_get_desc(pdev->dev.bsddev); 334 } 335 336 static inline void * 337 pci_get_drvdata(struct pci_dev *pdev) 338 { 339 return pdev->pci_dev_data; 340 } 341 342 static inline void 343 pci_set_drvdata(struct pci_dev *pdev, void *data) 344 { 345 pdev->pci_dev_data = data; 346 } 347 348 static inline int 349 pci_register_driver(struct pci_driver *drv) 350 { 351 /* pci_register_driver not implemented */ 352 return 0; 353 } 354 355 static inline void 356 pci_unregister_driver(struct pci_driver *dev) 357 { 358 /* pci_unregister_driver not implemented */ 359 } 360 361 static inline void 362 pci_clear_master(struct pci_dev *pdev) 363 { 364 pci_disable_busmaster(pdev->dev.bsddev); 365 } 366 367 static inline void 368 pci_set_master(struct pci_dev *pdev) 369 { 370 pci_enable_busmaster(pdev->dev.bsddev); 371 } 372 373 static inline int 374 pci_pcie_cap(struct pci_dev *pdev) 375 { 376 return pci_get_pciecap_ptr(pdev->dev.bsddev); 377 } 378 379 /* DRM_MAX_PCI_RESOURCE */ 380 #define DEVICE_COUNT_RESOURCE 6 381 382 #include <uapi/linux/pci_regs.h> 383 384 /* From FreeBSD */ 385 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 386 { 387 return true; 388 } 389 390 static inline int 391 pci_find_capability(struct pci_dev *pdev, int capid) 392 { 393 int reg; 394 395 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 396 return (0); 397 return (reg); 398 } 399 400 static inline u16 pcie_flags_reg(struct pci_dev *dev) 401 { 402 int pos; 403 u16 reg16; 404 405 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 406 if (!pos) 407 return 0; 408 409 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 410 411 return reg16; 412 } 413 414 static inline int pci_pcie_type(struct pci_dev *dev) 415 { 416 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 417 } 418 419 420 static inline int pcie_cap_version(struct pci_dev *dev) 421 { 422 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 423 } 424 425 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 426 { 427 int type = pci_pcie_type(dev); 428 429 return pcie_cap_version(dev) > 1 || 430 type == PCI_EXP_TYPE_ROOT_PORT || 431 type == PCI_EXP_TYPE_ENDPOINT || 432 type == PCI_EXP_TYPE_LEG_END; 433 } 434 435 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 436 { 437 int type = pci_pcie_type(dev); 438 439 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 440 (type == PCI_EXP_TYPE_DOWNSTREAM && 441 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 442 } 443 444 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 445 { 446 int type = pci_pcie_type(dev); 447 448 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 449 type == PCI_EXP_TYPE_RC_EC; 450 } 451 452 static inline bool 453 pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 454 { 455 if (!pci_is_pcie(dev->dev.bsddev)) 456 return false; 457 458 switch (pos) { 459 case PCI_EXP_FLAGS_TYPE: 460 return true; 461 case PCI_EXP_DEVCAP: 462 case PCI_EXP_DEVCTL: 463 case PCI_EXP_DEVSTA: 464 return pcie_cap_has_devctl(dev); 465 case PCI_EXP_LNKCAP: 466 case PCI_EXP_LNKCTL: 467 case PCI_EXP_LNKSTA: 468 return pcie_cap_has_lnkctl(dev); 469 case PCI_EXP_SLTCAP: 470 case PCI_EXP_SLTCTL: 471 case PCI_EXP_SLTSTA: 472 return pcie_cap_has_sltctl(dev); 473 case PCI_EXP_RTCTL: 474 case PCI_EXP_RTCAP: 475 case PCI_EXP_RTSTA: 476 return pcie_cap_has_rtctl(dev); 477 case PCI_EXP_DEVCAP2: 478 case PCI_EXP_DEVCTL2: 479 case PCI_EXP_LNKCAP2: 480 case PCI_EXP_LNKCTL2: 481 case PCI_EXP_LNKSTA2: 482 return pcie_cap_version(dev) > 1; 483 default: 484 return false; 485 } 486 } 487 488 static inline void __iomem __must_check * 489 pci_map_rom(struct pci_dev *pdev, size_t *size) 490 { 491 return vga_pci_map_bios(device_get_parent(pdev->dev.bsddev), size); 492 } 493 494 static inline void 495 pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) 496 { 497 vga_pci_unmap_bios(device_get_parent(pdev->dev.bsddev), rom); 498 } 499 500 static inline int 501 pci_resource_flags(struct pci_dev *pdev, int bar) 502 { 503 /* Hardcoded to return only the type */ 504 if ((bar & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) { 505 kprintf("pci_resource_flags: pdev=%p bar=%d type=IO\n", pdev, bar); 506 return IORESOURCE_IO; 507 } else { 508 kprintf("pci_resource_flags: pdev=%p bar=%d type=MEM\n", pdev, bar); 509 return IORESOURCE_MEM; 510 } 511 } 512 513 #include <linux/pci-dma-compat.h> 514 515 #endif /* LINUX_PCI_H */ 516