1 /* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * $FreeBSD: head/sys/dev/drm2/radeon/atombios.h 254885 2013-08-25 19:37:15Z dumbbell $ 23 */ 24 25 26 /****************************************************************************/ 27 /*Portion I: Definitions shared between VBIOS and Driver */ 28 /****************************************************************************/ 29 30 31 #ifndef _ATOMBIOS_H 32 #define _ATOMBIOS_H 33 34 #define ATOM_VERSION_MAJOR 0x00020000 35 #define ATOM_VERSION_MINOR 0x00000002 36 37 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 38 39 /* Endianness should be specified before inclusion, 40 * default to little endian 41 */ 42 #ifndef ATOM_BIG_ENDIAN 43 #error Endian not specified 44 #endif 45 46 #ifdef _H2INC 47 #ifndef ULONG 48 typedef unsigned long ULONG; 49 #endif 50 51 #ifndef UCHAR 52 typedef unsigned char UCHAR; 53 #endif 54 55 #ifndef USHORT 56 typedef unsigned short USHORT; 57 #endif 58 #endif 59 60 #define ATOM_DAC_A 0 61 #define ATOM_DAC_B 1 62 #define ATOM_EXT_DAC 2 63 64 #define ATOM_CRTC1 0 65 #define ATOM_CRTC2 1 66 #define ATOM_CRTC3 2 67 #define ATOM_CRTC4 3 68 #define ATOM_CRTC5 4 69 #define ATOM_CRTC6 5 70 #define ATOM_CRTC_INVALID 0xFF 71 72 #define ATOM_DIGA 0 73 #define ATOM_DIGB 1 74 75 #define ATOM_PPLL1 0 76 #define ATOM_PPLL2 1 77 #define ATOM_DCPLL 2 78 #define ATOM_PPLL0 2 79 #define ATOM_EXT_PLL1 8 80 #define ATOM_EXT_PLL2 9 81 #define ATOM_EXT_CLOCK 10 82 #define ATOM_PPLL_INVALID 0xFF 83 84 #define ENCODER_REFCLK_SRC_P1PLL 0 85 #define ENCODER_REFCLK_SRC_P2PLL 1 86 #define ENCODER_REFCLK_SRC_DCPLL 2 87 #define ENCODER_REFCLK_SRC_EXTCLK 3 88 #define ENCODER_REFCLK_SRC_INVALID 0xFF 89 90 #define ATOM_SCALER1 0 91 #define ATOM_SCALER2 1 92 93 #define ATOM_SCALER_DISABLE 0 94 #define ATOM_SCALER_CENTER 1 95 #define ATOM_SCALER_EXPANSION 2 96 #define ATOM_SCALER_MULTI_EX 3 97 98 #define ATOM_DISABLE 0 99 #define ATOM_ENABLE 1 100 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 101 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 102 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 103 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 104 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 105 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 106 #define ATOM_INIT (ATOM_DISABLE+7) 107 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 108 109 #define ATOM_BLANKING 1 110 #define ATOM_BLANKING_OFF 0 111 112 #define ATOM_CURSOR1 0 113 #define ATOM_CURSOR2 1 114 115 #define ATOM_ICON1 0 116 #define ATOM_ICON2 1 117 118 #define ATOM_CRT1 0 119 #define ATOM_CRT2 1 120 121 #define ATOM_TV_NTSC 1 122 #define ATOM_TV_NTSCJ 2 123 #define ATOM_TV_PAL 3 124 #define ATOM_TV_PALM 4 125 #define ATOM_TV_PALCN 5 126 #define ATOM_TV_PALN 6 127 #define ATOM_TV_PAL60 7 128 #define ATOM_TV_SECAM 8 129 #define ATOM_TV_CV 16 130 131 #define ATOM_DAC1_PS2 1 132 #define ATOM_DAC1_CV 2 133 #define ATOM_DAC1_NTSC 3 134 #define ATOM_DAC1_PAL 4 135 136 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 137 #define ATOM_DAC2_CV ATOM_DAC1_CV 138 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 139 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 140 141 #define ATOM_PM_ON 0 142 #define ATOM_PM_STANDBY 1 143 #define ATOM_PM_SUSPEND 2 144 #define ATOM_PM_OFF 3 145 146 /* Bit0:{=0:single, =1:dual}, 147 Bit1 {=0:666RGB, =1:888RGB}, 148 Bit2:3:{Grey level} 149 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 150 151 #define ATOM_PANEL_MISC_DUAL 0x00000001 152 #define ATOM_PANEL_MISC_888RGB 0x00000002 153 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 154 #define ATOM_PANEL_MISC_FPDI 0x00000010 155 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 156 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 157 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 158 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 159 160 161 #define MEMTYPE_DDR1 "DDR1" 162 #define MEMTYPE_DDR2 "DDR2" 163 #define MEMTYPE_DDR3 "DDR3" 164 #define MEMTYPE_DDR4 "DDR4" 165 166 #define ASIC_BUS_TYPE_PCI "PCI" 167 #define ASIC_BUS_TYPE_AGP "AGP" 168 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 169 170 /* Maximum size of that FireGL flag string */ 171 172 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 173 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 174 175 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 176 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 177 178 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 179 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 180 181 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 182 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 183 184 #pragma pack(1) /* BIOS data must use byte aligment */ 185 186 /* Define offset to location of ROM header. */ 187 188 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 189 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 190 191 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 192 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 193 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 194 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 195 196 /* Common header for all ROM Data tables. 197 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 198 And the pointer actually points to this header. */ 199 200 typedef struct _ATOM_COMMON_TABLE_HEADER 201 { 202 USHORT usStructureSize; 203 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 204 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 205 /*Image can't be updated, while Driver needs to carry the new table! */ 206 }ATOM_COMMON_TABLE_HEADER; 207 208 /****************************************************************************/ 209 // Structure stores the ROM header. 210 /****************************************************************************/ 211 typedef struct _ATOM_ROM_HEADER 212 { 213 ATOM_COMMON_TABLE_HEADER sHeader; 214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 215 atombios should init it as "ATOM", don't change the position */ 216 USHORT usBiosRuntimeSegmentAddress; 217 USHORT usProtectedModeInfoOffset; 218 USHORT usConfigFilenameOffset; 219 USHORT usCRC_BlockOffset; 220 USHORT usBIOS_BootupMessageOffset; 221 USHORT usInt10Offset; 222 USHORT usPciBusDevInitCode; 223 USHORT usIoBaseAddress; 224 USHORT usSubsystemVendorID; 225 USHORT usSubsystemID; 226 USHORT usPCI_InfoOffset; 227 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 228 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 229 UCHAR ucExtendedFunctionCode; 230 UCHAR ucReserved; 231 }ATOM_ROM_HEADER; 232 233 /*==============================Command Table Portion==================================== */ 234 235 #ifdef UEFI_BUILD 236 #define UTEMP USHORT 237 #define USHORT void* 238 #endif 239 240 /****************************************************************************/ 241 // Structures used in Command.mtb 242 /****************************************************************************/ 243 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 244 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 245 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 246 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 247 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 248 USHORT DIGxEncoderControl; //Only used by Bios 249 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 250 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 251 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 252 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 253 USHORT GPIOPinControl; //Atomic Table, only used by Bios 254 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 255 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 256 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 257 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 258 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 259 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 260 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 262 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 263 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 264 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios 265 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 266 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 267 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 269 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 272 USHORT GetConditionalGoldenSetting; //Only used by Bios 273 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 274 USHORT PatchMCSetting; //only used by BIOS 275 USHORT MC_SEQ_Control; //only used by BIOS 276 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 277 USHORT EnableScaler; //Atomic Table, used only by Bios 278 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 279 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 280 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 281 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 282 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 283 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 285 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 286 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 287 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 288 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 289 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 290 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 291 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 292 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 294 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 295 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 296 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 297 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 298 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 299 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 300 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 301 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 302 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 304 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 305 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 306 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 307 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 308 USHORT MemoryTraining; //Atomic Table, used only by Bios 309 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 310 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 312 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 314 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 315 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 316 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 317 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 318 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 319 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 320 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 321 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 322 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 323 USHORT DPEncoderService; //Function Table,only used by Bios 324 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 325 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 326 327 // For backward compatible 328 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 329 #define DPTranslatorControl DIG2EncoderControl 330 #define UNIPHYTransmitterControl DIG1TransmitterControl 331 #define LVTMATransmitterControl DIG2TransmitterControl 332 #define SetCRTC_DPM_State GetConditionalGoldenSetting 333 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 334 #define HPDInterruptService ReadHWAssistedI2CStatus 335 #define EnableVGA_Access GetSCLKOverMCLKRatio 336 #define EnableYUV GetDispObjectInfo 337 #define DynamicClockGating EnableDispPowerGating 338 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 339 340 #define TMDSAEncoderControl PatchMCSetting 341 #define LVDSEncoderControl MC_SEQ_Control 342 #define LCD1OutputControl HW_Misc_Operation 343 344 345 typedef struct _ATOM_MASTER_COMMAND_TABLE 346 { 347 ATOM_COMMON_TABLE_HEADER sHeader; 348 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 349 }ATOM_MASTER_COMMAND_TABLE; 350 351 /****************************************************************************/ 352 // Structures used in every command table 353 /****************************************************************************/ 354 typedef struct _ATOM_TABLE_ATTRIBUTE 355 { 356 #if ATOM_BIG_ENDIAN 357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 358 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360 #else 361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 362 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 363 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 364 #endif 365 }ATOM_TABLE_ATTRIBUTE; 366 367 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 368 { 369 ATOM_TABLE_ATTRIBUTE sbfAccess; 370 USHORT susAccess; 371 }ATOM_TABLE_ATTRIBUTE_ACCESS; 372 373 /****************************************************************************/ 374 // Common header for all command tables. 375 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 376 // And the pointer actually points to this header. 377 /****************************************************************************/ 378 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 379 { 380 ATOM_COMMON_TABLE_HEADER CommonHeader; 381 ATOM_TABLE_ATTRIBUTE TableAttribute; 382 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 383 384 /****************************************************************************/ 385 // Structures used by ComputeMemoryEnginePLLTable 386 /****************************************************************************/ 387 #define COMPUTE_MEMORY_PLL_PARAM 1 388 #define COMPUTE_ENGINE_PLL_PARAM 2 389 #define ADJUST_MC_SETTING_PARAM 3 390 391 /****************************************************************************/ 392 // Structures used by AdjustMemoryControllerTable 393 /****************************************************************************/ 394 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 395 { 396 #if ATOM_BIG_ENDIAN 397 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 399 ULONG ulClockFreq:24; 400 #else 401 ULONG ulClockFreq:24; 402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 403 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 404 #endif 405 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 406 #define POINTER_RETURN_FLAG 0x80 407 408 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 409 { 410 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 412 UCHAR ucReserved; //may expand to return larger Fbdiv later 413 UCHAR ucFbDiv; //return value 414 UCHAR ucPostDiv; //return value 415 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 416 417 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 418 { 419 ULONG ulClock; //When return, [23:0] return real clock 420 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 421 USHORT usFbDiv; //return Feedback value to be written to register 422 UCHAR ucPostDiv; //return post div to be written to register 423 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 424 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 425 426 427 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 428 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 429 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 430 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 431 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 432 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 433 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 434 435 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 436 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 437 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 438 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 439 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 440 441 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 442 { 443 #if ATOM_BIG_ENDIAN 444 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 445 ULONG ulClockFreq:24; // in unit of 10kHz 446 #else 447 ULONG ulClockFreq:24; // in unit of 10kHz 448 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 449 #endif 450 }ATOM_COMPUTE_CLOCK_FREQ; 451 452 typedef struct _ATOM_S_MPLL_FB_DIVIDER 453 { 454 USHORT usFbDivFrac; 455 USHORT usFbDiv; 456 }ATOM_S_MPLL_FB_DIVIDER; 457 458 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 459 { 460 union 461 { 462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 463 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 464 }; 465 UCHAR ucRefDiv; //Output Parameter 466 UCHAR ucPostDiv; //Output Parameter 467 UCHAR ucCntlFlag; //Output Parameter 468 UCHAR ucReserved; 469 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 470 471 // ucCntlFlag 472 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 473 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 474 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 475 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 476 477 478 // V4 are only used for APU which PLL outside GPU 479 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 480 { 481 #if ATOM_BIG_ENDIAN 482 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 483 ULONG ulClock:24; //Input= target clock, output = actual clock 484 #else 485 ULONG ulClock:24; //Input= target clock, output = actual clock 486 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 487 #endif 488 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 489 490 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 491 { 492 union 493 { 494 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 495 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 496 }; 497 UCHAR ucRefDiv; //Output Parameter 498 UCHAR ucPostDiv; //Output Parameter 499 union 500 { 501 UCHAR ucCntlFlag; //Output Flags 502 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 503 }; 504 UCHAR ucReserved; 505 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 506 507 // ucInputFlag 508 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 509 510 // use for ComputeMemoryClockParamTable 511 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 512 { 513 union 514 { 515 ULONG ulClock; 516 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 517 }; 518 UCHAR ucDllSpeed; //Output 519 UCHAR ucPostDiv; //Output 520 union{ 521 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 522 UCHAR ucPllCntlFlag; //Output: 523 }; 524 UCHAR ucBWCntl; 525 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 526 527 // definition of ucInputFlag 528 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 529 // definition of ucPllCntlFlag 530 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 531 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 532 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 533 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 534 535 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 536 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 537 538 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 539 { 540 ATOM_COMPUTE_CLOCK_FREQ ulClock; 541 ULONG ulReserved[2]; 542 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 543 544 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 545 { 546 ATOM_COMPUTE_CLOCK_FREQ ulClock; 547 ULONG ulMemoryClock; 548 ULONG ulReserved; 549 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 550 551 /****************************************************************************/ 552 // Structures used by SetEngineClockTable 553 /****************************************************************************/ 554 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 555 { 556 ULONG ulTargetEngineClock; //In 10Khz unit 557 }SET_ENGINE_CLOCK_PARAMETERS; 558 559 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 560 { 561 ULONG ulTargetEngineClock; //In 10Khz unit 562 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 563 }SET_ENGINE_CLOCK_PS_ALLOCATION; 564 565 /****************************************************************************/ 566 // Structures used by SetMemoryClockTable 567 /****************************************************************************/ 568 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 569 { 570 ULONG ulTargetMemoryClock; //In 10Khz unit 571 }SET_MEMORY_CLOCK_PARAMETERS; 572 573 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 574 { 575 ULONG ulTargetMemoryClock; //In 10Khz unit 576 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 577 }SET_MEMORY_CLOCK_PS_ALLOCATION; 578 579 /****************************************************************************/ 580 // Structures used by ASIC_Init.ctb 581 /****************************************************************************/ 582 typedef struct _ASIC_INIT_PARAMETERS 583 { 584 ULONG ulDefaultEngineClock; //In 10Khz unit 585 ULONG ulDefaultMemoryClock; //In 10Khz unit 586 }ASIC_INIT_PARAMETERS; 587 588 typedef struct _ASIC_INIT_PS_ALLOCATION 589 { 590 ASIC_INIT_PARAMETERS sASICInitClocks; 591 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 592 }ASIC_INIT_PS_ALLOCATION; 593 594 /****************************************************************************/ 595 // Structure used by DynamicClockGatingTable.ctb 596 /****************************************************************************/ 597 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 598 { 599 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 600 UCHAR ucPadding[3]; 601 }DYNAMIC_CLOCK_GATING_PARAMETERS; 602 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 603 604 /****************************************************************************/ 605 // Structure used by EnableDispPowerGatingTable.ctb 606 /****************************************************************************/ 607 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 608 { 609 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 610 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 611 UCHAR ucPadding[2]; 612 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 613 614 /****************************************************************************/ 615 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 616 /****************************************************************************/ 617 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 618 { 619 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 620 UCHAR ucPadding[3]; 621 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 622 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 623 624 /****************************************************************************/ 625 // Structures used by DAC_LoadDetectionTable.ctb 626 /****************************************************************************/ 627 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 628 { 629 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 630 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 631 UCHAR ucMisc; //Valid only when table revision =1.3 and above 632 }DAC_LOAD_DETECTION_PARAMETERS; 633 634 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 635 #define DAC_LOAD_MISC_YPrPb 0x01 636 637 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 638 { 639 DAC_LOAD_DETECTION_PARAMETERS sDacload; 640 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 641 }DAC_LOAD_DETECTION_PS_ALLOCATION; 642 643 /****************************************************************************/ 644 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 645 /****************************************************************************/ 646 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 647 { 648 USHORT usPixelClock; // in 10KHz; for bios convenient 649 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 650 UCHAR ucAction; // 0: turn off encoder 651 // 1: setup and turn on encoder 652 // 7: ATOM_ENCODER_INIT Initialize DAC 653 }DAC_ENCODER_CONTROL_PARAMETERS; 654 655 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 656 657 /****************************************************************************/ 658 // Structures used by DIG1EncoderControlTable 659 // DIG2EncoderControlTable 660 // ExternalEncoderControlTable 661 /****************************************************************************/ 662 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 663 { 664 USHORT usPixelClock; // in 10KHz; for bios convenient 665 UCHAR ucConfig; 666 // [2] Link Select: 667 // =0: PHY linkA if bfLane<3 668 // =1: PHY linkB if bfLanes<3 669 // =0: PHY linkA+B if bfLanes=3 670 // [3] Transmitter Sel 671 // =0: UNIPHY or PCIEPHY 672 // =1: LVTMA 673 UCHAR ucAction; // =0: turn off encoder 674 // =1: turn on encoder 675 UCHAR ucEncoderMode; 676 // =0: DP encoder 677 // =1: LVDS encoder 678 // =2: DVI encoder 679 // =3: HDMI encoder 680 // =4: SDVO encoder 681 UCHAR ucLaneNum; // how many lanes to enable 682 UCHAR ucReserved[2]; 683 }DIG_ENCODER_CONTROL_PARAMETERS; 684 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 685 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 686 687 //ucConfig 688 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 689 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 690 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 691 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 692 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 693 #define ATOM_ENCODER_CONFIG_LINKA 0x00 694 #define ATOM_ENCODER_CONFIG_LINKB 0x04 695 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 696 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 697 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 698 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 699 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 700 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 701 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 702 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 703 // ucAction 704 // ATOM_ENABLE: Enable Encoder 705 // ATOM_DISABLE: Disable Encoder 706 707 //ucEncoderMode 708 #define ATOM_ENCODER_MODE_DP 0 709 #define ATOM_ENCODER_MODE_LVDS 1 710 #define ATOM_ENCODER_MODE_DVI 2 711 #define ATOM_ENCODER_MODE_HDMI 3 712 #define ATOM_ENCODER_MODE_SDVO 4 713 #define ATOM_ENCODER_MODE_DP_AUDIO 5 714 #define ATOM_ENCODER_MODE_TV 13 715 #define ATOM_ENCODER_MODE_CV 14 716 #define ATOM_ENCODER_MODE_CRT 15 717 #define ATOM_ENCODER_MODE_DVO 16 718 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 719 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 720 721 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 722 { 723 #if ATOM_BIG_ENDIAN 724 UCHAR ucReserved1:2; 725 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 726 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 727 UCHAR ucReserved:1; 728 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 729 #else 730 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 731 UCHAR ucReserved:1; 732 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 733 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 734 UCHAR ucReserved1:2; 735 #endif 736 }ATOM_DIG_ENCODER_CONFIG_V2; 737 738 739 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 740 { 741 USHORT usPixelClock; // in 10KHz; for bios convenient 742 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 743 UCHAR ucAction; 744 UCHAR ucEncoderMode; 745 // =0: DP encoder 746 // =1: LVDS encoder 747 // =2: DVI encoder 748 // =3: HDMI encoder 749 // =4: SDVO encoder 750 UCHAR ucLaneNum; // how many lanes to enable 751 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 752 UCHAR ucReserved; 753 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 754 755 //ucConfig 756 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 757 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 758 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 759 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 760 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 761 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 762 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 763 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 764 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 765 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 766 767 // ucAction: 768 // ATOM_DISABLE 769 // ATOM_ENABLE 770 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 771 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 773 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 774 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 775 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 776 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 777 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 778 #define ATOM_ENCODER_CMD_SETUP 0x0f 779 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 780 781 // ucStatus 782 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 783 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 784 785 //ucTableFormatRevision=1 786 //ucTableContentRevision=3 787 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 788 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 789 { 790 #if ATOM_BIG_ENDIAN 791 UCHAR ucReserved1:1; 792 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 793 UCHAR ucReserved:3; 794 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 795 #else 796 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 797 UCHAR ucReserved:3; 798 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 799 UCHAR ucReserved1:1; 800 #endif 801 }ATOM_DIG_ENCODER_CONFIG_V3; 802 803 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 804 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 805 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 806 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 807 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 808 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 809 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 810 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 811 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 812 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 813 814 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 815 { 816 USHORT usPixelClock; // in 10KHz; for bios convenient 817 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 818 UCHAR ucAction; 819 union { 820 UCHAR ucEncoderMode; 821 // =0: DP encoder 822 // =1: LVDS encoder 823 // =2: DVI encoder 824 // =3: HDMI encoder 825 // =4: SDVO encoder 826 // =5: DP audio 827 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 828 // =0: external DP 829 // =1: internal DP2 830 // =0x11: internal DP1 for NutMeg/Travis DP translator 831 }; 832 UCHAR ucLaneNum; // how many lanes to enable 833 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 834 UCHAR ucReserved; 835 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 836 837 //ucTableFormatRevision=1 838 //ucTableContentRevision=4 839 // start from NI 840 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 841 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 842 { 843 #if ATOM_BIG_ENDIAN 844 UCHAR ucReserved1:1; 845 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 846 UCHAR ucReserved:2; 847 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 848 #else 849 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 850 UCHAR ucReserved:2; 851 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 852 UCHAR ucReserved1:1; 853 #endif 854 }ATOM_DIG_ENCODER_CONFIG_V4; 855 856 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 857 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 859 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 860 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 861 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 862 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 863 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 864 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 865 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 866 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 867 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 868 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 869 870 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 871 { 872 USHORT usPixelClock; // in 10KHz; for bios convenient 873 union{ 874 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 875 UCHAR ucConfig; 876 }; 877 UCHAR ucAction; 878 union { 879 UCHAR ucEncoderMode; 880 // =0: DP encoder 881 // =1: LVDS encoder 882 // =2: DVI encoder 883 // =3: HDMI encoder 884 // =4: SDVO encoder 885 // =5: DP audio 886 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 887 // =0: external DP 888 // =1: internal DP2 889 // =0x11: internal DP1 for NutMeg/Travis DP translator 890 }; 891 UCHAR ucLaneNum; // how many lanes to enable 892 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 893 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 894 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 895 896 // define ucBitPerColor: 897 #define PANEL_BPC_UNDEFINE 0x00 898 #define PANEL_6BIT_PER_COLOR 0x01 899 #define PANEL_8BIT_PER_COLOR 0x02 900 #define PANEL_10BIT_PER_COLOR 0x03 901 #define PANEL_12BIT_PER_COLOR 0x04 902 #define PANEL_16BIT_PER_COLOR 0x05 903 904 //define ucPanelMode 905 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 906 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 907 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 908 909 /****************************************************************************/ 910 // Structures used by UNIPHYTransmitterControlTable 911 // LVTMATransmitterControlTable 912 // DVOOutputControlTable 913 /****************************************************************************/ 914 typedef struct _ATOM_DP_VS_MODE 915 { 916 UCHAR ucLaneSel; 917 UCHAR ucLaneSet; 918 }ATOM_DP_VS_MODE; 919 920 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 921 { 922 union 923 { 924 USHORT usPixelClock; // in 10KHz; for bios convenient 925 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 926 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 927 }; 928 UCHAR ucConfig; 929 // [0]=0: 4 lane Link, 930 // =1: 8 lane Link ( Dual Links TMDS ) 931 // [1]=0: InCoherent mode 932 // =1: Coherent Mode 933 // [2] Link Select: 934 // =0: PHY linkA if bfLane<3 935 // =1: PHY linkB if bfLanes<3 936 // =0: PHY linkA+B if bfLanes=3 937 // [5:4]PCIE lane Sel 938 // =0: lane 0~3 or 0~7 939 // =1: lane 4~7 940 // =2: lane 8~11 or 8~15 941 // =3: lane 12~15 942 UCHAR ucAction; // =0: turn off encoder 943 // =1: turn on encoder 944 UCHAR ucReserved[4]; 945 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 946 947 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 948 949 //ucInitInfo 950 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 951 952 //ucConfig 953 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 954 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 955 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 956 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 957 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 958 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 959 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 960 961 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 962 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 963 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 964 965 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 966 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 967 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 968 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 969 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 970 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 971 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 972 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 973 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 974 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 975 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 976 977 //ucAction 978 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 979 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 980 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 981 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 982 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 983 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 984 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 985 #define ATOM_TRANSMITTER_ACTION_INIT 7 986 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 987 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 988 #define ATOM_TRANSMITTER_ACTION_SETUP 10 989 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 990 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 991 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 992 993 // Following are used for DigTransmitterControlTable ver1.2 994 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 995 { 996 #if ATOM_BIG_ENDIAN 997 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 998 // =1 Dig Transmitter 2 ( Uniphy CD ) 999 // =2 Dig Transmitter 3 ( Uniphy EF ) 1000 UCHAR ucReserved:1; 1001 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1002 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1003 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1004 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1005 1006 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1007 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1008 #else 1009 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1010 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1011 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1012 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1013 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1014 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1015 UCHAR ucReserved:1; 1016 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1017 // =1 Dig Transmitter 2 ( Uniphy CD ) 1018 // =2 Dig Transmitter 3 ( Uniphy EF ) 1019 #endif 1020 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1021 1022 //ucConfig 1023 //Bit0 1024 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1025 1026 //Bit1 1027 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1028 1029 //Bit2 1030 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1031 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1032 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1033 1034 // Bit3 1035 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1036 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1037 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1038 1039 // Bit4 1040 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1041 1042 // Bit7:6 1043 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1044 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1045 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1046 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1047 1048 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1049 { 1050 union 1051 { 1052 USHORT usPixelClock; // in 10KHz; for bios convenient 1053 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1054 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1055 }; 1056 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1057 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1058 UCHAR ucReserved[4]; 1059 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1060 1061 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1062 { 1063 #if ATOM_BIG_ENDIAN 1064 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1065 // =1 Dig Transmitter 2 ( Uniphy CD ) 1066 // =2 Dig Transmitter 3 ( Uniphy EF ) 1067 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1068 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1069 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1070 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1071 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1072 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1073 #else 1074 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1075 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1076 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1077 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1078 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1079 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1080 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1081 // =1 Dig Transmitter 2 ( Uniphy CD ) 1082 // =2 Dig Transmitter 3 ( Uniphy EF ) 1083 #endif 1084 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1085 1086 1087 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1088 { 1089 union 1090 { 1091 USHORT usPixelClock; // in 10KHz; for bios convenient 1092 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1093 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1094 }; 1095 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1096 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1097 UCHAR ucLaneNum; 1098 UCHAR ucReserved[3]; 1099 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1100 1101 //ucConfig 1102 //Bit0 1103 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1104 1105 //Bit1 1106 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1107 1108 //Bit2 1109 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1110 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1111 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1112 1113 // Bit3 1114 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1115 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1116 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1117 1118 // Bit5:4 1119 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1120 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1121 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1122 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1123 1124 // Bit7:6 1125 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1126 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1127 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1128 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1129 1130 1131 /****************************************************************************/ 1132 // Structures used by UNIPHYTransmitterControlTable V1.4 1133 // ASIC Families: NI 1134 // ucTableFormatRevision=1 1135 // ucTableContentRevision=4 1136 /****************************************************************************/ 1137 typedef struct _ATOM_DP_VS_MODE_V4 1138 { 1139 UCHAR ucLaneSel; 1140 union 1141 { 1142 UCHAR ucLaneSet; 1143 struct { 1144 #if ATOM_BIG_ENDIAN 1145 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1146 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1147 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1148 #else 1149 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1150 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1151 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1152 #endif 1153 }; 1154 }; 1155 }ATOM_DP_VS_MODE_V4; 1156 1157 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1158 { 1159 #if ATOM_BIG_ENDIAN 1160 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1161 // =1 Dig Transmitter 2 ( Uniphy CD ) 1162 // =2 Dig Transmitter 3 ( Uniphy EF ) 1163 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1164 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1165 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1166 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1167 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1168 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1169 #else 1170 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1171 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1172 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1173 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1174 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1175 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1176 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1177 // =1 Dig Transmitter 2 ( Uniphy CD ) 1178 // =2 Dig Transmitter 3 ( Uniphy EF ) 1179 #endif 1180 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1181 1182 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1183 { 1184 union 1185 { 1186 USHORT usPixelClock; // in 10KHz; for bios convenient 1187 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1188 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1189 }; 1190 union 1191 { 1192 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1193 UCHAR ucConfig; 1194 }; 1195 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1196 UCHAR ucLaneNum; 1197 UCHAR ucReserved[3]; 1198 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1199 1200 //ucConfig 1201 //Bit0 1202 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1203 //Bit1 1204 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1205 //Bit2 1206 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1207 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1208 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1209 // Bit3 1210 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1211 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1212 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1213 // Bit5:4 1214 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1215 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1216 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1217 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1218 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1219 // Bit7:6 1220 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1221 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1222 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1223 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1224 1225 1226 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1227 { 1228 #if ATOM_BIG_ENDIAN 1229 UCHAR ucReservd1:1; 1230 UCHAR ucHPDSel:3; 1231 UCHAR ucPhyClkSrcId:2; 1232 UCHAR ucCoherentMode:1; 1233 UCHAR ucReserved:1; 1234 #else 1235 UCHAR ucReserved:1; 1236 UCHAR ucCoherentMode:1; 1237 UCHAR ucPhyClkSrcId:2; 1238 UCHAR ucHPDSel:3; 1239 UCHAR ucReservd1:1; 1240 #endif 1241 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1242 1243 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1244 { 1245 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1246 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1247 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1248 UCHAR ucLaneNum; // indicate lane number 1-8 1249 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1250 UCHAR ucDigMode; // indicate DIG mode 1251 union{ 1252 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1253 UCHAR ucConfig; 1254 }; 1255 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1256 UCHAR ucDPLaneSet; 1257 UCHAR ucReserved; 1258 UCHAR ucReserved1; 1259 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1260 1261 //ucPhyId 1262 #define ATOM_PHY_ID_UNIPHYA 0 1263 #define ATOM_PHY_ID_UNIPHYB 1 1264 #define ATOM_PHY_ID_UNIPHYC 2 1265 #define ATOM_PHY_ID_UNIPHYD 3 1266 #define ATOM_PHY_ID_UNIPHYE 4 1267 #define ATOM_PHY_ID_UNIPHYF 5 1268 #define ATOM_PHY_ID_UNIPHYG 6 1269 1270 // ucDigEncoderSel 1271 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1272 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1273 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1274 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1275 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1276 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1277 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1278 1279 // ucDigMode 1280 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1281 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1282 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1283 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1284 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1285 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1286 1287 // ucDPLaneSet 1288 #define DP_LANE_SET__0DB_0_4V 0x00 1289 #define DP_LANE_SET__0DB_0_6V 0x01 1290 #define DP_LANE_SET__0DB_0_8V 0x02 1291 #define DP_LANE_SET__0DB_1_2V 0x03 1292 #define DP_LANE_SET__3_5DB_0_4V 0x08 1293 #define DP_LANE_SET__3_5DB_0_6V 0x09 1294 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1295 #define DP_LANE_SET__6DB_0_4V 0x10 1296 #define DP_LANE_SET__6DB_0_6V 0x11 1297 #define DP_LANE_SET__9_5DB_0_4V 0x18 1298 1299 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1300 // Bit1 1301 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1302 1303 // Bit3:2 1304 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1305 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1306 1307 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1308 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1309 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1310 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1311 // Bit6:4 1312 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1313 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1314 1315 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1316 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1317 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1320 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1321 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1322 1323 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1324 1325 1326 /****************************************************************************/ 1327 // Structures used by ExternalEncoderControlTable V1.3 1328 // ASIC Families: Evergreen, Llano, NI 1329 // ucTableFormatRevision=1 1330 // ucTableContentRevision=3 1331 /****************************************************************************/ 1332 1333 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1334 { 1335 union{ 1336 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1337 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1338 }; 1339 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1340 UCHAR ucAction; // 1341 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1342 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1343 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1344 UCHAR ucReserved; 1345 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1346 1347 // ucAction 1348 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1349 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1350 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1351 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1352 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1353 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1354 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1355 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1356 1357 // ucConfig 1358 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1359 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1360 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1361 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1362 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1363 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1364 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1365 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1366 1367 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1368 { 1369 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1370 ULONG ulReserved[2]; 1371 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1372 1373 1374 /****************************************************************************/ 1375 // Structures used by DAC1OuputControlTable 1376 // DAC2OuputControlTable 1377 // LVTMAOutputControlTable (Before DEC30) 1378 // TMDSAOutputControlTable (Before DEC30) 1379 /****************************************************************************/ 1380 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1381 { 1382 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1383 // When the display is LCD, in addition to above: 1384 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1385 // ATOM_LCD_SELFTEST_STOP 1386 1387 UCHAR aucPadding[3]; // padding to DWORD aligned 1388 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1389 1390 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1391 1392 1393 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1394 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1395 1396 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1397 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1398 1399 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1400 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1401 1402 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1403 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1404 1405 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1406 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1407 1408 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1409 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1410 1411 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1412 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1413 1414 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1415 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1416 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1417 1418 /****************************************************************************/ 1419 // Structures used by BlankCRTCTable 1420 /****************************************************************************/ 1421 typedef struct _BLANK_CRTC_PARAMETERS 1422 { 1423 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1424 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1425 USHORT usBlackColorRCr; 1426 USHORT usBlackColorGY; 1427 USHORT usBlackColorBCb; 1428 }BLANK_CRTC_PARAMETERS; 1429 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1430 1431 /****************************************************************************/ 1432 // Structures used by EnableCRTCTable 1433 // EnableCRTCMemReqTable 1434 // UpdateCRTC_DoubleBufferRegistersTable 1435 /****************************************************************************/ 1436 typedef struct _ENABLE_CRTC_PARAMETERS 1437 { 1438 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1439 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1440 UCHAR ucPadding[2]; 1441 }ENABLE_CRTC_PARAMETERS; 1442 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1443 1444 /****************************************************************************/ 1445 // Structures used by SetCRTC_OverScanTable 1446 /****************************************************************************/ 1447 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1448 { 1449 USHORT usOverscanRight; // right 1450 USHORT usOverscanLeft; // left 1451 USHORT usOverscanBottom; // bottom 1452 USHORT usOverscanTop; // top 1453 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1454 UCHAR ucPadding[3]; 1455 }SET_CRTC_OVERSCAN_PARAMETERS; 1456 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1457 1458 /****************************************************************************/ 1459 // Structures used by SetCRTC_ReplicationTable 1460 /****************************************************************************/ 1461 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1462 { 1463 UCHAR ucH_Replication; // horizontal replication 1464 UCHAR ucV_Replication; // vertical replication 1465 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1466 UCHAR ucPadding; 1467 }SET_CRTC_REPLICATION_PARAMETERS; 1468 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1469 1470 /****************************************************************************/ 1471 // Structures used by SelectCRTC_SourceTable 1472 /****************************************************************************/ 1473 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1474 { 1475 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1476 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1477 UCHAR ucPadding[2]; 1478 }SELECT_CRTC_SOURCE_PARAMETERS; 1479 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1480 1481 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1482 { 1483 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1484 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1485 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1486 UCHAR ucPadding; 1487 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1488 1489 //ucEncoderID 1490 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1491 //#define ASIC_INT_TV_ENCODER_ID 0x02 1492 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1493 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1494 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1495 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1496 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1497 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1498 1499 //ucEncodeMode 1500 //#define ATOM_ENCODER_MODE_DP 0 1501 //#define ATOM_ENCODER_MODE_LVDS 1 1502 //#define ATOM_ENCODER_MODE_DVI 2 1503 //#define ATOM_ENCODER_MODE_HDMI 3 1504 //#define ATOM_ENCODER_MODE_SDVO 4 1505 //#define ATOM_ENCODER_MODE_TV 13 1506 //#define ATOM_ENCODER_MODE_CV 14 1507 //#define ATOM_ENCODER_MODE_CRT 15 1508 1509 /****************************************************************************/ 1510 // Structures used by SetPixelClockTable 1511 // GetPixelClockTable 1512 /****************************************************************************/ 1513 //Major revision=1., Minor revision=1 1514 typedef struct _PIXEL_CLOCK_PARAMETERS 1515 { 1516 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1517 // 0 means disable PPLL 1518 USHORT usRefDiv; // Reference divider 1519 USHORT usFbDiv; // feedback divider 1520 UCHAR ucPostDiv; // post divider 1521 UCHAR ucFracFbDiv; // fractional feedback divider 1522 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1523 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1524 UCHAR ucCRTC; // Which CRTC uses this Ppll 1525 UCHAR ucPadding; 1526 }PIXEL_CLOCK_PARAMETERS; 1527 1528 //Major revision=1., Minor revision=2, add ucMiscIfno 1529 //ucMiscInfo: 1530 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1531 #define MISC_DEVICE_INDEX_MASK 0xF0 1532 #define MISC_DEVICE_INDEX_SHIFT 4 1533 1534 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1535 { 1536 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1537 // 0 means disable PPLL 1538 USHORT usRefDiv; // Reference divider 1539 USHORT usFbDiv; // feedback divider 1540 UCHAR ucPostDiv; // post divider 1541 UCHAR ucFracFbDiv; // fractional feedback divider 1542 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1543 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1544 UCHAR ucCRTC; // Which CRTC uses this Ppll 1545 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1546 }PIXEL_CLOCK_PARAMETERS_V2; 1547 1548 //Major revision=1., Minor revision=3, structure/definition change 1549 //ucEncoderMode: 1550 //ATOM_ENCODER_MODE_DP 1551 //ATOM_ENOCDER_MODE_LVDS 1552 //ATOM_ENOCDER_MODE_DVI 1553 //ATOM_ENOCDER_MODE_HDMI 1554 //ATOM_ENOCDER_MODE_SDVO 1555 //ATOM_ENCODER_MODE_TV 13 1556 //ATOM_ENCODER_MODE_CV 14 1557 //ATOM_ENCODER_MODE_CRT 15 1558 1559 //ucDVOConfig 1560 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1561 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1562 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1563 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1564 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1565 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1566 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1567 1568 //ucMiscInfo: also changed, see below 1569 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1570 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1571 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1572 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1573 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1574 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1575 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1576 // V1.4 for RoadRunner 1577 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1578 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1579 1580 1581 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1582 { 1583 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1584 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1585 USHORT usRefDiv; // Reference divider 1586 USHORT usFbDiv; // feedback divider 1587 UCHAR ucPostDiv; // post divider 1588 UCHAR ucFracFbDiv; // fractional feedback divider 1589 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1590 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1591 union 1592 { 1593 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1594 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1595 }; 1596 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1597 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1598 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1599 }PIXEL_CLOCK_PARAMETERS_V3; 1600 1601 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1602 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1603 1604 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1605 { 1606 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1607 // drive the pixel clock. not used for DCPLL case. 1608 union{ 1609 UCHAR ucReserved; 1610 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1611 }; 1612 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1613 // 0 means disable PPLL/DCPLL. 1614 USHORT usFbDiv; // feedback divider integer part. 1615 UCHAR ucPostDiv; // post divider. 1616 UCHAR ucRefDiv; // Reference divider 1617 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1618 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1619 // indicate which graphic encoder will be used. 1620 UCHAR ucEncoderMode; // Encoder mode: 1621 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1622 // bit[1]= when VGA timing is used. 1623 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1624 // bit[4]= RefClock source for PPLL. 1625 // =0: XTLAIN( default mode ) 1626 // =1: other external clock source, which is pre-defined 1627 // by VBIOS depend on the feature required. 1628 // bit[7:5]: reserved. 1629 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1630 1631 }PIXEL_CLOCK_PARAMETERS_V5; 1632 1633 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1634 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1635 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1636 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1637 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1638 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1639 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1640 1641 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1642 { 1643 #if ATOM_BIG_ENDIAN 1644 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1645 // drive the pixel clock. not used for DCPLL case. 1646 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1647 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1648 #else 1649 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1650 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1651 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1652 // drive the pixel clock. not used for DCPLL case. 1653 #endif 1654 }CRTC_PIXEL_CLOCK_FREQ; 1655 1656 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1657 { 1658 union{ 1659 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1660 ULONG ulDispEngClkFreq; // dispclk frequency 1661 }; 1662 USHORT usFbDiv; // feedback divider integer part. 1663 UCHAR ucPostDiv; // post divider. 1664 UCHAR ucRefDiv; // Reference divider 1665 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1666 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1667 // indicate which graphic encoder will be used. 1668 UCHAR ucEncoderMode; // Encoder mode: 1669 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1670 // bit[1]= when VGA timing is used. 1671 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1672 // bit[4]= RefClock source for PPLL. 1673 // =0: XTLAIN( default mode ) 1674 // =1: other external clock source, which is pre-defined 1675 // by VBIOS depend on the feature required. 1676 // bit[7:5]: reserved. 1677 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1678 1679 }PIXEL_CLOCK_PARAMETERS_V6; 1680 1681 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1682 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1683 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1684 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1685 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1686 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1687 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1688 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1689 1690 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1691 { 1692 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1693 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1694 1695 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1696 { 1697 UCHAR ucStatus; 1698 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1699 UCHAR ucReserved[2]; 1700 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1701 1702 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1703 { 1704 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1705 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1706 1707 /****************************************************************************/ 1708 // Structures used by AdjustDisplayPllTable 1709 /****************************************************************************/ 1710 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1711 { 1712 USHORT usPixelClock; 1713 UCHAR ucTransmitterID; 1714 UCHAR ucEncodeMode; 1715 union 1716 { 1717 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1718 UCHAR ucConfig; //if none DVO, not defined yet 1719 }; 1720 UCHAR ucReserved[3]; 1721 }ADJUST_DISPLAY_PLL_PARAMETERS; 1722 1723 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1724 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1725 1726 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1727 { 1728 USHORT usPixelClock; // target pixel clock 1729 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1730 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1731 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1732 UCHAR ucExtTransmitterID; // external encoder id. 1733 UCHAR ucReserved[2]; 1734 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1735 1736 // usDispPllConfig v1.2 for RoadRunner 1737 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1738 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1739 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1740 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1741 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1742 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1743 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1744 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1745 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1746 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1747 1748 1749 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1750 { 1751 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1752 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1753 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1754 UCHAR ucReserved[2]; 1755 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1756 1757 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1758 { 1759 union 1760 { 1761 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1762 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1763 }; 1764 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1765 1766 /****************************************************************************/ 1767 // Structures used by EnableYUVTable 1768 /****************************************************************************/ 1769 typedef struct _ENABLE_YUV_PARAMETERS 1770 { 1771 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1772 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1773 UCHAR ucPadding[2]; 1774 }ENABLE_YUV_PARAMETERS; 1775 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1776 1777 /****************************************************************************/ 1778 // Structures used by GetMemoryClockTable 1779 /****************************************************************************/ 1780 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1781 { 1782 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1783 } GET_MEMORY_CLOCK_PARAMETERS; 1784 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1785 1786 /****************************************************************************/ 1787 // Structures used by GetEngineClockTable 1788 /****************************************************************************/ 1789 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1790 { 1791 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1792 } GET_ENGINE_CLOCK_PARAMETERS; 1793 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1794 1795 /****************************************************************************/ 1796 // Following Structures and constant may be obsolete 1797 /****************************************************************************/ 1798 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1799 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1800 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1801 { 1802 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1803 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1804 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1805 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1806 UCHAR ucSlaveAddr; //Read from which slave 1807 UCHAR ucLineNumber; //Read from which HW assisted line 1808 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1809 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1810 1811 1812 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1813 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1814 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1815 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1816 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1817 1818 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1819 { 1820 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1821 USHORT usByteOffset; //Write to which byte 1822 //Upper portion of usByteOffset is Format of data 1823 //1bytePS+offsetPS 1824 //2bytesPS+offsetPS 1825 //blockID+offsetPS 1826 //blockID+offsetID 1827 //blockID+counterID+offsetID 1828 UCHAR ucData; //PS data1 1829 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1830 UCHAR ucSlaveAddr; //Write to which slave 1831 UCHAR ucLineNumber; //Write from which HW assisted line 1832 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1833 1834 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1835 1836 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1837 { 1838 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1839 UCHAR ucSlaveAddr; //Write to which slave 1840 UCHAR ucLineNumber; //Write from which HW assisted line 1841 }SET_UP_HW_I2C_DATA_PARAMETERS; 1842 1843 1844 /**************************************************************************/ 1845 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1846 1847 1848 /****************************************************************************/ 1849 // Structures used by PowerConnectorDetectionTable 1850 /****************************************************************************/ 1851 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1852 { 1853 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1854 UCHAR ucPwrBehaviorId; 1855 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1856 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1857 1858 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1859 { 1860 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1861 UCHAR ucReserved; 1862 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1863 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1864 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1865 1866 /****************************LVDS SS Command Table Definitions**********************/ 1867 1868 /****************************************************************************/ 1869 // Structures used by EnableSpreadSpectrumOnPPLLTable 1870 /****************************************************************************/ 1871 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1872 { 1873 USHORT usSpreadSpectrumPercentage; 1874 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1875 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1876 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1877 UCHAR ucPadding[3]; 1878 }ENABLE_LVDS_SS_PARAMETERS; 1879 1880 //ucTableFormatRevision=1,ucTableContentRevision=2 1881 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1882 { 1883 USHORT usSpreadSpectrumPercentage; 1884 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1885 UCHAR ucSpreadSpectrumStep; // 1886 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1887 UCHAR ucSpreadSpectrumDelay; 1888 UCHAR ucSpreadSpectrumRange; 1889 UCHAR ucPadding; 1890 }ENABLE_LVDS_SS_PARAMETERS_V2; 1891 1892 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1893 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1894 { 1895 USHORT usSpreadSpectrumPercentage; 1896 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1897 UCHAR ucSpreadSpectrumStep; // 1898 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1899 UCHAR ucSpreadSpectrumDelay; 1900 UCHAR ucSpreadSpectrumRange; 1901 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1902 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1903 1904 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1905 { 1906 USHORT usSpreadSpectrumPercentage; 1907 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1908 // Bit[1]: 1-Ext. 0-Int. 1909 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1910 // Bits[7:4] reserved 1911 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1912 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1913 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1914 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1915 1916 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1917 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1918 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1919 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1920 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1921 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1922 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1923 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1924 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1925 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1926 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1927 1928 // Used by DCE5.0 1929 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1930 { 1931 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1932 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1933 // Bit[1]: 1-Ext. 0-Int. 1934 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1935 // Bits[7:4] reserved 1936 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1937 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1938 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1939 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1940 1941 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1942 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1943 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1944 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1945 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1946 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1947 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1948 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1949 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1950 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1951 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1952 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1953 1954 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1955 1956 /**************************************************************************/ 1957 1958 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1959 { 1960 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1961 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1962 }SET_PIXEL_CLOCK_PS_ALLOCATION; 1963 1964 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1965 1966 /****************************************************************************/ 1967 // Structures used by ### 1968 /****************************************************************************/ 1969 typedef struct _MEMORY_TRAINING_PARAMETERS 1970 { 1971 ULONG ulTargetMemoryClock; //In 10Khz unit 1972 }MEMORY_TRAINING_PARAMETERS; 1973 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 1974 1975 1976 /****************************LVDS and other encoder command table definitions **********************/ 1977 1978 1979 /****************************************************************************/ 1980 // Structures used by LVDSEncoderControlTable (Before DCE30) 1981 // LVTMAEncoderControlTable (Before DCE30) 1982 // TMDSAEncoderControlTable (Before DCE30) 1983 /****************************************************************************/ 1984 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 1985 { 1986 USHORT usPixelClock; // in 10KHz; for bios convenient 1987 UCHAR ucMisc; // bit0=0: Enable single link 1988 // =1: Enable dual link 1989 // Bit1=0: 666RGB 1990 // =1: 888RGB 1991 UCHAR ucAction; // 0: turn off encoder 1992 // 1: setup and turn on encoder 1993 }LVDS_ENCODER_CONTROL_PARAMETERS; 1994 1995 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 1996 1997 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 1998 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 1999 2000 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2001 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2002 2003 2004 //ucTableFormatRevision=1,ucTableContentRevision=2 2005 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2006 { 2007 USHORT usPixelClock; // in 10KHz; for bios convenient 2008 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2009 UCHAR ucAction; // 0: turn off encoder 2010 // 1: setup and turn on encoder 2011 UCHAR ucTruncate; // bit0=0: Disable truncate 2012 // =1: Enable truncate 2013 // bit4=0: 666RGB 2014 // =1: 888RGB 2015 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2016 // =1: Enable spatial dithering 2017 // bit4=0: 666RGB 2018 // =1: 888RGB 2019 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2020 // =1: Enable temporal dithering 2021 // bit4=0: 666RGB 2022 // =1: 888RGB 2023 // bit5=0: Gray level 2 2024 // =1: Gray level 4 2025 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2026 // =1: 25FRC_SEL pattern F 2027 // bit6:5=0: 50FRC_SEL pattern A 2028 // =1: 50FRC_SEL pattern B 2029 // =2: 50FRC_SEL pattern C 2030 // =3: 50FRC_SEL pattern D 2031 // bit7=0: 75FRC_SEL pattern E 2032 // =1: 75FRC_SEL pattern F 2033 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2034 2035 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2036 2037 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2038 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2039 2040 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2041 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2042 2043 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2044 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2045 2046 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2047 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2048 2049 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2050 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2051 2052 /****************************************************************************/ 2053 // Structures used by ### 2054 /****************************************************************************/ 2055 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2056 { 2057 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2058 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2059 UCHAR ucPadding[2]; 2060 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2061 2062 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2063 { 2064 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2065 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2066 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2067 2068 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2069 2070 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2071 { 2072 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2073 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2074 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2075 2076 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2077 { 2078 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2079 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2080 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2081 2082 /****************************************************************************/ 2083 // Structures used by DVOEncoderControlTable 2084 /****************************************************************************/ 2085 //ucTableFormatRevision=1,ucTableContentRevision=3 2086 2087 //ucDVOConfig: 2088 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2089 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2090 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2091 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2092 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2093 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2094 #define DVO_ENCODER_CONFIG_24BIT 0x08 2095 2096 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2097 { 2098 USHORT usPixelClock; 2099 UCHAR ucDVOConfig; 2100 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2101 UCHAR ucReseved[4]; 2102 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2103 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2104 2105 //ucTableFormatRevision=1 2106 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2107 // bit1=0: non-coherent mode 2108 // =1: coherent mode 2109 2110 //========================================================================================== 2111 //Only change is here next time when changing encoder parameter definitions again! 2112 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2113 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2114 2115 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2116 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2117 2118 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2119 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2120 2121 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2122 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2123 2124 //========================================================================================== 2125 #define PANEL_ENCODER_MISC_DUAL 0x01 2126 #define PANEL_ENCODER_MISC_COHERENT 0x02 2127 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2128 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2129 2130 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2131 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2132 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2133 2134 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2135 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2136 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2137 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2138 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2139 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2140 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2141 #define PANEL_ENCODER_25FRC_MASK 0x10 2142 #define PANEL_ENCODER_25FRC_E 0x00 2143 #define PANEL_ENCODER_25FRC_F 0x10 2144 #define PANEL_ENCODER_50FRC_MASK 0x60 2145 #define PANEL_ENCODER_50FRC_A 0x00 2146 #define PANEL_ENCODER_50FRC_B 0x20 2147 #define PANEL_ENCODER_50FRC_C 0x40 2148 #define PANEL_ENCODER_50FRC_D 0x60 2149 #define PANEL_ENCODER_75FRC_MASK 0x80 2150 #define PANEL_ENCODER_75FRC_E 0x00 2151 #define PANEL_ENCODER_75FRC_F 0x80 2152 2153 /****************************************************************************/ 2154 // Structures used by SetVoltageTable 2155 /****************************************************************************/ 2156 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2157 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2158 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2159 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2160 #define SET_VOLTAGE_INIT_MODE 5 2161 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2162 2163 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2164 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2165 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2166 2167 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2168 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2169 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2170 2171 typedef struct _SET_VOLTAGE_PARAMETERS 2172 { 2173 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2174 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2175 UCHAR ucVoltageIndex; // An index to tell which voltage level 2176 UCHAR ucReserved; 2177 }SET_VOLTAGE_PARAMETERS; 2178 2179 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2180 { 2181 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2182 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2183 USHORT usVoltageLevel; // real voltage level 2184 }SET_VOLTAGE_PARAMETERS_V2; 2185 2186 2187 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2188 { 2189 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2190 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2191 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2192 }SET_VOLTAGE_PARAMETERS_V1_3; 2193 2194 //ucVoltageType 2195 #define VOLTAGE_TYPE_VDDC 1 2196 #define VOLTAGE_TYPE_MVDDC 2 2197 #define VOLTAGE_TYPE_MVDDQ 3 2198 #define VOLTAGE_TYPE_VDDCI 4 2199 2200 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2201 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2202 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2203 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase 2204 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3 2205 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID 2206 2207 // define vitual voltage id in usVoltageLevel 2208 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2209 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2210 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2211 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2212 2213 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2214 { 2215 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2216 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2217 }SET_VOLTAGE_PS_ALLOCATION; 2218 2219 // New Added from SI for GetVoltageInfoTable, input parameter structure 2220 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2221 { 2222 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2223 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2224 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2225 ULONG ulReserved; 2226 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2227 2228 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2229 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2230 { 2231 ULONG ulVotlageGpioState; 2232 ULONG ulVoltageGPioMask; 2233 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2234 2235 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2236 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2237 { 2238 USHORT usVoltageLevel; 2239 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2240 ULONG ulReseved; 2241 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2242 2243 2244 // GetVoltageInfo v1.1 ucVoltageMode 2245 #define ATOM_GET_VOLTAGE_VID 0x00 2246 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2247 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2248 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2249 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2250 2251 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2252 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2253 // undefined power state 2254 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2255 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2256 2257 /****************************************************************************/ 2258 // Structures used by TVEncoderControlTable 2259 /****************************************************************************/ 2260 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2261 { 2262 USHORT usPixelClock; // in 10KHz; for bios convenient 2263 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2264 UCHAR ucAction; // 0: turn off encoder 2265 // 1: setup and turn on encoder 2266 }TV_ENCODER_CONTROL_PARAMETERS; 2267 2268 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2269 { 2270 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2271 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2272 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2273 2274 //==============================Data Table Portion==================================== 2275 2276 /****************************************************************************/ 2277 // Structure used in Data.mtb 2278 /****************************************************************************/ 2279 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2280 { 2281 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2282 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2283 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2284 USHORT StandardVESA_Timing; // Only used by Bios 2285 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2286 USHORT PaletteData; // Only used by BIOS 2287 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2288 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2289 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2290 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2291 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2292 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2293 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2294 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2295 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2296 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2297 USHORT CompassionateData; // Will be obsolete from R600 2298 USHORT SaveRestoreInfo; // Only used by Bios 2299 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2300 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2301 USHORT XTMDS_Info; // Will be obsolete from R600 2302 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2303 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2304 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2305 USHORT MC_InitParameter; // Only used by command table 2306 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2307 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2308 USHORT TV_VideoMode; // Only used by command table 2309 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2310 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2311 USHORT IntegratedSystemInfo; // Shared by various SW components 2312 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2313 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2314 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2315 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2316 2317 typedef struct _ATOM_MASTER_DATA_TABLE 2318 { 2319 ATOM_COMMON_TABLE_HEADER sHeader; 2320 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2321 }ATOM_MASTER_DATA_TABLE; 2322 2323 // For backward compatible 2324 #define LVDS_Info LCD_Info 2325 #define DAC_Info PaletteData 2326 #define TMDS_Info DIGTransmitterInfo 2327 2328 /****************************************************************************/ 2329 // Structure used in MultimediaCapabilityInfoTable 2330 /****************************************************************************/ 2331 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2332 { 2333 ATOM_COMMON_TABLE_HEADER sHeader; 2334 ULONG ulSignature; // HW info table signature string "$ATI" 2335 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2336 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2337 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2338 UCHAR ucHostPortInfo; // Provides host port configuration information 2339 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2340 2341 /****************************************************************************/ 2342 // Structure used in MultimediaConfigInfoTable 2343 /****************************************************************************/ 2344 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2345 { 2346 ATOM_COMMON_TABLE_HEADER sHeader; 2347 ULONG ulSignature; // MM info table signature sting "$MMT" 2348 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2349 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2350 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2351 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2352 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2353 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2354 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2355 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2356 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2357 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2358 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2359 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2360 }ATOM_MULTIMEDIA_CONFIG_INFO; 2361 2362 2363 /****************************************************************************/ 2364 // Structures used in FirmwareInfoTable 2365 /****************************************************************************/ 2366 2367 // usBIOSCapability Definition: 2368 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2369 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2370 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2371 // Others: Reserved 2372 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2373 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2374 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2375 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2376 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2377 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2378 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2379 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2380 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2381 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2382 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2383 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2384 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2385 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2386 2387 #ifndef _H2INC 2388 2389 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2390 typedef struct _ATOM_FIRMWARE_CAPABILITY 2391 { 2392 #if ATOM_BIG_ENDIAN 2393 USHORT Reserved:1; 2394 USHORT SCL2Redefined:1; 2395 USHORT PostWithoutModeSet:1; 2396 USHORT HyperMemory_Size:4; 2397 USHORT HyperMemory_Support:1; 2398 USHORT PPMode_Assigned:1; 2399 USHORT WMI_SUPPORT:1; 2400 USHORT GPUControlsBL:1; 2401 USHORT EngineClockSS_Support:1; 2402 USHORT MemoryClockSS_Support:1; 2403 USHORT ExtendedDesktopSupport:1; 2404 USHORT DualCRTC_Support:1; 2405 USHORT FirmwarePosted:1; 2406 #else 2407 USHORT FirmwarePosted:1; 2408 USHORT DualCRTC_Support:1; 2409 USHORT ExtendedDesktopSupport:1; 2410 USHORT MemoryClockSS_Support:1; 2411 USHORT EngineClockSS_Support:1; 2412 USHORT GPUControlsBL:1; 2413 USHORT WMI_SUPPORT:1; 2414 USHORT PPMode_Assigned:1; 2415 USHORT HyperMemory_Support:1; 2416 USHORT HyperMemory_Size:4; 2417 USHORT PostWithoutModeSet:1; 2418 USHORT SCL2Redefined:1; 2419 USHORT Reserved:1; 2420 #endif 2421 }ATOM_FIRMWARE_CAPABILITY; 2422 2423 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2424 { 2425 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2426 USHORT susAccess; 2427 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2428 2429 #else 2430 2431 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2432 { 2433 USHORT susAccess; 2434 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2435 2436 #endif 2437 2438 typedef struct _ATOM_FIRMWARE_INFO 2439 { 2440 ATOM_COMMON_TABLE_HEADER sHeader; 2441 ULONG ulFirmwareRevision; 2442 ULONG ulDefaultEngineClock; //In 10Khz unit 2443 ULONG ulDefaultMemoryClock; //In 10Khz unit 2444 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2445 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2446 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2447 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2448 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2449 ULONG ulASICMaxEngineClock; //In 10Khz unit 2450 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2451 UCHAR ucASICMaxTemperature; 2452 UCHAR ucPadding[3]; //Don't use them 2453 ULONG aulReservedForBIOS[3]; //Don't use them 2454 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2455 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2456 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2457 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2458 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2459 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2460 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2461 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2462 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2463 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2464 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2465 USHORT usReferenceClock; //In 10Khz unit 2466 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2467 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2468 UCHAR ucDesign_ID; //Indicate what is the board design 2469 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2470 }ATOM_FIRMWARE_INFO; 2471 2472 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2473 { 2474 ATOM_COMMON_TABLE_HEADER sHeader; 2475 ULONG ulFirmwareRevision; 2476 ULONG ulDefaultEngineClock; //In 10Khz unit 2477 ULONG ulDefaultMemoryClock; //In 10Khz unit 2478 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2479 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2480 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2481 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2482 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2483 ULONG ulASICMaxEngineClock; //In 10Khz unit 2484 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2485 UCHAR ucASICMaxTemperature; 2486 UCHAR ucMinAllowedBL_Level; 2487 UCHAR ucPadding[2]; //Don't use them 2488 ULONG aulReservedForBIOS[2]; //Don't use them 2489 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2490 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2491 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2492 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2493 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2494 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2495 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2496 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2497 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2498 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2499 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2500 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2501 USHORT usReferenceClock; //In 10Khz unit 2502 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2503 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2504 UCHAR ucDesign_ID; //Indicate what is the board design 2505 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2506 }ATOM_FIRMWARE_INFO_V1_2; 2507 2508 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2509 { 2510 ATOM_COMMON_TABLE_HEADER sHeader; 2511 ULONG ulFirmwareRevision; 2512 ULONG ulDefaultEngineClock; //In 10Khz unit 2513 ULONG ulDefaultMemoryClock; //In 10Khz unit 2514 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2515 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2516 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2517 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2518 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2519 ULONG ulASICMaxEngineClock; //In 10Khz unit 2520 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2521 UCHAR ucASICMaxTemperature; 2522 UCHAR ucMinAllowedBL_Level; 2523 UCHAR ucPadding[2]; //Don't use them 2524 ULONG aulReservedForBIOS; //Don't use them 2525 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2526 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2527 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2528 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2529 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2530 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2531 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2532 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2533 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2534 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2535 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2536 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2537 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2538 USHORT usReferenceClock; //In 10Khz unit 2539 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2540 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2541 UCHAR ucDesign_ID; //Indicate what is the board design 2542 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2543 }ATOM_FIRMWARE_INFO_V1_3; 2544 2545 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2546 { 2547 ATOM_COMMON_TABLE_HEADER sHeader; 2548 ULONG ulFirmwareRevision; 2549 ULONG ulDefaultEngineClock; //In 10Khz unit 2550 ULONG ulDefaultMemoryClock; //In 10Khz unit 2551 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2552 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2553 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2554 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2555 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2556 ULONG ulASICMaxEngineClock; //In 10Khz unit 2557 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2558 UCHAR ucASICMaxTemperature; 2559 UCHAR ucMinAllowedBL_Level; 2560 USHORT usBootUpVDDCVoltage; //In MV unit 2561 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2562 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2563 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2564 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2565 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2566 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2567 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2568 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2569 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2570 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2571 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2572 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2573 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2574 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2575 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2576 USHORT usReferenceClock; //In 10Khz unit 2577 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2578 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2579 UCHAR ucDesign_ID; //Indicate what is the board design 2580 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2581 }ATOM_FIRMWARE_INFO_V1_4; 2582 2583 //the structure below to be used from Cypress 2584 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2585 { 2586 ATOM_COMMON_TABLE_HEADER sHeader; 2587 ULONG ulFirmwareRevision; 2588 ULONG ulDefaultEngineClock; //In 10Khz unit 2589 ULONG ulDefaultMemoryClock; //In 10Khz unit 2590 ULONG ulReserved1; 2591 ULONG ulReserved2; 2592 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2593 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2594 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2595 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2596 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2597 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2598 UCHAR ucMinAllowedBL_Level; 2599 USHORT usBootUpVDDCVoltage; //In MV unit 2600 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2601 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2602 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2603 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2604 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2605 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2606 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2607 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2608 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2609 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2610 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2611 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2612 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2613 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2614 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2615 USHORT usCoreReferenceClock; //In 10Khz unit 2616 USHORT usMemoryReferenceClock; //In 10Khz unit 2617 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2618 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2619 UCHAR ucReserved4[3]; 2620 }ATOM_FIRMWARE_INFO_V2_1; 2621 2622 //the structure below to be used from NI 2623 //ucTableFormatRevision=2 2624 //ucTableContentRevision=2 2625 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2626 { 2627 ATOM_COMMON_TABLE_HEADER sHeader; 2628 ULONG ulFirmwareRevision; 2629 ULONG ulDefaultEngineClock; //In 10Khz unit 2630 ULONG ulDefaultMemoryClock; //In 10Khz unit 2631 ULONG ulReserved[2]; 2632 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2633 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2634 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2635 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2636 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2637 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2638 UCHAR ucMinAllowedBL_Level; 2639 USHORT usBootUpVDDCVoltage; //In MV unit 2640 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2641 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2642 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2643 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2644 UCHAR ucRemoteDisplayConfig; 2645 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2646 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2647 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2648 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2649 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2650 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2651 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2652 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2653 USHORT usCoreReferenceClock; //In 10Khz unit 2654 USHORT usMemoryReferenceClock; //In 10Khz unit 2655 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2656 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2657 UCHAR ucReserved9[3]; 2658 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2659 USHORT usReserved12; 2660 ULONG ulReserved10[3]; // New added comparing to previous version 2661 }ATOM_FIRMWARE_INFO_V2_2; 2662 2663 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2664 2665 2666 // definition of ucRemoteDisplayConfig 2667 #define REMOTE_DISPLAY_DISABLE 0x00 2668 #define REMOTE_DISPLAY_ENABLE 0x01 2669 2670 /****************************************************************************/ 2671 // Structures used in IntegratedSystemInfoTable 2672 /****************************************************************************/ 2673 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2674 #define IGP_CAP_FLAG_AC_CARD 0x4 2675 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2676 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2677 2678 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2679 { 2680 ATOM_COMMON_TABLE_HEADER sHeader; 2681 ULONG ulBootUpEngineClock; //in 10kHz unit 2682 ULONG ulBootUpMemoryClock; //in 10kHz unit 2683 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2684 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2685 UCHAR ucNumberOfCyclesInPeriodHi; 2686 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2687 USHORT usReserved1; 2688 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2689 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2690 ULONG ulReserved[2]; 2691 2692 USHORT usFSBClock; //In MHz unit 2693 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2694 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2695 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2696 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2697 USHORT usK8MemoryClock; //in MHz unit 2698 USHORT usK8SyncStartDelay; //in 0.01 us unit 2699 USHORT usK8DataReturnTime; //in 0.01 us unit 2700 UCHAR ucMaxNBVoltage; 2701 UCHAR ucMinNBVoltage; 2702 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2703 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2704 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2705 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2706 UCHAR ucMaxNBVoltageHigh; 2707 UCHAR ucMinNBVoltageHigh; 2708 }ATOM_INTEGRATED_SYSTEM_INFO; 2709 2710 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2711 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2712 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2713 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2714 For AMD IGP,for now this can be 0 2715 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2716 For AMD IGP,for now this can be 0 2717 2718 usFSBClock: For Intel IGP,it's FSB Freq 2719 For AMD IGP,it's HT Link Speed 2720 2721 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2722 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2723 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2724 2725 VC:Voltage Control 2726 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2727 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2728 2729 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2730 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2731 2732 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2733 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2734 2735 2736 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2737 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2738 */ 2739 2740 2741 /* 2742 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2743 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2744 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2745 2746 SW components can access the IGP system infor structure in the same way as before 2747 */ 2748 2749 2750 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2751 { 2752 ATOM_COMMON_TABLE_HEADER sHeader; 2753 ULONG ulBootUpEngineClock; //in 10kHz unit 2754 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2755 ULONG ulBootUpUMAClock; //in 10kHz unit 2756 ULONG ulBootUpSidePortClock; //in 10kHz unit 2757 ULONG ulMinSidePortClock; //in 10kHz unit 2758 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2759 ULONG ulSystemConfig; //see explanation below 2760 ULONG ulBootUpReqDisplayVector; 2761 ULONG ulOtherDisplayMisc; 2762 ULONG ulDDISlot1Config; 2763 ULONG ulDDISlot2Config; 2764 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2765 UCHAR ucUMAChannelNumber; 2766 UCHAR ucDockingPinBit; 2767 UCHAR ucDockingPinPolarity; 2768 ULONG ulDockingPinCFGInfo; 2769 ULONG ulCPUCapInfo; 2770 USHORT usNumberOfCyclesInPeriod; 2771 USHORT usMaxNBVoltage; 2772 USHORT usMinNBVoltage; 2773 USHORT usBootUpNBVoltage; 2774 ULONG ulHTLinkFreq; //in 10Khz 2775 USHORT usMinHTLinkWidth; 2776 USHORT usMaxHTLinkWidth; 2777 USHORT usUMASyncStartDelay; 2778 USHORT usUMADataReturnTime; 2779 USHORT usLinkStatusZeroTime; 2780 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2781 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2782 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2783 USHORT usMaxUpStreamHTLinkWidth; 2784 USHORT usMaxDownStreamHTLinkWidth; 2785 USHORT usMinUpStreamHTLinkWidth; 2786 USHORT usMinDownStreamHTLinkWidth; 2787 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2788 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2789 ULONG ulReserved3[96]; //must be 0x0 2790 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2791 2792 /* 2793 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2794 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2795 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2796 2797 ulSystemConfig: 2798 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2799 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2800 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2801 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2802 Bit[3]=1: Only one power state(Performance) will be supported. 2803 =0: Multiple power states supported from PowerPlay table. 2804 Bit[4]=1: CLMC is supported and enabled on current system. 2805 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2806 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2807 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2808 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2809 =0: Voltage settings is determined by powerplay table. 2810 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2811 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2812 Bit[8]=1: CDLF is supported and enabled on current system. 2813 =0: CDLF is not supported or enabled on current system. 2814 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2815 =0: DLL Shut Down feature is not enabled or supported on current system. 2816 2817 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2818 2819 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2820 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2821 2822 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2823 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2824 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2825 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2826 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2827 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2828 2829 [15:8] - Lane configuration attribute; 2830 [23:16]- Connector type, possible value: 2831 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2832 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2833 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2834 CONNECTOR_OBJECT_ID_DISPLAYPORT 2835 CONNECTOR_OBJECT_ID_eDP 2836 [31:24]- Reserved 2837 2838 ulDDISlot2Config: Same as Slot1. 2839 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2840 For IGP, Hypermemory is the only memory type showed in CCC. 2841 2842 ucUMAChannelNumber: how many channels for the UMA; 2843 2844 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2845 ucDockingPinBit: which bit in this register to read the pin status; 2846 ucDockingPinPolarity:Polarity of the pin when docked; 2847 2848 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2849 2850 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2851 2852 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2853 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2854 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2855 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2856 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2857 2858 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2859 2860 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2861 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2862 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2863 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2864 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2865 2866 usUMASyncStartDelay: Memory access latency, required for watermark calculation 2867 usUMADataReturnTime: Memory access latency, required for watermark calculation 2868 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2869 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2870 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2871 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2872 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2873 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2874 2875 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2876 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2877 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2878 This must be less than or equal to ulHighVoltageHTLinkFreq. 2879 2880 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2881 usMaxDownStreamHTLinkWidth: same as above. 2882 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2883 usMinDownStreamHTLinkWidth: same as above. 2884 */ 2885 2886 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2887 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2888 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2889 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2890 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2891 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2892 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2893 2894 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2895 2896 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2897 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2898 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2899 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2900 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2901 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2902 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2903 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2904 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2905 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2906 2907 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2908 2909 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2910 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2911 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2912 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2913 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2914 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2915 2916 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2917 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2918 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2919 2920 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2921 2922 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2923 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2924 { 2925 ATOM_COMMON_TABLE_HEADER sHeader; 2926 ULONG ulBootUpEngineClock; //in 10kHz unit 2927 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2928 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2929 ULONG ulBootUpUMAClock; //in 10kHz unit 2930 ULONG ulReserved1[8]; //must be 0x0 for the reserved 2931 ULONG ulBootUpReqDisplayVector; 2932 ULONG ulOtherDisplayMisc; 2933 ULONG ulReserved2[4]; //must be 0x0 for the reserved 2934 ULONG ulSystemConfig; //TBD 2935 ULONG ulCPUCapInfo; //TBD 2936 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2937 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2938 USHORT usBootUpNBVoltage; //boot up NB voltage 2939 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2940 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2941 ULONG ulReserved3[4]; //must be 0x0 for the reserved 2942 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2943 ULONG ulDDISlot2Config; 2944 ULONG ulDDISlot3Config; 2945 ULONG ulDDISlot4Config; 2946 ULONG ulReserved4[4]; //must be 0x0 for the reserved 2947 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2948 UCHAR ucUMAChannelNumber; 2949 USHORT usReserved; 2950 ULONG ulReserved5[4]; //must be 0x0 for the reserved 2951 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2952 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2953 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 2954 ULONG ulReserved6[61]; //must be 0x0 2955 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 2956 2957 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 2958 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 2959 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 2960 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 2961 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 2962 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 2963 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 2964 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 2965 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 2966 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 2967 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 2968 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 2969 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 2970 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 2971 2972 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 2973 #define ASIC_INT_DAC1_ENCODER_ID 0x00 2974 #define ASIC_INT_TV_ENCODER_ID 0x02 2975 #define ASIC_INT_DIG1_ENCODER_ID 0x03 2976 #define ASIC_INT_DAC2_ENCODER_ID 0x04 2977 #define ASIC_EXT_TV_ENCODER_ID 0x06 2978 #define ASIC_INT_DVO_ENCODER_ID 0x07 2979 #define ASIC_INT_DIG2_ENCODER_ID 0x09 2980 #define ASIC_EXT_DIG_ENCODER_ID 0x05 2981 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 2982 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 2983 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 2984 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 2985 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 2986 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 2987 2988 //define Encoder attribute 2989 #define ATOM_ANALOG_ENCODER 0 2990 #define ATOM_DIGITAL_ENCODER 1 2991 #define ATOM_DP_ENCODER 2 2992 2993 #define ATOM_ENCODER_ENUM_MASK 0x70 2994 #define ATOM_ENCODER_ENUM_ID1 0x00 2995 #define ATOM_ENCODER_ENUM_ID2 0x10 2996 #define ATOM_ENCODER_ENUM_ID3 0x20 2997 #define ATOM_ENCODER_ENUM_ID4 0x30 2998 #define ATOM_ENCODER_ENUM_ID5 0x40 2999 #define ATOM_ENCODER_ENUM_ID6 0x50 3000 3001 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3002 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3003 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3004 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3005 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3006 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3007 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3008 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3009 #define ATOM_DEVICE_CV_INDEX 0x00000008 3010 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3011 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3012 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3013 3014 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3015 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3016 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3017 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3018 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3019 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3020 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3021 3022 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3023 3024 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3025 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3026 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3027 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3028 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3029 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3030 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3031 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3032 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3033 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3034 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3035 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3036 3037 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3038 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3039 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3040 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3041 3042 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3043 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3044 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3045 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3046 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3047 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3048 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3049 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3050 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3051 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3052 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3053 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3054 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3055 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3056 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3057 3058 3059 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3060 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3061 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3062 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3063 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3064 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3065 3066 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3067 3068 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3069 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3070 3071 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3072 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3073 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3074 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3075 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3076 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3077 3078 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3079 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3080 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3081 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3082 3083 // usDeviceSupport: 3084 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3085 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3086 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3087 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3088 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3089 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3090 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3091 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3092 // Bit 8 = 0 - no CV support= 1- CV is supported 3093 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3094 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3095 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3096 // 3097 // 3098 3099 /****************************************************************************/ 3100 /* Structure used in MclkSS_InfoTable */ 3101 /****************************************************************************/ 3102 // ucI2C_ConfigID 3103 // [7:0] - I2C LINE Associate ID 3104 // = 0 - no I2C 3105 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3106 // = 0, [6:0]=SW assisted I2C ID 3107 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3108 // = 2, HW engine for Multimedia use 3109 // = 3-7 Reserved for future I2C engines 3110 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3111 3112 typedef struct _ATOM_I2C_ID_CONFIG 3113 { 3114 #if ATOM_BIG_ENDIAN 3115 UCHAR bfHW_Capable:1; 3116 UCHAR bfHW_EngineID:3; 3117 UCHAR bfI2C_LineMux:4; 3118 #else 3119 UCHAR bfI2C_LineMux:4; 3120 UCHAR bfHW_EngineID:3; 3121 UCHAR bfHW_Capable:1; 3122 #endif 3123 }ATOM_I2C_ID_CONFIG; 3124 3125 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3126 { 3127 ATOM_I2C_ID_CONFIG sbfAccess; 3128 UCHAR ucAccess; 3129 }ATOM_I2C_ID_CONFIG_ACCESS; 3130 3131 3132 /****************************************************************************/ 3133 // Structure used in GPIO_I2C_InfoTable 3134 /****************************************************************************/ 3135 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3136 { 3137 USHORT usClkMaskRegisterIndex; 3138 USHORT usClkEnRegisterIndex; 3139 USHORT usClkY_RegisterIndex; 3140 USHORT usClkA_RegisterIndex; 3141 USHORT usDataMaskRegisterIndex; 3142 USHORT usDataEnRegisterIndex; 3143 USHORT usDataY_RegisterIndex; 3144 USHORT usDataA_RegisterIndex; 3145 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3146 UCHAR ucClkMaskShift; 3147 UCHAR ucClkEnShift; 3148 UCHAR ucClkY_Shift; 3149 UCHAR ucClkA_Shift; 3150 UCHAR ucDataMaskShift; 3151 UCHAR ucDataEnShift; 3152 UCHAR ucDataY_Shift; 3153 UCHAR ucDataA_Shift; 3154 UCHAR ucReserved1; 3155 UCHAR ucReserved2; 3156 }ATOM_GPIO_I2C_ASSIGMENT; 3157 3158 typedef struct _ATOM_GPIO_I2C_INFO 3159 { 3160 ATOM_COMMON_TABLE_HEADER sHeader; 3161 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3162 }ATOM_GPIO_I2C_INFO; 3163 3164 /****************************************************************************/ 3165 // Common Structure used in other structures 3166 /****************************************************************************/ 3167 3168 #ifndef _H2INC 3169 3170 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3171 typedef struct _ATOM_MODE_MISC_INFO 3172 { 3173 #if ATOM_BIG_ENDIAN 3174 USHORT Reserved:6; 3175 USHORT RGB888:1; 3176 USHORT DoubleClock:1; 3177 USHORT Interlace:1; 3178 USHORT CompositeSync:1; 3179 USHORT V_ReplicationBy2:1; 3180 USHORT H_ReplicationBy2:1; 3181 USHORT VerticalCutOff:1; 3182 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3183 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3184 USHORT HorizontalCutOff:1; 3185 #else 3186 USHORT HorizontalCutOff:1; 3187 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3188 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3189 USHORT VerticalCutOff:1; 3190 USHORT H_ReplicationBy2:1; 3191 USHORT V_ReplicationBy2:1; 3192 USHORT CompositeSync:1; 3193 USHORT Interlace:1; 3194 USHORT DoubleClock:1; 3195 USHORT RGB888:1; 3196 USHORT Reserved:6; 3197 #endif 3198 }ATOM_MODE_MISC_INFO; 3199 3200 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3201 { 3202 ATOM_MODE_MISC_INFO sbfAccess; 3203 USHORT usAccess; 3204 }ATOM_MODE_MISC_INFO_ACCESS; 3205 3206 #else 3207 3208 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3209 { 3210 USHORT usAccess; 3211 }ATOM_MODE_MISC_INFO_ACCESS; 3212 3213 #endif 3214 3215 // usModeMiscInfo- 3216 #define ATOM_H_CUTOFF 0x01 3217 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3218 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3219 #define ATOM_V_CUTOFF 0x08 3220 #define ATOM_H_REPLICATIONBY2 0x10 3221 #define ATOM_V_REPLICATIONBY2 0x20 3222 #define ATOM_COMPOSITESYNC 0x40 3223 #define ATOM_INTERLACE 0x80 3224 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3225 #define ATOM_RGB888_MODE 0x200 3226 3227 //usRefreshRate- 3228 #define ATOM_REFRESH_43 43 3229 #define ATOM_REFRESH_47 47 3230 #define ATOM_REFRESH_56 56 3231 #define ATOM_REFRESH_60 60 3232 #define ATOM_REFRESH_65 65 3233 #define ATOM_REFRESH_70 70 3234 #define ATOM_REFRESH_72 72 3235 #define ATOM_REFRESH_75 75 3236 #define ATOM_REFRESH_85 85 3237 3238 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3239 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3240 // 3241 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3242 // = EDID_HA + EDID_HBL 3243 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3244 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3245 // = EDID_HA + EDID_HSO 3246 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3247 // VESA_BORDER = EDID_BORDER 3248 3249 /****************************************************************************/ 3250 // Structure used in SetCRTC_UsingDTDTimingTable 3251 /****************************************************************************/ 3252 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3253 { 3254 USHORT usH_Size; 3255 USHORT usH_Blanking_Time; 3256 USHORT usV_Size; 3257 USHORT usV_Blanking_Time; 3258 USHORT usH_SyncOffset; 3259 USHORT usH_SyncWidth; 3260 USHORT usV_SyncOffset; 3261 USHORT usV_SyncWidth; 3262 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3263 UCHAR ucH_Border; // From DFP EDID 3264 UCHAR ucV_Border; 3265 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3266 UCHAR ucPadding[3]; 3267 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3268 3269 /****************************************************************************/ 3270 // Structure used in SetCRTC_TimingTable 3271 /****************************************************************************/ 3272 typedef struct _SET_CRTC_TIMING_PARAMETERS 3273 { 3274 USHORT usH_Total; // horizontal total 3275 USHORT usH_Disp; // horizontal display 3276 USHORT usH_SyncStart; // horozontal Sync start 3277 USHORT usH_SyncWidth; // horizontal Sync width 3278 USHORT usV_Total; // vertical total 3279 USHORT usV_Disp; // vertical display 3280 USHORT usV_SyncStart; // vertical Sync start 3281 USHORT usV_SyncWidth; // vertical Sync width 3282 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3283 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3284 UCHAR ucOverscanRight; // right 3285 UCHAR ucOverscanLeft; // left 3286 UCHAR ucOverscanBottom; // bottom 3287 UCHAR ucOverscanTop; // top 3288 UCHAR ucReserved; 3289 }SET_CRTC_TIMING_PARAMETERS; 3290 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3291 3292 /****************************************************************************/ 3293 // Structure used in StandardVESA_TimingTable 3294 // AnalogTV_InfoTable 3295 // ComponentVideoInfoTable 3296 /****************************************************************************/ 3297 typedef struct _ATOM_MODE_TIMING 3298 { 3299 USHORT usCRTC_H_Total; 3300 USHORT usCRTC_H_Disp; 3301 USHORT usCRTC_H_SyncStart; 3302 USHORT usCRTC_H_SyncWidth; 3303 USHORT usCRTC_V_Total; 3304 USHORT usCRTC_V_Disp; 3305 USHORT usCRTC_V_SyncStart; 3306 USHORT usCRTC_V_SyncWidth; 3307 USHORT usPixelClock; //in 10Khz unit 3308 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3309 USHORT usCRTC_OverscanRight; 3310 USHORT usCRTC_OverscanLeft; 3311 USHORT usCRTC_OverscanBottom; 3312 USHORT usCRTC_OverscanTop; 3313 USHORT usReserve; 3314 UCHAR ucInternalModeNumber; 3315 UCHAR ucRefreshRate; 3316 }ATOM_MODE_TIMING; 3317 3318 typedef struct _ATOM_DTD_FORMAT 3319 { 3320 USHORT usPixClk; 3321 USHORT usHActive; 3322 USHORT usHBlanking_Time; 3323 USHORT usVActive; 3324 USHORT usVBlanking_Time; 3325 USHORT usHSyncOffset; 3326 USHORT usHSyncWidth; 3327 USHORT usVSyncOffset; 3328 USHORT usVSyncWidth; 3329 USHORT usImageHSize; 3330 USHORT usImageVSize; 3331 UCHAR ucHBorder; 3332 UCHAR ucVBorder; 3333 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3334 UCHAR ucInternalModeNumber; 3335 UCHAR ucRefreshRate; 3336 }ATOM_DTD_FORMAT; 3337 3338 /****************************************************************************/ 3339 // Structure used in LVDS_InfoTable 3340 // * Need a document to describe this table 3341 /****************************************************************************/ 3342 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3343 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3344 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3345 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3346 3347 //ucTableFormatRevision=1 3348 //ucTableContentRevision=1 3349 typedef struct _ATOM_LVDS_INFO 3350 { 3351 ATOM_COMMON_TABLE_HEADER sHeader; 3352 ATOM_DTD_FORMAT sLCDTiming; 3353 USHORT usModePatchTableOffset; 3354 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3355 USHORT usOffDelayInMs; 3356 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3357 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3358 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3359 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3360 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3361 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3362 UCHAR ucPanelDefaultRefreshRate; 3363 UCHAR ucPanelIdentification; 3364 UCHAR ucSS_Id; 3365 }ATOM_LVDS_INFO; 3366 3367 //ucTableFormatRevision=1 3368 //ucTableContentRevision=2 3369 typedef struct _ATOM_LVDS_INFO_V12 3370 { 3371 ATOM_COMMON_TABLE_HEADER sHeader; 3372 ATOM_DTD_FORMAT sLCDTiming; 3373 USHORT usExtInfoTableOffset; 3374 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3375 USHORT usOffDelayInMs; 3376 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3377 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3378 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3379 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3380 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3381 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3382 UCHAR ucPanelDefaultRefreshRate; 3383 UCHAR ucPanelIdentification; 3384 UCHAR ucSS_Id; 3385 USHORT usLCDVenderID; 3386 USHORT usLCDProductID; 3387 UCHAR ucLCDPanel_SpecialHandlingCap; 3388 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3389 UCHAR ucReserved[2]; 3390 }ATOM_LVDS_INFO_V12; 3391 3392 //Definitions for ucLCDPanel_SpecialHandlingCap: 3393 3394 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3395 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3396 #define LCDPANEL_CAP_READ_EDID 0x1 3397 3398 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3399 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3400 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3401 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3402 3403 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3404 #define LCDPANEL_CAP_eDP 0x4 3405 3406 3407 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3408 //Bit 6 5 4 3409 // 0 0 0 - Color bit depth is undefined 3410 // 0 0 1 - 6 Bits per Primary Color 3411 // 0 1 0 - 8 Bits per Primary Color 3412 // 0 1 1 - 10 Bits per Primary Color 3413 // 1 0 0 - 12 Bits per Primary Color 3414 // 1 0 1 - 14 Bits per Primary Color 3415 // 1 1 0 - 16 Bits per Primary Color 3416 // 1 1 1 - Reserved 3417 3418 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3419 3420 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3421 #define PANEL_RANDOM_DITHER 0x80 3422 #define PANEL_RANDOM_DITHER_MASK 0x80 3423 3424 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3425 3426 /****************************************************************************/ 3427 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3428 // ASIC Families: NI 3429 // ucTableFormatRevision=1 3430 // ucTableContentRevision=3 3431 /****************************************************************************/ 3432 typedef struct _ATOM_LCD_INFO_V13 3433 { 3434 ATOM_COMMON_TABLE_HEADER sHeader; 3435 ATOM_DTD_FORMAT sLCDTiming; 3436 USHORT usExtInfoTableOffset; 3437 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3438 ULONG ulReserved0; 3439 UCHAR ucLCD_Misc; // Reorganized in V13 3440 // Bit0: {=0:single, =1:dual}, 3441 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3442 // Bit3:2: {Grey level} 3443 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3444 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3445 UCHAR ucPanelDefaultRefreshRate; 3446 UCHAR ucPanelIdentification; 3447 UCHAR ucSS_Id; 3448 USHORT usLCDVenderID; 3449 USHORT usLCDProductID; 3450 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3451 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3452 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3453 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3454 // Bit7-3: Reserved 3455 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3456 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3457 3458 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3459 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3460 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3461 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3462 3463 UCHAR ucOffDelay_in4Ms; 3464 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3465 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3466 UCHAR ucReserved1; 3467 3468 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3469 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3470 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3471 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3472 3473 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3474 UCHAR uceDPToLVDSRxId; 3475 UCHAR ucLcdReservd; 3476 ULONG ulReserved[2]; 3477 }ATOM_LCD_INFO_V13; 3478 3479 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3480 3481 //Definitions for ucLCD_Misc 3482 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3483 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3484 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3485 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3486 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3487 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3488 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3489 3490 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3491 //Bit 6 5 4 3492 // 0 0 0 - Color bit depth is undefined 3493 // 0 0 1 - 6 Bits per Primary Color 3494 // 0 1 0 - 8 Bits per Primary Color 3495 // 0 1 1 - 10 Bits per Primary Color 3496 // 1 0 0 - 12 Bits per Primary Color 3497 // 1 0 1 - 14 Bits per Primary Color 3498 // 1 1 0 - 16 Bits per Primary Color 3499 // 1 1 1 - Reserved 3500 3501 //Definitions for ucLCDPanel_SpecialHandlingCap: 3502 3503 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3504 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3505 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3506 3507 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3508 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3509 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3510 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3511 3512 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3513 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3514 3515 //uceDPToLVDSRxId 3516 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3517 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3518 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3519 3520 typedef struct _ATOM_PATCH_RECORD_MODE 3521 { 3522 UCHAR ucRecordType; 3523 USHORT usHDisp; 3524 USHORT usVDisp; 3525 }ATOM_PATCH_RECORD_MODE; 3526 3527 typedef struct _ATOM_LCD_RTS_RECORD 3528 { 3529 UCHAR ucRecordType; 3530 UCHAR ucRTSValue; 3531 }ATOM_LCD_RTS_RECORD; 3532 3533 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3534 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3535 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3536 { 3537 UCHAR ucRecordType; 3538 USHORT usLCDCap; 3539 }ATOM_LCD_MODE_CONTROL_CAP; 3540 3541 #define LCD_MODE_CAP_BL_OFF 1 3542 #define LCD_MODE_CAP_CRTC_OFF 2 3543 #define LCD_MODE_CAP_PANEL_OFF 4 3544 3545 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3546 { 3547 UCHAR ucRecordType; 3548 UCHAR ucFakeEDIDLength; 3549 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3550 } ATOM_FAKE_EDID_PATCH_RECORD; 3551 3552 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3553 { 3554 UCHAR ucRecordType; 3555 USHORT usHSize; 3556 USHORT usVSize; 3557 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3558 3559 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3560 #define LCD_RTS_RECORD_TYPE 2 3561 #define LCD_CAP_RECORD_TYPE 3 3562 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3563 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3564 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3565 #define ATOM_RECORD_END_TYPE 0xFF 3566 3567 /****************************Spread Spectrum Info Table Definitions **********************/ 3568 3569 //ucTableFormatRevision=1 3570 //ucTableContentRevision=2 3571 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3572 { 3573 USHORT usSpreadSpectrumPercentage; 3574 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3575 UCHAR ucSS_Step; 3576 UCHAR ucSS_Delay; 3577 UCHAR ucSS_Id; 3578 UCHAR ucRecommendedRef_Div; 3579 UCHAR ucSS_Range; //it was reserved for V11 3580 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3581 3582 #define ATOM_MAX_SS_ENTRY 16 3583 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3584 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3585 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3586 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3587 3588 3589 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3590 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3591 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3592 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3593 #define ATOM_INTERNAL_SS_MASK 0x00000000 3594 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3595 #define EXEC_SS_STEP_SIZE_SHIFT 2 3596 #define EXEC_SS_DELAY_SHIFT 4 3597 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3598 3599 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3600 { 3601 ATOM_COMMON_TABLE_HEADER sHeader; 3602 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3603 }ATOM_SPREAD_SPECTRUM_INFO; 3604 3605 /****************************************************************************/ 3606 // Structure used in AnalogTV_InfoTable (Top level) 3607 /****************************************************************************/ 3608 //ucTVBootUpDefaultStd definition: 3609 3610 //ATOM_TV_NTSC 1 3611 //ATOM_TV_NTSCJ 2 3612 //ATOM_TV_PAL 3 3613 //ATOM_TV_PALM 4 3614 //ATOM_TV_PALCN 5 3615 //ATOM_TV_PALN 6 3616 //ATOM_TV_PAL60 7 3617 //ATOM_TV_SECAM 8 3618 3619 //ucTVSupportedStd definition: 3620 #define NTSC_SUPPORT 0x1 3621 #define NTSCJ_SUPPORT 0x2 3622 3623 #define PAL_SUPPORT 0x4 3624 #define PALM_SUPPORT 0x8 3625 #define PALCN_SUPPORT 0x10 3626 #define PALN_SUPPORT 0x20 3627 #define PAL60_SUPPORT 0x40 3628 #define SECAM_SUPPORT 0x80 3629 3630 #define MAX_SUPPORTED_TV_TIMING 2 3631 3632 typedef struct _ATOM_ANALOG_TV_INFO 3633 { 3634 ATOM_COMMON_TABLE_HEADER sHeader; 3635 UCHAR ucTV_SupportedStandard; 3636 UCHAR ucTV_BootUpDefaultStandard; 3637 UCHAR ucExt_TV_ASIC_ID; 3638 UCHAR ucExt_TV_ASIC_SlaveAddr; 3639 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3640 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3641 }ATOM_ANALOG_TV_INFO; 3642 3643 #define MAX_SUPPORTED_TV_TIMING_V1_2 3 3644 3645 typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3646 { 3647 ATOM_COMMON_TABLE_HEADER sHeader; 3648 UCHAR ucTV_SupportedStandard; 3649 UCHAR ucTV_BootUpDefaultStandard; 3650 UCHAR ucExt_TV_ASIC_ID; 3651 UCHAR ucExt_TV_ASIC_SlaveAddr; 3652 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3653 }ATOM_ANALOG_TV_INFO_V1_2; 3654 3655 typedef struct _ATOM_DPCD_INFO 3656 { 3657 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3658 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3659 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3660 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3661 }ATOM_DPCD_INFO; 3662 3663 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3664 3665 /**************************************************************************/ 3666 // VRAM usage and their defintions 3667 3668 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3669 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3670 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3671 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3672 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3673 3674 #ifndef VESA_MEMORY_IN_64K_BLOCK 3675 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3676 #endif 3677 3678 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3679 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3680 #define ATOM_HWICON_INFOTABLE_SIZE 32 3681 #define MAX_DTD_MODE_IN_VRAM 6 3682 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3683 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3684 //20 bytes for Encoder Type and DPCD in STD EDID area 3685 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3686 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3687 3688 #define ATOM_HWICON1_SURFACE_ADDR 0 3689 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3690 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3691 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3692 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3693 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3694 3695 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3696 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3697 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3698 3699 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3700 3701 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3702 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3703 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3704 3705 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3706 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3707 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3708 3709 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3710 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3711 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3712 3713 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3714 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3715 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3716 3717 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3718 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3719 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3720 3721 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3722 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3723 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3724 3725 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3726 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3727 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3728 3729 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3730 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3731 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3732 3733 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3734 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3735 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3736 3737 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3738 3739 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3740 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3741 3742 //The size below is in Kb! 3743 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3744 3745 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3746 3747 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3748 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3749 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3750 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3751 3752 /***********************************************************************************/ 3753 // Structure used in VRAM_UsageByFirmwareTable 3754 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3755 // at running time. 3756 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3757 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3758 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3759 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3760 /***********************************************************************************/ 3761 // Note3: 3762 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3763 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3764 3765 If (ulStartAddrUsedByFirmware!=0) 3766 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3767 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3768 else //Non VGA case 3769 if (FB_Size<=2Gb) 3770 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3771 else 3772 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3773 3774 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3775 3776 /***********************************************************************************/ 3777 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3778 3779 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3780 { 3781 ULONG ulStartAddrUsedByFirmware; 3782 USHORT usFirmwareUseInKb; 3783 USHORT usReserved; 3784 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3785 3786 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3787 { 3788 ATOM_COMMON_TABLE_HEADER sHeader; 3789 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3790 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3791 3792 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3793 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3794 { 3795 ULONG ulStartAddrUsedByFirmware; 3796 USHORT usFirmwareUseInKb; 3797 USHORT usFBUsedByDrvInKb; 3798 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3799 3800 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3801 { 3802 ATOM_COMMON_TABLE_HEADER sHeader; 3803 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3804 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3805 3806 /****************************************************************************/ 3807 // Structure used in GPIO_Pin_LUTTable 3808 /****************************************************************************/ 3809 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3810 { 3811 USHORT usGpioPin_AIndex; 3812 UCHAR ucGpioPinBitShift; 3813 UCHAR ucGPIO_ID; 3814 }ATOM_GPIO_PIN_ASSIGNMENT; 3815 3816 typedef struct _ATOM_GPIO_PIN_LUT 3817 { 3818 ATOM_COMMON_TABLE_HEADER sHeader; 3819 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3820 }ATOM_GPIO_PIN_LUT; 3821 3822 /****************************************************************************/ 3823 // Structure used in ComponentVideoInfoTable 3824 /****************************************************************************/ 3825 #define GPIO_PIN_ACTIVE_HIGH 0x1 3826 3827 #define MAX_SUPPORTED_CV_STANDARDS 5 3828 3829 // definitions for ATOM_D_INFO.ucSettings 3830 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3831 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3832 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3833 3834 typedef struct _ATOM_GPIO_INFO 3835 { 3836 USHORT usAOffset; 3837 UCHAR ucSettings; 3838 UCHAR ucReserved; 3839 }ATOM_GPIO_INFO; 3840 3841 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3842 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3843 3844 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3845 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3846 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3847 3848 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3849 //Line 3 out put 5V. 3850 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3851 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3852 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3853 3854 //Line 3 out put 2.2V 3855 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3856 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3857 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3858 3859 //Line 3 out put 0V 3860 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3861 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3862 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3863 3864 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3865 3866 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3867 3868 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3869 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3870 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3871 3872 3873 typedef struct _ATOM_COMPONENT_VIDEO_INFO 3874 { 3875 ATOM_COMMON_TABLE_HEADER sHeader; 3876 USHORT usMask_PinRegisterIndex; 3877 USHORT usEN_PinRegisterIndex; 3878 USHORT usY_PinRegisterIndex; 3879 USHORT usA_PinRegisterIndex; 3880 UCHAR ucBitShift; 3881 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3882 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3883 UCHAR ucMiscInfo; 3884 UCHAR uc480i; 3885 UCHAR uc480p; 3886 UCHAR uc720p; 3887 UCHAR uc1080i; 3888 UCHAR ucLetterBoxMode; 3889 UCHAR ucReserved[3]; 3890 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3891 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3892 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3893 }ATOM_COMPONENT_VIDEO_INFO; 3894 3895 //ucTableFormatRevision=2 3896 //ucTableContentRevision=1 3897 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3898 { 3899 ATOM_COMMON_TABLE_HEADER sHeader; 3900 UCHAR ucMiscInfo; 3901 UCHAR uc480i; 3902 UCHAR uc480p; 3903 UCHAR uc720p; 3904 UCHAR uc1080i; 3905 UCHAR ucReserved; 3906 UCHAR ucLetterBoxMode; 3907 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3908 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3909 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3910 }ATOM_COMPONENT_VIDEO_INFO_V21; 3911 3912 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3913 3914 /****************************************************************************/ 3915 // Structure used in object_InfoTable 3916 /****************************************************************************/ 3917 typedef struct _ATOM_OBJECT_HEADER 3918 { 3919 ATOM_COMMON_TABLE_HEADER sHeader; 3920 USHORT usDeviceSupport; 3921 USHORT usConnectorObjectTableOffset; 3922 USHORT usRouterObjectTableOffset; 3923 USHORT usEncoderObjectTableOffset; 3924 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3925 USHORT usDisplayPathTableOffset; 3926 }ATOM_OBJECT_HEADER; 3927 3928 typedef struct _ATOM_OBJECT_HEADER_V3 3929 { 3930 ATOM_COMMON_TABLE_HEADER sHeader; 3931 USHORT usDeviceSupport; 3932 USHORT usConnectorObjectTableOffset; 3933 USHORT usRouterObjectTableOffset; 3934 USHORT usEncoderObjectTableOffset; 3935 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3936 USHORT usDisplayPathTableOffset; 3937 USHORT usMiscObjectTableOffset; 3938 }ATOM_OBJECT_HEADER_V3; 3939 3940 typedef struct _ATOM_DISPLAY_OBJECT_PATH 3941 { 3942 USHORT usDeviceTag; //supported device 3943 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3944 USHORT usConnObjectId; //Connector Object ID 3945 USHORT usGPUObjectId; //GPU ID 3946 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3947 }ATOM_DISPLAY_OBJECT_PATH; 3948 3949 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 3950 { 3951 USHORT usDeviceTag; //supported device 3952 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3953 USHORT usConnObjectId; //Connector Object ID 3954 USHORT usGPUObjectId; //GPU ID 3955 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 3956 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 3957 3958 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3959 { 3960 UCHAR ucNumOfDispPath; 3961 UCHAR ucVersion; 3962 UCHAR ucPadding[2]; 3963 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 3964 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 3965 3966 3967 typedef struct _ATOM_OBJECT //each object has this structure 3968 { 3969 USHORT usObjectID; 3970 USHORT usSrcDstTableOffset; 3971 USHORT usRecordOffset; //this pointing to a bunch of records defined below 3972 USHORT usReserved; 3973 }ATOM_OBJECT; 3974 3975 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 3976 { 3977 UCHAR ucNumberOfObjects; 3978 UCHAR ucPadding[3]; 3979 ATOM_OBJECT asObjects[1]; 3980 }ATOM_OBJECT_TABLE; 3981 3982 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 3983 { 3984 UCHAR ucNumberOfSrc; 3985 USHORT usSrcObjectID[1]; 3986 UCHAR ucNumberOfDst; 3987 USHORT usDstObjectID[1]; 3988 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 3989 3990 3991 //Two definitions below are for OPM on MXM module designs 3992 3993 #define EXT_HPDPIN_LUTINDEX_0 0 3994 #define EXT_HPDPIN_LUTINDEX_1 1 3995 #define EXT_HPDPIN_LUTINDEX_2 2 3996 #define EXT_HPDPIN_LUTINDEX_3 3 3997 #define EXT_HPDPIN_LUTINDEX_4 4 3998 #define EXT_HPDPIN_LUTINDEX_5 5 3999 #define EXT_HPDPIN_LUTINDEX_6 6 4000 #define EXT_HPDPIN_LUTINDEX_7 7 4001 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4002 4003 #define EXT_AUXDDC_LUTINDEX_0 0 4004 #define EXT_AUXDDC_LUTINDEX_1 1 4005 #define EXT_AUXDDC_LUTINDEX_2 2 4006 #define EXT_AUXDDC_LUTINDEX_3 3 4007 #define EXT_AUXDDC_LUTINDEX_4 4 4008 #define EXT_AUXDDC_LUTINDEX_5 5 4009 #define EXT_AUXDDC_LUTINDEX_6 6 4010 #define EXT_AUXDDC_LUTINDEX_7 7 4011 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4012 4013 //ucChannelMapping are defined as following 4014 //for DP connector, eDP, DP to VGA/LVDS 4015 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4016 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4017 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4018 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4019 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4020 { 4021 #if ATOM_BIG_ENDIAN 4022 UCHAR ucDP_Lane3_Source:2; 4023 UCHAR ucDP_Lane2_Source:2; 4024 UCHAR ucDP_Lane1_Source:2; 4025 UCHAR ucDP_Lane0_Source:2; 4026 #else 4027 UCHAR ucDP_Lane0_Source:2; 4028 UCHAR ucDP_Lane1_Source:2; 4029 UCHAR ucDP_Lane2_Source:2; 4030 UCHAR ucDP_Lane3_Source:2; 4031 #endif 4032 }ATOM_DP_CONN_CHANNEL_MAPPING; 4033 4034 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4035 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4036 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4037 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4038 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4039 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4040 { 4041 #if ATOM_BIG_ENDIAN 4042 UCHAR ucDVI_CLK_Source:2; 4043 UCHAR ucDVI_DATA0_Source:2; 4044 UCHAR ucDVI_DATA1_Source:2; 4045 UCHAR ucDVI_DATA2_Source:2; 4046 #else 4047 UCHAR ucDVI_DATA2_Source:2; 4048 UCHAR ucDVI_DATA1_Source:2; 4049 UCHAR ucDVI_DATA0_Source:2; 4050 UCHAR ucDVI_CLK_Source:2; 4051 #endif 4052 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4053 4054 typedef struct _EXT_DISPLAY_PATH 4055 { 4056 USHORT usDeviceTag; //A bit vector to show what devices are supported 4057 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4058 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4059 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4060 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4061 USHORT usExtEncoderObjId; //external encoder object id 4062 union{ 4063 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4064 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4065 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4066 }; 4067 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4068 USHORT usCaps; 4069 USHORT usReserved; 4070 }EXT_DISPLAY_PATH; 4071 4072 #define NUMBER_OF_UCHAR_FOR_GUID 16 4073 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4074 4075 //usCaps 4076 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4077 4078 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4079 { 4080 ATOM_COMMON_TABLE_HEADER sHeader; 4081 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4082 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4083 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4084 UCHAR uc3DStereoPinId; // use for eDP panel 4085 UCHAR ucRemoteDisplayConfig; 4086 UCHAR uceDPToLVDSRxId; 4087 UCHAR Reserved[4]; // for potential expansion 4088 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4089 4090 //Related definitions, all records are different but they have a commond header 4091 typedef struct _ATOM_COMMON_RECORD_HEADER 4092 { 4093 UCHAR ucRecordType; //An emun to indicate the record type 4094 UCHAR ucRecordSize; //The size of the whole record in byte 4095 }ATOM_COMMON_RECORD_HEADER; 4096 4097 4098 #define ATOM_I2C_RECORD_TYPE 1 4099 #define ATOM_HPD_INT_RECORD_TYPE 2 4100 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4101 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4102 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4103 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4104 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4105 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4106 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4107 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4108 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4109 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4110 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4111 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4112 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4113 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4114 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4115 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4116 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4117 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4118 4119 4120 //Must be updated when new record type is added,equal to that record definition! 4121 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4122 4123 typedef struct _ATOM_I2C_RECORD 4124 { 4125 ATOM_COMMON_RECORD_HEADER sheader; 4126 ATOM_I2C_ID_CONFIG sucI2cId; 4127 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4128 }ATOM_I2C_RECORD; 4129 4130 typedef struct _ATOM_HPD_INT_RECORD 4131 { 4132 ATOM_COMMON_RECORD_HEADER sheader; 4133 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4134 UCHAR ucPlugged_PinState; 4135 }ATOM_HPD_INT_RECORD; 4136 4137 4138 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4139 { 4140 ATOM_COMMON_RECORD_HEADER sheader; 4141 UCHAR ucProtectionFlag; 4142 UCHAR ucReserved; 4143 }ATOM_OUTPUT_PROTECTION_RECORD; 4144 4145 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4146 { 4147 ULONG ulACPIDeviceEnum; //Reserved for now 4148 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4149 USHORT usPadding; 4150 }ATOM_CONNECTOR_DEVICE_TAG; 4151 4152 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4153 { 4154 ATOM_COMMON_RECORD_HEADER sheader; 4155 UCHAR ucNumberOfDevice; 4156 UCHAR ucReserved; 4157 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4158 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4159 4160 4161 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4162 { 4163 ATOM_COMMON_RECORD_HEADER sheader; 4164 UCHAR ucConfigGPIOID; 4165 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4166 UCHAR ucFlowinGPIPID; 4167 UCHAR ucExtInGPIPID; 4168 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4169 4170 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4171 { 4172 ATOM_COMMON_RECORD_HEADER sheader; 4173 UCHAR ucCTL1GPIO_ID; 4174 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4175 UCHAR ucCTL2GPIO_ID; 4176 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4177 UCHAR ucCTL3GPIO_ID; 4178 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4179 UCHAR ucCTLFPGA_IN_ID; 4180 UCHAR ucPadding[3]; 4181 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4182 4183 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4184 { 4185 ATOM_COMMON_RECORD_HEADER sheader; 4186 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4187 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4188 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4189 4190 typedef struct _ATOM_JTAG_RECORD 4191 { 4192 ATOM_COMMON_RECORD_HEADER sheader; 4193 UCHAR ucTMSGPIO_ID; 4194 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4195 UCHAR ucTCKGPIO_ID; 4196 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4197 UCHAR ucTDOGPIO_ID; 4198 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4199 UCHAR ucTDIGPIO_ID; 4200 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4201 UCHAR ucPadding[2]; 4202 }ATOM_JTAG_RECORD; 4203 4204 4205 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4206 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4207 { 4208 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4209 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4210 }ATOM_GPIO_PIN_CONTROL_PAIR; 4211 4212 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4213 { 4214 ATOM_COMMON_RECORD_HEADER sheader; 4215 UCHAR ucFlags; // Future expnadibility 4216 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4217 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4218 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4219 4220 //Definitions for GPIO pin state 4221 #define GPIO_PIN_TYPE_INPUT 0x00 4222 #define GPIO_PIN_TYPE_OUTPUT 0x10 4223 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4224 4225 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4226 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4227 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4228 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4229 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4230 4231 // Indexes to GPIO array in GLSync record 4232 // GLSync record is for Frame Lock/Gen Lock feature. 4233 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4234 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4235 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4236 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4237 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4238 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4239 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4240 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4241 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4242 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4243 4244 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4245 { 4246 ATOM_COMMON_RECORD_HEADER sheader; 4247 ULONG ulStrengthControl; // DVOA strength control for CF 4248 UCHAR ucPadding[2]; 4249 }ATOM_ENCODER_DVO_CF_RECORD; 4250 4251 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4252 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4253 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4254 4255 typedef struct _ATOM_ENCODER_CAP_RECORD 4256 { 4257 ATOM_COMMON_RECORD_HEADER sheader; 4258 union { 4259 USHORT usEncoderCap; 4260 struct { 4261 #if ATOM_BIG_ENDIAN 4262 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4263 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4264 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4265 #else 4266 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4267 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4268 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4269 #endif 4270 }; 4271 }; 4272 }ATOM_ENCODER_CAP_RECORD; 4273 4274 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4275 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4276 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4277 4278 typedef struct _ATOM_CONNECTOR_CF_RECORD 4279 { 4280 ATOM_COMMON_RECORD_HEADER sheader; 4281 USHORT usMaxPixClk; 4282 UCHAR ucFlowCntlGpioId; 4283 UCHAR ucSwapCntlGpioId; 4284 UCHAR ucConnectedDvoBundle; 4285 UCHAR ucPadding; 4286 }ATOM_CONNECTOR_CF_RECORD; 4287 4288 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4289 { 4290 ATOM_COMMON_RECORD_HEADER sheader; 4291 ATOM_DTD_FORMAT asTiming; 4292 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4293 4294 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4295 { 4296 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4297 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4298 UCHAR ucReserved; 4299 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4300 4301 4302 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4303 { 4304 ATOM_COMMON_RECORD_HEADER sheader; 4305 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4306 UCHAR ucMuxControlPin; 4307 UCHAR ucMuxState[2]; //for alligment purpose 4308 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4309 4310 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4311 { 4312 ATOM_COMMON_RECORD_HEADER sheader; 4313 UCHAR ucMuxType; 4314 UCHAR ucMuxControlPin; 4315 UCHAR ucMuxState[2]; //for alligment purpose 4316 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4317 4318 // define ucMuxType 4319 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4320 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4321 4322 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4323 { 4324 ATOM_COMMON_RECORD_HEADER sheader; 4325 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4326 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4327 4328 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4329 { 4330 ATOM_COMMON_RECORD_HEADER sheader; 4331 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4332 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4333 4334 typedef struct _ATOM_OBJECT_LINK_RECORD 4335 { 4336 ATOM_COMMON_RECORD_HEADER sheader; 4337 USHORT usObjectID; //could be connector, encorder or other object in object.h 4338 }ATOM_OBJECT_LINK_RECORD; 4339 4340 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4341 { 4342 ATOM_COMMON_RECORD_HEADER sheader; 4343 USHORT usReserved; 4344 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4345 4346 /****************************************************************************/ 4347 // ASIC voltage data table 4348 /****************************************************************************/ 4349 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4350 { 4351 USHORT usVDDCBaseLevel; //In number of 50mv unit 4352 USHORT usReserved; //For possible extension table offset 4353 UCHAR ucNumOfVoltageEntries; 4354 UCHAR ucBytesPerVoltageEntry; 4355 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4356 UCHAR ucDefaultVoltageEntry; 4357 UCHAR ucVoltageControlI2cLine; 4358 UCHAR ucVoltageControlAddress; 4359 UCHAR ucVoltageControlOffset; 4360 }ATOM_VOLTAGE_INFO_HEADER; 4361 4362 typedef struct _ATOM_VOLTAGE_INFO 4363 { 4364 ATOM_COMMON_TABLE_HEADER sHeader; 4365 ATOM_VOLTAGE_INFO_HEADER viHeader; 4366 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4367 }ATOM_VOLTAGE_INFO; 4368 4369 4370 typedef struct _ATOM_VOLTAGE_FORMULA 4371 { 4372 USHORT usVoltageBaseLevel; // In number of 1mv unit 4373 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4374 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4375 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4376 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4377 UCHAR ucReserved; 4378 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4379 }ATOM_VOLTAGE_FORMULA; 4380 4381 typedef struct _VOLTAGE_LUT_ENTRY 4382 { 4383 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4384 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4385 }VOLTAGE_LUT_ENTRY; 4386 4387 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4388 { 4389 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4390 UCHAR ucReserved[3]; 4391 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4392 }ATOM_VOLTAGE_FORMULA_V2; 4393 4394 typedef struct _ATOM_VOLTAGE_CONTROL 4395 { 4396 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4397 UCHAR ucVoltageControlI2cLine; 4398 UCHAR ucVoltageControlAddress; 4399 UCHAR ucVoltageControlOffset; 4400 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4401 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4402 UCHAR ucReserved; 4403 }ATOM_VOLTAGE_CONTROL; 4404 4405 // Define ucVoltageControlId 4406 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4407 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4408 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4409 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4410 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4411 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4412 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4413 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4414 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4415 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4416 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4417 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4418 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 4419 4420 typedef struct _ATOM_VOLTAGE_OBJECT 4421 { 4422 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4423 UCHAR ucSize; //Size of Object 4424 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4425 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4426 }ATOM_VOLTAGE_OBJECT; 4427 4428 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4429 { 4430 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4431 UCHAR ucSize; //Size of Object 4432 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4433 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4434 }ATOM_VOLTAGE_OBJECT_V2; 4435 4436 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4437 { 4438 ATOM_COMMON_TABLE_HEADER sHeader; 4439 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4440 }ATOM_VOLTAGE_OBJECT_INFO; 4441 4442 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4443 { 4444 ATOM_COMMON_TABLE_HEADER sHeader; 4445 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4446 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4447 4448 typedef struct _ATOM_LEAKID_VOLTAGE 4449 { 4450 UCHAR ucLeakageId; 4451 UCHAR ucReserved; 4452 USHORT usVoltage; 4453 }ATOM_LEAKID_VOLTAGE; 4454 4455 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4456 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4457 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4458 USHORT usSize; //Size of Object 4459 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 4460 4461 typedef struct _VOLTAGE_LUT_ENTRY_V2 4462 { 4463 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4464 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4465 }VOLTAGE_LUT_ENTRY_V2; 4466 4467 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4468 { 4469 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4470 USHORT usVoltageId; 4471 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4472 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4473 4474 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4475 { 4476 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4477 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4478 UCHAR ucVoltageControlI2cLine; 4479 UCHAR ucVoltageControlAddress; 4480 UCHAR ucVoltageControlOffset; 4481 ULONG ulReserved; 4482 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4483 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4484 4485 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4486 { 4487 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4488 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4489 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4490 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4491 UCHAR ucReserved; 4492 ULONG ulGpioMaskVal; // GPIO Mask value 4493 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4494 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 4495 4496 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4497 { 4498 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4499 UCHAR ucLeakageCntlId; // default is 0 4500 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4501 UCHAR ucReserved[2]; 4502 ULONG ulMaxVoltageLevel; 4503 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4504 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4505 4506 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4507 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4508 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4509 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4510 }ATOM_VOLTAGE_OBJECT_V3; 4511 4512 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4513 { 4514 ATOM_COMMON_TABLE_HEADER sHeader; 4515 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4516 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4517 4518 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4519 { 4520 UCHAR ucProfileId; 4521 UCHAR ucReserved; 4522 USHORT usSize; 4523 USHORT usEfuseSpareStartAddr; 4524 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4525 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4526 }ATOM_ASIC_PROFILE_VOLTAGE; 4527 4528 //ucProfileId 4529 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4530 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4531 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4532 4533 typedef struct _ATOM_ASIC_PROFILING_INFO 4534 { 4535 ATOM_COMMON_TABLE_HEADER asHeader; 4536 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4537 }ATOM_ASIC_PROFILING_INFO; 4538 4539 typedef struct _ATOM_POWER_SOURCE_OBJECT 4540 { 4541 UCHAR ucPwrSrcId; // Power source 4542 UCHAR ucPwrSensorType; // GPIO, I2C or none 4543 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4544 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4545 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4546 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4547 UCHAR ucPwrSensActiveState; // high active or low active 4548 UCHAR ucReserve[3]; // reserve 4549 USHORT usSensPwr; // in unit of watt 4550 }ATOM_POWER_SOURCE_OBJECT; 4551 4552 typedef struct _ATOM_POWER_SOURCE_INFO 4553 { 4554 ATOM_COMMON_TABLE_HEADER asHeader; 4555 UCHAR asPwrbehave[16]; 4556 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4557 }ATOM_POWER_SOURCE_INFO; 4558 4559 4560 //Define ucPwrSrcId 4561 #define POWERSOURCE_PCIE_ID1 0x00 4562 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4563 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4564 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4565 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4566 4567 //define ucPwrSensorId 4568 #define POWER_SENSOR_ALWAYS 0x00 4569 #define POWER_SENSOR_GPIO 0x01 4570 #define POWER_SENSOR_I2C 0x02 4571 4572 typedef struct _ATOM_CLK_VOLT_CAPABILITY 4573 { 4574 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4575 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4576 }ATOM_CLK_VOLT_CAPABILITY; 4577 4578 typedef struct _ATOM_AVAILABLE_SCLK_LIST 4579 { 4580 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4581 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4582 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4583 }ATOM_AVAILABLE_SCLK_LIST; 4584 4585 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4586 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4587 4588 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 4589 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4590 { 4591 ATOM_COMMON_TABLE_HEADER sHeader; 4592 ULONG ulBootUpEngineClock; 4593 ULONG ulDentistVCOFreq; 4594 ULONG ulBootUpUMAClock; 4595 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4596 ULONG ulBootUpReqDisplayVector; 4597 ULONG ulOtherDisplayMisc; 4598 ULONG ulGPUCapInfo; 4599 ULONG ulSB_MMIO_Base_Addr; 4600 USHORT usRequestedPWMFreqInHz; 4601 UCHAR ucHtcTmpLmt; 4602 UCHAR ucHtcHystLmt; 4603 ULONG ulMinEngineClock; 4604 ULONG ulSystemConfig; 4605 ULONG ulCPUCapInfo; 4606 USHORT usNBP0Voltage; 4607 USHORT usNBP1Voltage; 4608 USHORT usBootUpNBVoltage; 4609 USHORT usExtDispConnInfoOffset; 4610 USHORT usPanelRefreshRateRange; 4611 UCHAR ucMemoryType; 4612 UCHAR ucUMAChannelNumber; 4613 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4614 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4615 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4616 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4617 ULONG ulGMCRestoreResetTime; 4618 ULONG ulMinimumNClk; 4619 ULONG ulIdleNClk; 4620 ULONG ulDDR_DLL_PowerUpTime; 4621 ULONG ulDDR_PLL_PowerUpTime; 4622 USHORT usPCIEClkSSPercentage; 4623 USHORT usPCIEClkSSType; 4624 USHORT usLvdsSSPercentage; 4625 USHORT usLvdsSSpreadRateIn10Hz; 4626 USHORT usHDMISSPercentage; 4627 USHORT usHDMISSpreadRateIn10Hz; 4628 USHORT usDVISSPercentage; 4629 USHORT usDVISSpreadRateIn10Hz; 4630 ULONG SclkDpmBoostMargin; 4631 ULONG SclkDpmThrottleMargin; 4632 USHORT SclkDpmTdpLimitPG; 4633 USHORT SclkDpmTdpLimitBoost; 4634 ULONG ulBoostEngineCLock; 4635 UCHAR ulBoostVid_2bit; 4636 UCHAR EnableBoost; 4637 USHORT GnbTdpLimit; 4638 USHORT usMaxLVDSPclkFreqInSingleLink; 4639 UCHAR ucLvdsMisc; 4640 UCHAR ucLVDSReserved; 4641 ULONG ulReserved3[15]; 4642 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4643 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 4644 4645 // ulGPUCapInfo 4646 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4647 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4648 4649 //ucLVDSMisc: 4650 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4651 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4652 #define SYS_INFO_LVDSMISC__888_BPC 0x04 4653 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4654 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4655 4656 // not used any more 4657 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4658 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4659 4660 /********************************************************************************************************************** 4661 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4662 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4663 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4664 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4665 sDISPCLK_Voltage: Report Display clock voltage requirement. 4666 4667 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4668 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4669 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4670 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4671 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4672 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4673 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4674 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4675 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4676 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4677 ulOtherDisplayMisc: Other display related flags, not defined yet. 4678 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4679 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4680 bit[3]=0: Enable HW AUX mode detection logic 4681 =1: Disable HW AUX mode dettion logic 4682 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4683 4684 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4685 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4686 4687 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4688 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4689 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4690 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4691 and enabling VariBri under the driver environment from PP table is optional. 4692 4693 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4694 that BL control from GPU is expected. 4695 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4696 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4697 it's per platform 4698 and enabling VariBri under the driver environment from PP table is optional. 4699 4700 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4701 Threshold on value to enter HTC_active state. 4702 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4703 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4704 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4705 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4706 =1: PCIE Power Gating Enabled 4707 Bit[1]=0: DDR-DLL shut-down feature disabled. 4708 1: DDR-DLL shut-down feature enabled. 4709 Bit[2]=0: DDR-PLL Power down feature disabled. 4710 1: DDR-PLL Power down feature enabled. 4711 ulCPUCapInfo: TBD 4712 usNBP0Voltage: VID for voltage on NB P0 State 4713 usNBP1Voltage: VID for voltage on NB P1 State 4714 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4715 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4716 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4717 to indicate a range. 4718 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4719 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4720 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4721 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4722 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4723 ucUMAChannelNumber: System memory channel numbers. 4724 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4725 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4726 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4727 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4728 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4729 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4730 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4731 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4732 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4733 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4734 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4735 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4736 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4737 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4738 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4739 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4740 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4741 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4742 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4743 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4744 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4745 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4746 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4747 **********************************************************************************************************************/ 4748 4749 // this Table is used for Liano/Ontario APU 4750 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4751 { 4752 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4753 ULONG ulPowerplayTable[128]; 4754 }ATOM_FUSION_SYSTEM_INFO_V1; 4755 /********************************************************************************************************************** 4756 ATOM_FUSION_SYSTEM_INFO_V1 Description 4757 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4758 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4759 **********************************************************************************************************************/ 4760 4761 // this IntegrateSystemInfoTable is used for Trinity APU 4762 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4763 { 4764 ATOM_COMMON_TABLE_HEADER sHeader; 4765 ULONG ulBootUpEngineClock; 4766 ULONG ulDentistVCOFreq; 4767 ULONG ulBootUpUMAClock; 4768 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4769 ULONG ulBootUpReqDisplayVector; 4770 ULONG ulOtherDisplayMisc; 4771 ULONG ulGPUCapInfo; 4772 ULONG ulSB_MMIO_Base_Addr; 4773 USHORT usRequestedPWMFreqInHz; 4774 UCHAR ucHtcTmpLmt; 4775 UCHAR ucHtcHystLmt; 4776 ULONG ulMinEngineClock; 4777 ULONG ulSystemConfig; 4778 ULONG ulCPUCapInfo; 4779 USHORT usNBP0Voltage; 4780 USHORT usNBP1Voltage; 4781 USHORT usBootUpNBVoltage; 4782 USHORT usExtDispConnInfoOffset; 4783 USHORT usPanelRefreshRateRange; 4784 UCHAR ucMemoryType; 4785 UCHAR ucUMAChannelNumber; 4786 UCHAR strVBIOSMsg[40]; 4787 ULONG ulReserved[20]; 4788 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4789 ULONG ulGMCRestoreResetTime; 4790 ULONG ulMinimumNClk; 4791 ULONG ulIdleNClk; 4792 ULONG ulDDR_DLL_PowerUpTime; 4793 ULONG ulDDR_PLL_PowerUpTime; 4794 USHORT usPCIEClkSSPercentage; 4795 USHORT usPCIEClkSSType; 4796 USHORT usLvdsSSPercentage; 4797 USHORT usLvdsSSpreadRateIn10Hz; 4798 USHORT usHDMISSPercentage; 4799 USHORT usHDMISSpreadRateIn10Hz; 4800 USHORT usDVISSPercentage; 4801 USHORT usDVISSpreadRateIn10Hz; 4802 ULONG SclkDpmBoostMargin; 4803 ULONG SclkDpmThrottleMargin; 4804 USHORT SclkDpmTdpLimitPG; 4805 USHORT SclkDpmTdpLimitBoost; 4806 ULONG ulBoostEngineCLock; 4807 UCHAR ulBoostVid_2bit; 4808 UCHAR EnableBoost; 4809 USHORT GnbTdpLimit; 4810 USHORT usMaxLVDSPclkFreqInSingleLink; 4811 UCHAR ucLvdsMisc; 4812 UCHAR ucLVDSReserved; 4813 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 4814 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 4815 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 4816 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 4817 UCHAR ucLVDSOffToOnDelay_in4Ms; 4818 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 4819 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 4820 UCHAR ucLVDSReserved1; 4821 ULONG ulLCDBitDepthControlVal; 4822 ULONG ulNbpStateMemclkFreq[4]; 4823 USHORT usNBP2Voltage; 4824 USHORT usNBP3Voltage; 4825 ULONG ulNbpStateNClkFreq[4]; 4826 UCHAR ucNBDPMEnable; 4827 UCHAR ucReserved[3]; 4828 UCHAR ucDPMState0VclkFid; 4829 UCHAR ucDPMState0DclkFid; 4830 UCHAR ucDPMState1VclkFid; 4831 UCHAR ucDPMState1DclkFid; 4832 UCHAR ucDPMState2VclkFid; 4833 UCHAR ucDPMState2DclkFid; 4834 UCHAR ucDPMState3VclkFid; 4835 UCHAR ucDPMState3DclkFid; 4836 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4837 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 4838 4839 // ulOtherDisplayMisc 4840 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 4841 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 4842 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 4843 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 4844 4845 // ulGPUCapInfo 4846 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4847 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 4848 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 4849 4850 /********************************************************************************************************************** 4851 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 4852 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4853 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4854 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4855 sDISPCLK_Voltage: Report Display clock voltage requirement. 4856 4857 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 4858 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4859 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4860 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4861 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4862 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4863 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4864 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4865 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4866 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 4867 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 4868 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 4869 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 4870 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 4871 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 4872 bit[3]=0: VBIOS fast boot is disable 4873 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 4874 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4875 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4876 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 4877 =1: DP mode use single PLL mode 4878 bit[3]=0: Enable AUX HW mode detection logic 4879 =1: Disable AUX HW mode detection logic 4880 4881 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4882 4883 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4884 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4885 4886 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4887 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4888 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4889 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4890 and enabling VariBri under the driver environment from PP table is optional. 4891 4892 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4893 that BL control from GPU is expected. 4894 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4895 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4896 it's per platform 4897 and enabling VariBri under the driver environment from PP table is optional. 4898 4899 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4900 Threshold on value to enter HTC_active state. 4901 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4902 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4903 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4904 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4905 =1: PCIE Power Gating Enabled 4906 Bit[1]=0: DDR-DLL shut-down feature disabled. 4907 1: DDR-DLL shut-down feature enabled. 4908 Bit[2]=0: DDR-PLL Power down feature disabled. 4909 1: DDR-PLL Power down feature enabled. 4910 ulCPUCapInfo: TBD 4911 usNBP0Voltage: VID for voltage on NB P0 State 4912 usNBP1Voltage: VID for voltage on NB P1 State 4913 usNBP2Voltage: VID for voltage on NB P2 State 4914 usNBP3Voltage: VID for voltage on NB P3 State 4915 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4916 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4917 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4918 to indicate a range. 4919 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4920 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4921 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4922 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4923 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4924 ucUMAChannelNumber: System memory channel numbers. 4925 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4926 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4927 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4928 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4929 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4930 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4931 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4932 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4933 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4934 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 4935 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4936 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4937 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4938 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4939 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4940 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4941 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4942 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4943 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4944 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4945 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4946 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4947 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4948 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 4949 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4950 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4951 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 4952 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4953 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4954 4955 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 4956 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4957 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4958 4959 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 4960 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4961 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4962 4963 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 4964 =0 means to use VBIOS default delay which is 125 ( 500ms ). 4965 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4966 4967 ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 4968 =0 means to use VBIOS default delay which is 0 ( 0ms ). 4969 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4970 4971 ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 4972 =0 means to use VBIOS default delay which is 0 ( 0ms ). 4973 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4974 4975 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 4976 4977 **********************************************************************************************************************/ 4978 4979 /**************************************************************************/ 4980 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 4981 //Memory SS Info Table 4982 //Define Memory Clock SS chip ID 4983 #define ICS91719 1 4984 #define ICS91720 2 4985 4986 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 4987 typedef struct _ATOM_I2C_DATA_RECORD 4988 { 4989 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 4990 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 4991 }ATOM_I2C_DATA_RECORD; 4992 4993 4994 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 4995 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 4996 { 4997 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 4998 UCHAR ucSSChipID; //SS chip being used 4999 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5000 UCHAR ucNumOfI2CDataRecords; //number of data block 5001 ATOM_I2C_DATA_RECORD asI2CData[1]; 5002 }ATOM_I2C_DEVICE_SETUP_INFO; 5003 5004 //========================================================================================== 5005 typedef struct _ATOM_ASIC_MVDD_INFO 5006 { 5007 ATOM_COMMON_TABLE_HEADER sHeader; 5008 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5009 }ATOM_ASIC_MVDD_INFO; 5010 5011 //========================================================================================== 5012 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5013 5014 //========================================================================================== 5015 /**************************************************************************/ 5016 5017 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5018 { 5019 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5020 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5021 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5022 UCHAR ucClockIndication; //Indicate which clock source needs SS 5023 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5024 UCHAR ucReserved[2]; 5025 }ATOM_ASIC_SS_ASSIGNMENT; 5026 5027 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5028 //SS is not required or enabled if a match is not found. 5029 #define ASIC_INTERNAL_MEMORY_SS 1 5030 #define ASIC_INTERNAL_ENGINE_SS 2 5031 #define ASIC_INTERNAL_UVD_SS 3 5032 #define ASIC_INTERNAL_SS_ON_TMDS 4 5033 #define ASIC_INTERNAL_SS_ON_HDMI 5 5034 #define ASIC_INTERNAL_SS_ON_LVDS 6 5035 #define ASIC_INTERNAL_SS_ON_DP 7 5036 #define ASIC_INTERNAL_SS_ON_DCPLL 8 5037 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5038 #define ASIC_INTERNAL_VCE_SS 10 5039 5040 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5041 { 5042 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5043 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5044 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5045 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5046 UCHAR ucClockIndication; //Indicate which clock source needs SS 5047 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5048 UCHAR ucReserved[2]; 5049 }ATOM_ASIC_SS_ASSIGNMENT_V2; 5050 5051 //ucSpreadSpectrumMode 5052 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5053 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5054 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5055 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5056 //#define ATOM_INTERNAL_SS_MASK 0x00000000 5057 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 5058 5059 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5060 { 5061 ATOM_COMMON_TABLE_HEADER sHeader; 5062 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5063 }ATOM_ASIC_INTERNAL_SS_INFO; 5064 5065 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5066 { 5067 ATOM_COMMON_TABLE_HEADER sHeader; 5068 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5069 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 5070 5071 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5072 { 5073 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5074 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5075 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5076 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5077 UCHAR ucClockIndication; //Indicate which clock source needs SS 5078 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5079 UCHAR ucReserved[2]; 5080 }ATOM_ASIC_SS_ASSIGNMENT_V3; 5081 5082 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5083 { 5084 ATOM_COMMON_TABLE_HEADER sHeader; 5085 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5086 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 5087 5088 5089 //==============================Scratch Pad Definition Portion=============================== 5090 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 5091 #define ATOM_ROM_LOCATION_DEF 1 5092 #define ATOM_TV_STANDARD_DEF 2 5093 #define ATOM_ACTIVE_INFO_DEF 3 5094 #define ATOM_LCD_INFO_DEF 4 5095 #define ATOM_DOS_REQ_INFO_DEF 5 5096 #define ATOM_ACC_CHANGE_INFO_DEF 6 5097 #define ATOM_DOS_MODE_INFO_DEF 7 5098 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 5099 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5100 #define ATOM_INTERNAL_TIMER_DEF 10 5101 5102 // BIOS_0_SCRATCH Definition 5103 #define ATOM_S0_CRT1_MONO 0x00000001L 5104 #define ATOM_S0_CRT1_COLOR 0x00000002L 5105 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5106 5107 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5108 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5109 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5110 5111 #define ATOM_S0_CV_A 0x00000010L 5112 #define ATOM_S0_CV_DIN_A 0x00000020L 5113 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5114 5115 5116 #define ATOM_S0_CRT2_MONO 0x00000100L 5117 #define ATOM_S0_CRT2_COLOR 0x00000200L 5118 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5119 5120 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 5121 #define ATOM_S0_TV1_SVIDEO 0x00000800L 5122 #define ATOM_S0_TV1_SCART 0x00004000L 5123 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5124 5125 #define ATOM_S0_CV 0x00001000L 5126 #define ATOM_S0_CV_DIN 0x00002000L 5127 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5128 5129 #define ATOM_S0_DFP1 0x00010000L 5130 #define ATOM_S0_DFP2 0x00020000L 5131 #define ATOM_S0_LCD1 0x00040000L 5132 #define ATOM_S0_LCD2 0x00080000L 5133 #define ATOM_S0_DFP6 0x00100000L 5134 #define ATOM_S0_DFP3 0x00200000L 5135 #define ATOM_S0_DFP4 0x00400000L 5136 #define ATOM_S0_DFP5 0x00800000L 5137 5138 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5139 5140 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5141 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5142 5143 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5144 #define ATOM_S0_THERMAL_STATE_SHIFT 26 5145 5146 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5147 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5148 5149 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5150 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5151 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5152 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5153 5154 //Byte aligned definition for BIOS usage 5155 #define ATOM_S0_CRT1_MONOb0 0x01 5156 #define ATOM_S0_CRT1_COLORb0 0x02 5157 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5158 5159 #define ATOM_S0_TV1_COMPOSITEb0 0x04 5160 #define ATOM_S0_TV1_SVIDEOb0 0x08 5161 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5162 5163 #define ATOM_S0_CVb0 0x10 5164 #define ATOM_S0_CV_DINb0 0x20 5165 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5166 5167 #define ATOM_S0_CRT2_MONOb1 0x01 5168 #define ATOM_S0_CRT2_COLORb1 0x02 5169 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5170 5171 #define ATOM_S0_TV1_COMPOSITEb1 0x04 5172 #define ATOM_S0_TV1_SVIDEOb1 0x08 5173 #define ATOM_S0_TV1_SCARTb1 0x40 5174 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5175 5176 #define ATOM_S0_CVb1 0x10 5177 #define ATOM_S0_CV_DINb1 0x20 5178 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5179 5180 #define ATOM_S0_DFP1b2 0x01 5181 #define ATOM_S0_DFP2b2 0x02 5182 #define ATOM_S0_LCD1b2 0x04 5183 #define ATOM_S0_LCD2b2 0x08 5184 #define ATOM_S0_DFP6b2 0x10 5185 #define ATOM_S0_DFP3b2 0x20 5186 #define ATOM_S0_DFP4b2 0x40 5187 #define ATOM_S0_DFP5b2 0x80 5188 5189 5190 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5191 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5192 5193 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5194 #define ATOM_S0_LCD1_SHIFT 18 5195 5196 // BIOS_1_SCRATCH Definition 5197 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5198 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5199 5200 // BIOS_2_SCRATCH Definition 5201 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5202 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5203 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5204 5205 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5206 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5207 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5208 5209 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5210 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5211 5212 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5213 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5214 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5215 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5216 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5217 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5218 5219 5220 //Byte aligned definition for BIOS usage 5221 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5222 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5223 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5224 5225 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5226 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5227 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5228 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5229 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5230 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5231 5232 5233 // BIOS_3_SCRATCH Definition 5234 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 5235 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 5236 #define ATOM_S3_TV1_ACTIVE 0x00000004L 5237 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 5238 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 5239 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 5240 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 5241 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 5242 #define ATOM_S3_CV_ACTIVE 0x00000100L 5243 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 5244 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 5245 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 5246 5247 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5248 5249 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5250 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5251 5252 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5253 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5254 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5255 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5256 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5257 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5258 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5259 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5260 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5261 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5262 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5263 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5264 5265 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5266 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5267 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 5268 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5269 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5270 5271 //Byte aligned definition for BIOS usage 5272 #define ATOM_S3_CRT1_ACTIVEb0 0x01 5273 #define ATOM_S3_LCD1_ACTIVEb0 0x02 5274 #define ATOM_S3_TV1_ACTIVEb0 0x04 5275 #define ATOM_S3_DFP1_ACTIVEb0 0x08 5276 #define ATOM_S3_CRT2_ACTIVEb0 0x10 5277 #define ATOM_S3_LCD2_ACTIVEb0 0x20 5278 #define ATOM_S3_DFP6_ACTIVEb0 0x40 5279 #define ATOM_S3_DFP2_ACTIVEb0 0x80 5280 #define ATOM_S3_CV_ACTIVEb1 0x01 5281 #define ATOM_S3_DFP3_ACTIVEb1 0x02 5282 #define ATOM_S3_DFP4_ACTIVEb1 0x04 5283 #define ATOM_S3_DFP5_ACTIVEb1 0x08 5284 5285 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5286 5287 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5288 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5289 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5290 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5291 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5292 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5293 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5294 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5295 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5296 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5297 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5298 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5299 5300 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5301 5302 // BIOS_4_SCRATCH Definition 5303 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5304 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5305 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 5306 5307 //Byte aligned definition for BIOS usage 5308 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5309 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5310 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5311 5312 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5313 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 5314 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 5315 #define ATOM_S5_DOS_REQ_TV1b0 0x04 5316 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 5317 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 5318 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 5319 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 5320 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 5321 #define ATOM_S5_DOS_REQ_CVb1 0x01 5322 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 5323 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 5324 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 5325 5326 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5327 5328 #define ATOM_S5_DOS_REQ_CRT1 0x0001 5329 #define ATOM_S5_DOS_REQ_LCD1 0x0002 5330 #define ATOM_S5_DOS_REQ_TV1 0x0004 5331 #define ATOM_S5_DOS_REQ_DFP1 0x0008 5332 #define ATOM_S5_DOS_REQ_CRT2 0x0010 5333 #define ATOM_S5_DOS_REQ_LCD2 0x0020 5334 #define ATOM_S5_DOS_REQ_DFP6 0x0040 5335 #define ATOM_S5_DOS_REQ_DFP2 0x0080 5336 #define ATOM_S5_DOS_REQ_CV 0x0100 5337 #define ATOM_S5_DOS_REQ_DFP3 0x0200 5338 #define ATOM_S5_DOS_REQ_DFP4 0x0400 5339 #define ATOM_S5_DOS_REQ_DFP5 0x0800 5340 5341 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5342 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5343 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5344 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5345 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5346 (ATOM_S5_DOS_FORCE_CVb3<<8)) 5347 5348 // BIOS_6_SCRATCH Definition 5349 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 5350 #define ATOM_S6_SCALER_CHANGE 0x00000002L 5351 #define ATOM_S6_LID_CHANGE 0x00000004L 5352 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 5353 #define ATOM_S6_ACC_MODE 0x00000010L 5354 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5355 #define ATOM_S6_LID_STATE 0x00000040L 5356 #define ATOM_S6_DOCK_STATE 0x00000080L 5357 #define ATOM_S6_CRITICAL_STATE 0x00000100L 5358 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5359 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5360 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5361 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5362 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5363 5364 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5365 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5366 5367 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5368 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5369 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 5370 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5371 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5372 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5373 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5374 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5375 #define ATOM_S6_ACC_REQ_CV 0x01000000L 5376 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5377 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5378 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5379 5380 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5381 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5382 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5383 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5384 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5385 5386 //Byte aligned definition for BIOS usage 5387 #define ATOM_S6_DEVICE_CHANGEb0 0x01 5388 #define ATOM_S6_SCALER_CHANGEb0 0x02 5389 #define ATOM_S6_LID_CHANGEb0 0x04 5390 #define ATOM_S6_DOCKING_CHANGEb0 0x08 5391 #define ATOM_S6_ACC_MODEb0 0x10 5392 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5393 #define ATOM_S6_LID_STATEb0 0x40 5394 #define ATOM_S6_DOCK_STATEb0 0x80 5395 #define ATOM_S6_CRITICAL_STATEb1 0x01 5396 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5397 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5398 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5399 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5400 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5401 5402 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 5403 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 5404 #define ATOM_S6_ACC_REQ_TV1b2 0x04 5405 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 5406 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 5407 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 5408 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 5409 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 5410 #define ATOM_S6_ACC_REQ_CVb3 0x01 5411 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 5412 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 5413 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 5414 5415 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5416 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5417 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5418 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5419 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5420 5421 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5422 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 5423 #define ATOM_S6_LID_CHANGE_SHIFT 2 5424 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5425 #define ATOM_S6_ACC_MODE_SHIFT 4 5426 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5427 #define ATOM_S6_LID_STATE_SHIFT 6 5428 #define ATOM_S6_DOCK_STATE_SHIFT 7 5429 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 5430 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5431 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5432 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5433 #define ATOM_S6_REQ_SCALER_SHIFT 12 5434 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5435 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5436 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5437 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5438 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5439 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5440 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5441 5442 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5443 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 5444 #define ATOM_S7_DOS_MODE_VGAb0 0x00 5445 #define ATOM_S7_DOS_MODE_VESAb0 0x01 5446 #define ATOM_S7_DOS_MODE_EXTb0 0x02 5447 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5448 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5449 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5450 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5451 5452 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5453 5454 // BIOS_8_SCRATCH Definition 5455 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5456 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5457 5458 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5459 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5460 5461 // BIOS_9_SCRATCH Definition 5462 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5463 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5464 #endif 5465 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5466 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5467 #endif 5468 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5469 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5470 #endif 5471 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5472 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5473 #endif 5474 5475 5476 #define ATOM_FLAG_SET 0x20 5477 #define ATOM_FLAG_CLEAR 0 5478 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5479 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5480 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5481 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5482 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5483 5484 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5485 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5486 5487 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5488 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5489 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5490 5491 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5492 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5493 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5494 5495 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5496 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5497 5498 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5499 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5500 5501 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5502 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5503 5504 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5505 5506 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5507 5508 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5509 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5510 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5511 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5512 5513 /****************************************************************************/ 5514 //Portion II: Definitinos only used in Driver 5515 /****************************************************************************/ 5516 5517 // Macros used by driver 5518 #ifdef __cplusplus 5519 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5520 5521 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5522 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5523 #else // not __cplusplus 5524 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 5525 5526 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5527 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5528 #endif // __cplusplus 5529 5530 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5531 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5532 5533 /****************************************************************************/ 5534 //Portion III: Definitinos only used in VBIOS 5535 /****************************************************************************/ 5536 #define ATOM_DAC_SRC 0x80 5537 #define ATOM_SRC_DAC1 0 5538 #define ATOM_SRC_DAC2 0x80 5539 5540 typedef struct _MEMORY_PLLINIT_PARAMETERS 5541 { 5542 ULONG ulTargetMemoryClock; //In 10Khz unit 5543 UCHAR ucAction; //not define yet 5544 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 5545 UCHAR ucFbDiv; //FB value 5546 UCHAR ucPostDiv; //Post div 5547 }MEMORY_PLLINIT_PARAMETERS; 5548 5549 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 5550 5551 5552 #define GPIO_PIN_WRITE 0x01 5553 #define GPIO_PIN_READ 0x00 5554 5555 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 5556 { 5557 UCHAR ucGPIO_ID; //return value, read from GPIO pins 5558 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 5559 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 5560 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 5561 }GPIO_PIN_CONTROL_PARAMETERS; 5562 5563 typedef struct _ENABLE_SCALER_PARAMETERS 5564 { 5565 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 5566 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 5567 UCHAR ucTVStandard; // 5568 UCHAR ucPadding[1]; 5569 }ENABLE_SCALER_PARAMETERS; 5570 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 5571 5572 //ucEnable: 5573 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 5574 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 5575 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 5576 #define SCALER_ENABLE_MULTITAP_MODE 3 5577 5578 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 5579 { 5580 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 5581 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 5582 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 5583 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 5584 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5585 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 5586 5587 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 5588 { 5589 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 5590 ENABLE_CRTC_PARAMETERS sReserved; 5591 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 5592 5593 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 5594 { 5595 USHORT usHight; // Image Hight 5596 USHORT usWidth; // Image Width 5597 UCHAR ucSurface; // Surface 1 or 2 5598 UCHAR ucPadding[3]; 5599 }ENABLE_GRAPH_SURFACE_PARAMETERS; 5600 5601 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 5602 { 5603 USHORT usHight; // Image Hight 5604 USHORT usWidth; // Image Width 5605 UCHAR ucSurface; // Surface 1 or 2 5606 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5607 UCHAR ucPadding[2]; 5608 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 5609 5610 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 5611 { 5612 USHORT usHight; // Image Hight 5613 USHORT usWidth; // Image Width 5614 UCHAR ucSurface; // Surface 1 or 2 5615 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5616 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 5617 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 5618 5619 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 5620 { 5621 USHORT usHight; // Image Hight 5622 USHORT usWidth; // Image Width 5623 USHORT usGraphPitch; 5624 UCHAR ucColorDepth; 5625 UCHAR ucPixelFormat; 5626 UCHAR ucSurface; // Surface 1 or 2 5627 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5628 UCHAR ucModeType; 5629 UCHAR ucReserved; 5630 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 5631 5632 // ucEnable 5633 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 5634 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 5635 5636 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 5637 { 5638 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 5639 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 5640 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 5641 5642 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 5643 { 5644 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 5645 USHORT usMemorySize; //8Kb blocks aligned 5646 }MEMORY_CLEAN_UP_PARAMETERS; 5647 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 5648 5649 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 5650 { 5651 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5652 USHORT usY_Size; 5653 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 5654 5655 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 5656 { 5657 union{ 5658 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5659 USHORT usSurface; 5660 }; 5661 USHORT usY_Size; 5662 USHORT usDispXStart; 5663 USHORT usDispYStart; 5664 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 5665 5666 5667 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 5668 { 5669 UCHAR ucLutId; 5670 UCHAR ucAction; 5671 USHORT usLutStartIndex; 5672 USHORT usLutLength; 5673 USHORT usLutOffsetInVram; 5674 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 5675 5676 // ucAction: 5677 #define PALETTE_DATA_AUTO_FILL 1 5678 #define PALETTE_DATA_READ 2 5679 #define PALETTE_DATA_WRITE 3 5680 5681 5682 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 5683 { 5684 UCHAR ucInterruptId; 5685 UCHAR ucServiceId; 5686 UCHAR ucStatus; 5687 UCHAR ucReserved; 5688 }INTERRUPT_SERVICE_PARAMETER_V2; 5689 5690 // ucInterruptId 5691 #define HDP1_INTERRUPT_ID 1 5692 #define HDP2_INTERRUPT_ID 2 5693 #define HDP3_INTERRUPT_ID 3 5694 #define HDP4_INTERRUPT_ID 4 5695 #define HDP5_INTERRUPT_ID 5 5696 #define HDP6_INTERRUPT_ID 6 5697 #define SW_INTERRUPT_ID 11 5698 5699 // ucAction 5700 #define INTERRUPT_SERVICE_GEN_SW_INT 1 5701 #define INTERRUPT_SERVICE_GET_STATUS 2 5702 5703 // ucStatus 5704 #define INTERRUPT_STATUS__INT_TRIGGER 1 5705 #define INTERRUPT_STATUS__HPD_HIGH 2 5706 5707 typedef struct _INDIRECT_IO_ACCESS 5708 { 5709 ATOM_COMMON_TABLE_HEADER sHeader; 5710 UCHAR IOAccessSequence[256]; 5711 } INDIRECT_IO_ACCESS; 5712 5713 #define INDIRECT_READ 0x00 5714 #define INDIRECT_WRITE 0x80 5715 5716 #define INDIRECT_IO_MM 0 5717 #define INDIRECT_IO_PLL 1 5718 #define INDIRECT_IO_MC 2 5719 #define INDIRECT_IO_PCIE 3 5720 #define INDIRECT_IO_PCIEP 4 5721 #define INDIRECT_IO_NBMISC 5 5722 5723 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 5724 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 5725 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 5726 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 5727 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 5728 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 5729 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 5730 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 5731 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 5732 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 5733 5734 typedef struct _ATOM_OEM_INFO 5735 { 5736 ATOM_COMMON_TABLE_HEADER sHeader; 5737 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 5738 }ATOM_OEM_INFO; 5739 5740 typedef struct _ATOM_TV_MODE 5741 { 5742 UCHAR ucVMode_Num; //Video mode number 5743 UCHAR ucTV_Mode_Num; //Internal TV mode number 5744 }ATOM_TV_MODE; 5745 5746 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 5747 { 5748 ATOM_COMMON_TABLE_HEADER sHeader; 5749 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 5750 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 5751 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 5752 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5753 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5754 }ATOM_BIOS_INT_TVSTD_MODE; 5755 5756 5757 typedef struct _ATOM_TV_MODE_SCALER_PTR 5758 { 5759 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 5760 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 5761 UCHAR ucTV_Mode_Num; 5762 }ATOM_TV_MODE_SCALER_PTR; 5763 5764 typedef struct _ATOM_STANDARD_VESA_TIMING 5765 { 5766 ATOM_COMMON_TABLE_HEADER sHeader; 5767 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 5768 }ATOM_STANDARD_VESA_TIMING; 5769 5770 5771 typedef struct _ATOM_STD_FORMAT 5772 { 5773 USHORT usSTD_HDisp; 5774 USHORT usSTD_VDisp; 5775 USHORT usSTD_RefreshRate; 5776 USHORT usReserved; 5777 }ATOM_STD_FORMAT; 5778 5779 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 5780 { 5781 USHORT usVESA_ModeNumber; 5782 USHORT usExtendedModeNumber; 5783 }ATOM_VESA_TO_EXTENDED_MODE; 5784 5785 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 5786 { 5787 ATOM_COMMON_TABLE_HEADER sHeader; 5788 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 5789 }ATOM_VESA_TO_INTENAL_MODE_LUT; 5790 5791 /*************** ATOM Memory Related Data Structure ***********************/ 5792 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 5793 UCHAR ucMemoryType; 5794 UCHAR ucMemoryVendor; 5795 UCHAR ucAdjMCId; 5796 UCHAR ucDynClkId; 5797 ULONG ulDllResetClkRange; 5798 }ATOM_MEMORY_VENDOR_BLOCK; 5799 5800 5801 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 5802 #if ATOM_BIG_ENDIAN 5803 ULONG ucMemBlkId:8; 5804 ULONG ulMemClockRange:24; 5805 #else 5806 ULONG ulMemClockRange:24; 5807 ULONG ucMemBlkId:8; 5808 #endif 5809 }ATOM_MEMORY_SETTING_ID_CONFIG; 5810 5811 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 5812 { 5813 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 5814 ULONG ulAccess; 5815 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 5816 5817 5818 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 5819 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 5820 ULONG aulMemData[1]; 5821 }ATOM_MEMORY_SETTING_DATA_BLOCK; 5822 5823 5824 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 5825 USHORT usRegIndex; // MC register index 5826 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 5827 }ATOM_INIT_REG_INDEX_FORMAT; 5828 5829 5830 typedef struct _ATOM_INIT_REG_BLOCK{ 5831 USHORT usRegIndexTblSize; //size of asRegIndexBuf 5832 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 5833 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 5834 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 5835 }ATOM_INIT_REG_BLOCK; 5836 5837 #define END_OF_REG_INDEX_BLOCK 0x0ffff 5838 #define END_OF_REG_DATA_BLOCK 0x00000000 5839 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 5840 #define CLOCK_RANGE_HIGHEST 0x00ffffff 5841 5842 #define VALUE_DWORD SIZEOF ULONG 5843 #define VALUE_SAME_AS_ABOVE 0 5844 #define VALUE_MASK_DWORD 0x84 5845 5846 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 5847 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 5848 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 5849 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 5850 #define ACCESS_PLACEHOLDER 0x80 5851 5852 typedef struct _ATOM_MC_INIT_PARAM_TABLE 5853 { 5854 ATOM_COMMON_TABLE_HEADER sHeader; 5855 USHORT usAdjustARB_SEQDataOffset; 5856 USHORT usMCInitMemTypeTblOffset; 5857 USHORT usMCInitCommonTblOffset; 5858 USHORT usMCInitPowerDownTblOffset; 5859 ULONG ulARB_SEQDataBuf[32]; 5860 ATOM_INIT_REG_BLOCK asMCInitMemType; 5861 ATOM_INIT_REG_BLOCK asMCInitCommon; 5862 }ATOM_MC_INIT_PARAM_TABLE; 5863 5864 5865 #define _4Mx16 0x2 5866 #define _4Mx32 0x3 5867 #define _8Mx16 0x12 5868 #define _8Mx32 0x13 5869 #define _16Mx16 0x22 5870 #define _16Mx32 0x23 5871 #define _32Mx16 0x32 5872 #define _32Mx32 0x33 5873 #define _64Mx8 0x41 5874 #define _64Mx16 0x42 5875 #define _64Mx32 0x43 5876 #define _128Mx8 0x51 5877 #define _128Mx16 0x52 5878 #define _256Mx8 0x61 5879 #define _256Mx16 0x62 5880 5881 #define SAMSUNG 0x1 5882 #define INFINEON 0x2 5883 #define ELPIDA 0x3 5884 #define ETRON 0x4 5885 #define NANYA 0x5 5886 #define HYNIX 0x6 5887 #define MOSEL 0x7 5888 #define WINBOND 0x8 5889 #define ESMT 0x9 5890 #define MICRON 0xF 5891 5892 #define QIMONDA INFINEON 5893 #define PROMOS MOSEL 5894 #define KRETON INFINEON 5895 #define ELIXIR NANYA 5896 5897 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 5898 5899 #define UCODE_ROM_START_ADDRESS 0x1b800 5900 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 5901 5902 //uCode block header for reference 5903 5904 typedef struct _MCuCodeHeader 5905 { 5906 ULONG ulSignature; 5907 UCHAR ucRevision; 5908 UCHAR ucChecksum; 5909 UCHAR ucReserved1; 5910 UCHAR ucReserved2; 5911 USHORT usParametersLength; 5912 USHORT usUCodeLength; 5913 USHORT usReserved1; 5914 USHORT usReserved2; 5915 } MCuCodeHeader; 5916 5917 ////////////////////////////////////////////////////////////////////////////////// 5918 5919 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 5920 5921 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 5922 typedef struct _ATOM_VRAM_MODULE_V1 5923 { 5924 ULONG ulReserved; 5925 USHORT usEMRSValue; 5926 USHORT usMRSValue; 5927 USHORT usReserved; 5928 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5929 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 5930 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 5931 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5932 UCHAR ucRow; // Number of Row,in power of 2; 5933 UCHAR ucColumn; // Number of Column,in power of 2; 5934 UCHAR ucBank; // Nunber of Bank; 5935 UCHAR ucRank; // Number of Rank, in power of 2 5936 UCHAR ucChannelNum; // Number of channel; 5937 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5938 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5939 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5940 UCHAR ucReserved[2]; 5941 }ATOM_VRAM_MODULE_V1; 5942 5943 5944 typedef struct _ATOM_VRAM_MODULE_V2 5945 { 5946 ULONG ulReserved; 5947 ULONG ulFlags; // To enable/disable functionalities based on memory type 5948 ULONG ulEngineClock; // Override of default engine clock for particular memory type 5949 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 5950 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5951 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5952 USHORT usEMRSValue; 5953 USHORT usMRSValue; 5954 USHORT usReserved; 5955 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5956 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 5957 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 5958 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5959 UCHAR ucRow; // Number of Row,in power of 2; 5960 UCHAR ucColumn; // Number of Column,in power of 2; 5961 UCHAR ucBank; // Nunber of Bank; 5962 UCHAR ucRank; // Number of Rank, in power of 2 5963 UCHAR ucChannelNum; // Number of channel; 5964 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5965 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5966 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5967 UCHAR ucRefreshRateFactor; 5968 UCHAR ucReserved[3]; 5969 }ATOM_VRAM_MODULE_V2; 5970 5971 5972 typedef struct _ATOM_MEMORY_TIMING_FORMAT 5973 { 5974 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5975 union{ 5976 USHORT usMRS; // mode register 5977 USHORT usDDR3_MR0; 5978 }; 5979 union{ 5980 USHORT usEMRS; // extended mode register 5981 USHORT usDDR3_MR1; 5982 }; 5983 UCHAR ucCL; // CAS latency 5984 UCHAR ucWL; // WRITE Latency 5985 UCHAR uctRAS; // tRAS 5986 UCHAR uctRC; // tRC 5987 UCHAR uctRFC; // tRFC 5988 UCHAR uctRCDR; // tRCDR 5989 UCHAR uctRCDW; // tRCDW 5990 UCHAR uctRP; // tRP 5991 UCHAR uctRRD; // tRRD 5992 UCHAR uctWR; // tWR 5993 UCHAR uctWTR; // tWTR 5994 UCHAR uctPDIX; // tPDIX 5995 UCHAR uctFAW; // tFAW 5996 UCHAR uctAOND; // tAOND 5997 union 5998 { 5999 struct { 6000 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6001 UCHAR ucReserved; 6002 }; 6003 USHORT usDDR3_MR2; 6004 }; 6005 }ATOM_MEMORY_TIMING_FORMAT; 6006 6007 6008 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6009 { 6010 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6011 USHORT usMRS; // mode register 6012 USHORT usEMRS; // extended mode register 6013 UCHAR ucCL; // CAS latency 6014 UCHAR ucWL; // WRITE Latency 6015 UCHAR uctRAS; // tRAS 6016 UCHAR uctRC; // tRC 6017 UCHAR uctRFC; // tRFC 6018 UCHAR uctRCDR; // tRCDR 6019 UCHAR uctRCDW; // tRCDW 6020 UCHAR uctRP; // tRP 6021 UCHAR uctRRD; // tRRD 6022 UCHAR uctWR; // tWR 6023 UCHAR uctWTR; // tWTR 6024 UCHAR uctPDIX; // tPDIX 6025 UCHAR uctFAW; // tFAW 6026 UCHAR uctAOND; // tAOND 6027 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6028 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6029 UCHAR uctCCDL; // 6030 UCHAR uctCRCRL; // 6031 UCHAR uctCRCWL; // 6032 UCHAR uctCKE; // 6033 UCHAR uctCKRSE; // 6034 UCHAR uctCKRSX; // 6035 UCHAR uctFAW32; // 6036 UCHAR ucMR5lo; // 6037 UCHAR ucMR5hi; // 6038 UCHAR ucTerminator; 6039 }ATOM_MEMORY_TIMING_FORMAT_V1; 6040 6041 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6042 { 6043 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6044 USHORT usMRS; // mode register 6045 USHORT usEMRS; // extended mode register 6046 UCHAR ucCL; // CAS latency 6047 UCHAR ucWL; // WRITE Latency 6048 UCHAR uctRAS; // tRAS 6049 UCHAR uctRC; // tRC 6050 UCHAR uctRFC; // tRFC 6051 UCHAR uctRCDR; // tRCDR 6052 UCHAR uctRCDW; // tRCDW 6053 UCHAR uctRP; // tRP 6054 UCHAR uctRRD; // tRRD 6055 UCHAR uctWR; // tWR 6056 UCHAR uctWTR; // tWTR 6057 UCHAR uctPDIX; // tPDIX 6058 UCHAR uctFAW; // tFAW 6059 UCHAR uctAOND; // tAOND 6060 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6061 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6062 UCHAR uctCCDL; // 6063 UCHAR uctCRCRL; // 6064 UCHAR uctCRCWL; // 6065 UCHAR uctCKE; // 6066 UCHAR uctCKRSE; // 6067 UCHAR uctCKRSX; // 6068 UCHAR uctFAW32; // 6069 UCHAR ucMR4lo; // 6070 UCHAR ucMR4hi; // 6071 UCHAR ucMR5lo; // 6072 UCHAR ucMR5hi; // 6073 UCHAR ucTerminator; 6074 UCHAR ucReserved; 6075 }ATOM_MEMORY_TIMING_FORMAT_V2; 6076 6077 typedef struct _ATOM_MEMORY_FORMAT 6078 { 6079 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6080 union{ 6081 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6082 USHORT usDDR3_Reserved; // Not used for DDR3 memory 6083 }; 6084 union{ 6085 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6086 USHORT usDDR3_MR3; // Used for DDR3 memory 6087 }; 6088 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6089 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6090 UCHAR ucRow; // Number of Row,in power of 2; 6091 UCHAR ucColumn; // Number of Column,in power of 2; 6092 UCHAR ucBank; // Nunber of Bank; 6093 UCHAR ucRank; // Number of Rank, in power of 2 6094 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6095 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6096 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6097 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6098 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6099 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6100 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6101 }ATOM_MEMORY_FORMAT; 6102 6103 6104 typedef struct _ATOM_VRAM_MODULE_V3 6105 { 6106 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6107 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6108 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6109 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6110 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6111 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6112 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6113 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6114 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6115 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6116 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6117 }ATOM_VRAM_MODULE_V3; 6118 6119 6120 //ATOM_VRAM_MODULE_V3.ucNPL_RT 6121 #define NPL_RT_MASK 0x0f 6122 #define BATTERY_ODT_MASK 0xc0 6123 6124 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6125 6126 typedef struct _ATOM_VRAM_MODULE_V4 6127 { 6128 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6129 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6130 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6131 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6132 USHORT usReserved; 6133 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6134 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6135 UCHAR ucChannelNum; // Number of channels present in this module config 6136 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6137 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6138 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6139 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6140 UCHAR ucVREFI; // board dependent parameter 6141 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6142 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6143 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6144 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6145 UCHAR ucReserved[3]; 6146 6147 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6148 union{ 6149 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6150 USHORT usDDR3_Reserved; 6151 }; 6152 union{ 6153 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6154 USHORT usDDR3_MR3; // Used for DDR3 memory 6155 }; 6156 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6157 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6158 UCHAR ucReserved2[2]; 6159 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6160 }ATOM_VRAM_MODULE_V4; 6161 6162 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6163 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6164 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6165 #define VRAM_MODULE_V4_MISC_BL8 0x4 6166 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6167 6168 typedef struct _ATOM_VRAM_MODULE_V5 6169 { 6170 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6171 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6172 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6173 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6174 USHORT usReserved; 6175 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6176 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6177 UCHAR ucChannelNum; // Number of channels present in this module config 6178 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6179 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6180 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6181 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6182 UCHAR ucVREFI; // board dependent parameter 6183 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6184 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6185 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6186 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6187 UCHAR ucReserved[3]; 6188 6189 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6190 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6191 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6192 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6193 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6194 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6195 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6196 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6197 }ATOM_VRAM_MODULE_V5; 6198 6199 typedef struct _ATOM_VRAM_MODULE_V6 6200 { 6201 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6202 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6203 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6204 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6205 USHORT usReserved; 6206 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6207 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6208 UCHAR ucChannelNum; // Number of channels present in this module config 6209 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6210 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6211 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6212 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6213 UCHAR ucVREFI; // board dependent parameter 6214 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6215 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6216 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6217 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6218 UCHAR ucReserved[3]; 6219 6220 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6221 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6222 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6223 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6224 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6225 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6226 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6227 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6228 }ATOM_VRAM_MODULE_V6; 6229 6230 typedef struct _ATOM_VRAM_MODULE_V7 6231 { 6232 // Design Specific Values 6233 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6234 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6235 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6236 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6237 UCHAR ucExtMemoryID; // Current memory module ID 6238 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6239 UCHAR ucChannelNum; // Number of mem. channels supported in this module 6240 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6241 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6242 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6243 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6244 UCHAR ucVREFI; // Not used. 6245 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6246 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6247 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6248 USHORT usSEQSettingOffset; 6249 UCHAR ucReserved; 6250 // Memory Module specific values 6251 USHORT usEMRS2Value; // EMRS2/MR2 Value. 6252 USHORT usEMRS3Value; // EMRS3/MR3 Value. 6253 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6254 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6255 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6256 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6257 char strMemPNString[20]; // part number end with '0'. 6258 }ATOM_VRAM_MODULE_V7; 6259 6260 typedef struct _ATOM_VRAM_INFO_V2 6261 { 6262 ATOM_COMMON_TABLE_HEADER sHeader; 6263 UCHAR ucNumOfVRAMModule; 6264 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6265 }ATOM_VRAM_INFO_V2; 6266 6267 typedef struct _ATOM_VRAM_INFO_V3 6268 { 6269 ATOM_COMMON_TABLE_HEADER sHeader; 6270 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6271 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6272 USHORT usRerseved; 6273 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6274 UCHAR ucNumOfVRAMModule; 6275 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6276 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6277 // ATOM_INIT_REG_BLOCK aMemAdjust; 6278 }ATOM_VRAM_INFO_V3; 6279 6280 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6281 6282 typedef struct _ATOM_VRAM_INFO_V4 6283 { 6284 ATOM_COMMON_TABLE_HEADER sHeader; 6285 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6286 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6287 USHORT usRerseved; 6288 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6289 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6290 UCHAR ucReservde[4]; 6291 UCHAR ucNumOfVRAMModule; 6292 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6293 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6294 // ATOM_INIT_REG_BLOCK aMemAdjust; 6295 }ATOM_VRAM_INFO_V4; 6296 6297 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6298 { 6299 ATOM_COMMON_TABLE_HEADER sHeader; 6300 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6301 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6302 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6303 USHORT usReserved[3]; 6304 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6305 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6306 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6307 UCHAR ucReserved; 6308 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6309 }ATOM_VRAM_INFO_HEADER_V2_1; 6310 6311 6312 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6313 { 6314 ATOM_COMMON_TABLE_HEADER sHeader; 6315 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6316 }ATOM_VRAM_GPIO_DETECTION_INFO; 6317 6318 6319 typedef struct _ATOM_MEMORY_TRAINING_INFO 6320 { 6321 ATOM_COMMON_TABLE_HEADER sHeader; 6322 UCHAR ucTrainingLoop; 6323 UCHAR ucReserved[3]; 6324 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6325 }ATOM_MEMORY_TRAINING_INFO; 6326 6327 6328 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 6329 { 6330 UCHAR ucControl; 6331 UCHAR ucData; 6332 UCHAR ucSatus; 6333 UCHAR ucTemp; 6334 } SW_I2C_CNTL_DATA_PARAMETERS; 6335 6336 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6337 6338 typedef struct _SW_I2C_IO_DATA_PARAMETERS 6339 { 6340 USHORT GPIO_Info; 6341 UCHAR ucAct; 6342 UCHAR ucData; 6343 } SW_I2C_IO_DATA_PARAMETERS; 6344 6345 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6346 6347 /****************************SW I2C CNTL DEFINITIONS**********************/ 6348 #define SW_I2C_IO_RESET 0 6349 #define SW_I2C_IO_GET 1 6350 #define SW_I2C_IO_DRIVE 2 6351 #define SW_I2C_IO_SET 3 6352 #define SW_I2C_IO_START 4 6353 6354 #define SW_I2C_IO_CLOCK 0 6355 #define SW_I2C_IO_DATA 0x80 6356 6357 #define SW_I2C_IO_ZERO 0 6358 #define SW_I2C_IO_ONE 0x100 6359 6360 #define SW_I2C_CNTL_READ 0 6361 #define SW_I2C_CNTL_WRITE 1 6362 #define SW_I2C_CNTL_START 2 6363 #define SW_I2C_CNTL_STOP 3 6364 #define SW_I2C_CNTL_OPEN 4 6365 #define SW_I2C_CNTL_CLOSE 5 6366 #define SW_I2C_CNTL_WRITE1BIT 6 6367 6368 //==============================VESA definition Portion=============================== 6369 #define VESA_OEM_PRODUCT_REV "01.00" 6370 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6371 #define VESA_MODE_WIN_ATTRIBUTE 7 6372 #define VESA_WIN_SIZE 64 6373 6374 typedef struct _PTR_32_BIT_STRUCTURE 6375 { 6376 USHORT Offset16; 6377 USHORT Segment16; 6378 } PTR_32_BIT_STRUCTURE; 6379 6380 typedef union _PTR_32_BIT_UNION 6381 { 6382 PTR_32_BIT_STRUCTURE SegmentOffset; 6383 ULONG Ptr32_Bit; 6384 } PTR_32_BIT_UNION; 6385 6386 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6387 { 6388 UCHAR VbeSignature[4]; 6389 USHORT VbeVersion; 6390 PTR_32_BIT_UNION OemStringPtr; 6391 UCHAR Capabilities[4]; 6392 PTR_32_BIT_UNION VideoModePtr; 6393 USHORT TotalMemory; 6394 } VBE_1_2_INFO_BLOCK_UPDATABLE; 6395 6396 6397 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6398 { 6399 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6400 USHORT OemSoftRev; 6401 PTR_32_BIT_UNION OemVendorNamePtr; 6402 PTR_32_BIT_UNION OemProductNamePtr; 6403 PTR_32_BIT_UNION OemProductRevPtr; 6404 } VBE_2_0_INFO_BLOCK_UPDATABLE; 6405 6406 typedef union _VBE_VERSION_UNION 6407 { 6408 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6409 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6410 } VBE_VERSION_UNION; 6411 6412 typedef struct _VBE_INFO_BLOCK 6413 { 6414 VBE_VERSION_UNION UpdatableVBE_Info; 6415 UCHAR Reserved[222]; 6416 UCHAR OemData[256]; 6417 } VBE_INFO_BLOCK; 6418 6419 typedef struct _VBE_FP_INFO 6420 { 6421 USHORT HSize; 6422 USHORT VSize; 6423 USHORT FPType; 6424 UCHAR RedBPP; 6425 UCHAR GreenBPP; 6426 UCHAR BlueBPP; 6427 UCHAR ReservedBPP; 6428 ULONG RsvdOffScrnMemSize; 6429 ULONG RsvdOffScrnMEmPtr; 6430 UCHAR Reserved[14]; 6431 } VBE_FP_INFO; 6432 6433 typedef struct _VESA_MODE_INFO_BLOCK 6434 { 6435 // Mandatory information for all VBE revisions 6436 USHORT ModeAttributes; // dw ? ; mode attributes 6437 UCHAR WinAAttributes; // db ? ; window A attributes 6438 UCHAR WinBAttributes; // db ? ; window B attributes 6439 USHORT WinGranularity; // dw ? ; window granularity 6440 USHORT WinSize; // dw ? ; window size 6441 USHORT WinASegment; // dw ? ; window A start segment 6442 USHORT WinBSegment; // dw ? ; window B start segment 6443 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6444 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6445 6446 //; Mandatory information for VBE 1.2 and above 6447 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6448 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6449 UCHAR XCharSize; // db ? ; character cell width in pixels 6450 UCHAR YCharSize; // db ? ; character cell height in pixels 6451 UCHAR NumberOfPlanes; // db ? ; number of memory planes 6452 UCHAR BitsPerPixel; // db ? ; bits per pixel 6453 UCHAR NumberOfBanks; // db ? ; number of banks 6454 UCHAR MemoryModel; // db ? ; memory model type 6455 UCHAR BankSize; // db ? ; bank size in KB 6456 UCHAR NumberOfImagePages;// db ? ; number of images 6457 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6458 6459 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 6460 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6461 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6462 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6463 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6464 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6465 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6466 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6467 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6468 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6469 6470 //; Mandatory information for VBE 2.0 and above 6471 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6472 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6473 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6474 6475 //; Mandatory information for VBE 3.0 and above 6476 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6477 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6478 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6479 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6480 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6481 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6482 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6483 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6484 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6485 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6486 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6487 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6488 UCHAR Reserved; // db 190 dup (0) 6489 } VESA_MODE_INFO_BLOCK; 6490 6491 // BIOS function CALLS 6492 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6493 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6494 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6495 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6496 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6497 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6498 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6499 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6500 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 6501 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6502 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6503 6504 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6505 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6506 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6507 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6508 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6509 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6510 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6511 6512 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6513 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6514 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6515 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6516 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6517 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6518 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6519 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6520 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6521 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6522 6523 6524 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6525 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6526 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6527 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6528 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 6529 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 6530 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 6531 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 6532 6533 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 6534 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 6535 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 6536 6537 // structure used for VBIOS only 6538 6539 //DispOutInfoTable 6540 typedef struct _ASIC_TRANSMITTER_INFO 6541 { 6542 USHORT usTransmitterObjId; 6543 USHORT usSupportDevice; 6544 UCHAR ucTransmitterCmdTblId; 6545 UCHAR ucConfig; 6546 UCHAR ucEncoderID; //available 1st encoder ( default ) 6547 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 6548 UCHAR uc2ndEncoderID; 6549 UCHAR ucReserved; 6550 }ASIC_TRANSMITTER_INFO; 6551 6552 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 6553 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 6554 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 6555 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 6556 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 6557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 6558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 6559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 6560 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 6561 6562 typedef struct _ASIC_ENCODER_INFO 6563 { 6564 UCHAR ucEncoderID; 6565 UCHAR ucEncoderConfig; 6566 USHORT usEncoderCmdTblId; 6567 }ASIC_ENCODER_INFO; 6568 6569 typedef struct _ATOM_DISP_OUT_INFO 6570 { 6571 ATOM_COMMON_TABLE_HEADER sHeader; 6572 USHORT ptrTransmitterInfo; 6573 USHORT ptrEncoderInfo; 6574 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6575 ASIC_ENCODER_INFO asEncoderInfo[1]; 6576 }ATOM_DISP_OUT_INFO; 6577 6578 typedef struct _ATOM_DISP_OUT_INFO_V2 6579 { 6580 ATOM_COMMON_TABLE_HEADER sHeader; 6581 USHORT ptrTransmitterInfo; 6582 USHORT ptrEncoderInfo; 6583 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6584 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6585 ASIC_ENCODER_INFO asEncoderInfo[1]; 6586 }ATOM_DISP_OUT_INFO_V2; 6587 6588 6589 typedef struct _ATOM_DISP_CLOCK_ID { 6590 UCHAR ucPpllId; 6591 UCHAR ucPpllAttribute; 6592 }ATOM_DISP_CLOCK_ID; 6593 6594 // ucPpllAttribute 6595 #define CLOCK_SOURCE_SHAREABLE 0x01 6596 #define CLOCK_SOURCE_DP_MODE 0x02 6597 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 6598 6599 //DispOutInfoTable 6600 typedef struct _ASIC_TRANSMITTER_INFO_V2 6601 { 6602 USHORT usTransmitterObjId; 6603 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 6604 UCHAR ucTransmitterCmdTblId; 6605 UCHAR ucConfig; 6606 UCHAR ucEncoderID; // available 1st encoder ( default ) 6607 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 6608 UCHAR uc2ndEncoderID; 6609 UCHAR ucReserved; 6610 }ASIC_TRANSMITTER_INFO_V2; 6611 6612 typedef struct _ATOM_DISP_OUT_INFO_V3 6613 { 6614 ATOM_COMMON_TABLE_HEADER sHeader; 6615 USHORT ptrTransmitterInfo; 6616 USHORT ptrEncoderInfo; 6617 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6618 USHORT usReserved; 6619 UCHAR ucDCERevision; 6620 UCHAR ucMaxDispEngineNum; 6621 UCHAR ucMaxActiveDispEngineNum; 6622 UCHAR ucMaxPPLLNum; 6623 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 6624 UCHAR ucReserved[3]; 6625 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 6626 }ATOM_DISP_OUT_INFO_V3; 6627 6628 typedef enum CORE_REF_CLK_SOURCE{ 6629 CLOCK_SRC_XTALIN=0, 6630 CLOCK_SRC_XO_IN=1, 6631 CLOCK_SRC_XO_IN2=2, 6632 }CORE_REF_CLK_SOURCE; 6633 6634 // DispDevicePriorityInfo 6635 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 6636 { 6637 ATOM_COMMON_TABLE_HEADER sHeader; 6638 USHORT asDevicePriority[16]; 6639 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 6640 6641 //ProcessAuxChannelTransactionTable 6642 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6643 { 6644 USHORT lpAuxRequest; 6645 USHORT lpDataOut; 6646 UCHAR ucChannelID; 6647 union 6648 { 6649 UCHAR ucReplyStatus; 6650 UCHAR ucDelay; 6651 }; 6652 UCHAR ucDataOutLen; 6653 UCHAR ucReserved; 6654 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 6655 6656 //ProcessAuxChannelTransactionTable 6657 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 6658 { 6659 USHORT lpAuxRequest; 6660 USHORT lpDataOut; 6661 UCHAR ucChannelID; 6662 union 6663 { 6664 UCHAR ucReplyStatus; 6665 UCHAR ucDelay; 6666 }; 6667 UCHAR ucDataOutLen; 6668 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 6669 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 6670 6671 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6672 6673 //GetSinkType 6674 6675 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 6676 { 6677 USHORT ucLinkClock; 6678 union 6679 { 6680 UCHAR ucConfig; // for DP training command 6681 UCHAR ucI2cId; // use for GET_SINK_TYPE command 6682 }; 6683 UCHAR ucAction; 6684 UCHAR ucStatus; 6685 UCHAR ucLaneNum; 6686 UCHAR ucReserved[2]; 6687 }DP_ENCODER_SERVICE_PARAMETERS; 6688 6689 // ucAction 6690 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 6691 /* obselete */ 6692 #define ATOM_DP_ACTION_TRAINING_START 0x02 6693 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 6694 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 6695 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 6696 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 6697 #define ATOM_DP_ACTION_BLANKING 0x07 6698 6699 // ucConfig 6700 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 6701 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 6702 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 6703 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 6704 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 6705 #define ATOM_DP_CONFIG_LINK_A 0x00 6706 #define ATOM_DP_CONFIG_LINK_B 0x04 6707 /* /obselete */ 6708 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 6709 6710 6711 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 6712 { 6713 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6714 UCHAR ucAuxId; 6715 UCHAR ucAction; 6716 UCHAR ucSinkType; // Iput and Output parameters. 6717 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6718 UCHAR ucReserved[2]; 6719 }DP_ENCODER_SERVICE_PARAMETERS_V2; 6720 6721 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 6722 { 6723 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 6724 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 6725 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 6726 6727 // ucAction 6728 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 6729 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 6730 6731 6732 // DP_TRAINING_TABLE 6733 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 6734 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 6735 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 6736 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 6737 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 6738 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 6739 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 6740 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 6741 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 6742 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 6743 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 6744 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 6745 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 6746 6747 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6748 { 6749 UCHAR ucI2CSpeed; 6750 union 6751 { 6752 UCHAR ucRegIndex; 6753 UCHAR ucStatus; 6754 }; 6755 USHORT lpI2CDataOut; 6756 UCHAR ucFlag; 6757 UCHAR ucTransBytes; 6758 UCHAR ucSlaveAddr; 6759 UCHAR ucLineNumber; 6760 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 6761 6762 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6763 6764 //ucFlag 6765 #define HW_I2C_WRITE 1 6766 #define HW_I2C_READ 0 6767 #define I2C_2BYTE_ADDR 0x02 6768 6769 /****************************************************************************/ 6770 // Structures used by HW_Misc_OperationTable 6771 /****************************************************************************/ 6772 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 6773 { 6774 UCHAR ucCmd; // Input: To tell which action to take 6775 UCHAR ucReserved[3]; 6776 ULONG ulReserved; 6777 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 6778 6779 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 6780 { 6781 UCHAR ucReturnCode; // Output: Return value base on action was taken 6782 UCHAR ucReserved[3]; 6783 ULONG ulReserved; 6784 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 6785 6786 // Actions code 6787 #define ATOM_GET_SDI_SUPPORT 0xF0 6788 6789 // Return code 6790 #define ATOM_UNKNOWN_CMD 0 6791 #define ATOM_FEATURE_NOT_SUPPORTED 1 6792 #define ATOM_FEATURE_SUPPORTED 2 6793 6794 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 6795 { 6796 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 6797 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 6798 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 6799 6800 /****************************************************************************/ 6801 6802 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 6803 { 6804 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 6805 UCHAR ucReserved[3]; 6806 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 6807 6808 #define HWBLKINST_INSTANCE_MASK 0x07 6809 #define HWBLKINST_HWBLK_MASK 0xF0 6810 #define HWBLKINST_HWBLK_SHIFT 0x04 6811 6812 //ucHWBlock 6813 #define SELECT_DISP_ENGINE 0 6814 #define SELECT_DISP_PLL 1 6815 #define SELECT_DCIO_UNIPHY_LINK0 2 6816 #define SELECT_DCIO_UNIPHY_LINK1 3 6817 #define SELECT_DCIO_IMPCAL 4 6818 #define SELECT_DCIO_DIG 6 6819 #define SELECT_CRTC_PIXEL_RATE 7 6820 #define SELECT_VGA_BLK 8 6821 6822 // DIGTransmitterInfoTable structure used to program UNIPHY settings 6823 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 6824 ATOM_COMMON_TABLE_HEADER sHeader; 6825 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 6826 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 6827 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 6828 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 6829 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 6830 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 6831 6832 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 6833 USHORT usRegisterIndex; 6834 UCHAR ucStartBit; 6835 UCHAR ucEndBit; 6836 }CLOCK_CONDITION_REGESTER_INFO; 6837 6838 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 6839 USHORT usMaxClockFreq; 6840 UCHAR ucEncodeMode; 6841 UCHAR ucPhySel; 6842 ULONG ulAnalogSetting[1]; 6843 }CLOCK_CONDITION_SETTING_ENTRY; 6844 6845 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 6846 USHORT usEntrySize; 6847 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 6848 }CLOCK_CONDITION_SETTING_INFO; 6849 6850 typedef struct _PHY_CONDITION_REG_VAL{ 6851 ULONG ulCondition; 6852 ULONG ulRegVal; 6853 }PHY_CONDITION_REG_VAL; 6854 6855 typedef struct _PHY_CONDITION_REG_INFO{ 6856 USHORT usRegIndex; 6857 USHORT usSize; 6858 PHY_CONDITION_REG_VAL asRegVal[1]; 6859 }PHY_CONDITION_REG_INFO; 6860 6861 typedef struct _PHY_ANALOG_SETTING_INFO{ 6862 UCHAR ucEncodeMode; 6863 UCHAR ucPhySel; 6864 USHORT usSize; 6865 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 6866 }PHY_ANALOG_SETTING_INFO; 6867 6868 /****************************************************************************/ 6869 //Portion VI: Definitinos for vbios MC scratch registers that driver used 6870 /****************************************************************************/ 6871 6872 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 6873 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 6874 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 6875 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 6876 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 6877 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 6878 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 6879 6880 /****************************************************************************/ 6881 //Portion VI: Definitinos being oboselete 6882 /****************************************************************************/ 6883 6884 //========================================================================================== 6885 //Remove the definitions below when driver is ready! 6886 typedef struct _ATOM_DAC_INFO 6887 { 6888 ATOM_COMMON_TABLE_HEADER sHeader; 6889 USHORT usMaxFrequency; // in 10kHz unit 6890 USHORT usReserved; 6891 }ATOM_DAC_INFO; 6892 6893 6894 typedef struct _COMPASSIONATE_DATA 6895 { 6896 ATOM_COMMON_TABLE_HEADER sHeader; 6897 6898 //============================== DAC1 portion 6899 UCHAR ucDAC1_BG_Adjustment; 6900 UCHAR ucDAC1_DAC_Adjustment; 6901 USHORT usDAC1_FORCE_Data; 6902 //============================== DAC2 portion 6903 UCHAR ucDAC2_CRT2_BG_Adjustment; 6904 UCHAR ucDAC2_CRT2_DAC_Adjustment; 6905 USHORT usDAC2_CRT2_FORCE_Data; 6906 USHORT usDAC2_CRT2_MUX_RegisterIndex; 6907 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6908 UCHAR ucDAC2_NTSC_BG_Adjustment; 6909 UCHAR ucDAC2_NTSC_DAC_Adjustment; 6910 USHORT usDAC2_TV1_FORCE_Data; 6911 USHORT usDAC2_TV1_MUX_RegisterIndex; 6912 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6913 UCHAR ucDAC2_CV_BG_Adjustment; 6914 UCHAR ucDAC2_CV_DAC_Adjustment; 6915 USHORT usDAC2_CV_FORCE_Data; 6916 USHORT usDAC2_CV_MUX_RegisterIndex; 6917 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6918 UCHAR ucDAC2_PAL_BG_Adjustment; 6919 UCHAR ucDAC2_PAL_DAC_Adjustment; 6920 USHORT usDAC2_TV2_FORCE_Data; 6921 }COMPASSIONATE_DATA; 6922 6923 /****************************Supported Device Info Table Definitions**********************/ 6924 // ucConnectInfo: 6925 // [7:4] - connector type 6926 // = 1 - VGA connector 6927 // = 2 - DVI-I 6928 // = 3 - DVI-D 6929 // = 4 - DVI-A 6930 // = 5 - SVIDEO 6931 // = 6 - COMPOSITE 6932 // = 7 - LVDS 6933 // = 8 - DIGITAL LINK 6934 // = 9 - SCART 6935 // = 0xA - HDMI_type A 6936 // = 0xB - HDMI_type B 6937 // = 0xE - Special case1 (DVI+DIN) 6938 // Others=TBD 6939 // [3:0] - DAC Associated 6940 // = 0 - no DAC 6941 // = 1 - DACA 6942 // = 2 - DACB 6943 // = 3 - External DAC 6944 // Others=TBD 6945 // 6946 6947 typedef struct _ATOM_CONNECTOR_INFO 6948 { 6949 #if ATOM_BIG_ENDIAN 6950 UCHAR bfConnectorType:4; 6951 UCHAR bfAssociatedDAC:4; 6952 #else 6953 UCHAR bfAssociatedDAC:4; 6954 UCHAR bfConnectorType:4; 6955 #endif 6956 }ATOM_CONNECTOR_INFO; 6957 6958 typedef union _ATOM_CONNECTOR_INFO_ACCESS 6959 { 6960 ATOM_CONNECTOR_INFO sbfAccess; 6961 UCHAR ucAccess; 6962 }ATOM_CONNECTOR_INFO_ACCESS; 6963 6964 typedef struct _ATOM_CONNECTOR_INFO_I2C 6965 { 6966 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 6967 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6968 }ATOM_CONNECTOR_INFO_I2C; 6969 6970 6971 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 6972 { 6973 ATOM_COMMON_TABLE_HEADER sHeader; 6974 USHORT usDeviceSupport; 6975 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 6976 }ATOM_SUPPORTED_DEVICES_INFO; 6977 6978 #define NO_INT_SRC_MAPPED 0xFF 6979 6980 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 6981 { 6982 UCHAR ucIntSrcBitmap; 6983 }ATOM_CONNECTOR_INC_SRC_BITMAP; 6984 6985 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 6986 { 6987 ATOM_COMMON_TABLE_HEADER sHeader; 6988 USHORT usDeviceSupport; 6989 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6990 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6991 }ATOM_SUPPORTED_DEVICES_INFO_2; 6992 6993 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 6994 { 6995 ATOM_COMMON_TABLE_HEADER sHeader; 6996 USHORT usDeviceSupport; 6997 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6998 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6999 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 7000 7001 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7002 7003 7004 7005 typedef struct _ATOM_MISC_CONTROL_INFO 7006 { 7007 USHORT usFrequency; 7008 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7009 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7010 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7011 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7012 }ATOM_MISC_CONTROL_INFO; 7013 7014 7015 #define ATOM_MAX_MISC_INFO 4 7016 7017 typedef struct _ATOM_TMDS_INFO 7018 { 7019 ATOM_COMMON_TABLE_HEADER sHeader; 7020 USHORT usMaxFrequency; // in 10Khz 7021 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7022 }ATOM_TMDS_INFO; 7023 7024 7025 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7026 { 7027 UCHAR ucTVStandard; //Same as TV standards defined above, 7028 UCHAR ucPadding[1]; 7029 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 7030 7031 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7032 { 7033 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7034 UCHAR ucPadding[1]; 7035 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7036 7037 typedef union _ATOM_ENCODER_ATTRIBUTE 7038 { 7039 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7040 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7041 }ATOM_ENCODER_ATTRIBUTE; 7042 7043 7044 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7045 { 7046 USHORT usPixelClock; 7047 USHORT usEncoderID; 7048 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7049 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7050 ATOM_ENCODER_ATTRIBUTE usDevAttr; 7051 }DVO_ENCODER_CONTROL_PARAMETERS; 7052 7053 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7054 { 7055 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7056 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7057 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 7058 7059 7060 #define ATOM_XTMDS_ASIC_SI164_ID 1 7061 #define ATOM_XTMDS_ASIC_SI178_ID 2 7062 #define ATOM_XTMDS_ASIC_TFP513_ID 3 7063 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7064 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7065 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 7066 7067 7068 typedef struct _ATOM_XTMDS_INFO 7069 { 7070 ATOM_COMMON_TABLE_HEADER sHeader; 7071 USHORT usSingleLinkMaxFrequency; 7072 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7073 UCHAR ucXtransimitterID; 7074 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7075 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7076 // due to design. This ID is used to alert driver that the sequence is not "standard"! 7077 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7078 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7079 }ATOM_XTMDS_INFO; 7080 7081 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7082 { 7083 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7084 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7085 UCHAR ucPadding[2]; 7086 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7087 7088 /****************************Legacy Power Play Table Definitions **********************/ 7089 7090 //Definitions for ulPowerPlayMiscInfo 7091 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7092 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7093 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7094 7095 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7096 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7097 7098 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7099 7100 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7101 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7102 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7103 7104 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7105 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7106 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7107 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7108 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7109 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7110 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7111 7112 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7113 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7114 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7115 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7116 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7117 7118 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7119 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7120 7121 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7122 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7123 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7124 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7125 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7126 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7127 7128 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7129 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7130 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7131 7132 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7133 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7134 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7135 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7136 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7137 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7138 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7139 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7140 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7141 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7142 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7143 7144 //ucTableFormatRevision=1 7145 //ucTableContentRevision=1 7146 typedef struct _ATOM_POWERMODE_INFO 7147 { 7148 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7149 ULONG ulReserved1; // must set to 0 7150 ULONG ulReserved2; // must set to 0 7151 USHORT usEngineClock; 7152 USHORT usMemoryClock; 7153 UCHAR ucVoltageDropIndex; // index to GPIO table 7154 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7155 UCHAR ucMinTemperature; 7156 UCHAR ucMaxTemperature; 7157 UCHAR ucNumPciELanes; // number of PCIE lanes 7158 }ATOM_POWERMODE_INFO; 7159 7160 //ucTableFormatRevision=2 7161 //ucTableContentRevision=1 7162 typedef struct _ATOM_POWERMODE_INFO_V2 7163 { 7164 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7165 ULONG ulMiscInfo2; 7166 ULONG ulEngineClock; 7167 ULONG ulMemoryClock; 7168 UCHAR ucVoltageDropIndex; // index to GPIO table 7169 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7170 UCHAR ucMinTemperature; 7171 UCHAR ucMaxTemperature; 7172 UCHAR ucNumPciELanes; // number of PCIE lanes 7173 }ATOM_POWERMODE_INFO_V2; 7174 7175 //ucTableFormatRevision=2 7176 //ucTableContentRevision=2 7177 typedef struct _ATOM_POWERMODE_INFO_V3 7178 { 7179 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7180 ULONG ulMiscInfo2; 7181 ULONG ulEngineClock; 7182 ULONG ulMemoryClock; 7183 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7184 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7185 UCHAR ucMinTemperature; 7186 UCHAR ucMaxTemperature; 7187 UCHAR ucNumPciELanes; // number of PCIE lanes 7188 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7189 }ATOM_POWERMODE_INFO_V3; 7190 7191 7192 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7193 7194 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7195 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7196 7197 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7198 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7199 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7200 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7201 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7202 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7203 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7204 7205 7206 typedef struct _ATOM_POWERPLAY_INFO 7207 { 7208 ATOM_COMMON_TABLE_HEADER sHeader; 7209 UCHAR ucOverdriveThermalController; 7210 UCHAR ucOverdriveI2cLine; 7211 UCHAR ucOverdriveIntBitmap; 7212 UCHAR ucOverdriveControllerAddress; 7213 UCHAR ucSizeOfPowerModeEntry; 7214 UCHAR ucNumOfPowerModeEntries; 7215 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7216 }ATOM_POWERPLAY_INFO; 7217 7218 typedef struct _ATOM_POWERPLAY_INFO_V2 7219 { 7220 ATOM_COMMON_TABLE_HEADER sHeader; 7221 UCHAR ucOverdriveThermalController; 7222 UCHAR ucOverdriveI2cLine; 7223 UCHAR ucOverdriveIntBitmap; 7224 UCHAR ucOverdriveControllerAddress; 7225 UCHAR ucSizeOfPowerModeEntry; 7226 UCHAR ucNumOfPowerModeEntries; 7227 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7228 }ATOM_POWERPLAY_INFO_V2; 7229 7230 typedef struct _ATOM_POWERPLAY_INFO_V3 7231 { 7232 ATOM_COMMON_TABLE_HEADER sHeader; 7233 UCHAR ucOverdriveThermalController; 7234 UCHAR ucOverdriveI2cLine; 7235 UCHAR ucOverdriveIntBitmap; 7236 UCHAR ucOverdriveControllerAddress; 7237 UCHAR ucSizeOfPowerModeEntry; 7238 UCHAR ucNumOfPowerModeEntries; 7239 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7240 }ATOM_POWERPLAY_INFO_V3; 7241 7242 /* New PPlib */ 7243 /**************************************************************************/ 7244 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 7245 7246 { 7247 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 7248 UCHAR ucI2cLine; // as interpreted by DAL I2C 7249 UCHAR ucI2cAddress; 7250 UCHAR ucFanParameters; // Fan Control Parameters. 7251 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 7252 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 7253 UCHAR ucReserved; // ---- 7254 UCHAR ucFlags; // to be defined 7255 } ATOM_PPLIB_THERMALCONTROLLER; 7256 7257 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 7258 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 7259 7260 #define ATOM_PP_THERMALCONTROLLER_NONE 0 7261 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 7262 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 7263 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 7264 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 7265 #define ATOM_PP_THERMALCONTROLLER_LM64 5 7266 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 7267 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 7268 #define ATOM_PP_THERMALCONTROLLER_RV770 8 7269 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 7270 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 7271 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 7272 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 7273 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 7274 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 7275 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 7276 #define ATOM_PP_THERMALCONTROLLER_LM96163 17 7277 7278 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 7279 // We probably should reserve the bit 0x80 for this use. 7280 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 7281 // The driver can pick the correct internal controller based on the ASIC. 7282 7283 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 7284 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 7285 7286 typedef struct _ATOM_PPLIB_STATE 7287 { 7288 UCHAR ucNonClockStateIndex; 7289 UCHAR ucClockStateIndices[1]; // variable-sized 7290 } ATOM_PPLIB_STATE; 7291 7292 7293 typedef struct _ATOM_PPLIB_FANTABLE 7294 { 7295 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 7296 UCHAR ucTHyst; // Temperature hysteresis. Integer. 7297 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 7298 USHORT usTMed; // The middle temperature where we change slopes. 7299 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 7300 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 7301 USHORT usPWMMed; // The PWM value (in percent) at TMed. 7302 USHORT usPWMHigh; // The PWM value at THigh. 7303 } ATOM_PPLIB_FANTABLE; 7304 7305 typedef struct _ATOM_PPLIB_FANTABLE2 7306 { 7307 ATOM_PPLIB_FANTABLE basicTable; 7308 USHORT usTMax; // The max temperature 7309 } ATOM_PPLIB_FANTABLE2; 7310 7311 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 7312 { 7313 USHORT usSize; 7314 ULONG ulMaxEngineClock; // For Overdrive. 7315 ULONG ulMaxMemoryClock; // For Overdrive. 7316 // Add extra system parameters here, always adjust size to include all fields. 7317 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 7318 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 7319 } ATOM_PPLIB_EXTENDEDHEADER; 7320 7321 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 7322 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 7323 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 7324 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 7325 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 7326 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 7327 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 7328 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 7329 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 7330 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 7331 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 7332 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 7333 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 7334 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 7335 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 7336 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 7337 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 7338 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 7339 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 7340 7341 7342 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 7343 { 7344 ATOM_COMMON_TABLE_HEADER sHeader; 7345 7346 UCHAR ucDataRevision; 7347 7348 UCHAR ucNumStates; 7349 UCHAR ucStateEntrySize; 7350 UCHAR ucClockInfoSize; 7351 UCHAR ucNonClockSize; 7352 7353 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 7354 USHORT usStateArrayOffset; 7355 7356 // offset from start of this table to array of ASIC-specific structures, 7357 // currently ATOM_PPLIB_CLOCK_INFO. 7358 USHORT usClockInfoArrayOffset; 7359 7360 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 7361 USHORT usNonClockInfoArrayOffset; 7362 7363 USHORT usBackbiasTime; // in microseconds 7364 USHORT usVoltageTime; // in microseconds 7365 USHORT usTableSize; //the size of this structure, or the extended structure 7366 7367 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 7368 7369 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 7370 7371 USHORT usBootClockInfoOffset; 7372 USHORT usBootNonClockInfoOffset; 7373 7374 } ATOM_PPLIB_POWERPLAYTABLE; 7375 7376 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 7377 { 7378 ATOM_PPLIB_POWERPLAYTABLE basicTable; 7379 UCHAR ucNumCustomThermalPolicy; 7380 USHORT usCustomThermalPolicyArrayOffset; 7381 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 7382 7383 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 7384 { 7385 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 7386 USHORT usFormatID; // To be used ONLY by PPGen. 7387 USHORT usFanTableOffset; 7388 USHORT usExtendendedHeaderOffset; 7389 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 7390 7391 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 7392 { 7393 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 7394 ULONG ulGoldenPPID; // PPGen use only 7395 ULONG ulGoldenRevision; // PPGen use only 7396 USHORT usVddcDependencyOnSCLKOffset; 7397 USHORT usVddciDependencyOnMCLKOffset; 7398 USHORT usVddcDependencyOnMCLKOffset; 7399 USHORT usMaxClockVoltageOnDCOffset; 7400 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 7401 USHORT usReserved; 7402 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 7403 7404 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 7405 { 7406 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 7407 ULONG ulTDPLimit; 7408 ULONG ulNearTDPLimit; 7409 ULONG ulSQRampingThreshold; 7410 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 7411 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 7412 USHORT usTDPODLimit; 7413 USHORT usLoadLineSlope; // in milliOhms * 100 7414 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 7415 7416 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 7417 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 7418 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 7419 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 7420 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 7421 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 7422 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 7423 // 2, 4, 6, 7 are reserved 7424 7425 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 7426 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 7427 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 7428 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 7429 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 7430 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 7431 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 7432 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 7433 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 7434 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 7435 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 7436 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 7437 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 7438 7439 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 7440 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 7441 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 7442 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 7443 7444 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 7445 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 7446 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 7447 7448 // 0 is 2.5Gb/s, 1 is 5Gb/s 7449 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 7450 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 7451 7452 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 7453 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 7454 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 7455 7456 // lookup into reduced refresh-rate table 7457 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 7458 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 7459 7460 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 7461 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 7462 // 2-15 TBD as needed. 7463 7464 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 7465 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 7466 7467 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 7468 7469 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 7470 7471 //memory related flags 7472 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 7473 7474 //M3 Arb //2bits, current 3 sets of parameters in total 7475 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 7476 #define ATOM_PPLIB_M3ARB_SHIFT 17 7477 7478 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 7479 7480 // remaining 16 bits are reserved 7481 typedef struct _ATOM_PPLIB_THERMAL_STATE 7482 { 7483 UCHAR ucMinTemperature; 7484 UCHAR ucMaxTemperature; 7485 UCHAR ucThermalAction; 7486 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 7487 7488 // Contained in an array starting at the offset 7489 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 7490 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 7491 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 7492 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 7493 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 7494 { 7495 USHORT usClassification; 7496 UCHAR ucMinTemperature; 7497 UCHAR ucMaxTemperature; 7498 ULONG ulCapsAndSettings; 7499 UCHAR ucRequiredPower; 7500 USHORT usClassification2; 7501 ULONG ulVCLK; 7502 ULONG ulDCLK; 7503 UCHAR ucUnused[5]; 7504 } ATOM_PPLIB_NONCLOCK_INFO; 7505 7506 // Contained in an array starting at the offset 7507 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 7508 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 7509 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 7510 { 7511 USHORT usEngineClockLow; 7512 UCHAR ucEngineClockHigh; 7513 7514 USHORT usMemoryClockLow; 7515 UCHAR ucMemoryClockHigh; 7516 7517 USHORT usVDDC; 7518 USHORT usUnused1; 7519 USHORT usUnused2; 7520 7521 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7522 7523 } ATOM_PPLIB_R600_CLOCK_INFO; 7524 7525 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 7526 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 7527 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 7528 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 7529 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 7530 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 7531 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 7532 7533 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 7534 { 7535 USHORT usEngineClockLow; 7536 UCHAR ucEngineClockHigh; 7537 7538 USHORT usMemoryClockLow; 7539 UCHAR ucMemoryClockHigh; 7540 7541 USHORT usVDDC; 7542 USHORT usVDDCI; 7543 USHORT usUnused; 7544 7545 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7546 7547 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 7548 7549 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 7550 { 7551 USHORT usEngineClockLow; 7552 UCHAR ucEngineClockHigh; 7553 7554 USHORT usMemoryClockLow; 7555 UCHAR ucMemoryClockHigh; 7556 7557 USHORT usVDDC; 7558 USHORT usVDDCI; 7559 UCHAR ucPCIEGen; 7560 UCHAR ucUnused1; 7561 7562 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 7563 7564 } ATOM_PPLIB_SI_CLOCK_INFO; 7565 7566 7567 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 7568 7569 { 7570 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 7571 UCHAR ucLowEngineClockHigh; 7572 USHORT usHighEngineClockLow; // High Engine clock in MHz. 7573 UCHAR ucHighEngineClockHigh; 7574 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 7575 UCHAR ucMemoryClockHigh; // Currentyl unused. 7576 UCHAR ucPadding; // For proper alignment and size. 7577 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 7578 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 7579 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. 7580 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 7581 ULONG ulFlags; 7582 } ATOM_PPLIB_RS780_CLOCK_INFO; 7583 7584 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 7585 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 7586 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 7587 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 7588 7589 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 7590 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 7591 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 7592 7593 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 7594 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 7595 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 7596 7597 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 7598 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 7599 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 7600 UCHAR vddcIndex; //2-bit vddc index; 7601 USHORT tdpLimit; 7602 //please initalize to 0 7603 USHORT rsv1; 7604 //please initialize to 0s 7605 ULONG rsv2[2]; 7606 }ATOM_PPLIB_SUMO_CLOCK_INFO; 7607 7608 7609 7610 typedef struct _ATOM_PPLIB_STATE_V2 7611 { 7612 //number of valid dpm levels in this state; Driver uses it to calculate the whole 7613 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 7614 UCHAR ucNumDPMLevels; 7615 7616 //a index to the array of nonClockInfos 7617 UCHAR nonClockInfoIndex; 7618 /** 7619 * Driver will read the first ucNumDPMLevels in this array 7620 */ 7621 UCHAR clockInfoIndex[1]; 7622 } ATOM_PPLIB_STATE_V2; 7623 7624 typedef struct _StateArray{ 7625 //how many states we have 7626 UCHAR ucNumEntries; 7627 7628 ATOM_PPLIB_STATE_V2 states[1]; 7629 }StateArray; 7630 7631 7632 typedef struct _ClockInfoArray{ 7633 //how many clock levels we have 7634 UCHAR ucNumEntries; 7635 7636 //sizeof(ATOM_PPLIB_CLOCK_INFO) 7637 UCHAR ucEntrySize; 7638 7639 UCHAR clockInfo[1]; 7640 }ClockInfoArray; 7641 7642 typedef struct _NonClockInfoArray{ 7643 7644 //how many non-clock levels we have. normally should be same as number of states 7645 UCHAR ucNumEntries; 7646 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 7647 UCHAR ucEntrySize; 7648 7649 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 7650 }NonClockInfoArray; 7651 7652 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 7653 { 7654 USHORT usClockLow; 7655 UCHAR ucClockHigh; 7656 USHORT usVoltage; 7657 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 7658 7659 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 7660 { 7661 UCHAR ucNumEntries; // Number of entries. 7662 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 7663 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 7664 7665 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 7666 { 7667 USHORT usSclkLow; 7668 UCHAR ucSclkHigh; 7669 USHORT usMclkLow; 7670 UCHAR ucMclkHigh; 7671 USHORT usVddc; 7672 USHORT usVddci; 7673 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 7674 7675 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 7676 { 7677 UCHAR ucNumEntries; // Number of entries. 7678 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 7679 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 7680 7681 typedef struct _ATOM_PPLIB_CAC_Leakage_Record 7682 { 7683 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations 7684 ULONG ulLeakageValue; 7685 }ATOM_PPLIB_CAC_Leakage_Record; 7686 7687 typedef struct _ATOM_PPLIB_CAC_Leakage_Table 7688 { 7689 UCHAR ucNumEntries; // Number of entries. 7690 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 7691 }ATOM_PPLIB_CAC_Leakage_Table; 7692 7693 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 7694 { 7695 USHORT usVoltage; 7696 USHORT usSclkLow; 7697 UCHAR ucSclkHigh; 7698 USHORT usMclkLow; 7699 UCHAR ucMclkHigh; 7700 }ATOM_PPLIB_PhaseSheddingLimits_Record; 7701 7702 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 7703 { 7704 UCHAR ucNumEntries; // Number of entries. 7705 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 7706 }ATOM_PPLIB_PhaseSheddingLimits_Table; 7707 7708 typedef struct _VCEClockInfo{ 7709 USHORT usEVClkLow; 7710 UCHAR ucEVClkHigh; 7711 USHORT usECClkLow; 7712 UCHAR ucECClkHigh; 7713 }VCEClockInfo; 7714 7715 typedef struct _VCEClockInfoArray{ 7716 UCHAR ucNumEntries; 7717 VCEClockInfo entries[1]; 7718 }VCEClockInfoArray; 7719 7720 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 7721 { 7722 USHORT usVoltage; 7723 UCHAR ucVCEClockInfoIndex; 7724 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 7725 7726 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 7727 { 7728 UCHAR numEntries; 7729 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 7730 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 7731 7732 typedef struct _ATOM_PPLIB_VCE_State_Record 7733 { 7734 UCHAR ucVCEClockInfoIndex; 7735 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7736 }ATOM_PPLIB_VCE_State_Record; 7737 7738 typedef struct _ATOM_PPLIB_VCE_State_Table 7739 { 7740 UCHAR numEntries; 7741 ATOM_PPLIB_VCE_State_Record entries[1]; 7742 }ATOM_PPLIB_VCE_State_Table; 7743 7744 7745 typedef struct _ATOM_PPLIB_VCE_Table 7746 { 7747 UCHAR revid; 7748 // VCEClockInfoArray array; 7749 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 7750 // ATOM_PPLIB_VCE_State_Table states; 7751 }ATOM_PPLIB_VCE_Table; 7752 7753 7754 typedef struct _UVDClockInfo{ 7755 USHORT usVClkLow; 7756 UCHAR ucVClkHigh; 7757 USHORT usDClkLow; 7758 UCHAR ucDClkHigh; 7759 }UVDClockInfo; 7760 7761 typedef struct _UVDClockInfoArray{ 7762 UCHAR ucNumEntries; 7763 UVDClockInfo entries[1]; 7764 }UVDClockInfoArray; 7765 7766 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 7767 { 7768 USHORT usVoltage; 7769 UCHAR ucUVDClockInfoIndex; 7770 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 7771 7772 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 7773 { 7774 UCHAR numEntries; 7775 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 7776 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 7777 7778 typedef struct _ATOM_PPLIB_UVD_State_Record 7779 { 7780 UCHAR ucUVDClockInfoIndex; 7781 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7782 }ATOM_PPLIB_UVD_State_Record; 7783 7784 typedef struct _ATOM_PPLIB_UVD_State_Table 7785 { 7786 UCHAR numEntries; 7787 ATOM_PPLIB_UVD_State_Record entries[1]; 7788 }ATOM_PPLIB_UVD_State_Table; 7789 7790 7791 typedef struct _ATOM_PPLIB_UVD_Table 7792 { 7793 UCHAR revid; 7794 // UVDClockInfoArray array; 7795 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 7796 // ATOM_PPLIB_UVD_State_Table states; 7797 }ATOM_PPLIB_UVD_Table; 7798 7799 /**************************************************************************/ 7800 7801 7802 // Following definitions are for compatibility issue in different SW components. 7803 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7804 #define Object_Info Object_Header 7805 #define AdjustARB_SEQ MC_InitParameter 7806 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7807 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 7808 #define ASIC_MVDDQ_Info MemoryTrainingInfo 7809 #define SS_Info PPLL_SS_Info 7810 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 7811 #define DispDevicePriorityInfo SaveRestoreInfo 7812 #define DispOutInfo TV_VideoMode 7813 7814 7815 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7816 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7817 7818 //New device naming, remove them when both DAL/VBIOS is ready 7819 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7820 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7821 7822 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7823 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7824 7825 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7826 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7827 7828 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7829 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7830 7831 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7832 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7833 7834 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7835 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7836 7837 #define ATOM_S0_DFP1I ATOM_S0_DFP1 7838 #define ATOM_S0_DFP1X ATOM_S0_DFP2 7839 7840 #define ATOM_S0_DFP2I 0x00200000L 7841 #define ATOM_S0_DFP2Ib2 0x20 7842 7843 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7844 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7845 7846 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7847 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7848 7849 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 7850 7851 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7852 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7853 7854 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7855 7856 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7857 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7858 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7859 7860 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7861 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7862 7863 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 7864 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7865 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7866 7867 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7868 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7869 7870 #define TMDS1XEncoderControl DVOEncoderControl 7871 #define DFP1XOutputControl DVOOutputControl 7872 7873 #define ExternalDFPOutputControl DFP1XOutputControl 7874 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7875 7876 #define DFP1IOutputControl TMDSAOutputControl 7877 #define DFP2IOutputControl LVTMAOutputControl 7878 7879 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7880 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7881 7882 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7883 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7884 7885 #define ucDac1Standard ucDacStandard 7886 #define ucDac2Standard ucDacStandard 7887 7888 #define TMDS1EncoderControl TMDSAEncoderControl 7889 #define TMDS2EncoderControl LVTMAEncoderControl 7890 7891 #define DFP1OutputControl TMDSAOutputControl 7892 #define DFP2OutputControl LVTMAOutputControl 7893 #define CRT1OutputControl DAC1OutputControl 7894 #define CRT2OutputControl DAC2OutputControl 7895 7896 //These two lines will be removed for sure in a few days, will follow up with Michael V. 7897 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7898 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7899 7900 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7901 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7902 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7903 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7904 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7905 7906 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 7907 #define ATOM_DEVICE_TV2_INDEX 0x00000006 7908 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7909 #define ATOM_S0_TV2 0x00100000L 7910 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7911 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7912 7913 // 7914 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7915 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7916 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7917 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7918 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7919 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7920 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7921 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7922 #define ATOM_S2_CV_DPMS_STATE 0x01000000L 7923 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7924 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7925 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7926 7927 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7928 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7929 #define ATOM_S2_TV1_DPMS_STATEb2 0x04 7930 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7931 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7932 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7933 #define ATOM_S2_TV2_DPMS_STATEb2 0x40 7934 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7935 #define ATOM_S2_CV_DPMS_STATEb3 0x01 7936 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7937 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7938 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7939 7940 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7941 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7942 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7943 7944 /*********************************************************************************/ 7945 7946 #pragma pack() // BIOS data must use byte aligment 7947 7948 // 7949 // AMD ACPI Table 7950 // 7951 #pragma pack(1) 7952 7953 typedef struct { 7954 ULONG Signature; 7955 ULONG TableLength; //Length 7956 UCHAR Revision; 7957 UCHAR Checksum; 7958 UCHAR OemId[6]; 7959 UCHAR OemTableId[8]; //UINT64 OemTableId; 7960 ULONG OemRevision; 7961 ULONG CreatorId; 7962 ULONG CreatorRevision; 7963 } AMD_ACPI_DESCRIPTION_HEADER; 7964 /* 7965 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7966 typedef struct { 7967 UINT32 Signature; //0x0 7968 UINT32 Length; //0x4 7969 UINT8 Revision; //0x8 7970 UINT8 Checksum; //0x9 7971 UINT8 OemId[6]; //0xA 7972 UINT64 OemTableId; //0x10 7973 UINT32 OemRevision; //0x18 7974 UINT32 CreatorId; //0x1C 7975 UINT32 CreatorRevision; //0x20 7976 }EFI_ACPI_DESCRIPTION_HEADER; 7977 */ 7978 typedef struct { 7979 AMD_ACPI_DESCRIPTION_HEADER SHeader; 7980 UCHAR TableUUID[16]; //0x24 7981 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 7982 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 7983 ULONG Reserved[4]; //0x3C 7984 }UEFI_ACPI_VFCT; 7985 7986 typedef struct { 7987 ULONG PCIBus; //0x4C 7988 ULONG PCIDevice; //0x50 7989 ULONG PCIFunction; //0x54 7990 USHORT VendorID; //0x58 7991 USHORT DeviceID; //0x5A 7992 USHORT SSVID; //0x5C 7993 USHORT SSID; //0x5E 7994 ULONG Revision; //0x60 7995 ULONG ImageLength; //0x64 7996 }VFCT_IMAGE_HEADER; 7997 7998 7999 typedef struct { 8000 VFCT_IMAGE_HEADER VbiosHeader; 8001 UCHAR VbiosContent[1]; 8002 }GOP_VBIOS_CONTENT; 8003 8004 typedef struct { 8005 VFCT_IMAGE_HEADER Lib1Header; 8006 UCHAR Lib1Content[1]; 8007 }GOP_LIB1_CONTENT; 8008 8009 #pragma pack() 8010 8011 8012 #endif /* _ATOMBIOS_H */ 8013