1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_fb_helper.h> 29 #include <uapi_drm/radeon_drm.h> 30 #include <drm/drm_fixed.h> 31 #include "radeon.h" 32 #include "atom.h" 33 #include "atom-bits.h" 34 35 static void atombios_overscan_setup(struct drm_crtc *crtc, 36 struct drm_display_mode *mode, 37 struct drm_display_mode *adjusted_mode) 38 { 39 struct drm_device *dev = crtc->dev; 40 struct radeon_device *rdev = dev->dev_private; 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 44 int a1, a2; 45 46 memset(&args, 0, sizeof(args)); 47 48 args.ucCRTC = radeon_crtc->crtc_id; 49 50 switch (radeon_crtc->rmx_type) { 51 case RMX_CENTER: 52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 56 break; 57 case RMX_ASPECT: 58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 60 61 if (a1 > a2) { 62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 64 } else if (a2 > a1) { 65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 67 } 68 break; 69 case RMX_FULL: 70 default: 71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 75 break; 76 } 77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 78 } 79 80 static void atombios_scaler_setup(struct drm_crtc *crtc) 81 { 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 85 ENABLE_SCALER_PS_ALLOCATION args; 86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 87 struct radeon_encoder *radeon_encoder = 88 to_radeon_encoder(radeon_crtc->encoder); 89 /* fixme - fill in enc_priv for atom dac */ 90 enum radeon_tv_std tv_std = TV_STD_NTSC; 91 bool is_tv = false, is_cv = false; 92 93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 94 return; 95 96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 98 tv_std = tv_dac->tv_std; 99 is_tv = true; 100 } 101 102 memset(&args, 0, sizeof(args)); 103 104 args.ucScaler = radeon_crtc->crtc_id; 105 106 if (is_tv) { 107 switch (tv_std) { 108 case TV_STD_NTSC: 109 default: 110 args.ucTVStandard = ATOM_TV_NTSC; 111 break; 112 case TV_STD_PAL: 113 args.ucTVStandard = ATOM_TV_PAL; 114 break; 115 case TV_STD_PAL_M: 116 args.ucTVStandard = ATOM_TV_PALM; 117 break; 118 case TV_STD_PAL_60: 119 args.ucTVStandard = ATOM_TV_PAL60; 120 break; 121 case TV_STD_NTSC_J: 122 args.ucTVStandard = ATOM_TV_NTSCJ; 123 break; 124 case TV_STD_SCART_PAL: 125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 126 break; 127 case TV_STD_SECAM: 128 args.ucTVStandard = ATOM_TV_SECAM; 129 break; 130 case TV_STD_PAL_CN: 131 args.ucTVStandard = ATOM_TV_PALCN; 132 break; 133 } 134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 135 } else if (is_cv) { 136 args.ucTVStandard = ATOM_TV_CV; 137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 138 } else { 139 switch (radeon_crtc->rmx_type) { 140 case RMX_FULL: 141 args.ucEnable = ATOM_SCALER_EXPANSION; 142 break; 143 case RMX_CENTER: 144 args.ucEnable = ATOM_SCALER_CENTER; 145 break; 146 case RMX_ASPECT: 147 args.ucEnable = ATOM_SCALER_EXPANSION; 148 break; 149 default: 150 if (ASIC_IS_AVIVO(rdev)) 151 args.ucEnable = ATOM_SCALER_DISABLE; 152 else 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 } 156 } 157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 158 if ((is_tv || is_cv) 159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 160 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 161 } 162 } 163 164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 struct drm_device *dev = crtc->dev; 168 struct radeon_device *rdev = dev->dev_private; 169 int index = 170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 171 ENABLE_CRTC_PS_ALLOCATION args; 172 173 memset(&args, 0, sizeof(args)); 174 175 args.ucCRTC = radeon_crtc->crtc_id; 176 args.ucEnable = lock; 177 178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 179 } 180 181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 182 { 183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 184 struct drm_device *dev = crtc->dev; 185 struct radeon_device *rdev = dev->dev_private; 186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 187 ENABLE_CRTC_PS_ALLOCATION args; 188 189 memset(&args, 0, sizeof(args)); 190 191 args.ucCRTC = radeon_crtc->crtc_id; 192 args.ucEnable = state; 193 194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 195 } 196 197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 198 { 199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 200 struct drm_device *dev = crtc->dev; 201 struct radeon_device *rdev = dev->dev_private; 202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 203 ENABLE_CRTC_PS_ALLOCATION args; 204 205 memset(&args, 0, sizeof(args)); 206 207 args.ucCRTC = radeon_crtc->crtc_id; 208 args.ucEnable = state; 209 210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 211 } 212 213 static const u32 vga_control_regs[6] = 214 { 215 AVIVO_D1VGA_CONTROL, 216 AVIVO_D2VGA_CONTROL, 217 EVERGREEN_D3VGA_CONTROL, 218 EVERGREEN_D4VGA_CONTROL, 219 EVERGREEN_D5VGA_CONTROL, 220 EVERGREEN_D6VGA_CONTROL, 221 }; 222 223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 224 { 225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 226 struct drm_device *dev = crtc->dev; 227 struct radeon_device *rdev = dev->dev_private; 228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 229 BLANK_CRTC_PS_ALLOCATION args; 230 u32 vga_control = 0; 231 232 memset(&args, 0, sizeof(args)); 233 234 if (ASIC_IS_DCE8(rdev)) { 235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); 236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); 237 } 238 239 args.ucCRTC = radeon_crtc->crtc_id; 240 args.ucBlanking = state; 241 242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 243 244 if (ASIC_IS_DCE8(rdev)) { 245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); 246 } 247 } 248 249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 struct drm_device *dev = crtc->dev; 253 struct radeon_device *rdev = dev->dev_private; 254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 256 257 memset(&args, 0, sizeof(args)); 258 259 args.ucDispPipeId = radeon_crtc->crtc_id; 260 args.ucEnable = state; 261 262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 263 } 264 265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 266 { 267 struct drm_device *dev = crtc->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 270 271 switch (mode) { 272 case DRM_MODE_DPMS_ON: 273 radeon_crtc->enabled = true; 274 atombios_enable_crtc(crtc, ATOM_ENABLE); 275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 277 atombios_blank_crtc(crtc, ATOM_DISABLE); 278 if (dev->num_crtcs > radeon_crtc->crtc_id) 279 drm_vblank_on(dev, radeon_crtc->crtc_id); 280 radeon_crtc_load_lut(crtc); 281 break; 282 case DRM_MODE_DPMS_STANDBY: 283 case DRM_MODE_DPMS_SUSPEND: 284 case DRM_MODE_DPMS_OFF: 285 if (dev->num_crtcs > radeon_crtc->crtc_id) 286 drm_vblank_off(dev, radeon_crtc->crtc_id); 287 if (radeon_crtc->enabled) 288 atombios_blank_crtc(crtc, ATOM_ENABLE); 289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 291 atombios_enable_crtc(crtc, ATOM_DISABLE); 292 radeon_crtc->enabled = false; 293 break; 294 } 295 /* adjust pm to dpms */ 296 radeon_pm_compute_clocks(rdev); 297 } 298 299 static void 300 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 301 struct drm_display_mode *mode) 302 { 303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 304 struct drm_device *dev = crtc->dev; 305 struct radeon_device *rdev = dev->dev_private; 306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 308 u16 misc = 0; 309 310 memset(&args, 0, sizeof(args)); 311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 312 args.usH_Blanking_Time = 313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 315 args.usV_Blanking_Time = 316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 317 args.usH_SyncOffset = 318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 319 args.usH_SyncWidth = 320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 321 args.usV_SyncOffset = 322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 323 args.usV_SyncWidth = 324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 325 args.ucH_Border = radeon_crtc->h_border; 326 args.ucV_Border = radeon_crtc->v_border; 327 328 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 329 misc |= ATOM_VSYNC_POLARITY; 330 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 331 misc |= ATOM_HSYNC_POLARITY; 332 if (mode->flags & DRM_MODE_FLAG_CSYNC) 333 misc |= ATOM_COMPOSITESYNC; 334 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 335 misc |= ATOM_INTERLACE; 336 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 337 misc |= ATOM_DOUBLE_CLOCK_MODE; 338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 340 341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 342 args.ucCRTC = radeon_crtc->crtc_id; 343 344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 345 } 346 347 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 348 struct drm_display_mode *mode) 349 { 350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 351 struct drm_device *dev = crtc->dev; 352 struct radeon_device *rdev = dev->dev_private; 353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 355 u16 misc = 0; 356 357 memset(&args, 0, sizeof(args)); 358 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 361 args.usH_SyncWidth = 362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 366 args.usV_SyncWidth = 367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 368 369 args.ucOverscanRight = radeon_crtc->h_border; 370 args.ucOverscanLeft = radeon_crtc->h_border; 371 args.ucOverscanBottom = radeon_crtc->v_border; 372 args.ucOverscanTop = radeon_crtc->v_border; 373 374 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 375 misc |= ATOM_VSYNC_POLARITY; 376 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 377 misc |= ATOM_HSYNC_POLARITY; 378 if (mode->flags & DRM_MODE_FLAG_CSYNC) 379 misc |= ATOM_COMPOSITESYNC; 380 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 381 misc |= ATOM_INTERLACE; 382 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 383 misc |= ATOM_DOUBLE_CLOCK_MODE; 384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 386 387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 388 args.ucCRTC = radeon_crtc->crtc_id; 389 390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 391 } 392 393 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 394 { 395 u32 ss_cntl; 396 397 if (ASIC_IS_DCE4(rdev)) { 398 switch (pll_id) { 399 case ATOM_PPLL1: 400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 403 break; 404 case ATOM_PPLL2: 405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 408 break; 409 case ATOM_DCPLL: 410 case ATOM_PPLL_INVALID: 411 return; 412 } 413 } else if (ASIC_IS_AVIVO(rdev)) { 414 switch (pll_id) { 415 case ATOM_PPLL1: 416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 417 ss_cntl &= ~1; 418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 419 break; 420 case ATOM_PPLL2: 421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 422 ss_cntl &= ~1; 423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 424 break; 425 case ATOM_DCPLL: 426 case ATOM_PPLL_INVALID: 427 return; 428 } 429 } 430 } 431 432 433 union atom_enable_ss { 434 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 439 }; 440 441 static void atombios_crtc_program_ss(struct radeon_device *rdev, 442 int enable, 443 int pll_id, 444 int crtc_id, 445 struct radeon_atom_ss *ss) 446 { 447 unsigned i; 448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 449 union atom_enable_ss args; 450 451 if (enable) { 452 /* Don't mess with SS if percentage is 0 or external ss. 453 * SS is already disabled previously, and disabling it 454 * again can cause display problems if the pll is already 455 * programmed. 456 */ 457 if (ss->percentage == 0) 458 return; 459 if (ss->type & ATOM_EXTERNAL_SS_MASK) 460 return; 461 } else { 462 for (i = 0; i < rdev->num_crtc; i++) { 463 if (rdev->mode_info.crtcs[i] && 464 rdev->mode_info.crtcs[i]->enabled && 465 i != crtc_id && 466 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 467 /* one other crtc is using this pll don't turn 468 * off spread spectrum as it might turn off 469 * display on active crtc 470 */ 471 return; 472 } 473 } 474 } 475 476 memset(&args, 0, sizeof(args)); 477 478 if (ASIC_IS_DCE5(rdev)) { 479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 481 switch (pll_id) { 482 case ATOM_PPLL1: 483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 484 break; 485 case ATOM_PPLL2: 486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 487 break; 488 case ATOM_DCPLL: 489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 490 break; 491 case ATOM_PPLL_INVALID: 492 return; 493 } 494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 496 args.v3.ucEnable = enable; 497 } else if (ASIC_IS_DCE4(rdev)) { 498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 500 switch (pll_id) { 501 case ATOM_PPLL1: 502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 503 break; 504 case ATOM_PPLL2: 505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 506 break; 507 case ATOM_DCPLL: 508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 509 break; 510 case ATOM_PPLL_INVALID: 511 return; 512 } 513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 515 args.v2.ucEnable = enable; 516 } else if (ASIC_IS_DCE3(rdev)) { 517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 519 args.v1.ucSpreadSpectrumStep = ss->step; 520 args.v1.ucSpreadSpectrumDelay = ss->delay; 521 args.v1.ucSpreadSpectrumRange = ss->range; 522 args.v1.ucPpll = pll_id; 523 args.v1.ucEnable = enable; 524 } else if (ASIC_IS_AVIVO(rdev)) { 525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 526 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 527 atombios_disable_ss(rdev, pll_id); 528 return; 529 } 530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 535 args.lvds_ss_2.ucEnable = enable; 536 } else { 537 if (enable == ATOM_DISABLE) { 538 atombios_disable_ss(rdev, pll_id); 539 return; 540 } 541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 545 args.lvds_ss.ucEnable = enable; 546 } 547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 548 } 549 550 union adjust_pixel_clock { 551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 553 }; 554 555 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 556 struct drm_display_mode *mode) 557 { 558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 559 struct drm_device *dev = crtc->dev; 560 struct radeon_device *rdev = dev->dev_private; 561 struct drm_encoder *encoder = radeon_crtc->encoder; 562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 564 u32 adjusted_clock = mode->clock; 565 int encoder_mode = atombios_get_encoder_mode(encoder); 566 u32 dp_clock = mode->clock; 567 u32 clock = mode->clock; 568 int bpc = radeon_crtc->bpc; 569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 570 571 /* reset the pll flags */ 572 radeon_crtc->pll_flags = 0; 573 574 if (ASIC_IS_AVIVO(rdev)) { 575 if ((rdev->family == CHIP_RS600) || 576 (rdev->family == CHIP_RS690) || 577 (rdev->family == CHIP_RS740)) 578 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 579 RADEON_PLL_PREFER_CLOSEST_LOWER); 580 581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 583 else 584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 585 586 if (rdev->family < CHIP_RV770) 587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 588 /* use frac fb div on APUs */ 589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 591 /* use frac fb div on RS780/RS880 */ 592 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 593 && !radeon_crtc->ss_enabled) 594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 595 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 597 } else { 598 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 599 600 if (mode->clock > 200000) /* range limits??? */ 601 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 602 else 603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 604 } 605 606 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 607 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 608 if (connector) { 609 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 610 struct radeon_connector_atom_dig *dig_connector = 611 radeon_connector->con_priv; 612 613 dp_clock = dig_connector->dp_clock; 614 } 615 } 616 617 /* use recommended ref_div for ss */ 618 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 619 if (radeon_crtc->ss_enabled) { 620 if (radeon_crtc->ss.refdiv) { 621 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 622 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 623 if (ASIC_IS_AVIVO(rdev) && 624 rdev->family != CHIP_RS780 && 625 rdev->family != CHIP_RS880) 626 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 627 } 628 } 629 } 630 631 if (ASIC_IS_AVIVO(rdev)) { 632 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 633 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 634 adjusted_clock = mode->clock * 2; 635 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 636 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 637 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 638 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 639 } else { 640 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 641 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 642 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 643 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 644 } 645 646 /* adjust pll for deep color modes */ 647 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 648 switch (bpc) { 649 case 8: 650 default: 651 break; 652 case 10: 653 clock = (clock * 5) / 4; 654 break; 655 case 12: 656 clock = (clock * 3) / 2; 657 break; 658 case 16: 659 clock = clock * 2; 660 break; 661 } 662 } 663 664 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 665 * accordingly based on the encoder/transmitter to work around 666 * special hw requirements. 667 */ 668 if (ASIC_IS_DCE3(rdev)) { 669 union adjust_pixel_clock args; 670 u8 frev, crev; 671 int index; 672 673 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 674 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 675 &crev)) 676 return adjusted_clock; 677 678 memset(&args, 0, sizeof(args)); 679 680 switch (frev) { 681 case 1: 682 switch (crev) { 683 case 1: 684 case 2: 685 args.v1.usPixelClock = cpu_to_le16(clock / 10); 686 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 687 args.v1.ucEncodeMode = encoder_mode; 688 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 689 args.v1.ucConfig |= 690 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 691 692 atom_execute_table(rdev->mode_info.atom_context, 693 index, (uint32_t *)&args); 694 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 695 break; 696 case 3: 697 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); 698 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 699 args.v3.sInput.ucEncodeMode = encoder_mode; 700 args.v3.sInput.ucDispPllConfig = 0; 701 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 702 args.v3.sInput.ucDispPllConfig |= 703 DISPPLL_CONFIG_SS_ENABLE; 704 if (ENCODER_MODE_IS_DP(encoder_mode)) { 705 args.v3.sInput.ucDispPllConfig |= 706 DISPPLL_CONFIG_COHERENT_MODE; 707 /* 16200 or 27000 */ 708 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 709 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 710 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 711 if (dig->coherent_mode) 712 args.v3.sInput.ucDispPllConfig |= 713 DISPPLL_CONFIG_COHERENT_MODE; 714 if (is_duallink) 715 args.v3.sInput.ucDispPllConfig |= 716 DISPPLL_CONFIG_DUAL_LINK; 717 } 718 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 719 ENCODER_OBJECT_ID_NONE) 720 args.v3.sInput.ucExtTransmitterID = 721 radeon_encoder_get_dp_bridge_encoder_id(encoder); 722 else 723 args.v3.sInput.ucExtTransmitterID = 0; 724 725 atom_execute_table(rdev->mode_info.atom_context, 726 index, (uint32_t *)&args); 727 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 728 if (args.v3.sOutput.ucRefDiv) { 729 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 730 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 731 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 732 } 733 if (args.v3.sOutput.ucPostDiv) { 734 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 735 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 736 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 737 } 738 break; 739 default: 740 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 741 return adjusted_clock; 742 } 743 break; 744 default: 745 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 746 return adjusted_clock; 747 } 748 } 749 return adjusted_clock; 750 } 751 752 union set_pixel_clock { 753 SET_PIXEL_CLOCK_PS_ALLOCATION base; 754 PIXEL_CLOCK_PARAMETERS v1; 755 PIXEL_CLOCK_PARAMETERS_V2 v2; 756 PIXEL_CLOCK_PARAMETERS_V3 v3; 757 PIXEL_CLOCK_PARAMETERS_V5 v5; 758 PIXEL_CLOCK_PARAMETERS_V6 v6; 759 }; 760 761 /* on DCE5, make sure the voltage is high enough to support the 762 * required disp clk. 763 */ 764 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 765 u32 dispclk) 766 { 767 u8 frev, crev; 768 int index; 769 union set_pixel_clock args; 770 771 memset(&args, 0, sizeof(args)); 772 773 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 774 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 775 &crev)) 776 return; 777 778 switch (frev) { 779 case 1: 780 switch (crev) { 781 case 5: 782 /* if the default dcpll clock is specified, 783 * SetPixelClock provides the dividers 784 */ 785 args.v5.ucCRTC = ATOM_CRTC_INVALID; 786 args.v5.usPixelClock = cpu_to_le16(dispclk); 787 args.v5.ucPpll = ATOM_DCPLL; 788 break; 789 case 6: 790 /* if the default dcpll clock is specified, 791 * SetPixelClock provides the dividers 792 */ 793 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 794 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 795 args.v6.ucPpll = ATOM_EXT_PLL1; 796 else if (ASIC_IS_DCE6(rdev)) 797 args.v6.ucPpll = ATOM_PPLL0; 798 else 799 args.v6.ucPpll = ATOM_DCPLL; 800 break; 801 default: 802 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 803 return; 804 } 805 break; 806 default: 807 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 808 return; 809 } 810 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 811 } 812 813 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 814 u32 crtc_id, 815 int pll_id, 816 u32 encoder_mode, 817 u32 encoder_id, 818 u32 clock, 819 u32 ref_div, 820 u32 fb_div, 821 u32 frac_fb_div, 822 u32 post_div, 823 int bpc, 824 bool ss_enabled, 825 struct radeon_atom_ss *ss) 826 { 827 struct drm_device *dev = crtc->dev; 828 struct radeon_device *rdev = dev->dev_private; 829 u8 frev, crev; 830 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 831 union set_pixel_clock args; 832 833 memset(&args, 0, sizeof(args)); 834 835 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 836 &crev)) 837 return; 838 839 switch (frev) { 840 case 1: 841 switch (crev) { 842 case 1: 843 if (clock == ATOM_DISABLE) 844 return; 845 args.v1.usPixelClock = cpu_to_le16(clock / 10); 846 args.v1.usRefDiv = cpu_to_le16(ref_div); 847 args.v1.usFbDiv = cpu_to_le16(fb_div); 848 args.v1.ucFracFbDiv = frac_fb_div; 849 args.v1.ucPostDiv = post_div; 850 args.v1.ucPpll = pll_id; 851 args.v1.ucCRTC = crtc_id; 852 args.v1.ucRefDivSrc = 1; 853 break; 854 case 2: 855 args.v2.usPixelClock = cpu_to_le16(clock / 10); 856 args.v2.usRefDiv = cpu_to_le16(ref_div); 857 args.v2.usFbDiv = cpu_to_le16(fb_div); 858 args.v2.ucFracFbDiv = frac_fb_div; 859 args.v2.ucPostDiv = post_div; 860 args.v2.ucPpll = pll_id; 861 args.v2.ucCRTC = crtc_id; 862 args.v2.ucRefDivSrc = 1; 863 break; 864 case 3: 865 args.v3.usPixelClock = cpu_to_le16(clock / 10); 866 args.v3.usRefDiv = cpu_to_le16(ref_div); 867 args.v3.usFbDiv = cpu_to_le16(fb_div); 868 args.v3.ucFracFbDiv = frac_fb_div; 869 args.v3.ucPostDiv = post_div; 870 args.v3.ucPpll = pll_id; 871 if (crtc_id == ATOM_CRTC2) 872 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 873 else 874 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 875 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 876 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 877 args.v3.ucTransmitterId = encoder_id; 878 args.v3.ucEncoderMode = encoder_mode; 879 break; 880 case 5: 881 args.v5.ucCRTC = crtc_id; 882 args.v5.usPixelClock = cpu_to_le16(clock / 10); 883 args.v5.ucRefDiv = ref_div; 884 args.v5.usFbDiv = cpu_to_le16(fb_div); 885 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 886 args.v5.ucPostDiv = post_div; 887 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 888 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 889 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 890 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 891 switch (bpc) { 892 case 8: 893 default: 894 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 895 break; 896 case 10: 897 /* yes this is correct, the atom define is wrong */ 898 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; 899 break; 900 case 12: 901 /* yes this is correct, the atom define is wrong */ 902 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 903 break; 904 } 905 } 906 args.v5.ucTransmitterID = encoder_id; 907 args.v5.ucEncoderMode = encoder_mode; 908 args.v5.ucPpll = pll_id; 909 break; 910 case 6: 911 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 912 args.v6.ucRefDiv = ref_div; 913 args.v6.usFbDiv = cpu_to_le16(fb_div); 914 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 915 args.v6.ucPostDiv = post_div; 916 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 917 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 918 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 919 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 920 switch (bpc) { 921 case 8: 922 default: 923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 924 break; 925 case 10: 926 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; 927 break; 928 case 12: 929 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; 930 break; 931 case 16: 932 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 933 break; 934 } 935 } 936 args.v6.ucTransmitterID = encoder_id; 937 args.v6.ucEncoderMode = encoder_mode; 938 args.v6.ucPpll = pll_id; 939 break; 940 default: 941 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 942 return; 943 } 944 break; 945 default: 946 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 947 return; 948 } 949 950 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 951 } 952 953 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 954 { 955 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 956 struct drm_device *dev = crtc->dev; 957 struct radeon_device *rdev = dev->dev_private; 958 struct radeon_encoder *radeon_encoder = 959 to_radeon_encoder(radeon_crtc->encoder); 960 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 961 962 radeon_crtc->bpc = 8; 963 radeon_crtc->ss_enabled = false; 964 965 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 966 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 967 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 968 struct drm_connector *connector = 969 radeon_get_connector_for_encoder(radeon_crtc->encoder); 970 struct radeon_connector *radeon_connector = 971 to_radeon_connector(connector); 972 struct radeon_connector_atom_dig *dig_connector = 973 radeon_connector->con_priv; 974 int dp_clock; 975 976 /* Assign mode clock for hdmi deep color max clock limit check */ 977 radeon_connector->pixelclock_for_modeset = mode->clock; 978 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 979 980 switch (encoder_mode) { 981 case ATOM_ENCODER_MODE_DP_MST: 982 case ATOM_ENCODER_MODE_DP: 983 /* DP/eDP */ 984 dp_clock = dig_connector->dp_clock / 10; 985 if (ASIC_IS_DCE4(rdev)) 986 radeon_crtc->ss_enabled = 987 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 988 ASIC_INTERNAL_SS_ON_DP, 989 dp_clock); 990 else { 991 if (dp_clock == 16200) { 992 radeon_crtc->ss_enabled = 993 radeon_atombios_get_ppll_ss_info(rdev, 994 &radeon_crtc->ss, 995 ATOM_DP_SS_ID2); 996 if (!radeon_crtc->ss_enabled) 997 radeon_crtc->ss_enabled = 998 radeon_atombios_get_ppll_ss_info(rdev, 999 &radeon_crtc->ss, 1000 ATOM_DP_SS_ID1); 1001 } else { 1002 radeon_crtc->ss_enabled = 1003 radeon_atombios_get_ppll_ss_info(rdev, 1004 &radeon_crtc->ss, 1005 ATOM_DP_SS_ID1); 1006 } 1007 /* disable spread spectrum on DCE3 DP */ 1008 radeon_crtc->ss_enabled = false; 1009 } 1010 break; 1011 case ATOM_ENCODER_MODE_LVDS: 1012 if (ASIC_IS_DCE4(rdev)) 1013 radeon_crtc->ss_enabled = 1014 radeon_atombios_get_asic_ss_info(rdev, 1015 &radeon_crtc->ss, 1016 dig->lcd_ss_id, 1017 mode->clock / 10); 1018 else 1019 radeon_crtc->ss_enabled = 1020 radeon_atombios_get_ppll_ss_info(rdev, 1021 &radeon_crtc->ss, 1022 dig->lcd_ss_id); 1023 break; 1024 case ATOM_ENCODER_MODE_DVI: 1025 if (ASIC_IS_DCE4(rdev)) 1026 radeon_crtc->ss_enabled = 1027 radeon_atombios_get_asic_ss_info(rdev, 1028 &radeon_crtc->ss, 1029 ASIC_INTERNAL_SS_ON_TMDS, 1030 mode->clock / 10); 1031 break; 1032 case ATOM_ENCODER_MODE_HDMI: 1033 if (ASIC_IS_DCE4(rdev)) 1034 radeon_crtc->ss_enabled = 1035 radeon_atombios_get_asic_ss_info(rdev, 1036 &radeon_crtc->ss, 1037 ASIC_INTERNAL_SS_ON_HDMI, 1038 mode->clock / 10); 1039 break; 1040 default: 1041 break; 1042 } 1043 } 1044 1045 /* adjust pixel clock as needed */ 1046 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 1047 1048 return true; 1049 } 1050 1051 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 1052 { 1053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1054 struct drm_device *dev = crtc->dev; 1055 struct radeon_device *rdev = dev->dev_private; 1056 struct radeon_encoder *radeon_encoder = 1057 to_radeon_encoder(radeon_crtc->encoder); 1058 u32 pll_clock = mode->clock; 1059 u32 clock = mode->clock; 1060 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1061 struct radeon_pll *pll; 1062 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1063 1064 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1065 if (ASIC_IS_DCE5(rdev) && 1066 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1067 (radeon_crtc->bpc > 8)) 1068 clock = radeon_crtc->adjusted_clock; 1069 1070 switch (radeon_crtc->pll_id) { 1071 case ATOM_PPLL1: 1072 pll = &rdev->clock.p1pll; 1073 break; 1074 case ATOM_PPLL2: 1075 pll = &rdev->clock.p2pll; 1076 break; 1077 case ATOM_DCPLL: 1078 case ATOM_PPLL_INVALID: 1079 default: 1080 pll = &rdev->clock.dcpll; 1081 break; 1082 } 1083 1084 /* update pll params */ 1085 pll->flags = radeon_crtc->pll_flags; 1086 pll->reference_div = radeon_crtc->pll_reference_div; 1087 pll->post_div = radeon_crtc->pll_post_div; 1088 1089 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1090 /* TV seems to prefer the legacy algo on some boards */ 1091 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1092 &fb_div, &frac_fb_div, &ref_div, &post_div); 1093 else if (ASIC_IS_AVIVO(rdev)) 1094 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1095 &fb_div, &frac_fb_div, &ref_div, &post_div); 1096 else 1097 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1098 &fb_div, &frac_fb_div, &ref_div, &post_div); 1099 1100 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1101 radeon_crtc->crtc_id, &radeon_crtc->ss); 1102 1103 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1104 encoder_mode, radeon_encoder->encoder_id, clock, 1105 ref_div, fb_div, frac_fb_div, post_div, 1106 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1107 1108 if (radeon_crtc->ss_enabled) { 1109 /* calculate ss amount and step size */ 1110 if (ASIC_IS_DCE4(rdev)) { 1111 u32 step_size; 1112 u32 amount = (((fb_div * 10) + frac_fb_div) * 1113 (u32)radeon_crtc->ss.percentage) / 1114 (100 * (u32)radeon_crtc->ss.percentage_divider); 1115 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1116 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1117 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1118 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1119 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1120 (125 * 25 * pll->reference_freq / 100); 1121 else 1122 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1123 (125 * 25 * pll->reference_freq / 100); 1124 radeon_crtc->ss.step = step_size; 1125 } 1126 1127 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1128 radeon_crtc->crtc_id, &radeon_crtc->ss); 1129 } 1130 } 1131 1132 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1133 struct drm_framebuffer *fb, 1134 int x, int y, int atomic) 1135 { 1136 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1137 struct drm_device *dev = crtc->dev; 1138 struct radeon_device *rdev = dev->dev_private; 1139 struct radeon_framebuffer *radeon_fb; 1140 struct drm_framebuffer *target_fb; 1141 struct drm_gem_object *obj; 1142 struct radeon_bo *rbo; 1143 uint64_t fb_location; 1144 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1145 unsigned bankw, bankh, mtaspect, tile_split; 1146 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1147 u32 tmp, viewport_w, viewport_h; 1148 int r; 1149 bool bypass_lut = false; 1150 1151 /* no fb bound */ 1152 if (!atomic && !crtc->primary->fb) { 1153 DRM_DEBUG_KMS("No FB bound\n"); 1154 return 0; 1155 } 1156 1157 if (atomic) { 1158 radeon_fb = to_radeon_framebuffer(fb); 1159 target_fb = fb; 1160 } 1161 else { 1162 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1163 target_fb = crtc->primary->fb; 1164 } 1165 1166 /* If atomic, assume fb object is pinned & idle & fenced and 1167 * just update base pointers 1168 */ 1169 obj = radeon_fb->obj; 1170 rbo = gem_to_radeon_bo(obj); 1171 r = radeon_bo_reserve(rbo, false); 1172 if (unlikely(r != 0)) 1173 return r; 1174 1175 if (atomic) 1176 fb_location = radeon_bo_gpu_offset(rbo); 1177 else { 1178 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location); 1179 if (unlikely(r != 0)) { 1180 radeon_bo_unreserve(rbo); 1181 return -EINVAL; 1182 } 1183 } 1184 1185 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1186 radeon_bo_unreserve(rbo); 1187 1188 switch (target_fb->pixel_format) { 1189 case DRM_FORMAT_C8: 1190 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1191 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1192 break; 1193 case DRM_FORMAT_XRGB4444: 1194 case DRM_FORMAT_ARGB4444: 1195 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1196 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1197 #ifdef __BIG_ENDIAN 1198 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1199 #endif 1200 break; 1201 case DRM_FORMAT_XRGB1555: 1202 case DRM_FORMAT_ARGB1555: 1203 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1204 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1205 #ifdef __BIG_ENDIAN 1206 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1207 #endif 1208 break; 1209 case DRM_FORMAT_BGRX5551: 1210 case DRM_FORMAT_BGRA5551: 1211 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1212 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1213 #ifdef __BIG_ENDIAN 1214 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1215 #endif 1216 break; 1217 case DRM_FORMAT_RGB565: 1218 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1219 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1220 #ifdef __BIG_ENDIAN 1221 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1222 #endif 1223 break; 1224 case DRM_FORMAT_XRGB8888: 1225 case DRM_FORMAT_ARGB8888: 1226 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1227 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1228 #ifdef __BIG_ENDIAN 1229 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1230 #endif 1231 break; 1232 case DRM_FORMAT_XRGB2101010: 1233 case DRM_FORMAT_ARGB2101010: 1234 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1235 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1236 #ifdef __BIG_ENDIAN 1237 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1238 #endif 1239 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1240 bypass_lut = true; 1241 break; 1242 case DRM_FORMAT_BGRX1010102: 1243 case DRM_FORMAT_BGRA1010102: 1244 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1245 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1246 #ifdef __BIG_ENDIAN 1247 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1248 #endif 1249 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1250 bypass_lut = true; 1251 break; 1252 default: 1253 DRM_ERROR("Unsupported screen format %s\n", 1254 drm_get_format_name(target_fb->pixel_format)); 1255 return -EINVAL; 1256 } 1257 1258 if (tiling_flags & RADEON_TILING_MACRO) { 1259 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1260 1261 /* Set NUM_BANKS. */ 1262 if (rdev->family >= CHIP_TAHITI) { 1263 unsigned index, num_banks; 1264 1265 if (rdev->family >= CHIP_BONAIRE) { 1266 unsigned tileb, tile_split_bytes; 1267 1268 /* Calculate the macrotile mode index. */ 1269 tile_split_bytes = 64 << tile_split; 1270 tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1271 tileb = min(tile_split_bytes, tileb); 1272 1273 for (index = 0; tileb > 64; index++) 1274 tileb >>= 1; 1275 1276 if (index >= 16) { 1277 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1278 target_fb->bits_per_pixel, tile_split); 1279 return -EINVAL; 1280 } 1281 1282 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1283 } else { 1284 switch (target_fb->bits_per_pixel) { 1285 case 8: 1286 index = 10; 1287 break; 1288 case 16: 1289 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1290 break; 1291 default: 1292 case 32: 1293 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1294 break; 1295 } 1296 1297 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1298 } 1299 1300 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1301 } else { 1302 /* NI and older. */ 1303 if (rdev->family >= CHIP_CAYMAN) 1304 tmp = rdev->config.cayman.tile_config; 1305 else 1306 tmp = rdev->config.evergreen.tile_config; 1307 1308 switch ((tmp & 0xf0) >> 4) { 1309 case 0: /* 4 banks */ 1310 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1311 break; 1312 case 1: /* 8 banks */ 1313 default: 1314 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1315 break; 1316 case 2: /* 16 banks */ 1317 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1318 break; 1319 } 1320 } 1321 1322 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1323 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1324 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1325 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1326 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1327 if (rdev->family >= CHIP_BONAIRE) { 1328 /* XXX need to know more about the surface tiling mode */ 1329 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1330 } 1331 } else if (tiling_flags & RADEON_TILING_MICRO) 1332 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1333 1334 if (rdev->family >= CHIP_BONAIRE) { 1335 /* Read the pipe config from the 2D TILED SCANOUT mode. 1336 * It should be the same for the other modes too, but not all 1337 * modes set the pipe config field. */ 1338 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1339 1340 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1341 } else if ((rdev->family == CHIP_TAHITI) || 1342 (rdev->family == CHIP_PITCAIRN)) 1343 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1344 else if ((rdev->family == CHIP_VERDE) || 1345 (rdev->family == CHIP_OLAND) || 1346 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1347 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1348 1349 switch (radeon_crtc->crtc_id) { 1350 case 0: 1351 WREG32(AVIVO_D1VGA_CONTROL, 0); 1352 break; 1353 case 1: 1354 WREG32(AVIVO_D2VGA_CONTROL, 0); 1355 break; 1356 case 2: 1357 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1358 break; 1359 case 3: 1360 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1361 break; 1362 case 4: 1363 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1364 break; 1365 case 5: 1366 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 /* Make sure surface address is updated at vertical blank rather than 1373 * horizontal blank 1374 */ 1375 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1376 1377 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1378 upper_32_bits(fb_location)); 1379 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1380 upper_32_bits(fb_location)); 1381 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1382 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1383 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1384 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1385 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1386 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1387 1388 /* 1389 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1390 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1391 * retain the full precision throughout the pipeline. 1392 */ 1393 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1394 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1395 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1396 1397 if (bypass_lut) 1398 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1399 1400 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1401 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1402 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1403 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1404 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1405 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1406 1407 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1408 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1409 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1410 1411 if (rdev->family >= CHIP_BONAIRE) 1412 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1413 target_fb->height); 1414 else 1415 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1416 target_fb->height); 1417 x &= ~3; 1418 y &= ~1; 1419 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1420 (x << 16) | y); 1421 viewport_w = crtc->mode.hdisplay; 1422 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1423 if ((rdev->family >= CHIP_BONAIRE) && 1424 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) 1425 viewport_h *= 2; 1426 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1427 (viewport_w << 16) | viewport_h); 1428 1429 /* set pageflip to happen only at start of vblank interval (front porch) */ 1430 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1431 1432 if (!atomic && fb && fb != crtc->primary->fb) { 1433 radeon_fb = to_radeon_framebuffer(fb); 1434 rbo = gem_to_radeon_bo(radeon_fb->obj); 1435 r = radeon_bo_reserve(rbo, false); 1436 if (unlikely(r != 0)) 1437 return r; 1438 radeon_bo_unpin(rbo); 1439 radeon_bo_unreserve(rbo); 1440 } 1441 1442 /* Bytes per pixel may have changed */ 1443 radeon_bandwidth_update(rdev); 1444 1445 return 0; 1446 } 1447 1448 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1449 struct drm_framebuffer *fb, 1450 int x, int y, int atomic) 1451 { 1452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1453 struct drm_device *dev = crtc->dev; 1454 struct radeon_device *rdev = dev->dev_private; 1455 struct radeon_framebuffer *radeon_fb; 1456 struct drm_gem_object *obj; 1457 struct radeon_bo *rbo; 1458 struct drm_framebuffer *target_fb; 1459 uint64_t fb_location; 1460 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1461 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1462 u32 viewport_w, viewport_h; 1463 int r; 1464 bool bypass_lut = false; 1465 1466 /* no fb bound */ 1467 if (!atomic && !crtc->primary->fb) { 1468 DRM_DEBUG_KMS("No FB bound\n"); 1469 return 0; 1470 } 1471 1472 if (atomic) { 1473 radeon_fb = to_radeon_framebuffer(fb); 1474 target_fb = fb; 1475 } 1476 else { 1477 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1478 target_fb = crtc->primary->fb; 1479 } 1480 1481 obj = radeon_fb->obj; 1482 rbo = gem_to_radeon_bo(obj); 1483 r = radeon_bo_reserve(rbo, false); 1484 if (unlikely(r != 0)) 1485 return r; 1486 1487 /* If atomic, assume fb object is pinned & idle & fenced and 1488 * just update base pointers 1489 */ 1490 if (atomic) 1491 fb_location = radeon_bo_gpu_offset(rbo); 1492 else { 1493 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location); 1494 if (unlikely(r != 0)) { 1495 radeon_bo_unreserve(rbo); 1496 return -EINVAL; 1497 } 1498 } 1499 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1500 radeon_bo_unreserve(rbo); 1501 1502 switch (target_fb->pixel_format) { 1503 case DRM_FORMAT_C8: 1504 fb_format = 1505 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1506 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1507 break; 1508 case DRM_FORMAT_XRGB4444: 1509 case DRM_FORMAT_ARGB4444: 1510 fb_format = 1511 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1512 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1513 #ifdef __BIG_ENDIAN 1514 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1515 #endif 1516 break; 1517 case DRM_FORMAT_XRGB1555: 1518 fb_format = 1519 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1520 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1521 #ifdef __BIG_ENDIAN 1522 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1523 #endif 1524 break; 1525 case DRM_FORMAT_RGB565: 1526 fb_format = 1527 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1528 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1529 #ifdef __BIG_ENDIAN 1530 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1531 #endif 1532 break; 1533 case DRM_FORMAT_XRGB8888: 1534 case DRM_FORMAT_ARGB8888: 1535 fb_format = 1536 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1537 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1538 #ifdef __BIG_ENDIAN 1539 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1540 #endif 1541 break; 1542 case DRM_FORMAT_XRGB2101010: 1543 case DRM_FORMAT_ARGB2101010: 1544 fb_format = 1545 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1546 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1547 #ifdef __BIG_ENDIAN 1548 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1549 #endif 1550 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1551 bypass_lut = true; 1552 break; 1553 default: 1554 DRM_ERROR("Unsupported screen format %s\n", 1555 drm_get_format_name(target_fb->pixel_format)); 1556 return -EINVAL; 1557 } 1558 1559 if (rdev->family >= CHIP_R600) { 1560 if (tiling_flags & RADEON_TILING_MACRO) 1561 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1562 else if (tiling_flags & RADEON_TILING_MICRO) 1563 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1564 } else { 1565 if (tiling_flags & RADEON_TILING_MACRO) 1566 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1567 1568 if (tiling_flags & RADEON_TILING_MICRO) 1569 fb_format |= AVIVO_D1GRPH_TILED; 1570 } 1571 1572 if (radeon_crtc->crtc_id == 0) 1573 WREG32(AVIVO_D1VGA_CONTROL, 0); 1574 else 1575 WREG32(AVIVO_D2VGA_CONTROL, 0); 1576 1577 /* Make sure surface address is update at vertical blank rather than 1578 * horizontal blank 1579 */ 1580 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1581 1582 if (rdev->family >= CHIP_RV770) { 1583 if (radeon_crtc->crtc_id) { 1584 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1585 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1586 } else { 1587 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1588 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1589 } 1590 } 1591 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1592 (u32) fb_location); 1593 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1594 radeon_crtc->crtc_offset, (u32) fb_location); 1595 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1596 if (rdev->family >= CHIP_R600) 1597 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1598 1599 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1600 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1601 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1602 1603 if (bypass_lut) 1604 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1605 1606 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1607 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1608 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1609 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1610 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1611 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1612 1613 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1614 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1615 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1616 1617 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1618 target_fb->height); 1619 x &= ~3; 1620 y &= ~1; 1621 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1622 (x << 16) | y); 1623 viewport_w = crtc->mode.hdisplay; 1624 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1625 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1626 (viewport_w << 16) | viewport_h); 1627 1628 /* set pageflip to happen only at start of vblank interval (front porch) */ 1629 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1630 1631 if (!atomic && fb && fb != crtc->primary->fb) { 1632 radeon_fb = to_radeon_framebuffer(fb); 1633 rbo = gem_to_radeon_bo(radeon_fb->obj); 1634 r = radeon_bo_reserve(rbo, false); 1635 if (unlikely(r != 0)) 1636 return r; 1637 radeon_bo_unpin(rbo); 1638 radeon_bo_unreserve(rbo); 1639 } 1640 1641 /* Bytes per pixel may have changed */ 1642 radeon_bandwidth_update(rdev); 1643 1644 return 0; 1645 } 1646 1647 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1648 struct drm_framebuffer *old_fb) 1649 { 1650 struct drm_device *dev = crtc->dev; 1651 struct radeon_device *rdev = dev->dev_private; 1652 1653 if (ASIC_IS_DCE4(rdev)) 1654 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1655 else if (ASIC_IS_AVIVO(rdev)) 1656 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1657 else 1658 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1659 } 1660 1661 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1662 struct drm_framebuffer *fb, 1663 int x, int y, enum mode_set_atomic state) 1664 { 1665 struct drm_device *dev = crtc->dev; 1666 struct radeon_device *rdev = dev->dev_private; 1667 1668 if (ASIC_IS_DCE4(rdev)) 1669 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1670 else if (ASIC_IS_AVIVO(rdev)) 1671 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1672 else 1673 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1674 } 1675 1676 /* properly set additional regs when using atombios */ 1677 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1678 { 1679 struct drm_device *dev = crtc->dev; 1680 struct radeon_device *rdev = dev->dev_private; 1681 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1682 u32 disp_merge_cntl; 1683 1684 switch (radeon_crtc->crtc_id) { 1685 case 0: 1686 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1687 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1688 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1689 break; 1690 case 1: 1691 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1692 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1693 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1694 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1695 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1696 break; 1697 } 1698 } 1699 1700 /** 1701 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1702 * 1703 * @crtc: drm crtc 1704 * 1705 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1706 */ 1707 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1708 { 1709 struct drm_device *dev = crtc->dev; 1710 struct drm_crtc *test_crtc; 1711 struct radeon_crtc *test_radeon_crtc; 1712 u32 pll_in_use = 0; 1713 1714 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1715 if (crtc == test_crtc) 1716 continue; 1717 1718 test_radeon_crtc = to_radeon_crtc(test_crtc); 1719 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1720 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1721 } 1722 return pll_in_use; 1723 } 1724 1725 /** 1726 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1727 * 1728 * @crtc: drm crtc 1729 * 1730 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1731 * also in DP mode. For DP, a single PPLL can be used for all DP 1732 * crtcs/encoders. 1733 */ 1734 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1735 { 1736 struct drm_device *dev = crtc->dev; 1737 struct radeon_device *rdev = dev->dev_private; 1738 struct drm_crtc *test_crtc; 1739 struct radeon_crtc *test_radeon_crtc; 1740 1741 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1742 if (crtc == test_crtc) 1743 continue; 1744 test_radeon_crtc = to_radeon_crtc(test_crtc); 1745 if (test_radeon_crtc->encoder && 1746 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1747 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1748 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1749 test_radeon_crtc->pll_id == ATOM_PPLL2) 1750 continue; 1751 /* for DP use the same PLL for all */ 1752 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1753 return test_radeon_crtc->pll_id; 1754 } 1755 } 1756 return ATOM_PPLL_INVALID; 1757 } 1758 1759 /** 1760 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1761 * 1762 * @crtc: drm crtc 1763 * @encoder: drm encoder 1764 * 1765 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1766 * be shared (i.e., same clock). 1767 */ 1768 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1769 { 1770 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1771 struct drm_device *dev = crtc->dev; 1772 struct radeon_device *rdev = dev->dev_private; 1773 struct drm_crtc *test_crtc; 1774 struct radeon_crtc *test_radeon_crtc; 1775 u32 adjusted_clock, test_adjusted_clock; 1776 1777 adjusted_clock = radeon_crtc->adjusted_clock; 1778 1779 if (adjusted_clock == 0) 1780 return ATOM_PPLL_INVALID; 1781 1782 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1783 if (crtc == test_crtc) 1784 continue; 1785 test_radeon_crtc = to_radeon_crtc(test_crtc); 1786 if (test_radeon_crtc->encoder && 1787 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1788 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1789 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1790 test_radeon_crtc->pll_id == ATOM_PPLL2) 1791 continue; 1792 /* check if we are already driving this connector with another crtc */ 1793 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1794 /* if we are, return that pll */ 1795 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1796 return test_radeon_crtc->pll_id; 1797 } 1798 /* for non-DP check the clock */ 1799 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1800 if ((crtc->mode.clock == test_crtc->mode.clock) && 1801 (adjusted_clock == test_adjusted_clock) && 1802 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1803 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1804 return test_radeon_crtc->pll_id; 1805 } 1806 } 1807 return ATOM_PPLL_INVALID; 1808 } 1809 1810 /** 1811 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1812 * 1813 * @crtc: drm crtc 1814 * 1815 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1816 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1817 * monitors a dedicated PPLL must be used. If a particular board has 1818 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1819 * as there is no need to program the PLL itself. If we are not able to 1820 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1821 * avoid messing up an existing monitor. 1822 * 1823 * Asic specific PLL information 1824 * 1825 * DCE 8.x 1826 * KB/KV 1827 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1828 * CI 1829 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1830 * 1831 * DCE 6.1 1832 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1833 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1834 * 1835 * DCE 6.0 1836 * - PPLL0 is available to all UNIPHY (DP only) 1837 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1838 * 1839 * DCE 5.0 1840 * - DCPLL is available to all UNIPHY (DP only) 1841 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1842 * 1843 * DCE 3.0/4.0/4.1 1844 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1845 * 1846 */ 1847 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1848 { 1849 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1850 struct drm_device *dev = crtc->dev; 1851 struct radeon_device *rdev = dev->dev_private; 1852 struct radeon_encoder *radeon_encoder = 1853 to_radeon_encoder(radeon_crtc->encoder); 1854 u32 pll_in_use; 1855 int pll; 1856 1857 if (ASIC_IS_DCE8(rdev)) { 1858 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1859 if (rdev->clock.dp_extclk) 1860 /* skip PPLL programming if using ext clock */ 1861 return ATOM_PPLL_INVALID; 1862 else { 1863 /* use the same PPLL for all DP monitors */ 1864 pll = radeon_get_shared_dp_ppll(crtc); 1865 if (pll != ATOM_PPLL_INVALID) 1866 return pll; 1867 } 1868 } else { 1869 /* use the same PPLL for all monitors with the same clock */ 1870 pll = radeon_get_shared_nondp_ppll(crtc); 1871 if (pll != ATOM_PPLL_INVALID) 1872 return pll; 1873 } 1874 /* otherwise, pick one of the plls */ 1875 if ((rdev->family == CHIP_KABINI) || 1876 (rdev->family == CHIP_MULLINS)) { 1877 /* KB/ML has PPLL1 and PPLL2 */ 1878 pll_in_use = radeon_get_pll_use_mask(crtc); 1879 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1880 return ATOM_PPLL2; 1881 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1882 return ATOM_PPLL1; 1883 DRM_ERROR("unable to allocate a PPLL\n"); 1884 return ATOM_PPLL_INVALID; 1885 } else { 1886 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 1887 pll_in_use = radeon_get_pll_use_mask(crtc); 1888 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1889 return ATOM_PPLL2; 1890 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1891 return ATOM_PPLL1; 1892 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1893 return ATOM_PPLL0; 1894 DRM_ERROR("unable to allocate a PPLL\n"); 1895 return ATOM_PPLL_INVALID; 1896 } 1897 } else if (ASIC_IS_DCE61(rdev)) { 1898 struct radeon_encoder_atom_dig *dig = 1899 radeon_encoder->enc_priv; 1900 1901 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1902 (dig->linkb == false)) 1903 /* UNIPHY A uses PPLL2 */ 1904 return ATOM_PPLL2; 1905 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1906 /* UNIPHY B/C/D/E/F */ 1907 if (rdev->clock.dp_extclk) 1908 /* skip PPLL programming if using ext clock */ 1909 return ATOM_PPLL_INVALID; 1910 else { 1911 /* use the same PPLL for all DP monitors */ 1912 pll = radeon_get_shared_dp_ppll(crtc); 1913 if (pll != ATOM_PPLL_INVALID) 1914 return pll; 1915 } 1916 } else { 1917 /* use the same PPLL for all monitors with the same clock */ 1918 pll = radeon_get_shared_nondp_ppll(crtc); 1919 if (pll != ATOM_PPLL_INVALID) 1920 return pll; 1921 } 1922 /* UNIPHY B/C/D/E/F */ 1923 pll_in_use = radeon_get_pll_use_mask(crtc); 1924 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1925 return ATOM_PPLL0; 1926 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1927 return ATOM_PPLL1; 1928 DRM_ERROR("unable to allocate a PPLL\n"); 1929 return ATOM_PPLL_INVALID; 1930 } else if (ASIC_IS_DCE41(rdev)) { 1931 /* Don't share PLLs on DCE4.1 chips */ 1932 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1933 if (rdev->clock.dp_extclk) 1934 /* skip PPLL programming if using ext clock */ 1935 return ATOM_PPLL_INVALID; 1936 } 1937 pll_in_use = radeon_get_pll_use_mask(crtc); 1938 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1939 return ATOM_PPLL1; 1940 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1941 return ATOM_PPLL2; 1942 DRM_ERROR("unable to allocate a PPLL\n"); 1943 return ATOM_PPLL_INVALID; 1944 } else if (ASIC_IS_DCE4(rdev)) { 1945 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1946 * depending on the asic: 1947 * DCE4: PPLL or ext clock 1948 * DCE5: PPLL, DCPLL, or ext clock 1949 * DCE6: PPLL, PPLL0, or ext clock 1950 * 1951 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1952 * PPLL/DCPLL programming and only program the DP DTO for the 1953 * crtc virtual pixel clock. 1954 */ 1955 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1956 if (rdev->clock.dp_extclk) 1957 /* skip PPLL programming if using ext clock */ 1958 return ATOM_PPLL_INVALID; 1959 else if (ASIC_IS_DCE6(rdev)) 1960 /* use PPLL0 for all DP */ 1961 return ATOM_PPLL0; 1962 else if (ASIC_IS_DCE5(rdev)) 1963 /* use DCPLL for all DP */ 1964 return ATOM_DCPLL; 1965 else { 1966 /* use the same PPLL for all DP monitors */ 1967 pll = radeon_get_shared_dp_ppll(crtc); 1968 if (pll != ATOM_PPLL_INVALID) 1969 return pll; 1970 } 1971 } else { 1972 /* use the same PPLL for all monitors with the same clock */ 1973 pll = radeon_get_shared_nondp_ppll(crtc); 1974 if (pll != ATOM_PPLL_INVALID) 1975 return pll; 1976 } 1977 /* all other cases */ 1978 pll_in_use = radeon_get_pll_use_mask(crtc); 1979 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1980 return ATOM_PPLL1; 1981 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1982 return ATOM_PPLL2; 1983 DRM_ERROR("unable to allocate a PPLL\n"); 1984 return ATOM_PPLL_INVALID; 1985 } else { 1986 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1987 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1988 * the matching btw pll and crtc is done through 1989 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1990 * pll (1 or 2) to select which register to write. ie if using 1991 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1992 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1993 * choose which value to write. Which is reverse order from 1994 * register logic. So only case that works is when pllid is 1995 * same as crtcid or when both pll and crtc are enabled and 1996 * both use same clock. 1997 * 1998 * So just return crtc id as if crtc and pll were hard linked 1999 * together even if they aren't 2000 */ 2001 return radeon_crtc->crtc_id; 2002 } 2003 } 2004 2005 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 2006 { 2007 /* always set DCPLL */ 2008 if (ASIC_IS_DCE6(rdev)) 2009 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2010 else if (ASIC_IS_DCE4(rdev)) { 2011 struct radeon_atom_ss ss; 2012 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 2013 ASIC_INTERNAL_SS_ON_DCPLL, 2014 rdev->clock.default_dispclk); 2015 if (ss_enabled) 2016 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 2017 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 2018 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2019 if (ss_enabled) 2020 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 2021 } 2022 2023 } 2024 2025 int atombios_crtc_mode_set(struct drm_crtc *crtc, 2026 struct drm_display_mode *mode, 2027 struct drm_display_mode *adjusted_mode, 2028 int x, int y, struct drm_framebuffer *old_fb) 2029 { 2030 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2031 struct drm_device *dev = crtc->dev; 2032 struct radeon_device *rdev = dev->dev_private; 2033 struct radeon_encoder *radeon_encoder = 2034 to_radeon_encoder(radeon_crtc->encoder); 2035 bool is_tvcv = false; 2036 2037 if (radeon_encoder->active_device & 2038 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2039 is_tvcv = true; 2040 2041 if (!radeon_crtc->adjusted_clock) 2042 return -EINVAL; 2043 2044 atombios_crtc_set_pll(crtc, adjusted_mode); 2045 2046 if (ASIC_IS_DCE4(rdev)) 2047 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2048 else if (ASIC_IS_AVIVO(rdev)) { 2049 if (is_tvcv) 2050 atombios_crtc_set_timing(crtc, adjusted_mode); 2051 else 2052 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2053 } else { 2054 atombios_crtc_set_timing(crtc, adjusted_mode); 2055 if (radeon_crtc->crtc_id == 0) 2056 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2057 radeon_legacy_atom_fixup(crtc); 2058 } 2059 atombios_crtc_set_base(crtc, x, y, old_fb); 2060 atombios_overscan_setup(crtc, mode, adjusted_mode); 2061 atombios_scaler_setup(crtc); 2062 radeon_cursor_reset(crtc); 2063 /* update the hw version fpr dpm */ 2064 radeon_crtc->hw_mode = *adjusted_mode; 2065 2066 return 0; 2067 } 2068 2069 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 2070 const struct drm_display_mode *mode, 2071 struct drm_display_mode *adjusted_mode) 2072 { 2073 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2074 struct drm_device *dev = crtc->dev; 2075 struct drm_encoder *encoder; 2076 2077 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 2078 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2079 if (encoder->crtc == crtc) { 2080 radeon_crtc->encoder = encoder; 2081 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 2082 break; 2083 } 2084 } 2085 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 2086 radeon_crtc->encoder = NULL; 2087 radeon_crtc->connector = NULL; 2088 return false; 2089 } 2090 if (radeon_crtc->encoder) { 2091 struct radeon_encoder *radeon_encoder = 2092 to_radeon_encoder(radeon_crtc->encoder); 2093 2094 radeon_crtc->output_csc = radeon_encoder->output_csc; 2095 } 2096 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2097 return false; 2098 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2099 return false; 2100 /* pick pll */ 2101 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 2102 /* if we can't get a PPLL for a non-DP encoder, fail */ 2103 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 2104 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 2105 return false; 2106 2107 return true; 2108 } 2109 2110 static void atombios_crtc_prepare(struct drm_crtc *crtc) 2111 { 2112 struct drm_device *dev = crtc->dev; 2113 struct radeon_device *rdev = dev->dev_private; 2114 2115 /* disable crtc pair power gating before programming */ 2116 if (ASIC_IS_DCE6(rdev)) 2117 atombios_powergate_crtc(crtc, ATOM_DISABLE); 2118 2119 atombios_lock_crtc(crtc, ATOM_ENABLE); 2120 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2121 } 2122 2123 static void atombios_crtc_commit(struct drm_crtc *crtc) 2124 { 2125 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2126 atombios_lock_crtc(crtc, ATOM_DISABLE); 2127 } 2128 2129 static void atombios_crtc_disable(struct drm_crtc *crtc) 2130 { 2131 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2132 struct drm_device *dev = crtc->dev; 2133 struct radeon_device *rdev = dev->dev_private; 2134 struct radeon_atom_ss ss; 2135 int i; 2136 2137 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2138 if (crtc->primary->fb) { 2139 int r; 2140 struct radeon_framebuffer *radeon_fb; 2141 struct radeon_bo *rbo; 2142 2143 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 2144 rbo = gem_to_radeon_bo(radeon_fb->obj); 2145 r = radeon_bo_reserve(rbo, false); 2146 if (unlikely(r)) 2147 DRM_ERROR("failed to reserve rbo before unpin\n"); 2148 else { 2149 radeon_bo_unpin(rbo); 2150 radeon_bo_unreserve(rbo); 2151 } 2152 } 2153 /* disable the GRPH */ 2154 if (ASIC_IS_DCE4(rdev)) 2155 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2156 else if (ASIC_IS_AVIVO(rdev)) 2157 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2158 2159 if (ASIC_IS_DCE6(rdev)) 2160 atombios_powergate_crtc(crtc, ATOM_ENABLE); 2161 2162 for (i = 0; i < rdev->num_crtc; i++) { 2163 if (rdev->mode_info.crtcs[i] && 2164 rdev->mode_info.crtcs[i]->enabled && 2165 i != radeon_crtc->crtc_id && 2166 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 2167 /* one other crtc is using this pll don't turn 2168 * off the pll 2169 */ 2170 goto done; 2171 } 2172 } 2173 2174 switch (radeon_crtc->pll_id) { 2175 case ATOM_PPLL1: 2176 case ATOM_PPLL2: 2177 /* disable the ppll */ 2178 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2179 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2180 break; 2181 case ATOM_PPLL0: 2182 /* disable the ppll */ 2183 if ((rdev->family == CHIP_ARUBA) || 2184 (rdev->family == CHIP_KAVERI) || 2185 (rdev->family == CHIP_BONAIRE) || 2186 (rdev->family == CHIP_HAWAII)) 2187 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2188 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2189 break; 2190 default: 2191 break; 2192 } 2193 done: 2194 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2195 radeon_crtc->adjusted_clock = 0; 2196 radeon_crtc->encoder = NULL; 2197 radeon_crtc->connector = NULL; 2198 } 2199 2200 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 2201 .dpms = atombios_crtc_dpms, 2202 .mode_fixup = atombios_crtc_mode_fixup, 2203 .mode_set = atombios_crtc_mode_set, 2204 .mode_set_base = atombios_crtc_set_base, 2205 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 2206 .prepare = atombios_crtc_prepare, 2207 .commit = atombios_crtc_commit, 2208 .load_lut = radeon_crtc_load_lut, 2209 .disable = atombios_crtc_disable, 2210 }; 2211 2212 void radeon_atombios_init_crtc(struct drm_device *dev, 2213 struct radeon_crtc *radeon_crtc) 2214 { 2215 struct radeon_device *rdev = dev->dev_private; 2216 2217 if (ASIC_IS_DCE4(rdev)) { 2218 switch (radeon_crtc->crtc_id) { 2219 case 0: 2220 default: 2221 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2222 break; 2223 case 1: 2224 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2225 break; 2226 case 2: 2227 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2228 break; 2229 case 3: 2230 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2231 break; 2232 case 4: 2233 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2234 break; 2235 case 5: 2236 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2237 break; 2238 } 2239 } else { 2240 if (radeon_crtc->crtc_id == 1) 2241 radeon_crtc->crtc_offset = 2242 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2243 else 2244 radeon_crtc->crtc_offset = 0; 2245 } 2246 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2247 radeon_crtc->adjusted_clock = 0; 2248 radeon_crtc->encoder = NULL; 2249 radeon_crtc->connector = NULL; 2250 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2251 } 2252