1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/atombios_crtc.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include <drm/drm_fixed.h> 33 #include "radeon.h" 34 #include "atom.h" 35 #include "atom-bits.h" 36 37 static void atombios_overscan_setup(struct drm_crtc *crtc, 38 struct drm_display_mode *mode, 39 struct drm_display_mode *adjusted_mode) 40 { 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 44 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 45 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 46 int a1, a2; 47 48 memset(&args, 0, sizeof(args)); 49 50 args.ucCRTC = radeon_crtc->crtc_id; 51 52 switch (radeon_crtc->rmx_type) { 53 case RMX_CENTER: 54 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 55 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 56 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 57 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 58 break; 59 case RMX_ASPECT: 60 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 61 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 62 63 if (a1 > a2) { 64 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 65 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 66 } else if (a2 > a1) { 67 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 68 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 69 } 70 break; 71 case RMX_FULL: 72 default: 73 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 74 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 75 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 76 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 77 break; 78 } 79 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 80 } 81 82 static void atombios_scaler_setup(struct drm_crtc *crtc) 83 { 84 struct drm_device *dev = crtc->dev; 85 struct radeon_device *rdev = dev->dev_private; 86 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 87 ENABLE_SCALER_PS_ALLOCATION args; 88 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 89 struct radeon_encoder *radeon_encoder = 90 to_radeon_encoder(radeon_crtc->encoder); 91 /* fixme - fill in enc_priv for atom dac */ 92 enum radeon_tv_std tv_std = TV_STD_NTSC; 93 bool is_tv = false, is_cv = false; 94 95 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 96 return; 97 98 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 100 tv_std = tv_dac->tv_std; 101 is_tv = true; 102 } 103 104 memset(&args, 0, sizeof(args)); 105 106 args.ucScaler = radeon_crtc->crtc_id; 107 108 if (is_tv) { 109 switch (tv_std) { 110 case TV_STD_NTSC: 111 default: 112 args.ucTVStandard = ATOM_TV_NTSC; 113 break; 114 case TV_STD_PAL: 115 args.ucTVStandard = ATOM_TV_PAL; 116 break; 117 case TV_STD_PAL_M: 118 args.ucTVStandard = ATOM_TV_PALM; 119 break; 120 case TV_STD_PAL_60: 121 args.ucTVStandard = ATOM_TV_PAL60; 122 break; 123 case TV_STD_NTSC_J: 124 args.ucTVStandard = ATOM_TV_NTSCJ; 125 break; 126 case TV_STD_SCART_PAL: 127 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 128 break; 129 case TV_STD_SECAM: 130 args.ucTVStandard = ATOM_TV_SECAM; 131 break; 132 case TV_STD_PAL_CN: 133 args.ucTVStandard = ATOM_TV_PALCN; 134 break; 135 } 136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 137 } else if (is_cv) { 138 args.ucTVStandard = ATOM_TV_CV; 139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 140 } else { 141 switch (radeon_crtc->rmx_type) { 142 case RMX_FULL: 143 args.ucEnable = ATOM_SCALER_EXPANSION; 144 break; 145 case RMX_CENTER: 146 args.ucEnable = ATOM_SCALER_CENTER; 147 break; 148 case RMX_ASPECT: 149 args.ucEnable = ATOM_SCALER_EXPANSION; 150 break; 151 default: 152 if (ASIC_IS_AVIVO(rdev)) 153 args.ucEnable = ATOM_SCALER_DISABLE; 154 else 155 args.ucEnable = ATOM_SCALER_CENTER; 156 break; 157 } 158 } 159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 160 if ((is_tv || is_cv) 161 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 162 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 163 } 164 } 165 166 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 167 { 168 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 169 struct drm_device *dev = crtc->dev; 170 struct radeon_device *rdev = dev->dev_private; 171 int index = 172 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 173 ENABLE_CRTC_PS_ALLOCATION args; 174 175 memset(&args, 0, sizeof(args)); 176 177 args.ucCRTC = radeon_crtc->crtc_id; 178 args.ucEnable = lock; 179 180 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 181 } 182 183 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 184 { 185 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 186 struct drm_device *dev = crtc->dev; 187 struct radeon_device *rdev = dev->dev_private; 188 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 189 ENABLE_CRTC_PS_ALLOCATION args; 190 191 memset(&args, 0, sizeof(args)); 192 193 args.ucCRTC = radeon_crtc->crtc_id; 194 args.ucEnable = state; 195 196 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 197 } 198 199 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 200 { 201 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 202 struct drm_device *dev = crtc->dev; 203 struct radeon_device *rdev = dev->dev_private; 204 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 205 ENABLE_CRTC_PS_ALLOCATION args; 206 207 memset(&args, 0, sizeof(args)); 208 209 args.ucCRTC = radeon_crtc->crtc_id; 210 args.ucEnable = state; 211 212 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 213 } 214 215 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 216 { 217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 218 struct drm_device *dev = crtc->dev; 219 struct radeon_device *rdev = dev->dev_private; 220 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 221 BLANK_CRTC_PS_ALLOCATION args; 222 223 memset(&args, 0, sizeof(args)); 224 225 args.ucCRTC = radeon_crtc->crtc_id; 226 args.ucBlanking = state; 227 228 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 229 } 230 231 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 232 { 233 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 234 struct drm_device *dev = crtc->dev; 235 struct radeon_device *rdev = dev->dev_private; 236 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 237 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 238 239 memset(&args, 0, sizeof(args)); 240 241 args.ucDispPipeId = radeon_crtc->crtc_id; 242 args.ucEnable = state; 243 244 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 245 } 246 247 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 248 { 249 struct drm_device *dev = crtc->dev; 250 struct radeon_device *rdev = dev->dev_private; 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 253 switch (mode) { 254 case DRM_MODE_DPMS_ON: 255 radeon_crtc->enabled = true; 256 /* adjust pm to dpms changes BEFORE enabling crtcs */ 257 radeon_pm_compute_clocks(rdev); 258 atombios_enable_crtc(crtc, ATOM_ENABLE); 259 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 260 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 261 atombios_blank_crtc(crtc, ATOM_DISABLE); 262 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 263 radeon_crtc_load_lut(crtc); 264 break; 265 case DRM_MODE_DPMS_STANDBY: 266 case DRM_MODE_DPMS_SUSPEND: 267 case DRM_MODE_DPMS_OFF: 268 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 269 if (radeon_crtc->enabled) 270 atombios_blank_crtc(crtc, ATOM_ENABLE); 271 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 272 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 273 atombios_enable_crtc(crtc, ATOM_DISABLE); 274 radeon_crtc->enabled = false; 275 /* adjust pm to dpms changes AFTER disabling crtcs */ 276 radeon_pm_compute_clocks(rdev); 277 break; 278 } 279 } 280 281 static void 282 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 283 struct drm_display_mode *mode) 284 { 285 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 286 struct drm_device *dev = crtc->dev; 287 struct radeon_device *rdev = dev->dev_private; 288 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 289 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 290 u16 misc = 0; 291 292 memset(&args, 0, sizeof(args)); 293 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 294 args.usH_Blanking_Time = 295 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 296 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 297 args.usV_Blanking_Time = 298 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 299 args.usH_SyncOffset = 300 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 301 args.usH_SyncWidth = 302 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 303 args.usV_SyncOffset = 304 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 305 args.usV_SyncWidth = 306 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 307 args.ucH_Border = radeon_crtc->h_border; 308 args.ucV_Border = radeon_crtc->v_border; 309 310 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 311 misc |= ATOM_VSYNC_POLARITY; 312 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 313 misc |= ATOM_HSYNC_POLARITY; 314 if (mode->flags & DRM_MODE_FLAG_CSYNC) 315 misc |= ATOM_COMPOSITESYNC; 316 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 317 misc |= ATOM_INTERLACE; 318 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 319 misc |= ATOM_DOUBLE_CLOCK_MODE; 320 321 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 322 args.ucCRTC = radeon_crtc->crtc_id; 323 324 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 325 } 326 327 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 328 struct drm_display_mode *mode) 329 { 330 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 331 struct drm_device *dev = crtc->dev; 332 struct radeon_device *rdev = dev->dev_private; 333 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 334 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 335 u16 misc = 0; 336 337 memset(&args, 0, sizeof(args)); 338 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 339 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 340 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 341 args.usH_SyncWidth = 342 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 343 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 344 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 345 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 346 args.usV_SyncWidth = 347 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 348 349 args.ucOverscanRight = radeon_crtc->h_border; 350 args.ucOverscanLeft = radeon_crtc->h_border; 351 args.ucOverscanBottom = radeon_crtc->v_border; 352 args.ucOverscanTop = radeon_crtc->v_border; 353 354 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 355 misc |= ATOM_VSYNC_POLARITY; 356 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 357 misc |= ATOM_HSYNC_POLARITY; 358 if (mode->flags & DRM_MODE_FLAG_CSYNC) 359 misc |= ATOM_COMPOSITESYNC; 360 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 361 misc |= ATOM_INTERLACE; 362 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 363 misc |= ATOM_DOUBLE_CLOCK_MODE; 364 365 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 366 args.ucCRTC = radeon_crtc->crtc_id; 367 368 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 369 } 370 371 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 372 { 373 u32 ss_cntl; 374 375 if (ASIC_IS_DCE4(rdev)) { 376 switch (pll_id) { 377 case ATOM_PPLL1: 378 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 379 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 380 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 381 break; 382 case ATOM_PPLL2: 383 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 384 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 385 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 386 break; 387 case ATOM_DCPLL: 388 case ATOM_PPLL_INVALID: 389 return; 390 } 391 } else if (ASIC_IS_AVIVO(rdev)) { 392 switch (pll_id) { 393 case ATOM_PPLL1: 394 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 395 ss_cntl &= ~1; 396 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 397 break; 398 case ATOM_PPLL2: 399 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 400 ss_cntl &= ~1; 401 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 402 break; 403 case ATOM_DCPLL: 404 case ATOM_PPLL_INVALID: 405 return; 406 } 407 } 408 } 409 410 411 union atom_enable_ss { 412 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 413 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 414 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 415 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 416 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 417 }; 418 419 static void atombios_crtc_program_ss(struct radeon_device *rdev, 420 int enable, 421 int pll_id, 422 int crtc_id, 423 struct radeon_atom_ss *ss) 424 { 425 unsigned i; 426 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 427 union atom_enable_ss args; 428 429 if (!enable) { 430 for (i = 0; i < rdev->num_crtc; i++) { 431 if (rdev->mode_info.crtcs[i] && 432 rdev->mode_info.crtcs[i]->enabled && 433 i != crtc_id && 434 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 435 /* one other crtc is using this pll don't turn 436 * off spread spectrum as it might turn off 437 * display on active crtc 438 */ 439 return; 440 } 441 } 442 } 443 444 memset(&args, 0, sizeof(args)); 445 446 if (ASIC_IS_DCE5(rdev)) { 447 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 448 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 449 switch (pll_id) { 450 case ATOM_PPLL1: 451 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 452 break; 453 case ATOM_PPLL2: 454 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 455 break; 456 case ATOM_DCPLL: 457 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 458 break; 459 case ATOM_PPLL_INVALID: 460 return; 461 } 462 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 463 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 464 args.v3.ucEnable = enable; 465 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 466 args.v3.ucEnable = ATOM_DISABLE; 467 } else if (ASIC_IS_DCE4(rdev)) { 468 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 469 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 470 switch (pll_id) { 471 case ATOM_PPLL1: 472 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 473 break; 474 case ATOM_PPLL2: 475 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 476 break; 477 case ATOM_DCPLL: 478 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 479 break; 480 case ATOM_PPLL_INVALID: 481 return; 482 } 483 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 484 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 485 args.v2.ucEnable = enable; 486 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 487 args.v2.ucEnable = ATOM_DISABLE; 488 } else if (ASIC_IS_DCE3(rdev)) { 489 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 490 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 491 args.v1.ucSpreadSpectrumStep = ss->step; 492 args.v1.ucSpreadSpectrumDelay = ss->delay; 493 args.v1.ucSpreadSpectrumRange = ss->range; 494 args.v1.ucPpll = pll_id; 495 args.v1.ucEnable = enable; 496 } else if (ASIC_IS_AVIVO(rdev)) { 497 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 498 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 499 atombios_disable_ss(rdev, pll_id); 500 return; 501 } 502 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 503 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 504 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 505 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 506 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 507 args.lvds_ss_2.ucEnable = enable; 508 } else { 509 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 510 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 511 atombios_disable_ss(rdev, pll_id); 512 return; 513 } 514 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 515 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 516 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 517 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 518 args.lvds_ss.ucEnable = enable; 519 } 520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 521 } 522 523 union adjust_pixel_clock { 524 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 525 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 526 }; 527 528 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 529 struct drm_display_mode *mode) 530 { 531 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 532 struct drm_device *dev = crtc->dev; 533 struct radeon_device *rdev = dev->dev_private; 534 struct drm_encoder *encoder = radeon_crtc->encoder; 535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 536 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 537 u32 adjusted_clock = mode->clock; 538 int encoder_mode = atombios_get_encoder_mode(encoder); 539 u32 dp_clock = mode->clock; 540 int bpc = radeon_get_monitor_bpc(connector); 541 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 542 543 /* reset the pll flags */ 544 radeon_crtc->pll_flags = 0; 545 546 if (ASIC_IS_AVIVO(rdev)) { 547 if ((rdev->family == CHIP_RS600) || 548 (rdev->family == CHIP_RS690) || 549 (rdev->family == CHIP_RS740)) 550 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 551 RADEON_PLL_PREFER_CLOSEST_LOWER); 552 553 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 554 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 555 else 556 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 557 558 if (rdev->family < CHIP_RV770) 559 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 560 /* use frac fb div on APUs */ 561 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 562 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 563 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 564 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 565 } else { 566 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 567 568 if (mode->clock > 200000) /* range limits??? */ 569 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 570 else 571 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 572 } 573 574 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 575 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 576 if (connector) { 577 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 578 struct radeon_connector_atom_dig *dig_connector = 579 radeon_connector->con_priv; 580 581 dp_clock = dig_connector->dp_clock; 582 } 583 } 584 585 /* use recommended ref_div for ss */ 586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 587 if (radeon_crtc->ss_enabled) { 588 if (radeon_crtc->ss.refdiv) { 589 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 590 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 591 if (ASIC_IS_AVIVO(rdev)) 592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 593 } 594 } 595 } 596 597 if (ASIC_IS_AVIVO(rdev)) { 598 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 599 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 600 adjusted_clock = mode->clock * 2; 601 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 602 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 604 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 605 } else { 606 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 607 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 608 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 609 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 610 } 611 612 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 613 * accordingly based on the encoder/transmitter to work around 614 * special hw requirements. 615 */ 616 if (ASIC_IS_DCE3(rdev)) { 617 union adjust_pixel_clock args; 618 u8 frev, crev; 619 int index; 620 621 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 622 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 623 &crev)) 624 return adjusted_clock; 625 626 memset(&args, 0, sizeof(args)); 627 628 switch (frev) { 629 case 1: 630 switch (crev) { 631 case 1: 632 case 2: 633 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 634 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 635 args.v1.ucEncodeMode = encoder_mode; 636 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 637 args.v1.ucConfig |= 638 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 639 640 atom_execute_table(rdev->mode_info.atom_context, 641 index, (uint32_t *)&args); 642 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 643 break; 644 case 3: 645 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 646 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 647 args.v3.sInput.ucEncodeMode = encoder_mode; 648 args.v3.sInput.ucDispPllConfig = 0; 649 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 650 args.v3.sInput.ucDispPllConfig |= 651 DISPPLL_CONFIG_SS_ENABLE; 652 if (ENCODER_MODE_IS_DP(encoder_mode)) { 653 args.v3.sInput.ucDispPllConfig |= 654 DISPPLL_CONFIG_COHERENT_MODE; 655 /* 16200 or 27000 */ 656 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 657 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 658 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 659 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 660 /* deep color support */ 661 args.v3.sInput.usPixelClock = 662 cpu_to_le16((mode->clock * bpc / 8) / 10); 663 if (dig->coherent_mode) 664 args.v3.sInput.ucDispPllConfig |= 665 DISPPLL_CONFIG_COHERENT_MODE; 666 if (is_duallink) 667 args.v3.sInput.ucDispPllConfig |= 668 DISPPLL_CONFIG_DUAL_LINK; 669 } 670 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 671 ENCODER_OBJECT_ID_NONE) 672 args.v3.sInput.ucExtTransmitterID = 673 radeon_encoder_get_dp_bridge_encoder_id(encoder); 674 else 675 args.v3.sInput.ucExtTransmitterID = 0; 676 677 atom_execute_table(rdev->mode_info.atom_context, 678 index, (uint32_t *)&args); 679 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 680 if (args.v3.sOutput.ucRefDiv) { 681 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 682 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 683 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 684 } 685 if (args.v3.sOutput.ucPostDiv) { 686 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 687 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 688 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 689 } 690 break; 691 default: 692 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 693 return adjusted_clock; 694 } 695 break; 696 default: 697 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 698 return adjusted_clock; 699 } 700 } 701 return adjusted_clock; 702 } 703 704 union set_pixel_clock { 705 SET_PIXEL_CLOCK_PS_ALLOCATION base; 706 PIXEL_CLOCK_PARAMETERS v1; 707 PIXEL_CLOCK_PARAMETERS_V2 v2; 708 PIXEL_CLOCK_PARAMETERS_V3 v3; 709 PIXEL_CLOCK_PARAMETERS_V5 v5; 710 PIXEL_CLOCK_PARAMETERS_V6 v6; 711 }; 712 713 /* on DCE5, make sure the voltage is high enough to support the 714 * required disp clk. 715 */ 716 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 717 u32 dispclk) 718 { 719 u8 frev, crev; 720 int index; 721 union set_pixel_clock args; 722 723 memset(&args, 0, sizeof(args)); 724 725 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 726 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 727 &crev)) 728 return; 729 730 switch (frev) { 731 case 1: 732 switch (crev) { 733 case 5: 734 /* if the default dcpll clock is specified, 735 * SetPixelClock provides the dividers 736 */ 737 args.v5.ucCRTC = ATOM_CRTC_INVALID; 738 args.v5.usPixelClock = cpu_to_le16(dispclk); 739 args.v5.ucPpll = ATOM_DCPLL; 740 break; 741 case 6: 742 /* if the default dcpll clock is specified, 743 * SetPixelClock provides the dividers 744 */ 745 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 746 if (ASIC_IS_DCE61(rdev)) 747 args.v6.ucPpll = ATOM_EXT_PLL1; 748 else if (ASIC_IS_DCE6(rdev)) 749 args.v6.ucPpll = ATOM_PPLL0; 750 else 751 args.v6.ucPpll = ATOM_DCPLL; 752 break; 753 default: 754 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 755 return; 756 } 757 break; 758 default: 759 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 760 return; 761 } 762 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 763 } 764 765 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 766 u32 crtc_id, 767 int pll_id, 768 u32 encoder_mode, 769 u32 encoder_id, 770 u32 clock, 771 u32 ref_div, 772 u32 fb_div, 773 u32 frac_fb_div, 774 u32 post_div, 775 int bpc, 776 bool ss_enabled, 777 struct radeon_atom_ss *ss) 778 { 779 struct drm_device *dev = crtc->dev; 780 struct radeon_device *rdev = dev->dev_private; 781 u8 frev, crev; 782 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 783 union set_pixel_clock args; 784 785 memset(&args, 0, sizeof(args)); 786 787 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 788 &crev)) 789 return; 790 791 switch (frev) { 792 case 1: 793 switch (crev) { 794 case 1: 795 if (clock == ATOM_DISABLE) 796 return; 797 args.v1.usPixelClock = cpu_to_le16(clock / 10); 798 args.v1.usRefDiv = cpu_to_le16(ref_div); 799 args.v1.usFbDiv = cpu_to_le16(fb_div); 800 args.v1.ucFracFbDiv = frac_fb_div; 801 args.v1.ucPostDiv = post_div; 802 args.v1.ucPpll = pll_id; 803 args.v1.ucCRTC = crtc_id; 804 args.v1.ucRefDivSrc = 1; 805 break; 806 case 2: 807 args.v2.usPixelClock = cpu_to_le16(clock / 10); 808 args.v2.usRefDiv = cpu_to_le16(ref_div); 809 args.v2.usFbDiv = cpu_to_le16(fb_div); 810 args.v2.ucFracFbDiv = frac_fb_div; 811 args.v2.ucPostDiv = post_div; 812 args.v2.ucPpll = pll_id; 813 args.v2.ucCRTC = crtc_id; 814 args.v2.ucRefDivSrc = 1; 815 break; 816 case 3: 817 args.v3.usPixelClock = cpu_to_le16(clock / 10); 818 args.v3.usRefDiv = cpu_to_le16(ref_div); 819 args.v3.usFbDiv = cpu_to_le16(fb_div); 820 args.v3.ucFracFbDiv = frac_fb_div; 821 args.v3.ucPostDiv = post_div; 822 args.v3.ucPpll = pll_id; 823 if (crtc_id == ATOM_CRTC2) 824 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 825 else 826 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 827 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 828 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 829 args.v3.ucTransmitterId = encoder_id; 830 args.v3.ucEncoderMode = encoder_mode; 831 break; 832 case 5: 833 args.v5.ucCRTC = crtc_id; 834 args.v5.usPixelClock = cpu_to_le16(clock / 10); 835 args.v5.ucRefDiv = ref_div; 836 args.v5.usFbDiv = cpu_to_le16(fb_div); 837 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 838 args.v5.ucPostDiv = post_div; 839 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 840 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 841 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 842 switch (bpc) { 843 case 8: 844 default: 845 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 846 break; 847 case 10: 848 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 849 break; 850 } 851 args.v5.ucTransmitterID = encoder_id; 852 args.v5.ucEncoderMode = encoder_mode; 853 args.v5.ucPpll = pll_id; 854 break; 855 case 6: 856 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 857 args.v6.ucRefDiv = ref_div; 858 args.v6.usFbDiv = cpu_to_le16(fb_div); 859 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 860 args.v6.ucPostDiv = post_div; 861 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 862 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 863 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 864 switch (bpc) { 865 case 8: 866 default: 867 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 868 break; 869 case 10: 870 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 871 break; 872 case 12: 873 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 874 break; 875 case 16: 876 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 877 break; 878 } 879 args.v6.ucTransmitterID = encoder_id; 880 args.v6.ucEncoderMode = encoder_mode; 881 args.v6.ucPpll = pll_id; 882 break; 883 default: 884 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 885 return; 886 } 887 break; 888 default: 889 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 890 return; 891 } 892 893 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 894 } 895 896 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 897 { 898 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 899 struct drm_device *dev = crtc->dev; 900 struct radeon_device *rdev = dev->dev_private; 901 struct radeon_encoder *radeon_encoder = 902 to_radeon_encoder(radeon_crtc->encoder); 903 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 904 905 radeon_crtc->bpc = 8; 906 radeon_crtc->ss_enabled = false; 907 908 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 909 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 910 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 911 struct drm_connector *connector = 912 radeon_get_connector_for_encoder(radeon_crtc->encoder); 913 struct radeon_connector *radeon_connector = 914 to_radeon_connector(connector); 915 struct radeon_connector_atom_dig *dig_connector = 916 radeon_connector->con_priv; 917 int dp_clock; 918 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 919 920 switch (encoder_mode) { 921 case ATOM_ENCODER_MODE_DP_MST: 922 case ATOM_ENCODER_MODE_DP: 923 /* DP/eDP */ 924 dp_clock = dig_connector->dp_clock / 10; 925 if (ASIC_IS_DCE4(rdev)) 926 radeon_crtc->ss_enabled = 927 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 928 ASIC_INTERNAL_SS_ON_DP, 929 dp_clock); 930 else { 931 if (dp_clock == 16200) { 932 radeon_crtc->ss_enabled = 933 radeon_atombios_get_ppll_ss_info(rdev, 934 &radeon_crtc->ss, 935 ATOM_DP_SS_ID2); 936 if (!radeon_crtc->ss_enabled) 937 radeon_crtc->ss_enabled = 938 radeon_atombios_get_ppll_ss_info(rdev, 939 &radeon_crtc->ss, 940 ATOM_DP_SS_ID1); 941 } else 942 radeon_crtc->ss_enabled = 943 radeon_atombios_get_ppll_ss_info(rdev, 944 &radeon_crtc->ss, 945 ATOM_DP_SS_ID1); 946 } 947 break; 948 case ATOM_ENCODER_MODE_LVDS: 949 if (ASIC_IS_DCE4(rdev)) 950 radeon_crtc->ss_enabled = 951 radeon_atombios_get_asic_ss_info(rdev, 952 &radeon_crtc->ss, 953 dig->lcd_ss_id, 954 mode->clock / 10); 955 else 956 radeon_crtc->ss_enabled = 957 radeon_atombios_get_ppll_ss_info(rdev, 958 &radeon_crtc->ss, 959 dig->lcd_ss_id); 960 break; 961 case ATOM_ENCODER_MODE_DVI: 962 if (ASIC_IS_DCE4(rdev)) 963 radeon_crtc->ss_enabled = 964 radeon_atombios_get_asic_ss_info(rdev, 965 &radeon_crtc->ss, 966 ASIC_INTERNAL_SS_ON_TMDS, 967 mode->clock / 10); 968 break; 969 case ATOM_ENCODER_MODE_HDMI: 970 if (ASIC_IS_DCE4(rdev)) 971 radeon_crtc->ss_enabled = 972 radeon_atombios_get_asic_ss_info(rdev, 973 &radeon_crtc->ss, 974 ASIC_INTERNAL_SS_ON_HDMI, 975 mode->clock / 10); 976 break; 977 default: 978 break; 979 } 980 } 981 982 /* adjust pixel clock as needed */ 983 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 984 985 return true; 986 } 987 988 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 989 { 990 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 991 struct drm_device *dev = crtc->dev; 992 struct radeon_device *rdev = dev->dev_private; 993 struct radeon_encoder *radeon_encoder = 994 to_radeon_encoder(radeon_crtc->encoder); 995 u32 pll_clock = mode->clock; 996 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 997 struct radeon_pll *pll; 998 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 999 1000 switch (radeon_crtc->pll_id) { 1001 case ATOM_PPLL1: 1002 pll = &rdev->clock.p1pll; 1003 break; 1004 case ATOM_PPLL2: 1005 pll = &rdev->clock.p2pll; 1006 break; 1007 case ATOM_DCPLL: 1008 case ATOM_PPLL_INVALID: 1009 default: 1010 pll = &rdev->clock.dcpll; 1011 break; 1012 } 1013 1014 /* update pll params */ 1015 pll->flags = radeon_crtc->pll_flags; 1016 pll->reference_div = radeon_crtc->pll_reference_div; 1017 pll->post_div = radeon_crtc->pll_post_div; 1018 1019 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1020 /* TV seems to prefer the legacy algo on some boards */ 1021 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1022 &fb_div, &frac_fb_div, &ref_div, &post_div); 1023 else if (ASIC_IS_AVIVO(rdev)) 1024 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1025 &fb_div, &frac_fb_div, &ref_div, &post_div); 1026 else 1027 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1028 &fb_div, &frac_fb_div, &ref_div, &post_div); 1029 1030 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1031 radeon_crtc->crtc_id, &radeon_crtc->ss); 1032 1033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1034 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1035 ref_div, fb_div, frac_fb_div, post_div, 1036 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1037 1038 if (radeon_crtc->ss_enabled) { 1039 /* calculate ss amount and step size */ 1040 if (ASIC_IS_DCE4(rdev)) { 1041 u32 step_size; 1042 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 1043 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1044 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1045 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1046 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1047 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1048 (125 * 25 * pll->reference_freq / 100); 1049 else 1050 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1051 (125 * 25 * pll->reference_freq / 100); 1052 radeon_crtc->ss.step = step_size; 1053 } 1054 1055 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1056 radeon_crtc->crtc_id, &radeon_crtc->ss); 1057 } 1058 } 1059 1060 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1061 struct drm_framebuffer *fb, 1062 int x, int y, int atomic) 1063 { 1064 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1065 struct drm_device *dev = crtc->dev; 1066 struct radeon_device *rdev = dev->dev_private; 1067 struct radeon_framebuffer *radeon_fb; 1068 struct drm_framebuffer *target_fb; 1069 struct drm_gem_object *obj; 1070 struct radeon_bo *rbo; 1071 uint64_t fb_location; 1072 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1073 unsigned bankw, bankh, mtaspect, tile_split; 1074 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1075 u32 tmp, viewport_w, viewport_h; 1076 int r; 1077 1078 /* no fb bound */ 1079 if (!atomic && !crtc->fb) { 1080 DRM_DEBUG_KMS("No FB bound\n"); 1081 return 0; 1082 } 1083 1084 if (atomic) { 1085 radeon_fb = to_radeon_framebuffer(fb); 1086 target_fb = fb; 1087 } 1088 else { 1089 radeon_fb = to_radeon_framebuffer(crtc->fb); 1090 target_fb = crtc->fb; 1091 } 1092 1093 /* If atomic, assume fb object is pinned & idle & fenced and 1094 * just update base pointers 1095 */ 1096 obj = radeon_fb->obj; 1097 rbo = gem_to_radeon_bo(obj); 1098 r = radeon_bo_reserve(rbo, false); 1099 if (unlikely(r != 0)) 1100 return r; 1101 1102 if (atomic) 1103 fb_location = radeon_bo_gpu_offset(rbo); 1104 else { 1105 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1106 if (unlikely(r != 0)) { 1107 radeon_bo_unreserve(rbo); 1108 return -EINVAL; 1109 } 1110 } 1111 1112 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1113 radeon_bo_unreserve(rbo); 1114 1115 switch (target_fb->bits_per_pixel) { 1116 case 8: 1117 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1118 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1119 break; 1120 case 15: 1121 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1122 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1123 break; 1124 case 16: 1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1127 #ifdef __BIG_ENDIAN 1128 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1129 #endif 1130 break; 1131 case 24: 1132 case 32: 1133 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1134 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1135 #ifdef __BIG_ENDIAN 1136 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1137 #endif 1138 break; 1139 default: 1140 DRM_ERROR("Unsupported screen depth %d\n", 1141 target_fb->bits_per_pixel); 1142 return -EINVAL; 1143 } 1144 1145 if (tiling_flags & RADEON_TILING_MACRO) { 1146 if (rdev->family >= CHIP_TAHITI) 1147 tmp = rdev->config.si.tile_config; 1148 else if (rdev->family >= CHIP_CAYMAN) 1149 tmp = rdev->config.cayman.tile_config; 1150 else 1151 tmp = rdev->config.evergreen.tile_config; 1152 1153 switch ((tmp & 0xf0) >> 4) { 1154 case 0: /* 4 banks */ 1155 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1156 break; 1157 case 1: /* 8 banks */ 1158 default: 1159 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1160 break; 1161 case 2: /* 16 banks */ 1162 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1163 break; 1164 } 1165 1166 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1167 1168 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1169 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1170 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1171 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1172 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1173 } else if (tiling_flags & RADEON_TILING_MICRO) 1174 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1175 1176 if ((rdev->family == CHIP_TAHITI) || 1177 (rdev->family == CHIP_PITCAIRN)) 1178 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1179 else if (rdev->family == CHIP_VERDE) 1180 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1181 1182 switch (radeon_crtc->crtc_id) { 1183 case 0: 1184 WREG32(AVIVO_D1VGA_CONTROL, 0); 1185 break; 1186 case 1: 1187 WREG32(AVIVO_D2VGA_CONTROL, 0); 1188 break; 1189 case 2: 1190 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1191 break; 1192 case 3: 1193 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1194 break; 1195 case 4: 1196 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1197 break; 1198 case 5: 1199 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1200 break; 1201 default: 1202 break; 1203 } 1204 1205 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1206 upper_32_bits(fb_location)); 1207 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1208 upper_32_bits(fb_location)); 1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1210 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1212 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1213 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1214 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1215 1216 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1217 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1218 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1219 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1220 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1221 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1222 1223 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1224 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1225 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1226 1227 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1228 target_fb->height); 1229 x &= ~3; 1230 y &= ~1; 1231 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1232 (x << 16) | y); 1233 viewport_w = crtc->mode.hdisplay; 1234 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1235 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1236 (viewport_w << 16) | viewport_h); 1237 1238 /* pageflip setup */ 1239 /* make sure flip is at vb rather than hb */ 1240 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1241 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1242 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1243 1244 /* set pageflip to happen anywhere in vblank interval */ 1245 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1246 1247 if (!atomic && fb && fb != crtc->fb) { 1248 radeon_fb = to_radeon_framebuffer(fb); 1249 rbo = gem_to_radeon_bo(radeon_fb->obj); 1250 r = radeon_bo_reserve(rbo, false); 1251 if (unlikely(r != 0)) 1252 return r; 1253 radeon_bo_unpin(rbo); 1254 radeon_bo_unreserve(rbo); 1255 } 1256 1257 /* Bytes per pixel may have changed */ 1258 radeon_bandwidth_update(rdev); 1259 1260 return 0; 1261 } 1262 1263 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1264 struct drm_framebuffer *fb, 1265 int x, int y, int atomic) 1266 { 1267 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1268 struct drm_device *dev = crtc->dev; 1269 struct radeon_device *rdev = dev->dev_private; 1270 struct radeon_framebuffer *radeon_fb; 1271 struct drm_gem_object *obj; 1272 struct radeon_bo *rbo; 1273 struct drm_framebuffer *target_fb; 1274 uint64_t fb_location; 1275 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1276 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1277 u32 tmp, viewport_w, viewport_h; 1278 int r; 1279 1280 /* no fb bound */ 1281 if (!atomic && !crtc->fb) { 1282 DRM_DEBUG_KMS("No FB bound\n"); 1283 return 0; 1284 } 1285 1286 if (atomic) { 1287 radeon_fb = to_radeon_framebuffer(fb); 1288 target_fb = fb; 1289 } 1290 else { 1291 radeon_fb = to_radeon_framebuffer(crtc->fb); 1292 target_fb = crtc->fb; 1293 } 1294 1295 obj = radeon_fb->obj; 1296 rbo = gem_to_radeon_bo(obj); 1297 r = radeon_bo_reserve(rbo, false); 1298 if (unlikely(r != 0)) 1299 return r; 1300 1301 /* If atomic, assume fb object is pinned & idle & fenced and 1302 * just update base pointers 1303 */ 1304 if (atomic) 1305 fb_location = radeon_bo_gpu_offset(rbo); 1306 else { 1307 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1308 if (unlikely(r != 0)) { 1309 radeon_bo_unreserve(rbo); 1310 return -EINVAL; 1311 } 1312 } 1313 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1314 radeon_bo_unreserve(rbo); 1315 1316 switch (target_fb->bits_per_pixel) { 1317 case 8: 1318 fb_format = 1319 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1320 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1321 break; 1322 case 15: 1323 fb_format = 1324 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1325 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1326 break; 1327 case 16: 1328 fb_format = 1329 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1330 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1331 #ifdef __BIG_ENDIAN 1332 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1333 #endif 1334 break; 1335 case 24: 1336 case 32: 1337 fb_format = 1338 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1339 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1340 #ifdef __BIG_ENDIAN 1341 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1342 #endif 1343 break; 1344 default: 1345 DRM_ERROR("Unsupported screen depth %d\n", 1346 target_fb->bits_per_pixel); 1347 return -EINVAL; 1348 } 1349 1350 if (rdev->family >= CHIP_R600) { 1351 if (tiling_flags & RADEON_TILING_MACRO) 1352 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1353 else if (tiling_flags & RADEON_TILING_MICRO) 1354 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1355 } else { 1356 if (tiling_flags & RADEON_TILING_MACRO) 1357 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1358 1359 if (tiling_flags & RADEON_TILING_MICRO) 1360 fb_format |= AVIVO_D1GRPH_TILED; 1361 } 1362 1363 if (radeon_crtc->crtc_id == 0) 1364 WREG32(AVIVO_D1VGA_CONTROL, 0); 1365 else 1366 WREG32(AVIVO_D2VGA_CONTROL, 0); 1367 1368 if (rdev->family >= CHIP_RV770) { 1369 if (radeon_crtc->crtc_id) { 1370 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1371 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1372 } else { 1373 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1374 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1375 } 1376 } 1377 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1378 (u32) fb_location); 1379 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1380 radeon_crtc->crtc_offset, (u32) fb_location); 1381 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1382 if (rdev->family >= CHIP_R600) 1383 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1384 1385 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1386 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1387 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1388 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1389 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1390 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1391 1392 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1393 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1394 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1395 1396 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1397 target_fb->height); 1398 x &= ~3; 1399 y &= ~1; 1400 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1401 (x << 16) | y); 1402 viewport_w = crtc->mode.hdisplay; 1403 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1404 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1405 (viewport_w << 16) | viewport_h); 1406 1407 /* pageflip setup */ 1408 /* make sure flip is at vb rather than hb */ 1409 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1410 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1411 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1412 1413 /* set pageflip to happen anywhere in vblank interval */ 1414 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1415 1416 if (!atomic && fb && fb != crtc->fb) { 1417 radeon_fb = to_radeon_framebuffer(fb); 1418 rbo = gem_to_radeon_bo(radeon_fb->obj); 1419 r = radeon_bo_reserve(rbo, false); 1420 if (unlikely(r != 0)) 1421 return r; 1422 radeon_bo_unpin(rbo); 1423 radeon_bo_unreserve(rbo); 1424 } 1425 1426 /* Bytes per pixel may have changed */ 1427 radeon_bandwidth_update(rdev); 1428 1429 return 0; 1430 } 1431 1432 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1433 struct drm_framebuffer *old_fb) 1434 { 1435 struct drm_device *dev = crtc->dev; 1436 struct radeon_device *rdev = dev->dev_private; 1437 1438 if (ASIC_IS_DCE4(rdev)) 1439 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1440 else if (ASIC_IS_AVIVO(rdev)) 1441 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1442 else 1443 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1444 } 1445 1446 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1447 struct drm_framebuffer *fb, 1448 int x, int y, enum mode_set_atomic state) 1449 { 1450 struct drm_device *dev = crtc->dev; 1451 struct radeon_device *rdev = dev->dev_private; 1452 1453 if (ASIC_IS_DCE4(rdev)) 1454 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1455 else if (ASIC_IS_AVIVO(rdev)) 1456 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1457 else 1458 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1459 } 1460 1461 /* properly set additional regs when using atombios */ 1462 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1463 { 1464 struct drm_device *dev = crtc->dev; 1465 struct radeon_device *rdev = dev->dev_private; 1466 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1467 u32 disp_merge_cntl; 1468 1469 switch (radeon_crtc->crtc_id) { 1470 case 0: 1471 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1472 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1473 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1474 break; 1475 case 1: 1476 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1477 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1478 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1479 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1480 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1481 break; 1482 } 1483 } 1484 1485 /** 1486 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1487 * 1488 * @crtc: drm crtc 1489 * 1490 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1491 */ 1492 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1493 { 1494 struct drm_device *dev = crtc->dev; 1495 struct drm_crtc *test_crtc; 1496 struct radeon_crtc *test_radeon_crtc; 1497 u32 pll_in_use = 0; 1498 1499 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1500 if (crtc == test_crtc) 1501 continue; 1502 1503 test_radeon_crtc = to_radeon_crtc(test_crtc); 1504 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1505 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1506 } 1507 return pll_in_use; 1508 } 1509 1510 /** 1511 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1512 * 1513 * @crtc: drm crtc 1514 * 1515 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1516 * also in DP mode. For DP, a single PPLL can be used for all DP 1517 * crtcs/encoders. 1518 */ 1519 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1520 { 1521 struct drm_device *dev = crtc->dev; 1522 struct drm_crtc *test_crtc; 1523 struct radeon_crtc *test_radeon_crtc; 1524 1525 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1526 if (crtc == test_crtc) 1527 continue; 1528 test_radeon_crtc = to_radeon_crtc(test_crtc); 1529 if (test_radeon_crtc->encoder && 1530 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1531 /* for DP use the same PLL for all */ 1532 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1533 return test_radeon_crtc->pll_id; 1534 } 1535 } 1536 return ATOM_PPLL_INVALID; 1537 } 1538 1539 /** 1540 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1541 * 1542 * @crtc: drm crtc 1543 * @encoder: drm encoder 1544 * 1545 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1546 * be shared (i.e., same clock). 1547 */ 1548 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1549 { 1550 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1551 struct drm_device *dev = crtc->dev; 1552 struct drm_crtc *test_crtc; 1553 struct radeon_crtc *test_radeon_crtc; 1554 u32 adjusted_clock, test_adjusted_clock; 1555 1556 adjusted_clock = radeon_crtc->adjusted_clock; 1557 1558 if (adjusted_clock == 0) 1559 return ATOM_PPLL_INVALID; 1560 1561 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1562 if (crtc == test_crtc) 1563 continue; 1564 test_radeon_crtc = to_radeon_crtc(test_crtc); 1565 if (test_radeon_crtc->encoder && 1566 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1567 /* check if we are already driving this connector with another crtc */ 1568 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1569 /* if we are, return that pll */ 1570 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1571 return test_radeon_crtc->pll_id; 1572 } 1573 /* for non-DP check the clock */ 1574 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1575 if ((crtc->mode.clock == test_crtc->mode.clock) && 1576 (adjusted_clock == test_adjusted_clock) && 1577 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1578 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1579 return test_radeon_crtc->pll_id; 1580 } 1581 } 1582 return ATOM_PPLL_INVALID; 1583 } 1584 1585 /** 1586 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1587 * 1588 * @crtc: drm crtc 1589 * 1590 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1591 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1592 * monitors a dedicated PPLL must be used. If a particular board has 1593 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1594 * as there is no need to program the PLL itself. If we are not able to 1595 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1596 * avoid messing up an existing monitor. 1597 * 1598 * Asic specific PLL information 1599 * 1600 * DCE 6.1 1601 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1602 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1603 * 1604 * DCE 6.0 1605 * - PPLL0 is available to all UNIPHY (DP only) 1606 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1607 * 1608 * DCE 5.0 1609 * - DCPLL is available to all UNIPHY (DP only) 1610 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1611 * 1612 * DCE 3.0/4.0/4.1 1613 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1614 * 1615 */ 1616 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1617 { 1618 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1619 struct drm_device *dev = crtc->dev; 1620 struct radeon_device *rdev = dev->dev_private; 1621 struct radeon_encoder *radeon_encoder = 1622 to_radeon_encoder(radeon_crtc->encoder); 1623 u32 pll_in_use; 1624 int pll; 1625 1626 if (ASIC_IS_DCE61(rdev)) { 1627 struct radeon_encoder_atom_dig *dig = 1628 radeon_encoder->enc_priv; 1629 1630 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1631 (dig->linkb == false)) 1632 /* UNIPHY A uses PPLL2 */ 1633 return ATOM_PPLL2; 1634 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1635 /* UNIPHY B/C/D/E/F */ 1636 if (rdev->clock.dp_extclk) 1637 /* skip PPLL programming if using ext clock */ 1638 return ATOM_PPLL_INVALID; 1639 else { 1640 /* use the same PPLL for all DP monitors */ 1641 pll = radeon_get_shared_dp_ppll(crtc); 1642 if (pll != ATOM_PPLL_INVALID) 1643 return pll; 1644 } 1645 } else { 1646 /* use the same PPLL for all monitors with the same clock */ 1647 pll = radeon_get_shared_nondp_ppll(crtc); 1648 if (pll != ATOM_PPLL_INVALID) 1649 return pll; 1650 } 1651 /* UNIPHY B/C/D/E/F */ 1652 pll_in_use = radeon_get_pll_use_mask(crtc); 1653 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1654 return ATOM_PPLL0; 1655 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1656 return ATOM_PPLL1; 1657 DRM_ERROR("unable to allocate a PPLL\n"); 1658 return ATOM_PPLL_INVALID; 1659 } else if (ASIC_IS_DCE4(rdev)) { 1660 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1661 * depending on the asic: 1662 * DCE4: PPLL or ext clock 1663 * DCE5: PPLL, DCPLL, or ext clock 1664 * DCE6: PPLL, PPLL0, or ext clock 1665 * 1666 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1667 * PPLL/DCPLL programming and only program the DP DTO for the 1668 * crtc virtual pixel clock. 1669 */ 1670 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1671 if (rdev->clock.dp_extclk) 1672 /* skip PPLL programming if using ext clock */ 1673 return ATOM_PPLL_INVALID; 1674 else if (ASIC_IS_DCE6(rdev)) 1675 /* use PPLL0 for all DP */ 1676 return ATOM_PPLL0; 1677 else if (ASIC_IS_DCE5(rdev)) 1678 /* use DCPLL for all DP */ 1679 return ATOM_DCPLL; 1680 else { 1681 /* use the same PPLL for all DP monitors */ 1682 pll = radeon_get_shared_dp_ppll(crtc); 1683 if (pll != ATOM_PPLL_INVALID) 1684 return pll; 1685 } 1686 } else { 1687 /* use the same PPLL for all monitors with the same clock */ 1688 pll = radeon_get_shared_nondp_ppll(crtc); 1689 if (pll != ATOM_PPLL_INVALID) 1690 return pll; 1691 } 1692 /* all other cases */ 1693 pll_in_use = radeon_get_pll_use_mask(crtc); 1694 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1695 return ATOM_PPLL1; 1696 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1697 return ATOM_PPLL2; 1698 DRM_ERROR("unable to allocate a PPLL\n"); 1699 return ATOM_PPLL_INVALID; 1700 } else { 1701 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1702 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1703 * the matching btw pll and crtc is done through 1704 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1705 * pll (1 or 2) to select which register to write. ie if using 1706 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1707 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1708 * choose which value to write. Which is reverse order from 1709 * register logic. So only case that works is when pllid is 1710 * same as crtcid or when both pll and crtc are enabled and 1711 * both use same clock. 1712 * 1713 * So just return crtc id as if crtc and pll were hard linked 1714 * together even if they aren't 1715 */ 1716 return radeon_crtc->crtc_id; 1717 } 1718 } 1719 1720 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 1721 { 1722 /* always set DCPLL */ 1723 if (ASIC_IS_DCE6(rdev)) 1724 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1725 else if (ASIC_IS_DCE4(rdev)) { 1726 struct radeon_atom_ss ss; 1727 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1728 ASIC_INTERNAL_SS_ON_DCPLL, 1729 rdev->clock.default_dispclk); 1730 if (ss_enabled) 1731 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 1732 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1733 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1734 if (ss_enabled) 1735 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 1736 } 1737 1738 } 1739 1740 int atombios_crtc_mode_set(struct drm_crtc *crtc, 1741 struct drm_display_mode *mode, 1742 struct drm_display_mode *adjusted_mode, 1743 int x, int y, struct drm_framebuffer *old_fb) 1744 { 1745 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1746 struct drm_device *dev = crtc->dev; 1747 struct radeon_device *rdev = dev->dev_private; 1748 struct radeon_encoder *radeon_encoder = 1749 to_radeon_encoder(radeon_crtc->encoder); 1750 bool is_tvcv = false; 1751 1752 if (radeon_encoder->active_device & 1753 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1754 is_tvcv = true; 1755 1756 atombios_crtc_set_pll(crtc, adjusted_mode); 1757 1758 if (ASIC_IS_DCE4(rdev)) 1759 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1760 else if (ASIC_IS_AVIVO(rdev)) { 1761 if (is_tvcv) 1762 atombios_crtc_set_timing(crtc, adjusted_mode); 1763 else 1764 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1765 } else { 1766 atombios_crtc_set_timing(crtc, adjusted_mode); 1767 if (radeon_crtc->crtc_id == 0) 1768 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1769 radeon_legacy_atom_fixup(crtc); 1770 } 1771 atombios_crtc_set_base(crtc, x, y, old_fb); 1772 atombios_overscan_setup(crtc, mode, adjusted_mode); 1773 atombios_scaler_setup(crtc); 1774 return 0; 1775 } 1776 1777 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1778 const struct drm_display_mode *mode, 1779 struct drm_display_mode *adjusted_mode) 1780 { 1781 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1782 struct drm_device *dev = crtc->dev; 1783 struct drm_encoder *encoder; 1784 1785 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 1786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1787 if (encoder->crtc == crtc) { 1788 radeon_crtc->encoder = encoder; 1789 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 1790 break; 1791 } 1792 } 1793 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 1794 radeon_crtc->encoder = NULL; 1795 radeon_crtc->connector = NULL; 1796 return false; 1797 } 1798 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1799 return false; 1800 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 1801 return false; 1802 /* pick pll */ 1803 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1804 /* if we can't get a PPLL for a non-DP encoder, fail */ 1805 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1806 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1807 return false; 1808 1809 return true; 1810 } 1811 1812 static void atombios_crtc_prepare(struct drm_crtc *crtc) 1813 { 1814 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1815 struct drm_device *dev = crtc->dev; 1816 struct radeon_device *rdev = dev->dev_private; 1817 1818 radeon_crtc->in_mode_set = true; 1819 1820 /* disable crtc pair power gating before programming */ 1821 if (ASIC_IS_DCE6(rdev)) 1822 atombios_powergate_crtc(crtc, ATOM_DISABLE); 1823 1824 atombios_lock_crtc(crtc, ATOM_ENABLE); 1825 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1826 } 1827 1828 static void atombios_crtc_commit(struct drm_crtc *crtc) 1829 { 1830 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1831 1832 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1833 atombios_lock_crtc(crtc, ATOM_DISABLE); 1834 radeon_crtc->in_mode_set = false; 1835 } 1836 1837 static void atombios_crtc_disable(struct drm_crtc *crtc) 1838 { 1839 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1840 struct drm_device *dev = crtc->dev; 1841 struct radeon_device *rdev = dev->dev_private; 1842 struct radeon_atom_ss ss; 1843 int i; 1844 1845 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1846 if (ASIC_IS_DCE6(rdev)) 1847 atombios_powergate_crtc(crtc, ATOM_ENABLE); 1848 1849 for (i = 0; i < rdev->num_crtc; i++) { 1850 if (rdev->mode_info.crtcs[i] && 1851 rdev->mode_info.crtcs[i]->enabled && 1852 i != radeon_crtc->crtc_id && 1853 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 1854 /* one other crtc is using this pll don't turn 1855 * off the pll 1856 */ 1857 goto done; 1858 } 1859 } 1860 1861 switch (radeon_crtc->pll_id) { 1862 case ATOM_PPLL1: 1863 case ATOM_PPLL2: 1864 /* disable the ppll */ 1865 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1866 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1867 break; 1868 case ATOM_PPLL0: 1869 /* disable the ppll */ 1870 if (ASIC_IS_DCE61(rdev)) 1871 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1872 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1873 break; 1874 default: 1875 break; 1876 } 1877 done: 1878 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1879 radeon_crtc->adjusted_clock = 0; 1880 radeon_crtc->encoder = NULL; 1881 radeon_crtc->connector = NULL; 1882 } 1883 1884 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1885 .dpms = atombios_crtc_dpms, 1886 .mode_fixup = atombios_crtc_mode_fixup, 1887 .mode_set = atombios_crtc_mode_set, 1888 .mode_set_base = atombios_crtc_set_base, 1889 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1890 .prepare = atombios_crtc_prepare, 1891 .commit = atombios_crtc_commit, 1892 .load_lut = radeon_crtc_load_lut, 1893 .disable = atombios_crtc_disable, 1894 }; 1895 1896 void radeon_atombios_init_crtc(struct drm_device *dev, 1897 struct radeon_crtc *radeon_crtc) 1898 { 1899 struct radeon_device *rdev = dev->dev_private; 1900 1901 if (ASIC_IS_DCE4(rdev)) { 1902 switch (radeon_crtc->crtc_id) { 1903 case 0: 1904 default: 1905 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1906 break; 1907 case 1: 1908 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1909 break; 1910 case 2: 1911 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1912 break; 1913 case 3: 1914 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1915 break; 1916 case 4: 1917 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1918 break; 1919 case 5: 1920 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1921 break; 1922 } 1923 } else { 1924 if (radeon_crtc->crtc_id == 1) 1925 radeon_crtc->crtc_offset = 1926 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1927 else 1928 radeon_crtc->crtc_offset = 0; 1929 } 1930 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1931 radeon_crtc->adjusted_clock = 0; 1932 radeon_crtc->encoder = NULL; 1933 radeon_crtc->connector = NULL; 1934 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1935 } 1936