1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 mutex_lock(&chan->mutex); 103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); 104 105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 106 107 radeon_atom_copy_swap(base, send, send_bytes, true); 108 109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 111 args.v1.ucDataOutLen = 0; 112 args.v1.ucChannelID = chan->rec.i2c_id; 113 args.v1.ucDelay = delay / 10; 114 if (ASIC_IS_DCE4(rdev)) 115 args.v2.ucHPD_ID = chan->rec.hpd; 116 117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 119 *ack = args.v1.ucReplyStatus; 120 121 /* timeout */ 122 if (args.v1.ucReplyStatus == 1) { 123 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 124 r = -ETIMEDOUT; 125 goto done; 126 } 127 128 /* flags not zero */ 129 if (args.v1.ucReplyStatus == 2) { 130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 131 r = -EIO; 132 goto done; 133 } 134 135 /* error */ 136 if (args.v1.ucReplyStatus == 3) { 137 DRM_DEBUG_KMS("dp_aux_ch error\n"); 138 r = -EIO; 139 goto done; 140 } 141 142 recv_bytes = args.v1.ucDataOutLen; 143 if (recv_bytes > recv_size) 144 recv_bytes = recv_size; 145 146 if (recv && recv_size) 147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 148 149 r = recv_bytes; 150 done: 151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); 152 mutex_unlock(&chan->mutex); 153 154 return r; 155 } 156 157 #define BARE_ADDRESS_SIZE 3 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 159 160 static ssize_t 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 162 { 163 struct radeon_i2c_chan *chan = 164 container_of(aux, struct radeon_i2c_chan, aux); 165 int ret; 166 u8 tx_buf[20]; 167 size_t tx_size; 168 u8 ack, delay = 0; 169 170 if (WARN_ON(msg->size > 16)) 171 return -E2BIG; 172 173 tx_buf[0] = msg->address & 0xff; 174 tx_buf[1] = (msg->address >> 8) & 0xff; 175 tx_buf[2] = (msg->request << 4) | 176 ((msg->address >> 16) & 0xf); 177 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 178 179 switch (msg->request & ~DP_AUX_I2C_MOT) { 180 case DP_AUX_NATIVE_WRITE: 181 case DP_AUX_I2C_WRITE: 182 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 183 /* The atom implementation only supports writes with a max payload of 184 * 12 bytes since it uses 4 bits for the total count (header + payload) 185 * in the parameter space. The atom interface supports 16 byte 186 * payloads for reads. The hw itself supports up to 16 bytes of payload. 187 */ 188 if (WARN_ON_ONCE(msg->size > 12)) 189 return -E2BIG; 190 /* tx_size needs to be 4 even for bare address packets since the atom 191 * table needs the info in tx_buf[3]. 192 */ 193 tx_size = HEADER_SIZE + msg->size; 194 if (msg->size == 0) 195 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 196 else 197 tx_buf[3] |= tx_size << 4; 198 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 199 ret = radeon_process_aux_ch(chan, 200 tx_buf, tx_size, NULL, 0, delay, &ack); 201 if (ret >= 0) 202 /* Return payload size. */ 203 ret = msg->size; 204 break; 205 case DP_AUX_NATIVE_READ: 206 case DP_AUX_I2C_READ: 207 /* tx_size needs to be 4 even for bare address packets since the atom 208 * table needs the info in tx_buf[3]. 209 */ 210 tx_size = HEADER_SIZE; 211 if (msg->size == 0) 212 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 213 else 214 tx_buf[3] |= tx_size << 4; 215 ret = radeon_process_aux_ch(chan, 216 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 217 break; 218 default: 219 ret = -EINVAL; 220 break; 221 } 222 223 if (ret >= 0) 224 msg->reply = ack >> 4; 225 226 return ret; 227 } 228 229 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 230 { 231 struct drm_device *dev = radeon_connector->base.dev; 232 struct radeon_device *rdev = dev->dev_private; 233 int ret; 234 235 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 236 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 237 if (ASIC_IS_DCE5(rdev)) { 238 if (radeon_auxch) 239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; 240 else 241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 242 } else { 243 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 244 } 245 246 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); 247 if (!ret) 248 radeon_connector->ddc_bus->has_aux = true; 249 250 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); 251 } 252 253 /***** general DP utility functions *****/ 254 255 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 256 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 257 258 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 259 int lane_count, 260 u8 train_set[4]) 261 { 262 u8 v = 0; 263 u8 p = 0; 264 int lane; 265 266 for (lane = 0; lane < lane_count; lane++) { 267 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 268 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 269 270 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 271 lane, 272 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 273 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 274 275 if (this_v > v) 276 v = this_v; 277 if (this_p > p) 278 p = this_p; 279 } 280 281 if (v >= DP_VOLTAGE_MAX) 282 v |= DP_TRAIN_MAX_SWING_REACHED; 283 284 if (p >= DP_PRE_EMPHASIS_MAX) 285 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 286 287 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 288 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 289 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 290 291 for (lane = 0; lane < 4; lane++) 292 train_set[lane] = v | p; 293 } 294 295 /* convert bits per color to bits per pixel */ 296 /* get bpc from the EDID */ 297 static int convert_bpc_to_bpp(int bpc) 298 { 299 if (bpc == 0) 300 return 24; 301 else 302 return bpc * 3; 303 } 304 305 /***** radeon specific DP functions *****/ 306 307 int radeon_dp_get_dp_link_config(struct drm_connector *connector, 308 const u8 dpcd[DP_DPCD_SIZE], 309 unsigned pix_clock, 310 unsigned *dp_lanes, unsigned *dp_rate) 311 { 312 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 313 static const unsigned link_rates[3] = { 162000, 270000, 540000 }; 314 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); 315 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 316 unsigned lane_num, i, max_pix_clock; 317 318 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 319 ENCODER_OBJECT_ID_NUTMEG) { 320 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 321 max_pix_clock = (lane_num * 270000 * 8) / bpp; 322 if (max_pix_clock >= pix_clock) { 323 *dp_lanes = lane_num; 324 *dp_rate = 270000; 325 return 0; 326 } 327 } 328 } else { 329 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { 330 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 331 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; 332 if (max_pix_clock >= pix_clock) { 333 *dp_lanes = lane_num; 334 *dp_rate = link_rates[i]; 335 return 0; 336 } 337 } 338 } 339 } 340 341 return -EINVAL; 342 } 343 344 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 345 int action, int dp_clock, 346 u8 ucconfig, u8 lane_num) 347 { 348 DP_ENCODER_SERVICE_PARAMETERS args; 349 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 350 351 memset(&args, 0, sizeof(args)); 352 args.ucLinkClock = dp_clock / 10; 353 args.ucConfig = ucconfig; 354 args.ucAction = action; 355 args.ucLaneNum = lane_num; 356 args.ucStatus = 0; 357 358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 359 return args.ucStatus; 360 } 361 362 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 363 { 364 struct drm_device *dev = radeon_connector->base.dev; 365 struct radeon_device *rdev = dev->dev_private; 366 367 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 368 radeon_connector->ddc_bus->rec.i2c_id, 0); 369 } 370 371 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 372 { 373 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 374 u8 buf[3]; 375 376 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 377 return; 378 379 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 380 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n", 381 buf[0], buf[1], buf[2]); 382 383 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 384 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n", 385 buf[0], buf[1], buf[2]); 386 } 387 388 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 389 { 390 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 391 u8 msg[DP_DPCD_SIZE]; 392 int ret, i; 393 394 char dpcd_hex_dump[DP_DPCD_SIZE * 3]; 395 396 for (i = 0; i < 7; i++) { 397 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 398 DP_DPCD_SIZE); 399 if (ret == DP_DPCD_SIZE) { 400 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 401 DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd, 402 sizeof(dig_connector->dpcd), 403 dpcd_hex_dump, sizeof(dpcd_hex_dump), " ")); 404 405 radeon_dp_probe_oui(radeon_connector); 406 407 return true; 408 } 409 } 410 dig_connector->dpcd[0] = 0; 411 return false; 412 } 413 414 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 415 struct drm_connector *connector) 416 { 417 struct drm_device *dev = encoder->dev; 418 struct radeon_device *rdev = dev->dev_private; 419 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 420 struct radeon_connector_atom_dig *dig_connector; 421 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 422 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 423 u8 tmp; 424 425 if (!ASIC_IS_DCE4(rdev)) 426 return panel_mode; 427 428 if (!radeon_connector->con_priv) 429 return panel_mode; 430 431 dig_connector = radeon_connector->con_priv; 432 433 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 434 /* DP bridge chips */ 435 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 436 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 437 if (tmp & 1) 438 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 439 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 440 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 441 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 442 else 443 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 444 } 445 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 446 /* eDP */ 447 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 448 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 449 if (tmp & 1) 450 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 451 } 452 } 453 454 return panel_mode; 455 } 456 457 void radeon_dp_set_link_config(struct drm_connector *connector, 458 const struct drm_display_mode *mode) 459 { 460 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 461 struct radeon_connector_atom_dig *dig_connector; 462 int ret; 463 464 if (!radeon_connector->con_priv) 465 return; 466 dig_connector = radeon_connector->con_priv; 467 468 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 469 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 470 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, 471 mode->clock, 472 &dig_connector->dp_lane_count, 473 &dig_connector->dp_clock); 474 if (ret) { 475 dig_connector->dp_clock = 0; 476 dig_connector->dp_lane_count = 0; 477 } 478 } 479 } 480 481 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 482 struct drm_display_mode *mode) 483 { 484 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 485 struct radeon_connector_atom_dig *dig_connector; 486 unsigned dp_clock, dp_lanes; 487 int ret; 488 489 if ((mode->clock > 340000) && 490 (!radeon_connector_is_dp12_capable(connector))) 491 return MODE_CLOCK_HIGH; 492 493 if (!radeon_connector->con_priv) 494 return MODE_CLOCK_HIGH; 495 dig_connector = radeon_connector->con_priv; 496 497 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, 498 mode->clock, 499 &dp_lanes, 500 &dp_clock); 501 if (ret) 502 return MODE_CLOCK_HIGH; 503 504 if ((dp_clock == 540000) && 505 (!radeon_connector_is_dp12_capable(connector))) 506 return MODE_CLOCK_HIGH; 507 508 return MODE_OK; 509 } 510 511 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 512 { 513 u8 link_status[DP_LINK_STATUS_SIZE]; 514 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 515 516 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 517 <= 0) 518 return false; 519 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 520 return false; 521 return true; 522 } 523 524 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 525 u8 power_state) 526 { 527 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 528 struct radeon_connector_atom_dig *dig_connector; 529 530 if (!radeon_connector->con_priv) 531 return; 532 533 dig_connector = radeon_connector->con_priv; 534 535 /* power up/down the sink */ 536 if (dig_connector->dpcd[0] >= 0x11) { 537 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 538 DP_SET_POWER, power_state); 539 usleep_range(1000, 2000); 540 } 541 } 542 543 544 struct radeon_dp_link_train_info { 545 struct radeon_device *rdev; 546 struct drm_encoder *encoder; 547 struct drm_connector *connector; 548 int enc_id; 549 int dp_clock; 550 int dp_lane_count; 551 bool tp3_supported; 552 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 553 u8 train_set[4]; 554 u8 link_status[DP_LINK_STATUS_SIZE]; 555 u8 tries; 556 bool use_dpencoder; 557 struct drm_dp_aux *aux; 558 }; 559 560 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 561 { 562 /* set the initial vs/emph on the source */ 563 atombios_dig_transmitter_setup(dp_info->encoder, 564 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 565 0, dp_info->train_set[0]); /* sets all lanes at once */ 566 567 /* set the vs/emph on the sink */ 568 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 569 dp_info->train_set, dp_info->dp_lane_count); 570 } 571 572 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 573 { 574 int rtp = 0; 575 576 /* set training pattern on the source */ 577 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 578 switch (tp) { 579 case DP_TRAINING_PATTERN_1: 580 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 581 break; 582 case DP_TRAINING_PATTERN_2: 583 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 584 break; 585 case DP_TRAINING_PATTERN_3: 586 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 587 break; 588 } 589 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 590 } else { 591 switch (tp) { 592 case DP_TRAINING_PATTERN_1: 593 rtp = 0; 594 break; 595 case DP_TRAINING_PATTERN_2: 596 rtp = 1; 597 break; 598 } 599 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 600 dp_info->dp_clock, dp_info->enc_id, rtp); 601 } 602 603 /* enable training pattern on the sink */ 604 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 605 } 606 607 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 608 { 609 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 610 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 611 u8 tmp; 612 613 /* power up the sink */ 614 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 615 616 /* possibly enable downspread on the sink */ 617 if (dp_info->dpcd[3] & 0x1) 618 drm_dp_dpcd_writeb(dp_info->aux, 619 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 620 else 621 drm_dp_dpcd_writeb(dp_info->aux, 622 DP_DOWNSPREAD_CTRL, 0); 623 624 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 625 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 626 627 /* set the lane count on the sink */ 628 tmp = dp_info->dp_lane_count; 629 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 630 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 631 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 632 633 /* set the link rate on the sink */ 634 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 635 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 636 637 /* start training on the source */ 638 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 639 atombios_dig_encoder_setup(dp_info->encoder, 640 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 641 else 642 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 643 dp_info->dp_clock, dp_info->enc_id, 0); 644 645 /* disable the training pattern on the sink */ 646 drm_dp_dpcd_writeb(dp_info->aux, 647 DP_TRAINING_PATTERN_SET, 648 DP_TRAINING_PATTERN_DISABLE); 649 650 return 0; 651 } 652 653 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 654 { 655 udelay(400); 656 657 /* disable the training pattern on the sink */ 658 drm_dp_dpcd_writeb(dp_info->aux, 659 DP_TRAINING_PATTERN_SET, 660 DP_TRAINING_PATTERN_DISABLE); 661 662 /* disable the training pattern on the source */ 663 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 664 atombios_dig_encoder_setup(dp_info->encoder, 665 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 666 else 667 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 668 dp_info->dp_clock, dp_info->enc_id, 0); 669 670 return 0; 671 } 672 673 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 674 { 675 bool clock_recovery; 676 u8 voltage; 677 int i; 678 679 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 680 memset(dp_info->train_set, 0, 4); 681 radeon_dp_update_vs_emph(dp_info); 682 683 udelay(400); 684 685 /* clock recovery loop */ 686 clock_recovery = false; 687 dp_info->tries = 0; 688 voltage = 0xff; 689 while (1) { 690 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 691 692 if (drm_dp_dpcd_read_link_status(dp_info->aux, 693 dp_info->link_status) <= 0) { 694 DRM_ERROR("displayport link status failed\n"); 695 break; 696 } 697 698 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 699 clock_recovery = true; 700 break; 701 } 702 703 for (i = 0; i < dp_info->dp_lane_count; i++) { 704 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 705 break; 706 } 707 if (i == dp_info->dp_lane_count) { 708 DRM_ERROR("clock recovery reached max voltage\n"); 709 break; 710 } 711 712 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 713 ++dp_info->tries; 714 if (dp_info->tries == 5) { 715 DRM_ERROR("clock recovery tried 5 times\n"); 716 break; 717 } 718 } else 719 dp_info->tries = 0; 720 721 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 722 723 /* Compute new train_set as requested by sink */ 724 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 725 726 radeon_dp_update_vs_emph(dp_info); 727 } 728 if (!clock_recovery) { 729 DRM_ERROR("clock recovery failed\n"); 730 return -1; 731 } else { 732 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 733 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 734 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 735 DP_TRAIN_PRE_EMPHASIS_SHIFT); 736 return 0; 737 } 738 } 739 740 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 741 { 742 bool channel_eq; 743 744 if (dp_info->tp3_supported) 745 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 746 else 747 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 748 749 /* channel equalization loop */ 750 dp_info->tries = 0; 751 channel_eq = false; 752 while (1) { 753 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 754 755 if (drm_dp_dpcd_read_link_status(dp_info->aux, 756 dp_info->link_status) <= 0) { 757 DRM_ERROR("displayport link status failed\n"); 758 break; 759 } 760 761 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 762 channel_eq = true; 763 break; 764 } 765 766 /* Try 5 times */ 767 if (dp_info->tries > 5) { 768 DRM_ERROR("channel eq failed: 5 tries\n"); 769 break; 770 } 771 772 /* Compute new train_set as requested by sink */ 773 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 774 775 radeon_dp_update_vs_emph(dp_info); 776 dp_info->tries++; 777 } 778 779 if (!channel_eq) { 780 DRM_ERROR("channel eq failed\n"); 781 return -1; 782 } else { 783 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 784 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 785 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 786 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 787 return 0; 788 } 789 } 790 791 void radeon_dp_link_train(struct drm_encoder *encoder, 792 struct drm_connector *connector) 793 { 794 struct drm_device *dev = encoder->dev; 795 struct radeon_device *rdev = dev->dev_private; 796 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 797 struct radeon_encoder_atom_dig *dig; 798 struct radeon_connector *radeon_connector; 799 struct radeon_connector_atom_dig *dig_connector; 800 struct radeon_dp_link_train_info dp_info; 801 int index; 802 u8 tmp, frev, crev; 803 804 if (!radeon_encoder->enc_priv) 805 return; 806 dig = radeon_encoder->enc_priv; 807 808 radeon_connector = to_radeon_connector(connector); 809 if (!radeon_connector->con_priv) 810 return; 811 dig_connector = radeon_connector->con_priv; 812 813 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 814 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 815 return; 816 817 /* DPEncoderService newer than 1.1 can't program properly the 818 * training pattern. When facing such version use the 819 * DIGXEncoderControl (X== 1 | 2) 820 */ 821 dp_info.use_dpencoder = true; 822 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 823 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 824 if (crev > 1) { 825 dp_info.use_dpencoder = false; 826 } 827 } 828 829 dp_info.enc_id = 0; 830 if (dig->dig_encoder) 831 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 832 else 833 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 834 if (dig->linkb) 835 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 836 else 837 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 838 839 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 840 == 1) { 841 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 842 dp_info.tp3_supported = true; 843 else 844 dp_info.tp3_supported = false; 845 } else { 846 dp_info.tp3_supported = false; 847 } 848 849 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 850 dp_info.rdev = rdev; 851 dp_info.encoder = encoder; 852 dp_info.connector = connector; 853 dp_info.dp_lane_count = dig_connector->dp_lane_count; 854 dp_info.dp_clock = dig_connector->dp_clock; 855 dp_info.aux = &radeon_connector->ddc_bus->aux; 856 857 if (radeon_dp_link_train_init(&dp_info)) 858 goto done; 859 if (radeon_dp_link_train_cr(&dp_info)) 860 goto done; 861 if (radeon_dp_link_train_ce(&dp_info)) 862 goto done; 863 done: 864 if (radeon_dp_link_train_finish(&dp_info)) 865 return; 866 } 867