1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 99 memset(&args, 0, sizeof(args)); 100 101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 102 103 radeon_atom_copy_swap(base, send, send_bytes, true); 104 105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 107 args.v1.ucDataOutLen = 0; 108 args.v1.ucChannelID = chan->rec.i2c_id; 109 args.v1.ucDelay = delay / 10; 110 if (ASIC_IS_DCE4(rdev)) 111 args.v2.ucHPD_ID = chan->rec.hpd; 112 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 115 *ack = args.v1.ucReplyStatus; 116 117 /* timeout */ 118 if (args.v1.ucReplyStatus == 1) { 119 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 120 return -ETIMEDOUT; 121 } 122 123 /* flags not zero */ 124 if (args.v1.ucReplyStatus == 2) { 125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 126 return -EIO; 127 } 128 129 /* error */ 130 if (args.v1.ucReplyStatus == 3) { 131 DRM_DEBUG_KMS("dp_aux_ch error\n"); 132 return -EIO; 133 } 134 135 recv_bytes = args.v1.ucDataOutLen; 136 if (recv_bytes > recv_size) 137 recv_bytes = recv_size; 138 139 if (recv && recv_size) 140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 141 142 return recv_bytes; 143 } 144 145 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 146 u16 address, u8 *send, u8 send_bytes, u8 delay) 147 { 148 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 149 int ret; 150 u8 msg[20]; 151 int msg_bytes = send_bytes + 4; 152 u8 ack; 153 unsigned retry; 154 155 if (send_bytes > 16) 156 return -1; 157 158 msg[0] = address; 159 msg[1] = address >> 8; 160 msg[2] = DP_AUX_NATIVE_WRITE << 4; 161 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 162 memcpy(&msg[4], send, send_bytes); 163 164 for (retry = 0; retry < 7; retry++) { 165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 166 msg, msg_bytes, NULL, 0, delay, &ack); 167 if (ret == -EBUSY) 168 continue; 169 else if (ret < 0) 170 return ret; 171 ack >>= 4; 172 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 173 return send_bytes; 174 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 175 usleep_range(400, 500); 176 else 177 return -EIO; 178 } 179 180 return -EIO; 181 } 182 183 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 184 u16 address, u8 *recv, int recv_bytes, u8 delay) 185 { 186 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 187 u8 msg[4]; 188 int msg_bytes = 4; 189 u8 ack; 190 int ret; 191 unsigned retry; 192 193 msg[0] = address; 194 msg[1] = address >> 8; 195 msg[2] = DP_AUX_NATIVE_READ << 4; 196 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 197 198 for (retry = 0; retry < 7; retry++) { 199 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 200 msg, msg_bytes, recv, recv_bytes, delay, &ack); 201 if (ret == -EBUSY) 202 continue; 203 else if (ret < 0) 204 return ret; 205 ack >>= 4; 206 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 207 return ret; 208 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 209 usleep_range(400, 500); 210 else if (ret == 0) 211 return -EPROTO; 212 else 213 return -EIO; 214 } 215 216 return -EIO; 217 } 218 219 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 220 u16 reg, u8 val) 221 { 222 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); 223 } 224 225 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, 226 u16 reg) 227 { 228 u8 val = 0; 229 230 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); 231 232 return val; 233 } 234 235 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte) 236 { 237 struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev); 238 struct radeon_i2c_chan *auxch = algo_data->priv; 239 u16 address = algo_data->address; 240 u8 msg[5]; 241 u8 reply[2]; 242 unsigned retry; 243 int msg_bytes; 244 int reply_bytes = 1; 245 int ret; 246 u8 ack; 247 248 /* Set up the address */ 249 msg[0] = address; 250 msg[1] = address >> 8; 251 252 /* Set up the command byte */ 253 if (mode & MODE_I2C_READ) { 254 msg[2] = DP_AUX_I2C_READ << 4; 255 msg_bytes = 4; 256 msg[3] = msg_bytes << 4; 257 } else { 258 msg[2] = DP_AUX_I2C_WRITE << 4; 259 msg_bytes = 5; 260 msg[3] = msg_bytes << 4; 261 msg[4] = write_byte; 262 } 263 264 /* special handling for start/stop */ 265 if (mode & (MODE_I2C_START | MODE_I2C_STOP)) 266 msg[3] = 3 << 4; 267 268 /* Set MOT bit for all but stop */ 269 if ((mode & MODE_I2C_STOP) == 0) 270 msg[2] |= DP_AUX_I2C_MOT << 4; 271 272 for (retry = 0; retry < 7; retry++) { 273 ret = radeon_process_aux_ch(auxch, 274 msg, msg_bytes, reply, reply_bytes, 0, &ack); 275 if (ret == -EBUSY) 276 continue; 277 else if (ret < 0) { 278 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 279 return ret; 280 } 281 282 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 283 case DP_AUX_NATIVE_REPLY_ACK: 284 /* I2C-over-AUX Reply field is only valid 285 * when paired with AUX ACK. 286 */ 287 break; 288 case DP_AUX_NATIVE_REPLY_NACK: 289 DRM_DEBUG_KMS("aux_ch native nack\n"); 290 return -EREMOTEIO; 291 case DP_AUX_NATIVE_REPLY_DEFER: 292 DRM_DEBUG_KMS("aux_ch native defer\n"); 293 usleep_range(500, 600); 294 continue; 295 default: 296 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); 297 return -EREMOTEIO; 298 } 299 300 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { 301 case DP_AUX_I2C_REPLY_ACK: 302 if (mode == MODE_I2C_READ) 303 *read_byte = reply[0]; 304 return ret; 305 case DP_AUX_I2C_REPLY_NACK: 306 DRM_DEBUG_KMS("aux_i2c nack\n"); 307 return -EREMOTEIO; 308 case DP_AUX_I2C_REPLY_DEFER: 309 DRM_DEBUG_KMS("aux_i2c defer\n"); 310 usleep_range(400, 500); 311 break; 312 default: 313 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); 314 return -EREMOTEIO; 315 } 316 } 317 318 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); 319 return -EREMOTEIO; 320 } 321 322 /***** general DP utility functions *****/ 323 324 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 325 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 326 327 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 328 int lane_count, 329 u8 train_set[4]) 330 { 331 u8 v = 0; 332 u8 p = 0; 333 int lane; 334 335 for (lane = 0; lane < lane_count; lane++) { 336 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 337 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 338 339 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 340 lane, 341 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 342 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 343 344 if (this_v > v) 345 v = this_v; 346 if (this_p > p) 347 p = this_p; 348 } 349 350 if (v >= DP_VOLTAGE_MAX) 351 v |= DP_TRAIN_MAX_SWING_REACHED; 352 353 if (p >= DP_PRE_EMPHASIS_MAX) 354 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 355 356 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 357 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 358 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 359 360 for (lane = 0; lane < 4; lane++) 361 train_set[lane] = v | p; 362 } 363 364 /* convert bits per color to bits per pixel */ 365 /* get bpc from the EDID */ 366 static int convert_bpc_to_bpp(int bpc) 367 { 368 if (bpc == 0) 369 return 24; 370 else 371 return bpc * 3; 372 } 373 374 /* get the max pix clock supported by the link rate and lane num */ 375 static int dp_get_max_dp_pix_clock(int link_rate, 376 int lane_num, 377 int bpp) 378 { 379 return (link_rate * lane_num * 8) / bpp; 380 } 381 382 /***** radeon specific DP functions *****/ 383 384 static int radeon_dp_get_max_link_rate(struct drm_connector *connector, 385 u8 dpcd[DP_DPCD_SIZE]) 386 { 387 int max_link_rate; 388 389 if (radeon_connector_is_dp12_capable(connector)) 390 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 391 else 392 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 393 394 return max_link_rate; 395 } 396 397 /* First get the min lane# when low rate is used according to pixel clock 398 * (prefer low rate), second check max lane# supported by DP panel, 399 * if the max lane# < low rate lane# then use max lane# instead. 400 */ 401 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 402 u8 dpcd[DP_DPCD_SIZE], 403 int pix_clock) 404 { 405 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 406 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 407 int max_lane_num = drm_dp_max_lane_count(dpcd); 408 int lane_num; 409 int max_dp_pix_clock; 410 411 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 412 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 413 if (pix_clock <= max_dp_pix_clock) 414 break; 415 } 416 417 return lane_num; 418 } 419 420 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 421 u8 dpcd[DP_DPCD_SIZE], 422 int pix_clock) 423 { 424 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 425 int lane_num, max_pix_clock; 426 427 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 428 ENCODER_OBJECT_ID_NUTMEG) 429 return 270000; 430 431 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 432 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 433 if (pix_clock <= max_pix_clock) 434 return 162000; 435 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 436 if (pix_clock <= max_pix_clock) 437 return 270000; 438 if (radeon_connector_is_dp12_capable(connector)) { 439 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 440 if (pix_clock <= max_pix_clock) 441 return 540000; 442 } 443 444 return radeon_dp_get_max_link_rate(connector, dpcd); 445 } 446 447 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 448 int action, int dp_clock, 449 u8 ucconfig, u8 lane_num) 450 { 451 DP_ENCODER_SERVICE_PARAMETERS args; 452 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 453 454 memset(&args, 0, sizeof(args)); 455 args.ucLinkClock = dp_clock / 10; 456 args.ucConfig = ucconfig; 457 args.ucAction = action; 458 args.ucLaneNum = lane_num; 459 args.ucStatus = 0; 460 461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 462 return args.ucStatus; 463 } 464 465 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 466 { 467 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 468 struct drm_device *dev = radeon_connector->base.dev; 469 struct radeon_device *rdev = dev->dev_private; 470 471 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 472 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 473 } 474 475 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 476 { 477 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 478 u8 buf[3]; 479 480 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 481 return; 482 483 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) 484 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n", 485 buf[0], buf[1], buf[2]); 486 487 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) 488 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n", 489 buf[0], buf[1], buf[2]); 490 } 491 492 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 493 { 494 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 495 u8 msg[DP_DPCD_SIZE]; 496 int ret, i; 497 498 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 499 DP_DPCD_SIZE, 0); 500 if (ret > 0) { 501 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 502 DRM_DEBUG_KMS("DPCD: "); 503 for (i = 0; i < DP_DPCD_SIZE; i++) 504 DRM_DEBUG_KMS("%02x ", msg[i]); 505 DRM_DEBUG_KMS("\n"); 506 507 radeon_dp_probe_oui(radeon_connector); 508 509 return true; 510 } 511 dig_connector->dpcd[0] = 0; 512 return false; 513 } 514 515 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 516 struct drm_connector *connector) 517 { 518 struct drm_device *dev = encoder->dev; 519 struct radeon_device *rdev = dev->dev_private; 520 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 521 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 522 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 523 u8 tmp; 524 525 if (!ASIC_IS_DCE4(rdev)) 526 return panel_mode; 527 528 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 529 /* DP bridge chips */ 530 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 531 if (tmp & 1) 532 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 533 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 534 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 535 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 536 else 537 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 538 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 539 /* eDP */ 540 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 541 if (tmp & 1) 542 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 543 } 544 545 return panel_mode; 546 } 547 548 void radeon_dp_set_link_config(struct drm_connector *connector, 549 const struct drm_display_mode *mode) 550 { 551 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 552 struct radeon_connector_atom_dig *dig_connector; 553 554 if (!radeon_connector->con_priv) 555 return; 556 dig_connector = radeon_connector->con_priv; 557 558 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 559 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 560 dig_connector->dp_clock = 561 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 562 dig_connector->dp_lane_count = 563 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 564 } 565 } 566 567 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 568 struct drm_display_mode *mode) 569 { 570 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 571 struct radeon_connector_atom_dig *dig_connector; 572 int dp_clock; 573 574 if (!radeon_connector->con_priv) 575 return MODE_CLOCK_HIGH; 576 dig_connector = radeon_connector->con_priv; 577 578 dp_clock = 579 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 580 581 if ((dp_clock == 540000) && 582 (!radeon_connector_is_dp12_capable(connector))) 583 return MODE_CLOCK_HIGH; 584 585 return MODE_OK; 586 } 587 588 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, 589 u8 link_status[DP_LINK_STATUS_SIZE]) 590 { 591 int ret; 592 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 593 link_status, DP_LINK_STATUS_SIZE, 100); 594 if (ret <= 0) { 595 return false; 596 } 597 598 DRM_DEBUG_KMS("link status %6ph\n", link_status); 599 return true; 600 } 601 602 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 603 { 604 u8 link_status[DP_LINK_STATUS_SIZE]; 605 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 606 607 if (!radeon_dp_get_link_status(radeon_connector, link_status)) 608 return false; 609 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 610 return false; 611 return true; 612 } 613 614 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 615 u8 power_state) 616 { 617 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 618 struct radeon_connector_atom_dig *dig_connector; 619 620 if (!radeon_connector->con_priv) 621 return; 622 623 dig_connector = radeon_connector->con_priv; 624 625 /* power up/down the sink */ 626 if (dig_connector->dpcd[0] >= 0x11) { 627 radeon_write_dpcd_reg(radeon_connector, 628 DP_SET_POWER, power_state); 629 usleep_range(1000, 2000); 630 } 631 } 632 633 634 struct radeon_dp_link_train_info { 635 struct radeon_device *rdev; 636 struct drm_encoder *encoder; 637 struct drm_connector *connector; 638 struct radeon_connector *radeon_connector; 639 int enc_id; 640 int dp_clock; 641 int dp_lane_count; 642 bool tp3_supported; 643 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 644 u8 train_set[4]; 645 u8 link_status[DP_LINK_STATUS_SIZE]; 646 u8 tries; 647 bool use_dpencoder; 648 }; 649 650 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 651 { 652 /* set the initial vs/emph on the source */ 653 atombios_dig_transmitter_setup(dp_info->encoder, 654 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 655 0, dp_info->train_set[0]); /* sets all lanes at once */ 656 657 /* set the vs/emph on the sink */ 658 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, 659 dp_info->train_set, dp_info->dp_lane_count, 0); 660 } 661 662 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 663 { 664 int rtp = 0; 665 666 /* set training pattern on the source */ 667 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 668 switch (tp) { 669 case DP_TRAINING_PATTERN_1: 670 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 671 break; 672 case DP_TRAINING_PATTERN_2: 673 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 674 break; 675 case DP_TRAINING_PATTERN_3: 676 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 677 break; 678 } 679 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 680 } else { 681 switch (tp) { 682 case DP_TRAINING_PATTERN_1: 683 rtp = 0; 684 break; 685 case DP_TRAINING_PATTERN_2: 686 rtp = 1; 687 break; 688 } 689 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 690 dp_info->dp_clock, dp_info->enc_id, rtp); 691 } 692 693 /* enable training pattern on the sink */ 694 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); 695 } 696 697 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 698 { 699 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 700 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 701 u8 tmp; 702 703 /* power up the sink */ 704 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 705 706 /* possibly enable downspread on the sink */ 707 if (dp_info->dpcd[3] & 0x1) 708 radeon_write_dpcd_reg(dp_info->radeon_connector, 709 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 710 else 711 radeon_write_dpcd_reg(dp_info->radeon_connector, 712 DP_DOWNSPREAD_CTRL, 0); 713 714 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 715 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 716 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); 717 } 718 719 /* set the lane count on the sink */ 720 tmp = dp_info->dp_lane_count; 721 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 722 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 723 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); 724 725 /* set the link rate on the sink */ 726 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 727 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); 728 729 /* start training on the source */ 730 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 731 atombios_dig_encoder_setup(dp_info->encoder, 732 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 733 else 734 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 735 dp_info->dp_clock, dp_info->enc_id, 0); 736 737 /* disable the training pattern on the sink */ 738 radeon_write_dpcd_reg(dp_info->radeon_connector, 739 DP_TRAINING_PATTERN_SET, 740 DP_TRAINING_PATTERN_DISABLE); 741 742 return 0; 743 } 744 745 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 746 { 747 udelay(400); 748 749 /* disable the training pattern on the sink */ 750 radeon_write_dpcd_reg(dp_info->radeon_connector, 751 DP_TRAINING_PATTERN_SET, 752 DP_TRAINING_PATTERN_DISABLE); 753 754 /* disable the training pattern on the source */ 755 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 756 atombios_dig_encoder_setup(dp_info->encoder, 757 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 758 else 759 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 760 dp_info->dp_clock, dp_info->enc_id, 0); 761 762 return 0; 763 } 764 765 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 766 { 767 bool clock_recovery; 768 u8 voltage; 769 int i; 770 771 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 772 memset(dp_info->train_set, 0, 4); 773 radeon_dp_update_vs_emph(dp_info); 774 775 udelay(400); 776 777 /* clock recovery loop */ 778 clock_recovery = false; 779 dp_info->tries = 0; 780 voltage = 0xff; 781 while (1) { 782 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 783 784 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 785 DRM_ERROR("displayport link status failed\n"); 786 break; 787 } 788 789 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 790 clock_recovery = true; 791 break; 792 } 793 794 for (i = 0; i < dp_info->dp_lane_count; i++) { 795 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 796 break; 797 } 798 if (i == dp_info->dp_lane_count) { 799 DRM_ERROR("clock recovery reached max voltage\n"); 800 break; 801 } 802 803 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 804 ++dp_info->tries; 805 if (dp_info->tries == 5) { 806 DRM_ERROR("clock recovery tried 5 times\n"); 807 break; 808 } 809 } else 810 dp_info->tries = 0; 811 812 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 813 814 /* Compute new train_set as requested by sink */ 815 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 816 817 radeon_dp_update_vs_emph(dp_info); 818 } 819 if (!clock_recovery) { 820 DRM_ERROR("clock recovery failed\n"); 821 return -1; 822 } else { 823 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 824 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 825 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 826 DP_TRAIN_PRE_EMPHASIS_SHIFT); 827 return 0; 828 } 829 } 830 831 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 832 { 833 bool channel_eq; 834 835 if (dp_info->tp3_supported) 836 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 837 else 838 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 839 840 /* channel equalization loop */ 841 dp_info->tries = 0; 842 channel_eq = false; 843 while (1) { 844 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 845 846 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 847 DRM_ERROR("displayport link status failed\n"); 848 break; 849 } 850 851 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 852 channel_eq = true; 853 break; 854 } 855 856 /* Try 5 times */ 857 if (dp_info->tries > 5) { 858 DRM_ERROR("channel eq failed: 5 tries\n"); 859 break; 860 } 861 862 /* Compute new train_set as requested by sink */ 863 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 864 865 radeon_dp_update_vs_emph(dp_info); 866 dp_info->tries++; 867 } 868 869 if (!channel_eq) { 870 DRM_ERROR("channel eq failed\n"); 871 return -1; 872 } else { 873 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 874 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 875 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 876 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 877 return 0; 878 } 879 } 880 881 void radeon_dp_link_train(struct drm_encoder *encoder, 882 struct drm_connector *connector) 883 { 884 struct drm_device *dev = encoder->dev; 885 struct radeon_device *rdev = dev->dev_private; 886 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 887 struct radeon_encoder_atom_dig *dig; 888 struct radeon_connector *radeon_connector; 889 struct radeon_connector_atom_dig *dig_connector; 890 struct radeon_dp_link_train_info dp_info; 891 int index; 892 u8 tmp, frev, crev; 893 894 if (!radeon_encoder->enc_priv) 895 return; 896 dig = radeon_encoder->enc_priv; 897 898 radeon_connector = to_radeon_connector(connector); 899 if (!radeon_connector->con_priv) 900 return; 901 dig_connector = radeon_connector->con_priv; 902 903 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 904 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 905 return; 906 907 /* DPEncoderService newer than 1.1 can't program properly the 908 * training pattern. When facing such version use the 909 * DIGXEncoderControl (X== 1 | 2) 910 */ 911 dp_info.use_dpencoder = true; 912 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 913 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 914 if (crev > 1) { 915 dp_info.use_dpencoder = false; 916 } 917 } 918 919 dp_info.enc_id = 0; 920 if (dig->dig_encoder) 921 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 922 else 923 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 924 if (dig->linkb) 925 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 926 else 927 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 928 929 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); 930 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 931 dp_info.tp3_supported = true; 932 else 933 dp_info.tp3_supported = false; 934 935 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 936 dp_info.rdev = rdev; 937 dp_info.encoder = encoder; 938 dp_info.connector = connector; 939 dp_info.radeon_connector = radeon_connector; 940 dp_info.dp_lane_count = dig_connector->dp_lane_count; 941 dp_info.dp_clock = dig_connector->dp_clock; 942 943 if (radeon_dp_link_train_init(&dp_info)) 944 goto done; 945 if (radeon_dp_link_train_cr(&dp_info)) 946 goto done; 947 if (radeon_dp_link_train_ce(&dp_info)) 948 goto done; 949 done: 950 if (radeon_dp_link_train_finish(&dp_info)) 951 return; 952 } 953