1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "atom.h" 32 33 static u8 34 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 35 { 36 u8 backlight_level; 37 u32 bios_2_scratch; 38 39 if (rdev->family >= CHIP_R600) 40 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 41 else 42 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 43 44 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 45 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 46 47 return backlight_level; 48 } 49 50 static void 51 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 52 u8 backlight_level) 53 { 54 u32 bios_2_scratch; 55 56 if (rdev->family >= CHIP_R600) 57 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 58 else 59 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 60 61 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 62 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 63 ATOM_S2_CURRENT_BL_LEVEL_MASK); 64 65 if (rdev->family >= CHIP_R600) 66 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 67 else 68 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 69 } 70 71 u8 72 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 73 { 74 struct drm_device *dev = radeon_encoder->base.dev; 75 struct radeon_device *rdev = dev->dev_private; 76 77 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 78 return 0; 79 80 return radeon_atom_get_backlight_level_from_reg(rdev); 81 } 82 83 void 84 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 85 { 86 struct drm_encoder *encoder = &radeon_encoder->base; 87 struct drm_device *dev = radeon_encoder->base.dev; 88 struct radeon_device *rdev = dev->dev_private; 89 struct radeon_encoder_atom_dig *dig; 90 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 91 int index; 92 93 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 94 return; 95 96 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 97 radeon_encoder->enc_priv) { 98 dig = radeon_encoder->enc_priv; 99 dig->backlight_level = level; 100 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 101 102 switch (radeon_encoder->encoder_id) { 103 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 104 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 105 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 106 if (dig->backlight_level == 0) { 107 args.ucAction = ATOM_LCD_BLOFF; 108 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 109 } else { 110 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 112 args.ucAction = ATOM_LCD_BLON; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 } 115 break; 116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 117 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 120 if (dig->backlight_level == 0) 121 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 122 else { 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 125 } 126 break; 127 default: 128 break; 129 } 130 } 131 } 132 133 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 134 135 #if 0 136 static u8 radeon_atom_bl_level(struct backlight_device *bd) 137 { 138 u8 level; 139 140 /* Convert brightness to hardware level */ 141 if (bd->props.brightness < 0) 142 level = 0; 143 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 144 level = RADEON_MAX_BL_LEVEL; 145 else 146 level = bd->props.brightness; 147 148 return level; 149 } 150 151 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 152 { 153 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 154 struct radeon_encoder *radeon_encoder = pdata->encoder; 155 156 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 157 158 return 0; 159 } 160 161 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 162 { 163 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 164 struct radeon_encoder *radeon_encoder = pdata->encoder; 165 struct drm_device *dev = radeon_encoder->base.dev; 166 struct radeon_device *rdev = dev->dev_private; 167 168 return radeon_atom_get_backlight_level_from_reg(rdev); 169 } 170 171 static const struct backlight_ops radeon_atom_backlight_ops = { 172 .get_brightness = radeon_atom_backlight_get_brightness, 173 .update_status = radeon_atom_backlight_update_status, 174 }; 175 #endif 176 177 /* 178 * Read max backlight level 179 */ 180 static int 181 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 182 { 183 int err, val; 184 185 val = RADEON_MAX_BL_LEVEL; 186 err = sysctl_handle_int(oidp, &val, 0, req); 187 return(err); 188 } 189 190 /* 191 * Read/write backlight level 192 */ 193 static int 194 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 195 { 196 struct radeon_encoder *encoder; 197 struct radeon_encoder_atom_dig *dig; 198 int err, val; 199 200 encoder = (struct radeon_encoder *)arg1; 201 dig = encoder->enc_priv; 202 val = dig->backlight_level; 203 204 err = sysctl_handle_int(oidp, &val, 0, req); 205 if (err != 0 || req->newptr == NULL) { 206 return(err); 207 } 208 if (dig->backlight_level != val && val >= 0 && 209 val <= RADEON_MAX_BL_LEVEL) { 210 atombios_set_backlight_level(encoder, val); 211 } 212 213 return(err); 214 } 215 216 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 217 struct drm_connector *drm_connector) 218 { 219 struct drm_device *dev = radeon_encoder->base.dev; 220 struct radeon_device *rdev = dev->dev_private; 221 struct radeon_encoder_atom_dig *dig; 222 223 if (!radeon_encoder->enc_priv) 224 return; 225 226 if (!rdev->is_atom_bios) 227 return; 228 229 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 230 return; 231 232 dig = radeon_encoder->enc_priv; 233 dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 234 235 DRM_INFO("radeon atom DIG backlight initialized\n"); 236 237 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 238 OID_AUTO, "backlight_max", 239 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 240 radeon_encoder, sizeof(int), 241 sysctl_backlight_max, 242 "I", "Max backlight level"); 243 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 244 OID_AUTO, "backlight_level", 245 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 246 radeon_encoder, sizeof(int), 247 sysctl_backlight_handler, 248 "I", "Backlight level"); 249 return; 250 } 251 252 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 253 { 254 #if 0 255 struct drm_device *dev = radeon_encoder->base.dev; 256 struct radeon_device *rdev = dev->dev_private; 257 struct backlight_device *bd = NULL; 258 struct radeon_encoder_atom_dig *dig; 259 260 if (!radeon_encoder->enc_priv) 261 return; 262 263 if (!rdev->is_atom_bios) 264 return; 265 266 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 267 return; 268 269 dig = radeon_encoder->enc_priv; 270 bd = dig->bl_dev; 271 dig->bl_dev = NULL; 272 273 if (bd) { 274 struct radeon_legacy_backlight_privdata *pdata; 275 276 pdata = bl_get_data(bd); 277 backlight_device_unregister(bd); 278 kfree(pdata); 279 280 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 281 } 282 #endif 283 } 284 285 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 286 287 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 288 struct drm_connector *drm_connector) 289 { 290 } 291 292 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 293 { 294 } 295 296 #endif 297 298 299 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 300 const struct drm_display_mode *mode, 301 struct drm_display_mode *adjusted_mode) 302 { 303 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 304 struct drm_device *dev = encoder->dev; 305 struct radeon_device *rdev = dev->dev_private; 306 307 /* set the active encoder to connector routing */ 308 radeon_encoder_set_active_device(encoder); 309 drm_mode_set_crtcinfo(adjusted_mode, 0); 310 311 /* hw bug */ 312 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 313 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 314 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 315 316 /* get the native mode for scaling */ 317 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 318 radeon_panel_mode_fixup(encoder, adjusted_mode); 319 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 320 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 321 if (tv_dac) { 322 if (tv_dac->tv_std == TV_STD_NTSC || 323 tv_dac->tv_std == TV_STD_NTSC_J || 324 tv_dac->tv_std == TV_STD_PAL_M) 325 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 326 else 327 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 328 } 329 } else if (radeon_encoder->rmx_type != RMX_OFF) { 330 radeon_panel_mode_fixup(encoder, adjusted_mode); 331 } 332 333 if (ASIC_IS_DCE3(rdev) && 334 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 335 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 337 radeon_dp_set_link_config(connector, adjusted_mode); 338 } 339 340 return true; 341 } 342 343 static void 344 atombios_dac_setup(struct drm_encoder *encoder, int action) 345 { 346 struct drm_device *dev = encoder->dev; 347 struct radeon_device *rdev = dev->dev_private; 348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 349 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 350 int index = 0; 351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 352 353 memset(&args, 0, sizeof(args)); 354 355 switch (radeon_encoder->encoder_id) { 356 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 359 break; 360 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 363 break; 364 } 365 366 args.ucAction = action; 367 368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 369 args.ucDacStandard = ATOM_DAC1_PS2; 370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 371 args.ucDacStandard = ATOM_DAC1_CV; 372 else { 373 switch (dac_info->tv_std) { 374 case TV_STD_PAL: 375 case TV_STD_PAL_M: 376 case TV_STD_SCART_PAL: 377 case TV_STD_SECAM: 378 case TV_STD_PAL_CN: 379 args.ucDacStandard = ATOM_DAC1_PAL; 380 break; 381 case TV_STD_NTSC: 382 case TV_STD_NTSC_J: 383 case TV_STD_PAL_60: 384 default: 385 args.ucDacStandard = ATOM_DAC1_NTSC; 386 break; 387 } 388 } 389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 390 391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 392 393 } 394 395 static void 396 atombios_tv_setup(struct drm_encoder *encoder, int action) 397 { 398 struct drm_device *dev = encoder->dev; 399 struct radeon_device *rdev = dev->dev_private; 400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 401 TV_ENCODER_CONTROL_PS_ALLOCATION args; 402 int index = 0; 403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 404 405 memset(&args, 0, sizeof(args)); 406 407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 408 409 args.sTVEncoder.ucAction = action; 410 411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 413 else { 414 switch (dac_info->tv_std) { 415 case TV_STD_NTSC: 416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 417 break; 418 case TV_STD_PAL: 419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 420 break; 421 case TV_STD_PAL_M: 422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 423 break; 424 case TV_STD_PAL_60: 425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 426 break; 427 case TV_STD_NTSC_J: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 429 break; 430 case TV_STD_SCART_PAL: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 432 break; 433 case TV_STD_SECAM: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 435 break; 436 case TV_STD_PAL_CN: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 438 break; 439 default: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 441 break; 442 } 443 } 444 445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 446 447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 448 449 } 450 451 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 452 { 453 int bpc = 8; 454 455 if (encoder->crtc) { 456 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 457 bpc = radeon_crtc->bpc; 458 } 459 460 switch (bpc) { 461 case 0: 462 return PANEL_BPC_UNDEFINE; 463 case 6: 464 return PANEL_6BIT_PER_COLOR; 465 case 8: 466 default: 467 return PANEL_8BIT_PER_COLOR; 468 case 10: 469 return PANEL_10BIT_PER_COLOR; 470 case 12: 471 return PANEL_12BIT_PER_COLOR; 472 case 16: 473 return PANEL_16BIT_PER_COLOR; 474 } 475 } 476 477 union dvo_encoder_control { 478 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 479 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 480 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 481 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 482 }; 483 484 void 485 atombios_dvo_setup(struct drm_encoder *encoder, int action) 486 { 487 struct drm_device *dev = encoder->dev; 488 struct radeon_device *rdev = dev->dev_private; 489 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 490 union dvo_encoder_control args; 491 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 492 uint8_t frev, crev; 493 494 memset(&args, 0, sizeof(args)); 495 496 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 497 return; 498 499 /* some R4xx chips have the wrong frev */ 500 if (rdev->family <= CHIP_RV410) 501 frev = 1; 502 503 switch (frev) { 504 case 1: 505 switch (crev) { 506 case 1: 507 /* R4xx, R5xx */ 508 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 509 510 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 511 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 512 513 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 514 break; 515 case 2: 516 /* RS600/690/740 */ 517 args.dvo.sDVOEncoder.ucAction = action; 518 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 519 /* DFP1, CRT1, TV1 depending on the type of port */ 520 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 521 522 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 523 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 524 break; 525 case 3: 526 /* R6xx */ 527 args.dvo_v3.ucAction = action; 528 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 529 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 530 break; 531 case 4: 532 /* DCE8 */ 533 args.dvo_v4.ucAction = action; 534 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 535 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 536 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 537 break; 538 default: 539 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 540 break; 541 } 542 break; 543 default: 544 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 545 break; 546 } 547 548 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 549 } 550 551 union lvds_encoder_control { 552 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 553 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 554 }; 555 556 void 557 atombios_digital_setup(struct drm_encoder *encoder, int action) 558 { 559 struct drm_device *dev = encoder->dev; 560 struct radeon_device *rdev = dev->dev_private; 561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 562 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 563 union lvds_encoder_control args; 564 int index = 0; 565 int hdmi_detected = 0; 566 uint8_t frev, crev; 567 568 if (!dig) 569 return; 570 571 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 572 hdmi_detected = 1; 573 574 memset(&args, 0, sizeof(args)); 575 576 switch (radeon_encoder->encoder_id) { 577 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 578 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 579 break; 580 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 582 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 583 break; 584 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 585 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 586 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 587 else 588 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 589 break; 590 } 591 592 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 593 return; 594 595 switch (frev) { 596 case 1: 597 case 2: 598 switch (crev) { 599 case 1: 600 args.v1.ucMisc = 0; 601 args.v1.ucAction = action; 602 if (hdmi_detected) 603 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 604 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 605 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 606 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 607 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 608 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 609 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 610 } else { 611 if (dig->linkb) 612 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 613 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 614 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 615 /*if (pScrn->rgbBits == 8) */ 616 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 617 } 618 break; 619 case 2: 620 case 3: 621 args.v2.ucMisc = 0; 622 args.v2.ucAction = action; 623 if (crev == 3) { 624 if (dig->coherent_mode) 625 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 626 } 627 if (hdmi_detected) 628 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 629 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 630 args.v2.ucTruncate = 0; 631 args.v2.ucSpatial = 0; 632 args.v2.ucTemporal = 0; 633 args.v2.ucFRC = 0; 634 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 635 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 636 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 637 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 638 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 639 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 640 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 641 } 642 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 643 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 644 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 646 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 647 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 648 } 649 } else { 650 if (dig->linkb) 651 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 652 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 653 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 654 } 655 break; 656 default: 657 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 658 break; 659 } 660 break; 661 default: 662 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 663 break; 664 } 665 666 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 667 } 668 669 int 670 atombios_get_encoder_mode(struct drm_encoder *encoder) 671 { 672 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 673 struct drm_connector *connector; 674 struct radeon_connector *radeon_connector; 675 struct radeon_connector_atom_dig *dig_connector; 676 677 /* dp bridges are always DP */ 678 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 679 return ATOM_ENCODER_MODE_DP; 680 681 /* DVO is always DVO */ 682 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 683 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 684 return ATOM_ENCODER_MODE_DVO; 685 686 connector = radeon_get_connector_for_encoder(encoder); 687 /* if we don't have an active device yet, just use one of 688 * the connectors tied to the encoder. 689 */ 690 if (!connector) 691 connector = radeon_get_connector_for_encoder_init(encoder); 692 radeon_connector = to_radeon_connector(connector); 693 694 switch (connector->connector_type) { 695 case DRM_MODE_CONNECTOR_DVII: 696 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 697 if (radeon_audio != 0) { 698 if (radeon_connector->use_digital && 699 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 700 return ATOM_ENCODER_MODE_HDMI; 701 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 702 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 703 return ATOM_ENCODER_MODE_HDMI; 704 else if (radeon_connector->use_digital) 705 return ATOM_ENCODER_MODE_DVI; 706 else 707 return ATOM_ENCODER_MODE_CRT; 708 } else if (radeon_connector->use_digital) { 709 return ATOM_ENCODER_MODE_DVI; 710 } else { 711 return ATOM_ENCODER_MODE_CRT; 712 } 713 break; 714 case DRM_MODE_CONNECTOR_DVID: 715 case DRM_MODE_CONNECTOR_HDMIA: 716 default: 717 if (radeon_audio != 0) { 718 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 719 return ATOM_ENCODER_MODE_HDMI; 720 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 721 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 722 return ATOM_ENCODER_MODE_HDMI; 723 else 724 return ATOM_ENCODER_MODE_DVI; 725 } else { 726 return ATOM_ENCODER_MODE_DVI; 727 } 728 break; 729 case DRM_MODE_CONNECTOR_LVDS: 730 return ATOM_ENCODER_MODE_LVDS; 731 break; 732 case DRM_MODE_CONNECTOR_DisplayPort: 733 dig_connector = radeon_connector->con_priv; 734 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 735 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 736 return ATOM_ENCODER_MODE_DP; 737 } else if (radeon_audio != 0) { 738 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 739 return ATOM_ENCODER_MODE_HDMI; 740 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 741 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 742 return ATOM_ENCODER_MODE_HDMI; 743 else 744 return ATOM_ENCODER_MODE_DVI; 745 } else { 746 return ATOM_ENCODER_MODE_DVI; 747 } 748 break; 749 case DRM_MODE_CONNECTOR_eDP: 750 return ATOM_ENCODER_MODE_DP; 751 case DRM_MODE_CONNECTOR_DVIA: 752 case DRM_MODE_CONNECTOR_VGA: 753 return ATOM_ENCODER_MODE_CRT; 754 break; 755 case DRM_MODE_CONNECTOR_Composite: 756 case DRM_MODE_CONNECTOR_SVIDEO: 757 case DRM_MODE_CONNECTOR_9PinDIN: 758 /* fix me */ 759 return ATOM_ENCODER_MODE_TV; 760 /*return ATOM_ENCODER_MODE_CV;*/ 761 break; 762 } 763 } 764 765 /* 766 * DIG Encoder/Transmitter Setup 767 * 768 * DCE 3.0/3.1 769 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 770 * Supports up to 3 digital outputs 771 * - 2 DIG encoder blocks. 772 * DIG1 can drive UNIPHY link A or link B 773 * DIG2 can drive UNIPHY link B or LVTMA 774 * 775 * DCE 3.2 776 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 777 * Supports up to 5 digital outputs 778 * - 2 DIG encoder blocks. 779 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 780 * 781 * DCE 4.0/5.0/6.0 782 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 783 * Supports up to 6 digital outputs 784 * - 6 DIG encoder blocks. 785 * - DIG to PHY mapping is hardcoded 786 * DIG1 drives UNIPHY0 link A, A+B 787 * DIG2 drives UNIPHY0 link B 788 * DIG3 drives UNIPHY1 link A, A+B 789 * DIG4 drives UNIPHY1 link B 790 * DIG5 drives UNIPHY2 link A, A+B 791 * DIG6 drives UNIPHY2 link B 792 * 793 * DCE 4.1 794 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 795 * Supports up to 6 digital outputs 796 * - 2 DIG encoder blocks. 797 * llano 798 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 799 * ontario 800 * DIG1 drives UNIPHY0/1/2 link A 801 * DIG2 drives UNIPHY0/1/2 link B 802 * 803 * Routing 804 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 805 * Examples: 806 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 807 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 808 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 809 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 810 */ 811 812 union dig_encoder_control { 813 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 814 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 815 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 816 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 817 }; 818 819 void 820 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 821 { 822 struct drm_device *dev = encoder->dev; 823 struct radeon_device *rdev = dev->dev_private; 824 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 825 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 826 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 827 union dig_encoder_control args; 828 int index = 0; 829 uint8_t frev, crev; 830 int dp_clock = 0; 831 int dp_lane_count = 0; 832 int hpd_id = RADEON_HPD_NONE; 833 834 if (connector) { 835 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 836 struct radeon_connector_atom_dig *dig_connector = 837 radeon_connector->con_priv; 838 839 dp_clock = dig_connector->dp_clock; 840 dp_lane_count = dig_connector->dp_lane_count; 841 hpd_id = radeon_connector->hpd.hpd; 842 } 843 844 /* no dig encoder assigned */ 845 if (dig->dig_encoder == -1) 846 return; 847 848 memset(&args, 0, sizeof(args)); 849 850 if (ASIC_IS_DCE4(rdev)) 851 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 852 else { 853 if (dig->dig_encoder) 854 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 855 else 856 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 857 } 858 859 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 860 return; 861 862 switch (frev) { 863 case 1: 864 switch (crev) { 865 case 1: 866 args.v1.ucAction = action; 867 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 868 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 869 args.v3.ucPanelMode = panel_mode; 870 else 871 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 872 873 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 874 args.v1.ucLaneNum = dp_lane_count; 875 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 876 args.v1.ucLaneNum = 8; 877 else 878 args.v1.ucLaneNum = 4; 879 880 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 881 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 882 switch (radeon_encoder->encoder_id) { 883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 884 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 885 break; 886 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 887 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 888 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 889 break; 890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 891 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 892 break; 893 } 894 if (dig->linkb) 895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 896 else 897 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 898 break; 899 case 2: 900 case 3: 901 args.v3.ucAction = action; 902 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 903 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 904 args.v3.ucPanelMode = panel_mode; 905 else 906 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 907 908 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 909 args.v3.ucLaneNum = dp_lane_count; 910 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 911 args.v3.ucLaneNum = 8; 912 else 913 args.v3.ucLaneNum = 4; 914 915 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 916 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 917 args.v3.acConfig.ucDigSel = dig->dig_encoder; 918 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 919 break; 920 case 4: 921 args.v4.ucAction = action; 922 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 923 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 924 args.v4.ucPanelMode = panel_mode; 925 else 926 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 927 928 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 929 args.v4.ucLaneNum = dp_lane_count; 930 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 931 args.v4.ucLaneNum = 8; 932 else 933 args.v4.ucLaneNum = 4; 934 935 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 936 if (dp_clock == 540000) 937 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 938 else if (dp_clock == 324000) 939 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 940 else if (dp_clock == 270000) 941 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 942 else 943 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 944 } 945 args.v4.acConfig.ucDigSel = dig->dig_encoder; 946 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 947 if (hpd_id == RADEON_HPD_NONE) 948 args.v4.ucHPD_ID = 0; 949 else 950 args.v4.ucHPD_ID = hpd_id + 1; 951 break; 952 default: 953 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 954 break; 955 } 956 break; 957 default: 958 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 959 break; 960 } 961 962 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 963 964 } 965 966 union dig_transmitter_control { 967 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 968 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 969 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 970 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 971 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 972 }; 973 974 void 975 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 976 { 977 struct drm_device *dev = encoder->dev; 978 struct radeon_device *rdev = dev->dev_private; 979 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 980 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 981 struct drm_connector *connector; 982 union dig_transmitter_control args; 983 int index = 0; 984 uint8_t frev, crev; 985 bool is_dp = false; 986 int pll_id = 0; 987 int dp_clock = 0; 988 int dp_lane_count = 0; 989 int connector_object_id = 0; 990 int igp_lane_info = 0; 991 int dig_encoder = dig->dig_encoder; 992 int hpd_id = RADEON_HPD_NONE; 993 994 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 995 connector = radeon_get_connector_for_encoder_init(encoder); 996 /* just needed to avoid bailing in the encoder check. the encoder 997 * isn't used for init 998 */ 999 dig_encoder = 0; 1000 } else 1001 connector = radeon_get_connector_for_encoder(encoder); 1002 1003 if (connector) { 1004 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1005 struct radeon_connector_atom_dig *dig_connector = 1006 radeon_connector->con_priv; 1007 1008 hpd_id = radeon_connector->hpd.hpd; 1009 dp_clock = dig_connector->dp_clock; 1010 dp_lane_count = dig_connector->dp_lane_count; 1011 connector_object_id = 1012 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1013 igp_lane_info = dig_connector->igp_lane_info; 1014 } 1015 1016 if (encoder->crtc) { 1017 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1018 pll_id = radeon_crtc->pll_id; 1019 } 1020 1021 /* no dig encoder assigned */ 1022 if (dig_encoder == -1) 1023 return; 1024 1025 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1026 is_dp = true; 1027 1028 memset(&args, 0, sizeof(args)); 1029 1030 switch (radeon_encoder->encoder_id) { 1031 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1032 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1033 break; 1034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1038 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1039 break; 1040 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1041 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1042 break; 1043 } 1044 1045 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1046 return; 1047 1048 switch (frev) { 1049 case 1: 1050 switch (crev) { 1051 case 1: 1052 args.v1.ucAction = action; 1053 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1054 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1055 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1056 args.v1.asMode.ucLaneSel = lane_num; 1057 args.v1.asMode.ucLaneSet = lane_set; 1058 } else { 1059 if (is_dp) 1060 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1061 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1062 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1063 else 1064 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1065 } 1066 1067 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1068 1069 if (dig_encoder) 1070 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1071 else 1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1073 1074 if ((rdev->flags & RADEON_IS_IGP) && 1075 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1076 if (is_dp || 1077 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1078 if (igp_lane_info & 0x1) 1079 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1080 else if (igp_lane_info & 0x2) 1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1082 else if (igp_lane_info & 0x4) 1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1084 else if (igp_lane_info & 0x8) 1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1086 } else { 1087 if (igp_lane_info & 0x3) 1088 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1089 else if (igp_lane_info & 0xc) 1090 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1091 } 1092 } 1093 1094 if (dig->linkb) 1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1096 else 1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1098 1099 if (is_dp) 1100 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1101 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1102 if (dig->coherent_mode) 1103 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1104 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1105 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1106 } 1107 break; 1108 case 2: 1109 args.v2.ucAction = action; 1110 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1111 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1112 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1113 args.v2.asMode.ucLaneSel = lane_num; 1114 args.v2.asMode.ucLaneSet = lane_set; 1115 } else { 1116 if (is_dp) 1117 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1118 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1119 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1120 else 1121 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1122 } 1123 1124 args.v2.acConfig.ucEncoderSel = dig_encoder; 1125 if (dig->linkb) 1126 args.v2.acConfig.ucLinkSel = 1; 1127 1128 switch (radeon_encoder->encoder_id) { 1129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1130 args.v2.acConfig.ucTransmitterSel = 0; 1131 break; 1132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1133 args.v2.acConfig.ucTransmitterSel = 1; 1134 break; 1135 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1136 args.v2.acConfig.ucTransmitterSel = 2; 1137 break; 1138 } 1139 1140 if (is_dp) { 1141 args.v2.acConfig.fCoherentMode = 1; 1142 args.v2.acConfig.fDPConnector = 1; 1143 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1144 if (dig->coherent_mode) 1145 args.v2.acConfig.fCoherentMode = 1; 1146 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1147 args.v2.acConfig.fDualLinkConnector = 1; 1148 } 1149 break; 1150 case 3: 1151 args.v3.ucAction = action; 1152 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1153 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1154 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1155 args.v3.asMode.ucLaneSel = lane_num; 1156 args.v3.asMode.ucLaneSet = lane_set; 1157 } else { 1158 if (is_dp) 1159 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1160 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1161 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1162 else 1163 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1164 } 1165 1166 if (is_dp) 1167 args.v3.ucLaneNum = dp_lane_count; 1168 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1169 args.v3.ucLaneNum = 8; 1170 else 1171 args.v3.ucLaneNum = 4; 1172 1173 if (dig->linkb) 1174 args.v3.acConfig.ucLinkSel = 1; 1175 if (dig_encoder & 1) 1176 args.v3.acConfig.ucEncoderSel = 1; 1177 1178 /* Select the PLL for the PHY 1179 * DP PHY should be clocked from external src if there is 1180 * one. 1181 */ 1182 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1183 if (is_dp && rdev->clock.dp_extclk) 1184 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1185 else 1186 args.v3.acConfig.ucRefClkSource = pll_id; 1187 1188 switch (radeon_encoder->encoder_id) { 1189 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1190 args.v3.acConfig.ucTransmitterSel = 0; 1191 break; 1192 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1193 args.v3.acConfig.ucTransmitterSel = 1; 1194 break; 1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1196 args.v3.acConfig.ucTransmitterSel = 2; 1197 break; 1198 } 1199 1200 if (is_dp) 1201 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1202 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1203 if (dig->coherent_mode) 1204 args.v3.acConfig.fCoherentMode = 1; 1205 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1206 args.v3.acConfig.fDualLinkConnector = 1; 1207 } 1208 break; 1209 case 4: 1210 args.v4.ucAction = action; 1211 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1212 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1213 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1214 args.v4.asMode.ucLaneSel = lane_num; 1215 args.v4.asMode.ucLaneSet = lane_set; 1216 } else { 1217 if (is_dp) 1218 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1219 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1220 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1221 else 1222 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1223 } 1224 1225 if (is_dp) 1226 args.v4.ucLaneNum = dp_lane_count; 1227 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1228 args.v4.ucLaneNum = 8; 1229 else 1230 args.v4.ucLaneNum = 4; 1231 1232 if (dig->linkb) 1233 args.v4.acConfig.ucLinkSel = 1; 1234 if (dig_encoder & 1) 1235 args.v4.acConfig.ucEncoderSel = 1; 1236 1237 /* Select the PLL for the PHY 1238 * DP PHY should be clocked from external src if there is 1239 * one. 1240 */ 1241 /* On DCE5 DCPLL usually generates the DP ref clock */ 1242 if (is_dp) { 1243 if (rdev->clock.dp_extclk) 1244 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1245 else 1246 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1247 } else 1248 args.v4.acConfig.ucRefClkSource = pll_id; 1249 1250 switch (radeon_encoder->encoder_id) { 1251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1252 args.v4.acConfig.ucTransmitterSel = 0; 1253 break; 1254 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1255 args.v4.acConfig.ucTransmitterSel = 1; 1256 break; 1257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1258 args.v4.acConfig.ucTransmitterSel = 2; 1259 break; 1260 } 1261 1262 if (is_dp) 1263 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1264 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1265 if (dig->coherent_mode) 1266 args.v4.acConfig.fCoherentMode = 1; 1267 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1268 args.v4.acConfig.fDualLinkConnector = 1; 1269 } 1270 break; 1271 case 5: 1272 args.v5.ucAction = action; 1273 if (is_dp) 1274 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1275 else 1276 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1277 1278 switch (radeon_encoder->encoder_id) { 1279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1280 if (dig->linkb) 1281 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1282 else 1283 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1284 break; 1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1286 if (dig->linkb) 1287 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1288 else 1289 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1290 break; 1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1292 if (dig->linkb) 1293 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1294 else 1295 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1296 break; 1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1298 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1299 break; 1300 } 1301 if (is_dp) 1302 args.v5.ucLaneNum = dp_lane_count; 1303 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1304 args.v5.ucLaneNum = 8; 1305 else 1306 args.v5.ucLaneNum = 4; 1307 args.v5.ucConnObjId = connector_object_id; 1308 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1309 1310 if (is_dp && rdev->clock.dp_extclk) 1311 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1312 else 1313 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1314 1315 if (is_dp) 1316 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1317 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1318 if (dig->coherent_mode) 1319 args.v5.asConfig.ucCoherentMode = 1; 1320 } 1321 if (hpd_id == RADEON_HPD_NONE) 1322 args.v5.asConfig.ucHPDSel = 0; 1323 else 1324 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1325 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1326 args.v5.ucDPLaneSet = lane_set; 1327 break; 1328 default: 1329 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1330 break; 1331 } 1332 break; 1333 default: 1334 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1335 break; 1336 } 1337 1338 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1339 } 1340 1341 bool 1342 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1343 { 1344 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1345 struct drm_device *dev = radeon_connector->base.dev; 1346 struct radeon_device *rdev = dev->dev_private; 1347 union dig_transmitter_control args; 1348 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1349 uint8_t frev, crev; 1350 1351 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1352 goto done; 1353 1354 if (!ASIC_IS_DCE4(rdev)) 1355 goto done; 1356 1357 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1358 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1359 goto done; 1360 1361 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1362 goto done; 1363 1364 memset(&args, 0, sizeof(args)); 1365 1366 args.v1.ucAction = action; 1367 1368 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1369 1370 /* wait for the panel to power up */ 1371 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1372 int i; 1373 1374 for (i = 0; i < 300; i++) { 1375 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1376 return true; 1377 mdelay(1); 1378 } 1379 return false; 1380 } 1381 done: 1382 return true; 1383 } 1384 1385 union external_encoder_control { 1386 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1387 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1388 }; 1389 1390 static void 1391 atombios_external_encoder_setup(struct drm_encoder *encoder, 1392 struct drm_encoder *ext_encoder, 1393 int action) 1394 { 1395 struct drm_device *dev = encoder->dev; 1396 struct radeon_device *rdev = dev->dev_private; 1397 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1398 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1399 union external_encoder_control args; 1400 struct drm_connector *connector; 1401 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1402 u8 frev, crev; 1403 int dp_clock = 0; 1404 int dp_lane_count = 0; 1405 int connector_object_id = 0; 1406 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1407 1408 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1409 connector = radeon_get_connector_for_encoder_init(encoder); 1410 else 1411 connector = radeon_get_connector_for_encoder(encoder); 1412 1413 if (connector) { 1414 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1415 struct radeon_connector_atom_dig *dig_connector = 1416 radeon_connector->con_priv; 1417 1418 dp_clock = dig_connector->dp_clock; 1419 dp_lane_count = dig_connector->dp_lane_count; 1420 connector_object_id = 1421 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1422 } 1423 1424 memset(&args, 0, sizeof(args)); 1425 1426 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1427 return; 1428 1429 switch (frev) { 1430 case 1: 1431 /* no params on frev 1 */ 1432 break; 1433 case 2: 1434 switch (crev) { 1435 case 1: 1436 case 2: 1437 args.v1.sDigEncoder.ucAction = action; 1438 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1439 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1440 1441 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1442 if (dp_clock == 270000) 1443 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1444 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1445 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1446 args.v1.sDigEncoder.ucLaneNum = 8; 1447 else 1448 args.v1.sDigEncoder.ucLaneNum = 4; 1449 break; 1450 case 3: 1451 args.v3.sExtEncoder.ucAction = action; 1452 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1453 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1454 else 1455 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1456 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1457 1458 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1459 if (dp_clock == 270000) 1460 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1461 else if (dp_clock == 540000) 1462 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1463 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1464 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1465 args.v3.sExtEncoder.ucLaneNum = 8; 1466 else 1467 args.v3.sExtEncoder.ucLaneNum = 4; 1468 switch (ext_enum) { 1469 case GRAPH_OBJECT_ENUM_ID1: 1470 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1471 break; 1472 case GRAPH_OBJECT_ENUM_ID2: 1473 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1474 break; 1475 case GRAPH_OBJECT_ENUM_ID3: 1476 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1477 break; 1478 } 1479 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1480 break; 1481 default: 1482 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1483 return; 1484 } 1485 break; 1486 default: 1487 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1488 return; 1489 } 1490 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1491 } 1492 1493 static void 1494 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1495 { 1496 struct drm_device *dev = encoder->dev; 1497 struct radeon_device *rdev = dev->dev_private; 1498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1499 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1500 ENABLE_YUV_PS_ALLOCATION args; 1501 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1502 uint32_t temp, reg; 1503 1504 memset(&args, 0, sizeof(args)); 1505 1506 if (rdev->family >= CHIP_R600) 1507 reg = R600_BIOS_3_SCRATCH; 1508 else 1509 reg = RADEON_BIOS_3_SCRATCH; 1510 1511 /* XXX: fix up scratch reg handling */ 1512 temp = RREG32(reg); 1513 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1514 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1515 (radeon_crtc->crtc_id << 18))); 1516 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1517 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1518 else 1519 WREG32(reg, 0); 1520 1521 if (enable) 1522 args.ucEnable = ATOM_ENABLE; 1523 args.ucCRTC = radeon_crtc->crtc_id; 1524 1525 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1526 1527 WREG32(reg, temp); 1528 } 1529 1530 static void 1531 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1532 { 1533 struct drm_device *dev = encoder->dev; 1534 struct radeon_device *rdev = dev->dev_private; 1535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1536 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1537 int index = 0; 1538 1539 memset(&args, 0, sizeof(args)); 1540 1541 switch (radeon_encoder->encoder_id) { 1542 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1544 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1545 break; 1546 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1547 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1549 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1550 break; 1551 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1552 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1553 break; 1554 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1555 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1556 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1557 else 1558 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1559 break; 1560 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1562 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1563 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1564 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1565 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1566 else 1567 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1568 break; 1569 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1570 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1571 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1572 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1573 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1574 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1575 else 1576 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1577 break; 1578 default: 1579 return; 1580 } 1581 1582 switch (mode) { 1583 case DRM_MODE_DPMS_ON: 1584 args.ucAction = ATOM_ENABLE; 1585 /* workaround for DVOOutputControl on some RS690 systems */ 1586 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1587 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1588 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1589 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1590 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1591 } else 1592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1593 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1594 args.ucAction = ATOM_LCD_BLON; 1595 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1596 } 1597 break; 1598 case DRM_MODE_DPMS_STANDBY: 1599 case DRM_MODE_DPMS_SUSPEND: 1600 case DRM_MODE_DPMS_OFF: 1601 args.ucAction = ATOM_DISABLE; 1602 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1604 args.ucAction = ATOM_LCD_BLOFF; 1605 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1606 } 1607 break; 1608 } 1609 } 1610 1611 static void 1612 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1613 { 1614 struct drm_device *dev = encoder->dev; 1615 struct radeon_device *rdev = dev->dev_private; 1616 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1617 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1618 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1619 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1620 struct radeon_connector *radeon_connector = NULL; 1621 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1622 bool travis_quirk = false; 1623 1624 if (connector) { 1625 radeon_connector = to_radeon_connector(connector); 1626 radeon_dig_connector = radeon_connector->con_priv; 1627 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1628 ENCODER_OBJECT_ID_TRAVIS) && 1629 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1630 !ASIC_IS_DCE5(rdev)) 1631 travis_quirk = true; 1632 } 1633 1634 switch (mode) { 1635 case DRM_MODE_DPMS_ON: 1636 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1637 if (!connector) 1638 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1639 else 1640 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1641 1642 /* setup and enable the encoder */ 1643 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1644 atombios_dig_encoder_setup(encoder, 1645 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1646 dig->panel_mode); 1647 if (ext_encoder) { 1648 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1649 atombios_external_encoder_setup(encoder, ext_encoder, 1650 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1651 } 1652 } else if (ASIC_IS_DCE4(rdev)) { 1653 /* setup and enable the encoder */ 1654 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1655 } else { 1656 /* setup and enable the encoder and transmitter */ 1657 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1659 } 1660 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1661 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1662 atombios_set_edp_panel_power(connector, 1663 ATOM_TRANSMITTER_ACTION_POWER_ON); 1664 radeon_dig_connector->edp_on = true; 1665 } 1666 } 1667 /* enable the transmitter */ 1668 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1669 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1670 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1671 radeon_dp_link_train(encoder, connector); 1672 if (ASIC_IS_DCE4(rdev)) 1673 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1674 } 1675 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1676 atombios_dig_transmitter_setup(encoder, 1677 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1678 if (ext_encoder) 1679 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1680 break; 1681 case DRM_MODE_DPMS_STANDBY: 1682 case DRM_MODE_DPMS_SUSPEND: 1683 case DRM_MODE_DPMS_OFF: 1684 if (ASIC_IS_DCE4(rdev)) { 1685 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1686 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1687 } 1688 if (ext_encoder) 1689 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1690 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1691 atombios_dig_transmitter_setup(encoder, 1692 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1693 1694 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1695 connector && !travis_quirk) 1696 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1697 if (ASIC_IS_DCE4(rdev)) { 1698 /* disable the transmitter */ 1699 atombios_dig_transmitter_setup(encoder, 1700 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1701 } else { 1702 /* disable the encoder and transmitter */ 1703 atombios_dig_transmitter_setup(encoder, 1704 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1705 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1706 } 1707 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1708 if (travis_quirk) 1709 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1710 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1711 atombios_set_edp_panel_power(connector, 1712 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1713 radeon_dig_connector->edp_on = false; 1714 } 1715 } 1716 break; 1717 } 1718 } 1719 1720 static void 1721 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1722 { 1723 struct drm_device *dev = encoder->dev; 1724 struct radeon_device *rdev = dev->dev_private; 1725 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1726 1727 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1728 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1729 radeon_encoder->active_device); 1730 switch (radeon_encoder->encoder_id) { 1731 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1733 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1734 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1735 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1736 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1737 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1739 radeon_atom_encoder_dpms_avivo(encoder, mode); 1740 break; 1741 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1745 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1746 radeon_atom_encoder_dpms_dig(encoder, mode); 1747 break; 1748 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1749 if (ASIC_IS_DCE5(rdev)) { 1750 switch (mode) { 1751 case DRM_MODE_DPMS_ON: 1752 atombios_dvo_setup(encoder, ATOM_ENABLE); 1753 break; 1754 case DRM_MODE_DPMS_STANDBY: 1755 case DRM_MODE_DPMS_SUSPEND: 1756 case DRM_MODE_DPMS_OFF: 1757 atombios_dvo_setup(encoder, ATOM_DISABLE); 1758 break; 1759 } 1760 } else if (ASIC_IS_DCE3(rdev)) 1761 radeon_atom_encoder_dpms_dig(encoder, mode); 1762 else 1763 radeon_atom_encoder_dpms_avivo(encoder, mode); 1764 break; 1765 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1767 if (ASIC_IS_DCE5(rdev)) { 1768 switch (mode) { 1769 case DRM_MODE_DPMS_ON: 1770 atombios_dac_setup(encoder, ATOM_ENABLE); 1771 break; 1772 case DRM_MODE_DPMS_STANDBY: 1773 case DRM_MODE_DPMS_SUSPEND: 1774 case DRM_MODE_DPMS_OFF: 1775 atombios_dac_setup(encoder, ATOM_DISABLE); 1776 break; 1777 } 1778 } else 1779 radeon_atom_encoder_dpms_avivo(encoder, mode); 1780 break; 1781 default: 1782 return; 1783 } 1784 1785 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1786 1787 } 1788 1789 union crtc_source_param { 1790 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1791 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1792 }; 1793 1794 static void 1795 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1796 { 1797 struct drm_device *dev = encoder->dev; 1798 struct radeon_device *rdev = dev->dev_private; 1799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1800 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1801 union crtc_source_param args; 1802 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1803 uint8_t frev, crev; 1804 struct radeon_encoder_atom_dig *dig; 1805 1806 memset(&args, 0, sizeof(args)); 1807 1808 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1809 return; 1810 1811 switch (frev) { 1812 case 1: 1813 switch (crev) { 1814 case 1: 1815 default: 1816 if (ASIC_IS_AVIVO(rdev)) 1817 args.v1.ucCRTC = radeon_crtc->crtc_id; 1818 else { 1819 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1820 args.v1.ucCRTC = radeon_crtc->crtc_id; 1821 } else { 1822 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1823 } 1824 } 1825 switch (radeon_encoder->encoder_id) { 1826 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1827 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1828 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1829 break; 1830 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1831 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1832 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1833 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1834 else 1835 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1836 break; 1837 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1838 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1840 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1841 break; 1842 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1843 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1844 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1845 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1846 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1847 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1848 else 1849 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1850 break; 1851 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1852 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1853 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1854 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1855 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1856 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1857 else 1858 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1859 break; 1860 } 1861 break; 1862 case 2: 1863 args.v2.ucCRTC = radeon_crtc->crtc_id; 1864 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1865 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1866 1867 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1868 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1869 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1870 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1871 else 1872 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1873 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1874 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1875 } else { 1876 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1877 } 1878 switch (radeon_encoder->encoder_id) { 1879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1884 dig = radeon_encoder->enc_priv; 1885 switch (dig->dig_encoder) { 1886 case 0: 1887 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1888 break; 1889 case 1: 1890 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1891 break; 1892 case 2: 1893 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1894 break; 1895 case 3: 1896 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1897 break; 1898 case 4: 1899 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1900 break; 1901 case 5: 1902 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1903 break; 1904 case 6: 1905 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1906 break; 1907 } 1908 break; 1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1910 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1911 break; 1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1913 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1914 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1915 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1916 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1917 else 1918 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1919 break; 1920 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1921 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1922 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1923 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1924 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1925 else 1926 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1927 break; 1928 } 1929 break; 1930 } 1931 break; 1932 default: 1933 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1934 return; 1935 } 1936 1937 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1938 1939 /* update scratch regs with new routing */ 1940 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1941 } 1942 1943 static void 1944 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1945 struct drm_display_mode *mode) 1946 { 1947 struct drm_device *dev = encoder->dev; 1948 struct radeon_device *rdev = dev->dev_private; 1949 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1950 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1951 1952 /* Funky macbooks */ 1953 if ((dev->pdev->device == 0x71C5) && 1954 (dev->pdev->subsystem_vendor == 0x106b) && 1955 (dev->pdev->subsystem_device == 0x0080)) { 1956 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1957 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1958 1959 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1960 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1961 1962 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1963 } 1964 } 1965 1966 /* set scaler clears this on some chips */ 1967 if (ASIC_IS_AVIVO(rdev) && 1968 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1969 if (ASIC_IS_DCE8(rdev)) { 1970 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1971 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 1972 CIK_INTERLEAVE_EN); 1973 else 1974 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1975 } else if (ASIC_IS_DCE4(rdev)) { 1976 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1977 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1978 EVERGREEN_INTERLEAVE_EN); 1979 else 1980 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1981 } else { 1982 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1983 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1984 AVIVO_D1MODE_INTERLEAVE_EN); 1985 else 1986 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1987 } 1988 } 1989 } 1990 1991 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1992 { 1993 struct drm_device *dev = encoder->dev; 1994 struct radeon_device *rdev = dev->dev_private; 1995 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1996 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1997 struct drm_encoder *test_encoder; 1998 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1999 uint32_t dig_enc_in_use = 0; 2000 2001 if (ASIC_IS_DCE6(rdev)) { 2002 /* DCE6 */ 2003 switch (radeon_encoder->encoder_id) { 2004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2005 if (dig->linkb) 2006 return 1; 2007 else 2008 return 0; 2009 break; 2010 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2011 if (dig->linkb) 2012 return 3; 2013 else 2014 return 2; 2015 break; 2016 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2017 if (dig->linkb) 2018 return 5; 2019 else 2020 return 4; 2021 break; 2022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2023 return 6; 2024 break; 2025 } 2026 } else if (ASIC_IS_DCE4(rdev)) { 2027 /* DCE4/5 */ 2028 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2029 /* ontario follows DCE4 */ 2030 if (rdev->family == CHIP_PALM) { 2031 if (dig->linkb) 2032 return 1; 2033 else 2034 return 0; 2035 } else 2036 /* llano follows DCE3.2 */ 2037 return radeon_crtc->crtc_id; 2038 } else { 2039 switch (radeon_encoder->encoder_id) { 2040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2041 if (dig->linkb) 2042 return 1; 2043 else 2044 return 0; 2045 break; 2046 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2047 if (dig->linkb) 2048 return 3; 2049 else 2050 return 2; 2051 break; 2052 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2053 if (dig->linkb) 2054 return 5; 2055 else 2056 return 4; 2057 break; 2058 } 2059 } 2060 } 2061 2062 /* on DCE32 and encoder can driver any block so just crtc id */ 2063 if (ASIC_IS_DCE32(rdev)) { 2064 return radeon_crtc->crtc_id; 2065 } 2066 2067 /* on DCE3 - LVTMA can only be driven by DIGB */ 2068 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2069 struct radeon_encoder *radeon_test_encoder; 2070 2071 if (encoder == test_encoder) 2072 continue; 2073 2074 if (!radeon_encoder_is_digital(test_encoder)) 2075 continue; 2076 2077 radeon_test_encoder = to_radeon_encoder(test_encoder); 2078 dig = radeon_test_encoder->enc_priv; 2079 2080 if (dig->dig_encoder >= 0) 2081 dig_enc_in_use |= (1 << dig->dig_encoder); 2082 } 2083 2084 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2085 if (dig_enc_in_use & 0x2) 2086 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2087 return 1; 2088 } 2089 if (!(dig_enc_in_use & 1)) 2090 return 0; 2091 return 1; 2092 } 2093 2094 /* This only needs to be called once at startup */ 2095 void 2096 radeon_atom_encoder_init(struct radeon_device *rdev) 2097 { 2098 struct drm_device *dev = rdev->ddev; 2099 struct drm_encoder *encoder; 2100 2101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2102 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2103 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2104 2105 switch (radeon_encoder->encoder_id) { 2106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2111 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2112 break; 2113 default: 2114 break; 2115 } 2116 2117 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2118 atombios_external_encoder_setup(encoder, ext_encoder, 2119 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2120 } 2121 } 2122 2123 static void 2124 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2125 struct drm_display_mode *mode, 2126 struct drm_display_mode *adjusted_mode) 2127 { 2128 struct drm_device *dev = encoder->dev; 2129 struct radeon_device *rdev = dev->dev_private; 2130 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2131 2132 radeon_encoder->pixel_clock = adjusted_mode->clock; 2133 2134 /* need to call this here rather than in prepare() since we need some crtc info */ 2135 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2136 2137 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2138 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2139 atombios_yuv_setup(encoder, true); 2140 else 2141 atombios_yuv_setup(encoder, false); 2142 } 2143 2144 switch (radeon_encoder->encoder_id) { 2145 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2147 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2148 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2149 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2150 break; 2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2152 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2156 /* handled in dpms */ 2157 break; 2158 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2159 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2160 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2161 atombios_dvo_setup(encoder, ATOM_ENABLE); 2162 break; 2163 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2165 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2167 atombios_dac_setup(encoder, ATOM_ENABLE); 2168 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2169 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2170 atombios_tv_setup(encoder, ATOM_ENABLE); 2171 else 2172 atombios_tv_setup(encoder, ATOM_DISABLE); 2173 } 2174 break; 2175 } 2176 2177 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2178 2179 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2180 if (rdev->asic->display.hdmi_enable) 2181 radeon_hdmi_enable(rdev, encoder, true); 2182 if (rdev->asic->display.hdmi_setmode) 2183 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2184 } 2185 } 2186 2187 static bool 2188 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2189 { 2190 struct drm_device *dev = encoder->dev; 2191 struct radeon_device *rdev = dev->dev_private; 2192 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2193 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2194 2195 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2196 ATOM_DEVICE_CV_SUPPORT | 2197 ATOM_DEVICE_CRT_SUPPORT)) { 2198 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2199 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2200 uint8_t frev, crev; 2201 2202 memset(&args, 0, sizeof(args)); 2203 2204 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2205 return false; 2206 2207 args.sDacload.ucMisc = 0; 2208 2209 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2210 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2211 args.sDacload.ucDacType = ATOM_DAC_A; 2212 else 2213 args.sDacload.ucDacType = ATOM_DAC_B; 2214 2215 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2216 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2217 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2218 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2219 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2220 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2221 if (crev >= 3) 2222 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2223 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2224 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2225 if (crev >= 3) 2226 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2227 } 2228 2229 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2230 2231 return true; 2232 } else 2233 return false; 2234 } 2235 2236 static enum drm_connector_status 2237 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2238 { 2239 struct drm_device *dev = encoder->dev; 2240 struct radeon_device *rdev = dev->dev_private; 2241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2242 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2243 uint32_t bios_0_scratch; 2244 2245 if (!atombios_dac_load_detect(encoder, connector)) { 2246 DRM_DEBUG_KMS("detect returned false \n"); 2247 return connector_status_unknown; 2248 } 2249 2250 if (rdev->family >= CHIP_R600) 2251 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2252 else 2253 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2254 2255 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2256 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2257 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2258 return connector_status_connected; 2259 } 2260 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2261 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2262 return connector_status_connected; 2263 } 2264 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2265 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2266 return connector_status_connected; 2267 } 2268 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2269 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2270 return connector_status_connected; /* CTV */ 2271 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2272 return connector_status_connected; /* STV */ 2273 } 2274 return connector_status_disconnected; 2275 } 2276 2277 static enum drm_connector_status 2278 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2279 { 2280 struct drm_device *dev = encoder->dev; 2281 struct radeon_device *rdev = dev->dev_private; 2282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2283 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2284 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2285 u32 bios_0_scratch; 2286 2287 if (!ASIC_IS_DCE4(rdev)) 2288 return connector_status_unknown; 2289 2290 if (!ext_encoder) 2291 return connector_status_unknown; 2292 2293 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2294 return connector_status_unknown; 2295 2296 /* load detect on the dp bridge */ 2297 atombios_external_encoder_setup(encoder, ext_encoder, 2298 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2299 2300 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2301 2302 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2303 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2304 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2305 return connector_status_connected; 2306 } 2307 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2308 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2309 return connector_status_connected; 2310 } 2311 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2312 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2313 return connector_status_connected; 2314 } 2315 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2316 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2317 return connector_status_connected; /* CTV */ 2318 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2319 return connector_status_connected; /* STV */ 2320 } 2321 return connector_status_disconnected; 2322 } 2323 2324 void 2325 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2326 { 2327 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2328 2329 if (ext_encoder) 2330 /* ddc_setup on the dp bridge */ 2331 atombios_external_encoder_setup(encoder, ext_encoder, 2332 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2333 2334 } 2335 2336 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2337 { 2338 struct radeon_device *rdev = encoder->dev->dev_private; 2339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2340 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2341 2342 if ((radeon_encoder->active_device & 2343 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2344 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2345 ENCODER_OBJECT_ID_NONE)) { 2346 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2347 if (dig) { 2348 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2349 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2350 if (rdev->family >= CHIP_R600) 2351 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2352 else 2353 /* RS600/690/740 have only 1 afmt block */ 2354 dig->afmt = rdev->mode_info.afmt[0]; 2355 } 2356 } 2357 } 2358 2359 radeon_atom_output_lock(encoder, true); 2360 2361 if (connector) { 2362 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2363 2364 /* select the clock/data port if it uses a router */ 2365 if (radeon_connector->router.cd_valid) 2366 radeon_router_select_cd_port(radeon_connector); 2367 2368 /* turn eDP panel on for mode set */ 2369 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2370 atombios_set_edp_panel_power(connector, 2371 ATOM_TRANSMITTER_ACTION_POWER_ON); 2372 } 2373 2374 /* this is needed for the pll/ss setup to work correctly in some cases */ 2375 atombios_set_encoder_crtc_source(encoder); 2376 /* set up the FMT blocks */ 2377 if (ASIC_IS_DCE8(rdev)) 2378 dce8_program_fmt(encoder); 2379 else if (ASIC_IS_DCE4(rdev)) 2380 dce4_program_fmt(encoder); 2381 else if (ASIC_IS_DCE3(rdev)) 2382 dce3_program_fmt(encoder); 2383 else if (ASIC_IS_AVIVO(rdev)) 2384 avivo_program_fmt(encoder); 2385 } 2386 2387 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2388 { 2389 /* need to call this here as we need the crtc set up */ 2390 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2391 radeon_atom_output_lock(encoder, false); 2392 } 2393 2394 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2395 { 2396 struct drm_device *dev = encoder->dev; 2397 struct radeon_device *rdev = dev->dev_private; 2398 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2399 struct radeon_encoder_atom_dig *dig; 2400 2401 /* check for pre-DCE3 cards with shared encoders; 2402 * can't really use the links individually, so don't disable 2403 * the encoder if it's in use by another connector 2404 */ 2405 if (!ASIC_IS_DCE3(rdev)) { 2406 struct drm_encoder *other_encoder; 2407 struct radeon_encoder *other_radeon_encoder; 2408 2409 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2410 other_radeon_encoder = to_radeon_encoder(other_encoder); 2411 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2412 drm_helper_encoder_in_use(other_encoder)) 2413 goto disable_done; 2414 } 2415 } 2416 2417 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2418 2419 switch (radeon_encoder->encoder_id) { 2420 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2421 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2422 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2423 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2424 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2425 break; 2426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2431 /* handled in dpms */ 2432 break; 2433 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2434 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2435 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2436 atombios_dvo_setup(encoder, ATOM_DISABLE); 2437 break; 2438 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2440 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2441 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2442 atombios_dac_setup(encoder, ATOM_DISABLE); 2443 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2444 atombios_tv_setup(encoder, ATOM_DISABLE); 2445 break; 2446 } 2447 2448 disable_done: 2449 if (radeon_encoder_is_digital(encoder)) { 2450 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2451 if (rdev->asic->display.hdmi_enable) 2452 radeon_hdmi_enable(rdev, encoder, false); 2453 } 2454 dig = radeon_encoder->enc_priv; 2455 dig->dig_encoder = -1; 2456 } 2457 radeon_encoder->active_device = 0; 2458 } 2459 2460 /* these are handled by the primary encoders */ 2461 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2462 { 2463 2464 } 2465 2466 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2467 { 2468 2469 } 2470 2471 static void 2472 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2473 struct drm_display_mode *mode, 2474 struct drm_display_mode *adjusted_mode) 2475 { 2476 2477 } 2478 2479 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2480 { 2481 2482 } 2483 2484 static void 2485 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2486 { 2487 2488 } 2489 2490 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2491 const struct drm_display_mode *mode, 2492 struct drm_display_mode *adjusted_mode) 2493 { 2494 return true; 2495 } 2496 2497 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2498 .dpms = radeon_atom_ext_dpms, 2499 .mode_fixup = radeon_atom_ext_mode_fixup, 2500 .prepare = radeon_atom_ext_prepare, 2501 .mode_set = radeon_atom_ext_mode_set, 2502 .commit = radeon_atom_ext_commit, 2503 .disable = radeon_atom_ext_disable, 2504 /* no detect for TMDS/LVDS yet */ 2505 }; 2506 2507 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2508 .dpms = radeon_atom_encoder_dpms, 2509 .mode_fixup = radeon_atom_mode_fixup, 2510 .prepare = radeon_atom_encoder_prepare, 2511 .mode_set = radeon_atom_encoder_mode_set, 2512 .commit = radeon_atom_encoder_commit, 2513 .disable = radeon_atom_encoder_disable, 2514 .detect = radeon_atom_dig_detect, 2515 }; 2516 2517 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2518 .dpms = radeon_atom_encoder_dpms, 2519 .mode_fixup = radeon_atom_mode_fixup, 2520 .prepare = radeon_atom_encoder_prepare, 2521 .mode_set = radeon_atom_encoder_mode_set, 2522 .commit = radeon_atom_encoder_commit, 2523 .detect = radeon_atom_dac_detect, 2524 }; 2525 2526 void radeon_enc_destroy(struct drm_encoder *encoder) 2527 { 2528 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2529 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2530 radeon_atom_backlight_exit(radeon_encoder); 2531 kfree(radeon_encoder->enc_priv); 2532 drm_encoder_cleanup(encoder); 2533 kfree(radeon_encoder); 2534 } 2535 2536 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2537 .destroy = radeon_enc_destroy, 2538 }; 2539 2540 static struct radeon_encoder_atom_dac * 2541 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2542 { 2543 struct drm_device *dev = radeon_encoder->base.dev; 2544 struct radeon_device *rdev = dev->dev_private; 2545 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2546 2547 if (!dac) 2548 return NULL; 2549 2550 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2551 return dac; 2552 } 2553 2554 static struct radeon_encoder_atom_dig * 2555 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2556 { 2557 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2558 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2559 2560 if (!dig) 2561 return NULL; 2562 2563 /* coherent mode by default */ 2564 dig->coherent_mode = true; 2565 dig->dig_encoder = -1; 2566 2567 if (encoder_enum == 2) 2568 dig->linkb = true; 2569 else 2570 dig->linkb = false; 2571 2572 return dig; 2573 } 2574 2575 void 2576 radeon_add_atom_encoder(struct drm_device *dev, 2577 uint32_t encoder_enum, 2578 uint32_t supported_device, 2579 u16 caps) 2580 { 2581 struct radeon_device *rdev = dev->dev_private; 2582 struct drm_encoder *encoder; 2583 struct radeon_encoder *radeon_encoder; 2584 2585 /* see if we already added it */ 2586 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2587 radeon_encoder = to_radeon_encoder(encoder); 2588 if (radeon_encoder->encoder_enum == encoder_enum) { 2589 radeon_encoder->devices |= supported_device; 2590 return; 2591 } 2592 2593 } 2594 2595 /* add a new one */ 2596 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2597 if (!radeon_encoder) 2598 return; 2599 2600 encoder = &radeon_encoder->base; 2601 switch (rdev->num_crtc) { 2602 case 1: 2603 encoder->possible_crtcs = 0x1; 2604 break; 2605 case 2: 2606 default: 2607 encoder->possible_crtcs = 0x3; 2608 break; 2609 case 4: 2610 encoder->possible_crtcs = 0xf; 2611 break; 2612 case 6: 2613 encoder->possible_crtcs = 0x3f; 2614 break; 2615 } 2616 2617 radeon_encoder->enc_priv = NULL; 2618 2619 radeon_encoder->encoder_enum = encoder_enum; 2620 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2621 radeon_encoder->devices = supported_device; 2622 radeon_encoder->rmx_type = RMX_OFF; 2623 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2624 radeon_encoder->is_ext_encoder = false; 2625 radeon_encoder->caps = caps; 2626 2627 switch (radeon_encoder->encoder_id) { 2628 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2629 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2631 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2632 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2633 radeon_encoder->rmx_type = RMX_FULL; 2634 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2635 DRM_MODE_ENCODER_LVDS, NULL); 2636 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2637 } else { 2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2639 DRM_MODE_ENCODER_TMDS, NULL); 2640 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2641 } 2642 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2643 break; 2644 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2645 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2646 DRM_MODE_ENCODER_DAC, NULL); 2647 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2648 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2649 break; 2650 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2652 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2653 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2654 DRM_MODE_ENCODER_TVDAC, NULL); 2655 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2656 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2657 break; 2658 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2660 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2664 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2665 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2666 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2667 radeon_encoder->rmx_type = RMX_FULL; 2668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2669 DRM_MODE_ENCODER_LVDS, NULL); 2670 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2671 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2672 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2673 DRM_MODE_ENCODER_DAC, NULL); 2674 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2675 } else { 2676 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2677 DRM_MODE_ENCODER_TMDS, NULL); 2678 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2679 } 2680 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2681 break; 2682 case ENCODER_OBJECT_ID_SI170B: 2683 case ENCODER_OBJECT_ID_CH7303: 2684 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2685 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2686 case ENCODER_OBJECT_ID_TITFP513: 2687 case ENCODER_OBJECT_ID_VT1623: 2688 case ENCODER_OBJECT_ID_HDMI_SI1930: 2689 case ENCODER_OBJECT_ID_TRAVIS: 2690 case ENCODER_OBJECT_ID_NUTMEG: 2691 /* these are handled by the primary encoders */ 2692 radeon_encoder->is_ext_encoder = true; 2693 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2694 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2695 DRM_MODE_ENCODER_LVDS, NULL); 2696 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2697 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2698 DRM_MODE_ENCODER_DAC, NULL); 2699 else 2700 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2701 DRM_MODE_ENCODER_TMDS, NULL); 2702 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2703 break; 2704 } 2705 } 2706