1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/atombios_encoders.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon.h" 33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */ 34 #include "atom.h" 35 36 static u8 37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 38 { 39 u8 backlight_level; 40 u32 bios_2_scratch; 41 42 if (rdev->family >= CHIP_R600) 43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 44 else 45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 46 47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 49 50 return backlight_level; 51 } 52 53 static void 54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 55 u8 backlight_level) 56 { 57 u32 bios_2_scratch; 58 59 if (rdev->family >= CHIP_R600) 60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 61 else 62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 63 64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 66 ATOM_S2_CURRENT_BL_LEVEL_MASK); 67 68 if (rdev->family >= CHIP_R600) 69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 70 else 71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 72 } 73 74 u8 75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 76 { 77 struct drm_device *dev = radeon_encoder->base.dev; 78 struct radeon_device *rdev = dev->dev_private; 79 80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 81 return 0; 82 83 return radeon_atom_get_backlight_level_from_reg(rdev); 84 } 85 86 void 87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 88 { 89 struct drm_encoder *encoder = &radeon_encoder->base; 90 struct drm_device *dev = radeon_encoder->base.dev; 91 struct radeon_device *rdev = dev->dev_private; 92 struct radeon_encoder_atom_dig *dig; 93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 94 int index; 95 96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 97 return; 98 99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 100 radeon_encoder->enc_priv) { 101 dig = radeon_encoder->enc_priv; 102 dig->backlight_level = level; 103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 104 105 switch (radeon_encoder->encoder_id) { 106 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 109 if (dig->backlight_level == 0) { 110 args.ucAction = ATOM_LCD_BLOFF; 111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 112 } else { 113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 115 args.ucAction = ATOM_LCD_BLON; 116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 117 } 118 break; 119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 123 if (dig->backlight_level == 0) 124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 125 else { 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 128 } 129 break; 130 default: 131 break; 132 } 133 } 134 } 135 136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 137 138 static u8 radeon_atom_bl_level(struct backlight_device *bd) 139 { 140 u8 level; 141 142 /* Convert brightness to hardware level */ 143 if (bd->props.brightness < 0) 144 level = 0; 145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 146 level = RADEON_MAX_BL_LEVEL; 147 else 148 level = bd->props.brightness; 149 150 return level; 151 } 152 153 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 154 { 155 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 156 struct radeon_encoder *radeon_encoder = pdata->encoder; 157 158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 159 160 return 0; 161 } 162 163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 164 { 165 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 166 struct radeon_encoder *radeon_encoder = pdata->encoder; 167 struct drm_device *dev = radeon_encoder->base.dev; 168 struct radeon_device *rdev = dev->dev_private; 169 170 return radeon_atom_get_backlight_level_from_reg(rdev); 171 } 172 173 static const struct backlight_ops radeon_atom_backlight_ops = { 174 .get_brightness = radeon_atom_backlight_get_brightness, 175 .update_status = radeon_atom_backlight_update_status, 176 }; 177 178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 179 struct drm_connector *drm_connector) 180 { 181 struct drm_device *dev = radeon_encoder->base.dev; 182 struct radeon_device *rdev = dev->dev_private; 183 struct backlight_device *bd; 184 struct backlight_properties props; 185 struct radeon_backlight_privdata *pdata; 186 struct radeon_encoder_atom_dig *dig; 187 u8 backlight_level; 188 char bl_name[16]; 189 190 /* Mac laptops with multiple GPUs use the gmux driver for backlight 191 * so don't register a backlight device 192 */ 193 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 194 (rdev->ddev->pci_device == 0x6741)) 195 return; 196 197 if (!radeon_encoder->enc_priv) 198 return; 199 200 if (!rdev->is_atom_bios) 201 return; 202 203 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 204 return; 205 206 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), 207 M_DRM, M_WAITOK); 208 if (!pdata) { 209 DRM_ERROR("Memory allocation failed\n"); 210 goto error; 211 } 212 213 memset(&props, 0, sizeof(props)); 214 props.max_brightness = RADEON_MAX_BL_LEVEL; 215 props.type = BACKLIGHT_RAW; 216 snprintf(bl_name, sizeof(bl_name), 217 "radeon_bl%d", dev->primary->index); 218 bd = backlight_device_register(bl_name, &drm_connector->kdev, 219 pdata, &radeon_atom_backlight_ops, &props); 220 if (IS_ERR(bd)) { 221 DRM_ERROR("Backlight registration failed\n"); 222 goto error; 223 } 224 225 pdata->encoder = radeon_encoder; 226 227 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 228 229 dig = radeon_encoder->enc_priv; 230 dig->bl_dev = bd; 231 232 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 233 bd->props.power = FB_BLANK_UNBLANK; 234 backlight_update_status(bd); 235 236 DRM_INFO("radeon atom DIG backlight initialized\n"); 237 238 return; 239 240 error: 241 kfree(pdata); 242 return; 243 } 244 245 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 246 { 247 struct drm_device *dev = radeon_encoder->base.dev; 248 struct radeon_device *rdev = dev->dev_private; 249 struct backlight_device *bd = NULL; 250 struct radeon_encoder_atom_dig *dig; 251 252 if (!radeon_encoder->enc_priv) 253 return; 254 255 if (!rdev->is_atom_bios) 256 return; 257 258 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 259 return; 260 261 dig = radeon_encoder->enc_priv; 262 bd = dig->bl_dev; 263 dig->bl_dev = NULL; 264 265 if (bd) { 266 struct radeon_legacy_backlight_privdata *pdata; 267 268 pdata = bl_get_data(bd); 269 backlight_device_unregister(bd); 270 kfree(pdata); 271 272 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 273 } 274 } 275 276 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 277 278 /* 279 * Read max backlight level 280 */ 281 static int 282 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 283 { 284 int err, val; 285 286 val = RADEON_MAX_BL_LEVEL; 287 err = sysctl_handle_int(oidp, &val, 0, req); 288 return(err); 289 } 290 291 /* 292 * Read/write backlight level 293 */ 294 static int 295 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 296 { 297 struct radeon_encoder *encoder; 298 struct radeon_encoder_atom_dig *dig; 299 int err, val; 300 301 encoder = (struct radeon_encoder *)arg1; 302 dig = encoder->enc_priv; 303 val = dig->backlight_level; 304 305 err = sysctl_handle_int(oidp, &val, 0, req); 306 if (err != 0 || req->newptr == NULL) { 307 return(err); 308 } 309 if (dig->backlight_level != val && val >= 0 && 310 val <= RADEON_MAX_BL_LEVEL) { 311 atombios_set_backlight_level(encoder, val); 312 } 313 314 return(err); 315 } 316 317 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 318 struct drm_connector *drm_connector) 319 { 320 struct drm_device *dev = radeon_encoder->base.dev; 321 struct radeon_device *rdev = dev->dev_private; 322 struct radeon_encoder_atom_dig *dig; 323 324 if (!radeon_encoder->enc_priv) 325 return; 326 327 if (!rdev->is_atom_bios) 328 return; 329 330 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 331 return; 332 333 dig = radeon_encoder->enc_priv; 334 dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 335 336 DRM_INFO("radeon atom DIG backlight initialized\n"); 337 338 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 339 OID_AUTO, "backlight_max", 340 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 341 radeon_encoder, sizeof(int), 342 sysctl_backlight_max, 343 "I", "Max backlight level"); 344 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 345 OID_AUTO, "backlight_level", 346 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 347 radeon_encoder, sizeof(int), 348 sysctl_backlight_handler, 349 "I", "Backlight level"); 350 return; 351 } 352 353 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 354 { 355 } 356 357 #endif 358 359 360 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 361 { 362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 363 switch (radeon_encoder->encoder_id) { 364 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 365 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 367 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 368 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 370 case ENCODER_OBJECT_ID_INTERNAL_DDI: 371 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 375 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 376 return true; 377 default: 378 return false; 379 } 380 } 381 382 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 383 const struct drm_display_mode *mode, 384 struct drm_display_mode *adjusted_mode) 385 { 386 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 387 struct drm_device *dev = encoder->dev; 388 struct radeon_device *rdev = dev->dev_private; 389 390 /* set the active encoder to connector routing */ 391 radeon_encoder_set_active_device(encoder); 392 drm_mode_set_crtcinfo(adjusted_mode, 0); 393 394 /* hw bug */ 395 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 396 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 397 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 398 399 /* get the native mode for LVDS */ 400 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 401 radeon_panel_mode_fixup(encoder, adjusted_mode); 402 403 /* get the native mode for TV */ 404 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 405 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 406 if (tv_dac) { 407 if (tv_dac->tv_std == TV_STD_NTSC || 408 tv_dac->tv_std == TV_STD_NTSC_J || 409 tv_dac->tv_std == TV_STD_PAL_M) 410 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 411 else 412 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 413 } 414 } 415 416 if (ASIC_IS_DCE3(rdev) && 417 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 418 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 419 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 420 radeon_dp_set_link_config(connector, adjusted_mode); 421 } 422 423 return true; 424 } 425 426 static void 427 atombios_dac_setup(struct drm_encoder *encoder, int action) 428 { 429 struct drm_device *dev = encoder->dev; 430 struct radeon_device *rdev = dev->dev_private; 431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 432 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 433 int index = 0; 434 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 435 436 memset(&args, 0, sizeof(args)); 437 438 switch (radeon_encoder->encoder_id) { 439 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 440 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 441 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 442 break; 443 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 444 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 445 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 446 break; 447 } 448 449 args.ucAction = action; 450 451 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 452 args.ucDacStandard = ATOM_DAC1_PS2; 453 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 454 args.ucDacStandard = ATOM_DAC1_CV; 455 else { 456 switch (dac_info->tv_std) { 457 case TV_STD_PAL: 458 case TV_STD_PAL_M: 459 case TV_STD_SCART_PAL: 460 case TV_STD_SECAM: 461 case TV_STD_PAL_CN: 462 args.ucDacStandard = ATOM_DAC1_PAL; 463 break; 464 case TV_STD_NTSC: 465 case TV_STD_NTSC_J: 466 case TV_STD_PAL_60: 467 default: 468 args.ucDacStandard = ATOM_DAC1_NTSC; 469 break; 470 } 471 } 472 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 473 474 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 475 476 } 477 478 static void 479 atombios_tv_setup(struct drm_encoder *encoder, int action) 480 { 481 struct drm_device *dev = encoder->dev; 482 struct radeon_device *rdev = dev->dev_private; 483 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 484 TV_ENCODER_CONTROL_PS_ALLOCATION args; 485 int index = 0; 486 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 487 488 memset(&args, 0, sizeof(args)); 489 490 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 491 492 args.sTVEncoder.ucAction = action; 493 494 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 495 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 496 else { 497 switch (dac_info->tv_std) { 498 case TV_STD_NTSC: 499 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 500 break; 501 case TV_STD_PAL: 502 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 503 break; 504 case TV_STD_PAL_M: 505 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 506 break; 507 case TV_STD_PAL_60: 508 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 509 break; 510 case TV_STD_NTSC_J: 511 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 512 break; 513 case TV_STD_SCART_PAL: 514 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 515 break; 516 case TV_STD_SECAM: 517 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 518 break; 519 case TV_STD_PAL_CN: 520 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 521 break; 522 default: 523 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 524 break; 525 } 526 } 527 528 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 529 530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 531 532 } 533 534 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 535 { 536 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 537 int bpc = 8; 538 539 if (connector) 540 bpc = radeon_get_monitor_bpc(connector); 541 542 switch (bpc) { 543 case 0: 544 return PANEL_BPC_UNDEFINE; 545 case 6: 546 return PANEL_6BIT_PER_COLOR; 547 case 8: 548 default: 549 return PANEL_8BIT_PER_COLOR; 550 case 10: 551 return PANEL_10BIT_PER_COLOR; 552 case 12: 553 return PANEL_12BIT_PER_COLOR; 554 case 16: 555 return PANEL_16BIT_PER_COLOR; 556 } 557 } 558 559 union dvo_encoder_control { 560 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 561 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 562 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 563 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 564 }; 565 566 void 567 atombios_dvo_setup(struct drm_encoder *encoder, int action) 568 { 569 struct drm_device *dev = encoder->dev; 570 struct radeon_device *rdev = dev->dev_private; 571 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 572 union dvo_encoder_control args; 573 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 574 uint8_t frev, crev; 575 576 memset(&args, 0, sizeof(args)); 577 578 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 579 return; 580 581 /* some R4xx chips have the wrong frev */ 582 if (rdev->family <= CHIP_RV410) 583 frev = 1; 584 585 switch (frev) { 586 case 1: 587 switch (crev) { 588 case 1: 589 /* R4xx, R5xx */ 590 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 591 592 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 593 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 594 595 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 596 break; 597 case 2: 598 /* RS600/690/740 */ 599 args.dvo.sDVOEncoder.ucAction = action; 600 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 601 /* DFP1, CRT1, TV1 depending on the type of port */ 602 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 603 604 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 605 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 606 break; 607 case 3: 608 /* R6xx */ 609 args.dvo_v3.ucAction = action; 610 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 611 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 612 break; 613 case 4: 614 /* DCE8 */ 615 args.dvo_v4.ucAction = action; 616 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 617 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 618 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 619 break; 620 default: 621 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 622 break; 623 } 624 break; 625 default: 626 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 627 break; 628 } 629 630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 631 } 632 633 union lvds_encoder_control { 634 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 635 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 636 }; 637 638 void 639 atombios_digital_setup(struct drm_encoder *encoder, int action) 640 { 641 struct drm_device *dev = encoder->dev; 642 struct radeon_device *rdev = dev->dev_private; 643 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 644 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 645 union lvds_encoder_control args; 646 int index = 0; 647 int hdmi_detected = 0; 648 uint8_t frev, crev; 649 650 if (!dig) 651 return; 652 653 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 654 hdmi_detected = 1; 655 656 memset(&args, 0, sizeof(args)); 657 658 switch (radeon_encoder->encoder_id) { 659 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 660 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 661 break; 662 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 663 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 664 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 665 break; 666 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 667 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 668 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 669 else 670 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 671 break; 672 } 673 674 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 675 return; 676 677 switch (frev) { 678 case 1: 679 case 2: 680 switch (crev) { 681 case 1: 682 args.v1.ucMisc = 0; 683 args.v1.ucAction = action; 684 if (hdmi_detected) 685 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 686 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 687 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 688 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 689 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 690 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 691 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 692 } else { 693 if (dig->linkb) 694 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 695 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 696 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 697 /*if (pScrn->rgbBits == 8) */ 698 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 699 } 700 break; 701 case 2: 702 case 3: 703 args.v2.ucMisc = 0; 704 args.v2.ucAction = action; 705 if (crev == 3) { 706 if (dig->coherent_mode) 707 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 708 } 709 if (hdmi_detected) 710 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 711 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 712 args.v2.ucTruncate = 0; 713 args.v2.ucSpatial = 0; 714 args.v2.ucTemporal = 0; 715 args.v2.ucFRC = 0; 716 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 717 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 718 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 719 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 720 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 721 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 722 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 723 } 724 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 725 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 726 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 727 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 728 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 729 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 730 } 731 } else { 732 if (dig->linkb) 733 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 734 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 735 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 736 } 737 break; 738 default: 739 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 740 break; 741 } 742 break; 743 default: 744 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 745 break; 746 } 747 748 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 749 } 750 751 int 752 atombios_get_encoder_mode(struct drm_encoder *encoder) 753 { 754 struct drm_device *dev = encoder->dev; 755 struct radeon_device *rdev = dev->dev_private; 756 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 757 struct drm_connector *connector; 758 struct radeon_connector *radeon_connector; 759 struct radeon_connector_atom_dig *dig_connector; 760 761 /* dp bridges are always DP */ 762 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 763 return ATOM_ENCODER_MODE_DP; 764 765 /* DVO is always DVO */ 766 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 767 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 768 return ATOM_ENCODER_MODE_DVO; 769 770 connector = radeon_get_connector_for_encoder(encoder); 771 /* if we don't have an active device yet, just use one of 772 * the connectors tied to the encoder. 773 */ 774 if (!connector) 775 connector = radeon_get_connector_for_encoder_init(encoder); 776 radeon_connector = to_radeon_connector(connector); 777 778 switch (connector->connector_type) { 779 case DRM_MODE_CONNECTOR_DVII: 780 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 781 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 782 radeon_audio && 783 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 784 return ATOM_ENCODER_MODE_HDMI; 785 else if (radeon_connector->use_digital) 786 return ATOM_ENCODER_MODE_DVI; 787 else 788 return ATOM_ENCODER_MODE_CRT; 789 break; 790 case DRM_MODE_CONNECTOR_DVID: 791 case DRM_MODE_CONNECTOR_HDMIA: 792 default: 793 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 794 radeon_audio && 795 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 796 return ATOM_ENCODER_MODE_HDMI; 797 else 798 return ATOM_ENCODER_MODE_DVI; 799 break; 800 case DRM_MODE_CONNECTOR_LVDS: 801 return ATOM_ENCODER_MODE_LVDS; 802 break; 803 case DRM_MODE_CONNECTOR_DisplayPort: 804 dig_connector = radeon_connector->con_priv; 805 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 806 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 807 return ATOM_ENCODER_MODE_DP; 808 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 809 radeon_audio && 810 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 811 return ATOM_ENCODER_MODE_HDMI; 812 else 813 return ATOM_ENCODER_MODE_DVI; 814 break; 815 case DRM_MODE_CONNECTOR_eDP: 816 return ATOM_ENCODER_MODE_DP; 817 case DRM_MODE_CONNECTOR_DVIA: 818 case DRM_MODE_CONNECTOR_VGA: 819 return ATOM_ENCODER_MODE_CRT; 820 break; 821 case DRM_MODE_CONNECTOR_Composite: 822 case DRM_MODE_CONNECTOR_SVIDEO: 823 case DRM_MODE_CONNECTOR_9PinDIN: 824 /* fix me */ 825 return ATOM_ENCODER_MODE_TV; 826 /*return ATOM_ENCODER_MODE_CV;*/ 827 break; 828 } 829 } 830 831 /* 832 * DIG Encoder/Transmitter Setup 833 * 834 * DCE 3.0/3.1 835 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 836 * Supports up to 3 digital outputs 837 * - 2 DIG encoder blocks. 838 * DIG1 can drive UNIPHY link A or link B 839 * DIG2 can drive UNIPHY link B or LVTMA 840 * 841 * DCE 3.2 842 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 843 * Supports up to 5 digital outputs 844 * - 2 DIG encoder blocks. 845 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 846 * 847 * DCE 4.0/5.0/6.0 848 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 849 * Supports up to 6 digital outputs 850 * - 6 DIG encoder blocks. 851 * - DIG to PHY mapping is hardcoded 852 * DIG1 drives UNIPHY0 link A, A+B 853 * DIG2 drives UNIPHY0 link B 854 * DIG3 drives UNIPHY1 link A, A+B 855 * DIG4 drives UNIPHY1 link B 856 * DIG5 drives UNIPHY2 link A, A+B 857 * DIG6 drives UNIPHY2 link B 858 * 859 * DCE 4.1 860 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 861 * Supports up to 6 digital outputs 862 * - 2 DIG encoder blocks. 863 * llano 864 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 865 * ontario 866 * DIG1 drives UNIPHY0/1/2 link A 867 * DIG2 drives UNIPHY0/1/2 link B 868 * 869 * Routing 870 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 871 * Examples: 872 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 873 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 874 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 875 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 876 */ 877 878 union dig_encoder_control { 879 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 880 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 881 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 882 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 883 }; 884 885 void 886 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 887 { 888 struct drm_device *dev = encoder->dev; 889 struct radeon_device *rdev = dev->dev_private; 890 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 891 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 892 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 893 union dig_encoder_control args; 894 int index = 0; 895 uint8_t frev, crev; 896 int dp_clock = 0; 897 int dp_lane_count = 0; 898 int hpd_id = RADEON_HPD_NONE; 899 900 if (connector) { 901 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 902 struct radeon_connector_atom_dig *dig_connector = 903 radeon_connector->con_priv; 904 905 dp_clock = dig_connector->dp_clock; 906 dp_lane_count = dig_connector->dp_lane_count; 907 hpd_id = radeon_connector->hpd.hpd; 908 } 909 910 /* no dig encoder assigned */ 911 if (dig->dig_encoder == -1) 912 return; 913 914 memset(&args, 0, sizeof(args)); 915 916 if (ASIC_IS_DCE4(rdev)) 917 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 918 else { 919 if (dig->dig_encoder) 920 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 921 else 922 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 923 } 924 925 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 926 return; 927 928 switch (frev) { 929 case 1: 930 switch (crev) { 931 case 1: 932 args.v1.ucAction = action; 933 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 934 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 935 args.v3.ucPanelMode = panel_mode; 936 else 937 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 938 939 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 940 args.v1.ucLaneNum = dp_lane_count; 941 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 942 args.v1.ucLaneNum = 8; 943 else 944 args.v1.ucLaneNum = 4; 945 946 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 947 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 948 switch (radeon_encoder->encoder_id) { 949 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 950 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 951 break; 952 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 953 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 954 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 955 break; 956 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 957 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 958 break; 959 } 960 if (dig->linkb) 961 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 962 else 963 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 964 break; 965 case 2: 966 case 3: 967 args.v3.ucAction = action; 968 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 969 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 970 args.v3.ucPanelMode = panel_mode; 971 else 972 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 973 974 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 975 args.v3.ucLaneNum = dp_lane_count; 976 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 977 args.v3.ucLaneNum = 8; 978 else 979 args.v3.ucLaneNum = 4; 980 981 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 982 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 983 args.v3.acConfig.ucDigSel = dig->dig_encoder; 984 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 985 break; 986 case 4: 987 args.v4.ucAction = action; 988 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 989 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 990 args.v4.ucPanelMode = panel_mode; 991 else 992 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 993 994 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 995 args.v4.ucLaneNum = dp_lane_count; 996 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 997 args.v4.ucLaneNum = 8; 998 else 999 args.v4.ucLaneNum = 4; 1000 1001 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 1002 if (dp_clock == 540000) 1003 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 1004 else if (dp_clock == 324000) 1005 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 1006 else if (dp_clock == 270000) 1007 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 1008 else 1009 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 1010 } 1011 args.v4.acConfig.ucDigSel = dig->dig_encoder; 1012 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 1013 if (hpd_id == RADEON_HPD_NONE) 1014 args.v4.ucHPD_ID = 0; 1015 else 1016 args.v4.ucHPD_ID = hpd_id + 1; 1017 break; 1018 default: 1019 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1020 break; 1021 } 1022 break; 1023 default: 1024 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1025 break; 1026 } 1027 1028 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1029 1030 } 1031 1032 union dig_transmitter_control { 1033 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1034 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1035 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1036 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1037 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1038 }; 1039 1040 void 1041 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1042 { 1043 struct drm_device *dev = encoder->dev; 1044 struct radeon_device *rdev = dev->dev_private; 1045 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1046 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1047 struct drm_connector *connector; 1048 union dig_transmitter_control args; 1049 int index = 0; 1050 uint8_t frev, crev; 1051 bool is_dp = false; 1052 int pll_id = 0; 1053 int dp_clock = 0; 1054 int dp_lane_count = 0; 1055 int connector_object_id = 0; 1056 int igp_lane_info = 0; 1057 int dig_encoder = dig->dig_encoder; 1058 int hpd_id = RADEON_HPD_NONE; 1059 1060 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1061 connector = radeon_get_connector_for_encoder_init(encoder); 1062 /* just needed to avoid bailing in the encoder check. the encoder 1063 * isn't used for init 1064 */ 1065 dig_encoder = 0; 1066 } else 1067 connector = radeon_get_connector_for_encoder(encoder); 1068 1069 if (connector) { 1070 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1071 struct radeon_connector_atom_dig *dig_connector = 1072 radeon_connector->con_priv; 1073 1074 hpd_id = radeon_connector->hpd.hpd; 1075 dp_clock = dig_connector->dp_clock; 1076 dp_lane_count = dig_connector->dp_lane_count; 1077 connector_object_id = 1078 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1079 igp_lane_info = dig_connector->igp_lane_info; 1080 } 1081 1082 if (encoder->crtc) { 1083 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1084 pll_id = radeon_crtc->pll_id; 1085 } 1086 1087 /* no dig encoder assigned */ 1088 if (dig_encoder == -1) 1089 return; 1090 1091 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1092 is_dp = true; 1093 1094 memset(&args, 0, sizeof(args)); 1095 1096 switch (radeon_encoder->encoder_id) { 1097 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1098 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1099 break; 1100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1104 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1105 break; 1106 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1107 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1108 break; 1109 } 1110 1111 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1112 return; 1113 1114 switch (frev) { 1115 case 1: 1116 switch (crev) { 1117 case 1: 1118 args.v1.ucAction = action; 1119 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1120 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1121 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1122 args.v1.asMode.ucLaneSel = lane_num; 1123 args.v1.asMode.ucLaneSet = lane_set; 1124 } else { 1125 if (is_dp) 1126 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1127 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1128 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1129 else 1130 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1131 } 1132 1133 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1134 1135 if (dig_encoder) 1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1137 else 1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1139 1140 if ((rdev->flags & RADEON_IS_IGP) && 1141 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1142 if (is_dp || 1143 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1144 if (igp_lane_info & 0x1) 1145 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1146 else if (igp_lane_info & 0x2) 1147 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1148 else if (igp_lane_info & 0x4) 1149 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1150 else if (igp_lane_info & 0x8) 1151 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1152 } else { 1153 if (igp_lane_info & 0x3) 1154 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1155 else if (igp_lane_info & 0xc) 1156 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1157 } 1158 } 1159 1160 if (dig->linkb) 1161 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1162 else 1163 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1164 1165 if (is_dp) 1166 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1167 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1168 if (dig->coherent_mode) 1169 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1170 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1171 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1172 } 1173 break; 1174 case 2: 1175 args.v2.ucAction = action; 1176 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1177 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1178 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1179 args.v2.asMode.ucLaneSel = lane_num; 1180 args.v2.asMode.ucLaneSet = lane_set; 1181 } else { 1182 if (is_dp) 1183 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1184 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1185 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1186 else 1187 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1188 } 1189 1190 args.v2.acConfig.ucEncoderSel = dig_encoder; 1191 if (dig->linkb) 1192 args.v2.acConfig.ucLinkSel = 1; 1193 1194 switch (radeon_encoder->encoder_id) { 1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1196 args.v2.acConfig.ucTransmitterSel = 0; 1197 break; 1198 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1199 args.v2.acConfig.ucTransmitterSel = 1; 1200 break; 1201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1202 args.v2.acConfig.ucTransmitterSel = 2; 1203 break; 1204 } 1205 1206 if (is_dp) { 1207 args.v2.acConfig.fCoherentMode = 1; 1208 args.v2.acConfig.fDPConnector = 1; 1209 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1210 if (dig->coherent_mode) 1211 args.v2.acConfig.fCoherentMode = 1; 1212 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1213 args.v2.acConfig.fDualLinkConnector = 1; 1214 } 1215 break; 1216 case 3: 1217 args.v3.ucAction = action; 1218 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1219 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1220 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1221 args.v3.asMode.ucLaneSel = lane_num; 1222 args.v3.asMode.ucLaneSet = lane_set; 1223 } else { 1224 if (is_dp) 1225 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1226 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1227 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1228 else 1229 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1230 } 1231 1232 if (is_dp) 1233 args.v3.ucLaneNum = dp_lane_count; 1234 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1235 args.v3.ucLaneNum = 8; 1236 else 1237 args.v3.ucLaneNum = 4; 1238 1239 if (dig->linkb) 1240 args.v3.acConfig.ucLinkSel = 1; 1241 if (dig_encoder & 1) 1242 args.v3.acConfig.ucEncoderSel = 1; 1243 1244 /* Select the PLL for the PHY 1245 * DP PHY should be clocked from external src if there is 1246 * one. 1247 */ 1248 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1249 if (is_dp && rdev->clock.dp_extclk) 1250 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1251 else 1252 args.v3.acConfig.ucRefClkSource = pll_id; 1253 1254 switch (radeon_encoder->encoder_id) { 1255 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1256 args.v3.acConfig.ucTransmitterSel = 0; 1257 break; 1258 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1259 args.v3.acConfig.ucTransmitterSel = 1; 1260 break; 1261 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1262 args.v3.acConfig.ucTransmitterSel = 2; 1263 break; 1264 } 1265 1266 if (is_dp) 1267 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1268 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1269 if (dig->coherent_mode) 1270 args.v3.acConfig.fCoherentMode = 1; 1271 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1272 args.v3.acConfig.fDualLinkConnector = 1; 1273 } 1274 break; 1275 case 4: 1276 args.v4.ucAction = action; 1277 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1278 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1279 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1280 args.v4.asMode.ucLaneSel = lane_num; 1281 args.v4.asMode.ucLaneSet = lane_set; 1282 } else { 1283 if (is_dp) 1284 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1285 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1286 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1287 else 1288 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1289 } 1290 1291 if (is_dp) 1292 args.v4.ucLaneNum = dp_lane_count; 1293 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1294 args.v4.ucLaneNum = 8; 1295 else 1296 args.v4.ucLaneNum = 4; 1297 1298 if (dig->linkb) 1299 args.v4.acConfig.ucLinkSel = 1; 1300 if (dig_encoder & 1) 1301 args.v4.acConfig.ucEncoderSel = 1; 1302 1303 /* Select the PLL for the PHY 1304 * DP PHY should be clocked from external src if there is 1305 * one. 1306 */ 1307 /* On DCE5 DCPLL usually generates the DP ref clock */ 1308 if (is_dp) { 1309 if (rdev->clock.dp_extclk) 1310 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1311 else 1312 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1313 } else 1314 args.v4.acConfig.ucRefClkSource = pll_id; 1315 1316 switch (radeon_encoder->encoder_id) { 1317 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1318 args.v4.acConfig.ucTransmitterSel = 0; 1319 break; 1320 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1321 args.v4.acConfig.ucTransmitterSel = 1; 1322 break; 1323 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1324 args.v4.acConfig.ucTransmitterSel = 2; 1325 break; 1326 } 1327 1328 if (is_dp) 1329 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1330 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1331 if (dig->coherent_mode) 1332 args.v4.acConfig.fCoherentMode = 1; 1333 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1334 args.v4.acConfig.fDualLinkConnector = 1; 1335 } 1336 break; 1337 case 5: 1338 args.v5.ucAction = action; 1339 if (is_dp) 1340 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1341 else 1342 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1343 1344 switch (radeon_encoder->encoder_id) { 1345 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1346 if (dig->linkb) 1347 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1348 else 1349 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1350 break; 1351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1352 if (dig->linkb) 1353 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1354 else 1355 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1356 break; 1357 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1358 if (dig->linkb) 1359 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1360 else 1361 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1362 break; 1363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1364 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1365 break; 1366 } 1367 if (is_dp) 1368 args.v5.ucLaneNum = dp_lane_count; 1369 else if (radeon_encoder->pixel_clock > 165000) 1370 args.v5.ucLaneNum = 8; 1371 else 1372 args.v5.ucLaneNum = 4; 1373 args.v5.ucConnObjId = connector_object_id; 1374 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1375 1376 if (is_dp && rdev->clock.dp_extclk) 1377 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1378 else 1379 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1380 1381 if (is_dp) 1382 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1383 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1384 if (dig->coherent_mode) 1385 args.v5.asConfig.ucCoherentMode = 1; 1386 } 1387 if (hpd_id == RADEON_HPD_NONE) 1388 args.v5.asConfig.ucHPDSel = 0; 1389 else 1390 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1391 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1392 args.v5.ucDPLaneSet = lane_set; 1393 break; 1394 default: 1395 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1396 break; 1397 } 1398 break; 1399 default: 1400 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1401 break; 1402 } 1403 1404 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1405 } 1406 1407 bool 1408 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1409 { 1410 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1411 struct drm_device *dev = radeon_connector->base.dev; 1412 struct radeon_device *rdev = dev->dev_private; 1413 union dig_transmitter_control args; 1414 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1415 uint8_t frev, crev; 1416 1417 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1418 goto done; 1419 1420 if (!ASIC_IS_DCE4(rdev)) 1421 goto done; 1422 1423 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1424 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1425 goto done; 1426 1427 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1428 goto done; 1429 1430 memset(&args, 0, sizeof(args)); 1431 1432 args.v1.ucAction = action; 1433 1434 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1435 1436 /* wait for the panel to power up */ 1437 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1438 int i; 1439 1440 for (i = 0; i < 300; i++) { 1441 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1442 return true; 1443 mdelay(1); 1444 } 1445 return false; 1446 } 1447 done: 1448 return true; 1449 } 1450 1451 union external_encoder_control { 1452 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1453 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1454 }; 1455 1456 static void 1457 atombios_external_encoder_setup(struct drm_encoder *encoder, 1458 struct drm_encoder *ext_encoder, 1459 int action) 1460 { 1461 struct drm_device *dev = encoder->dev; 1462 struct radeon_device *rdev = dev->dev_private; 1463 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1464 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1465 union external_encoder_control args; 1466 struct drm_connector *connector; 1467 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1468 u8 frev, crev; 1469 int dp_clock = 0; 1470 int dp_lane_count = 0; 1471 int connector_object_id = 0; 1472 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1473 1474 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1475 connector = radeon_get_connector_for_encoder_init(encoder); 1476 else 1477 connector = radeon_get_connector_for_encoder(encoder); 1478 1479 if (connector) { 1480 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1481 struct radeon_connector_atom_dig *dig_connector = 1482 radeon_connector->con_priv; 1483 1484 dp_clock = dig_connector->dp_clock; 1485 dp_lane_count = dig_connector->dp_lane_count; 1486 connector_object_id = 1487 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1488 } 1489 1490 memset(&args, 0, sizeof(args)); 1491 1492 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1493 return; 1494 1495 switch (frev) { 1496 case 1: 1497 /* no params on frev 1 */ 1498 break; 1499 case 2: 1500 switch (crev) { 1501 case 1: 1502 case 2: 1503 args.v1.sDigEncoder.ucAction = action; 1504 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1505 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1506 1507 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1508 if (dp_clock == 270000) 1509 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1510 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1511 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1512 args.v1.sDigEncoder.ucLaneNum = 8; 1513 else 1514 args.v1.sDigEncoder.ucLaneNum = 4; 1515 break; 1516 case 3: 1517 args.v3.sExtEncoder.ucAction = action; 1518 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1519 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1520 else 1521 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1522 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1523 1524 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1525 if (dp_clock == 270000) 1526 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1527 else if (dp_clock == 540000) 1528 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1529 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1530 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1531 args.v3.sExtEncoder.ucLaneNum = 8; 1532 else 1533 args.v3.sExtEncoder.ucLaneNum = 4; 1534 switch (ext_enum) { 1535 case GRAPH_OBJECT_ENUM_ID1: 1536 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1537 break; 1538 case GRAPH_OBJECT_ENUM_ID2: 1539 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1540 break; 1541 case GRAPH_OBJECT_ENUM_ID3: 1542 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1543 break; 1544 } 1545 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1546 break; 1547 default: 1548 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1549 return; 1550 } 1551 break; 1552 default: 1553 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1554 return; 1555 } 1556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1557 } 1558 1559 static void 1560 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1561 { 1562 struct drm_device *dev = encoder->dev; 1563 struct radeon_device *rdev = dev->dev_private; 1564 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1565 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1566 ENABLE_YUV_PS_ALLOCATION args; 1567 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1568 uint32_t temp, reg; 1569 1570 memset(&args, 0, sizeof(args)); 1571 1572 if (rdev->family >= CHIP_R600) 1573 reg = R600_BIOS_3_SCRATCH; 1574 else 1575 reg = RADEON_BIOS_3_SCRATCH; 1576 1577 /* XXX: fix up scratch reg handling */ 1578 temp = RREG32(reg); 1579 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1580 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1581 (radeon_crtc->crtc_id << 18))); 1582 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1583 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1584 else 1585 WREG32(reg, 0); 1586 1587 if (enable) 1588 args.ucEnable = ATOM_ENABLE; 1589 args.ucCRTC = radeon_crtc->crtc_id; 1590 1591 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1592 1593 WREG32(reg, temp); 1594 } 1595 1596 static void 1597 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1598 { 1599 struct drm_device *dev = encoder->dev; 1600 struct radeon_device *rdev = dev->dev_private; 1601 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1602 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1603 int index = 0; 1604 1605 memset(&args, 0, sizeof(args)); 1606 1607 switch (radeon_encoder->encoder_id) { 1608 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1610 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1611 break; 1612 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1613 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1615 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1616 break; 1617 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1618 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1619 break; 1620 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1621 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1622 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1623 else 1624 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1625 break; 1626 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1628 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1629 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1630 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1631 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1632 else 1633 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1634 break; 1635 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1636 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1637 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1638 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1639 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1640 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1641 else 1642 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1643 break; 1644 default: 1645 return; 1646 } 1647 1648 switch (mode) { 1649 case DRM_MODE_DPMS_ON: 1650 args.ucAction = ATOM_ENABLE; 1651 /* workaround for DVOOutputControl on some RS690 systems */ 1652 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1653 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1654 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1655 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1656 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1657 } else 1658 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1659 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1660 args.ucAction = ATOM_LCD_BLON; 1661 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1662 } 1663 break; 1664 case DRM_MODE_DPMS_STANDBY: 1665 case DRM_MODE_DPMS_SUSPEND: 1666 case DRM_MODE_DPMS_OFF: 1667 args.ucAction = ATOM_DISABLE; 1668 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1669 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1670 args.ucAction = ATOM_LCD_BLOFF; 1671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1672 } 1673 break; 1674 } 1675 } 1676 1677 static void 1678 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1679 { 1680 struct drm_device *dev = encoder->dev; 1681 struct radeon_device *rdev = dev->dev_private; 1682 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1683 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1684 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1685 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1686 struct radeon_connector *radeon_connector = NULL; 1687 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1688 1689 if (connector) { 1690 radeon_connector = to_radeon_connector(connector); 1691 radeon_dig_connector = radeon_connector->con_priv; 1692 } 1693 1694 switch (mode) { 1695 case DRM_MODE_DPMS_ON: 1696 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1697 if (!connector) 1698 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1699 else 1700 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1701 1702 /* setup and enable the encoder */ 1703 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1704 atombios_dig_encoder_setup(encoder, 1705 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1706 dig->panel_mode); 1707 if (ext_encoder) { 1708 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1709 atombios_external_encoder_setup(encoder, ext_encoder, 1710 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1711 } 1712 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1713 } else if (ASIC_IS_DCE4(rdev)) { 1714 /* setup and enable the encoder */ 1715 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1716 /* enable the transmitter */ 1717 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1718 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1719 } else { 1720 /* setup and enable the encoder and transmitter */ 1721 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1722 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1723 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1724 /* some early dce3.2 boards have a bug in their transmitter control table */ 1725 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730)) 1726 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1727 } 1728 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1729 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1730 atombios_set_edp_panel_power(connector, 1731 ATOM_TRANSMITTER_ACTION_POWER_ON); 1732 radeon_dig_connector->edp_on = true; 1733 } 1734 radeon_dp_link_train(encoder, connector); 1735 if (ASIC_IS_DCE4(rdev)) 1736 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1737 } 1738 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1739 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1740 break; 1741 case DRM_MODE_DPMS_STANDBY: 1742 case DRM_MODE_DPMS_SUSPEND: 1743 case DRM_MODE_DPMS_OFF: 1744 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1745 /* disable the transmitter */ 1746 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1747 } else if (ASIC_IS_DCE4(rdev)) { 1748 /* disable the transmitter */ 1749 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1750 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1751 } else { 1752 /* disable the encoder and transmitter */ 1753 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1754 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1755 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1756 } 1757 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1758 if (ASIC_IS_DCE4(rdev)) 1759 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1760 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1761 atombios_set_edp_panel_power(connector, 1762 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1763 radeon_dig_connector->edp_on = false; 1764 } 1765 } 1766 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1767 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1768 break; 1769 } 1770 } 1771 1772 static void 1773 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1774 struct drm_encoder *ext_encoder, 1775 int mode) 1776 { 1777 struct drm_device *dev = encoder->dev; 1778 struct radeon_device *rdev = dev->dev_private; 1779 1780 switch (mode) { 1781 case DRM_MODE_DPMS_ON: 1782 default: 1783 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1784 atombios_external_encoder_setup(encoder, ext_encoder, 1785 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1786 atombios_external_encoder_setup(encoder, ext_encoder, 1787 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1788 } else 1789 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1790 break; 1791 case DRM_MODE_DPMS_STANDBY: 1792 case DRM_MODE_DPMS_SUSPEND: 1793 case DRM_MODE_DPMS_OFF: 1794 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1795 atombios_external_encoder_setup(encoder, ext_encoder, 1796 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1797 atombios_external_encoder_setup(encoder, ext_encoder, 1798 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1799 } else 1800 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1801 break; 1802 } 1803 } 1804 1805 static void 1806 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1807 { 1808 struct drm_device *dev = encoder->dev; 1809 struct radeon_device *rdev = dev->dev_private; 1810 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1811 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1812 1813 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1814 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1815 radeon_encoder->active_device); 1816 switch (radeon_encoder->encoder_id) { 1817 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1819 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1820 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1821 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1822 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1823 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1824 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1825 radeon_atom_encoder_dpms_avivo(encoder, mode); 1826 break; 1827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1828 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1829 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1830 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1832 radeon_atom_encoder_dpms_dig(encoder, mode); 1833 break; 1834 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1835 if (ASIC_IS_DCE5(rdev)) { 1836 switch (mode) { 1837 case DRM_MODE_DPMS_ON: 1838 atombios_dvo_setup(encoder, ATOM_ENABLE); 1839 break; 1840 case DRM_MODE_DPMS_STANDBY: 1841 case DRM_MODE_DPMS_SUSPEND: 1842 case DRM_MODE_DPMS_OFF: 1843 atombios_dvo_setup(encoder, ATOM_DISABLE); 1844 break; 1845 } 1846 } else if (ASIC_IS_DCE3(rdev)) 1847 radeon_atom_encoder_dpms_dig(encoder, mode); 1848 else 1849 radeon_atom_encoder_dpms_avivo(encoder, mode); 1850 break; 1851 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1852 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1853 if (ASIC_IS_DCE5(rdev)) { 1854 switch (mode) { 1855 case DRM_MODE_DPMS_ON: 1856 atombios_dac_setup(encoder, ATOM_ENABLE); 1857 break; 1858 case DRM_MODE_DPMS_STANDBY: 1859 case DRM_MODE_DPMS_SUSPEND: 1860 case DRM_MODE_DPMS_OFF: 1861 atombios_dac_setup(encoder, ATOM_DISABLE); 1862 break; 1863 } 1864 } else 1865 radeon_atom_encoder_dpms_avivo(encoder, mode); 1866 break; 1867 default: 1868 return; 1869 } 1870 1871 if (ext_encoder) 1872 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1873 1874 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1875 1876 } 1877 1878 union crtc_source_param { 1879 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1880 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1881 }; 1882 1883 static void 1884 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1885 { 1886 struct drm_device *dev = encoder->dev; 1887 struct radeon_device *rdev = dev->dev_private; 1888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1889 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1890 union crtc_source_param args; 1891 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1892 uint8_t frev, crev; 1893 struct radeon_encoder_atom_dig *dig; 1894 1895 memset(&args, 0, sizeof(args)); 1896 1897 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1898 return; 1899 1900 switch (frev) { 1901 case 1: 1902 switch (crev) { 1903 case 1: 1904 default: 1905 if (ASIC_IS_AVIVO(rdev)) 1906 args.v1.ucCRTC = radeon_crtc->crtc_id; 1907 else { 1908 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1909 args.v1.ucCRTC = radeon_crtc->crtc_id; 1910 } else { 1911 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1912 } 1913 } 1914 switch (radeon_encoder->encoder_id) { 1915 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1917 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1918 break; 1919 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1920 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1921 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1922 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1923 else 1924 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1925 break; 1926 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1927 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1928 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1929 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1930 break; 1931 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1932 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1933 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1934 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1935 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1936 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1937 else 1938 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1939 break; 1940 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1941 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1942 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1943 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1944 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1945 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1946 else 1947 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1948 break; 1949 } 1950 break; 1951 case 2: 1952 args.v2.ucCRTC = radeon_crtc->crtc_id; 1953 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1954 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1955 1956 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1957 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1958 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1959 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1960 else 1961 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1962 } else 1963 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1964 switch (radeon_encoder->encoder_id) { 1965 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1966 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1968 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1969 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1970 dig = radeon_encoder->enc_priv; 1971 switch (dig->dig_encoder) { 1972 case 0: 1973 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1974 break; 1975 case 1: 1976 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1977 break; 1978 case 2: 1979 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1980 break; 1981 case 3: 1982 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1983 break; 1984 case 4: 1985 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1986 break; 1987 case 5: 1988 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1989 break; 1990 case 6: 1991 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1992 break; 1993 } 1994 break; 1995 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1996 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1997 break; 1998 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1999 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2000 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2001 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2002 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2003 else 2004 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 2005 break; 2006 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2007 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2008 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2009 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2010 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2011 else 2012 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 2013 break; 2014 } 2015 break; 2016 } 2017 break; 2018 default: 2019 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2020 return; 2021 } 2022 2023 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2024 2025 /* update scratch regs with new routing */ 2026 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2027 } 2028 2029 static void 2030 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2031 struct drm_display_mode *mode) 2032 { 2033 struct drm_device *dev = encoder->dev; 2034 struct radeon_device *rdev = dev->dev_private; 2035 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2036 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2037 2038 /* Funky macbooks */ 2039 if ((dev->pci_device == 0x71C5) && 2040 (dev->pci_subvendor == 0x106b) && 2041 (dev->pci_subdevice == 0x0080)) { 2042 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2043 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2044 2045 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2046 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2047 2048 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2049 } 2050 } 2051 2052 /* set scaler clears this on some chips */ 2053 if (ASIC_IS_AVIVO(rdev) && 2054 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2055 if (ASIC_IS_DCE8(rdev)) { 2056 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2057 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2058 CIK_INTERLEAVE_EN); 2059 else 2060 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2061 } else if (ASIC_IS_DCE4(rdev)) { 2062 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2063 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2064 EVERGREEN_INTERLEAVE_EN); 2065 else 2066 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2067 } else { 2068 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2069 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2070 AVIVO_D1MODE_INTERLEAVE_EN); 2071 else 2072 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2073 } 2074 } 2075 } 2076 2077 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 2078 { 2079 struct drm_device *dev = encoder->dev; 2080 struct radeon_device *rdev = dev->dev_private; 2081 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2082 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2083 struct drm_encoder *test_encoder; 2084 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2085 uint32_t dig_enc_in_use = 0; 2086 2087 if (ASIC_IS_DCE6(rdev)) { 2088 /* DCE6 */ 2089 switch (radeon_encoder->encoder_id) { 2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2091 if (dig->linkb) 2092 return 1; 2093 else 2094 return 0; 2095 break; 2096 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2097 if (dig->linkb) 2098 return 3; 2099 else 2100 return 2; 2101 break; 2102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2103 if (dig->linkb) 2104 return 5; 2105 else 2106 return 4; 2107 break; 2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2109 return 6; 2110 break; 2111 } 2112 } else if (ASIC_IS_DCE4(rdev)) { 2113 /* DCE4/5 */ 2114 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2115 /* ontario follows DCE4 */ 2116 if (rdev->family == CHIP_PALM) { 2117 if (dig->linkb) 2118 return 1; 2119 else 2120 return 0; 2121 } else 2122 /* llano follows DCE3.2 */ 2123 return radeon_crtc->crtc_id; 2124 } else { 2125 switch (radeon_encoder->encoder_id) { 2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2127 if (dig->linkb) 2128 return 1; 2129 else 2130 return 0; 2131 break; 2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2133 if (dig->linkb) 2134 return 3; 2135 else 2136 return 2; 2137 break; 2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2139 if (dig->linkb) 2140 return 5; 2141 else 2142 return 4; 2143 break; 2144 } 2145 } 2146 } 2147 2148 /* on DCE32 and encoder can driver any block so just crtc id */ 2149 if (ASIC_IS_DCE32(rdev)) { 2150 return radeon_crtc->crtc_id; 2151 } 2152 2153 /* on DCE3 - LVTMA can only be driven by DIGB */ 2154 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2155 struct radeon_encoder *radeon_test_encoder; 2156 2157 if (encoder == test_encoder) 2158 continue; 2159 2160 if (!radeon_encoder_is_digital(test_encoder)) 2161 continue; 2162 2163 radeon_test_encoder = to_radeon_encoder(test_encoder); 2164 dig = radeon_test_encoder->enc_priv; 2165 2166 if (dig->dig_encoder >= 0) 2167 dig_enc_in_use |= (1 << dig->dig_encoder); 2168 } 2169 2170 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2171 if (dig_enc_in_use & 0x2) 2172 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2173 return 1; 2174 } 2175 if (!(dig_enc_in_use & 1)) 2176 return 0; 2177 return 1; 2178 } 2179 2180 /* This only needs to be called once at startup */ 2181 void 2182 radeon_atom_encoder_init(struct radeon_device *rdev) 2183 { 2184 struct drm_device *dev = rdev->ddev; 2185 struct drm_encoder *encoder; 2186 2187 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2189 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2190 2191 switch (radeon_encoder->encoder_id) { 2192 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2193 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2196 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2197 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2198 break; 2199 default: 2200 break; 2201 } 2202 2203 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2204 atombios_external_encoder_setup(encoder, ext_encoder, 2205 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2206 } 2207 } 2208 2209 static void 2210 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2211 struct drm_display_mode *mode, 2212 struct drm_display_mode *adjusted_mode) 2213 { 2214 struct drm_device *dev = encoder->dev; 2215 struct radeon_device *rdev = dev->dev_private; 2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2217 2218 radeon_encoder->pixel_clock = adjusted_mode->clock; 2219 2220 /* need to call this here rather than in prepare() since we need some crtc info */ 2221 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2222 2223 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2224 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2225 atombios_yuv_setup(encoder, true); 2226 else 2227 atombios_yuv_setup(encoder, false); 2228 } 2229 2230 switch (radeon_encoder->encoder_id) { 2231 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2232 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2233 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2234 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2235 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2236 break; 2237 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2240 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2241 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2242 /* handled in dpms */ 2243 break; 2244 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2245 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2246 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2247 atombios_dvo_setup(encoder, ATOM_ENABLE); 2248 break; 2249 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2250 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2251 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2252 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2253 atombios_dac_setup(encoder, ATOM_ENABLE); 2254 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2255 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2256 atombios_tv_setup(encoder, ATOM_ENABLE); 2257 else 2258 atombios_tv_setup(encoder, ATOM_DISABLE); 2259 } 2260 break; 2261 } 2262 2263 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2264 2265 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2266 if (rdev->asic->display.hdmi_enable) 2267 radeon_hdmi_enable(rdev, encoder, true); 2268 if (rdev->asic->display.hdmi_setmode) 2269 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2270 } 2271 } 2272 2273 static bool 2274 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2275 { 2276 struct drm_device *dev = encoder->dev; 2277 struct radeon_device *rdev = dev->dev_private; 2278 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2279 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2280 2281 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2282 ATOM_DEVICE_CV_SUPPORT | 2283 ATOM_DEVICE_CRT_SUPPORT)) { 2284 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2285 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2286 uint8_t frev, crev; 2287 2288 memset(&args, 0, sizeof(args)); 2289 2290 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2291 return false; 2292 2293 args.sDacload.ucMisc = 0; 2294 2295 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2296 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2297 args.sDacload.ucDacType = ATOM_DAC_A; 2298 else 2299 args.sDacload.ucDacType = ATOM_DAC_B; 2300 2301 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2302 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2303 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2304 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2305 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2306 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2307 if (crev >= 3) 2308 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2309 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2310 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2311 if (crev >= 3) 2312 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2313 } 2314 2315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2316 2317 return true; 2318 } else 2319 return false; 2320 } 2321 2322 static enum drm_connector_status 2323 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2324 { 2325 struct drm_device *dev = encoder->dev; 2326 struct radeon_device *rdev = dev->dev_private; 2327 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2328 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2329 uint32_t bios_0_scratch; 2330 2331 if (!atombios_dac_load_detect(encoder, connector)) { 2332 DRM_DEBUG_KMS("detect returned false \n"); 2333 return connector_status_unknown; 2334 } 2335 2336 if (rdev->family >= CHIP_R600) 2337 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2338 else 2339 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2340 2341 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2342 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2343 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2344 return connector_status_connected; 2345 } 2346 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2347 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2348 return connector_status_connected; 2349 } 2350 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2351 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2352 return connector_status_connected; 2353 } 2354 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2355 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2356 return connector_status_connected; /* CTV */ 2357 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2358 return connector_status_connected; /* STV */ 2359 } 2360 return connector_status_disconnected; 2361 } 2362 2363 static enum drm_connector_status 2364 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2365 { 2366 struct drm_device *dev = encoder->dev; 2367 struct radeon_device *rdev = dev->dev_private; 2368 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2369 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2370 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2371 u32 bios_0_scratch; 2372 2373 if (!ASIC_IS_DCE4(rdev)) 2374 return connector_status_unknown; 2375 2376 if (!ext_encoder) 2377 return connector_status_unknown; 2378 2379 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2380 return connector_status_unknown; 2381 2382 /* load detect on the dp bridge */ 2383 atombios_external_encoder_setup(encoder, ext_encoder, 2384 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2385 2386 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2387 2388 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2389 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2390 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2391 return connector_status_connected; 2392 } 2393 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2394 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2395 return connector_status_connected; 2396 } 2397 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2398 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2399 return connector_status_connected; 2400 } 2401 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2402 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2403 return connector_status_connected; /* CTV */ 2404 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2405 return connector_status_connected; /* STV */ 2406 } 2407 return connector_status_disconnected; 2408 } 2409 2410 void 2411 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2412 { 2413 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2414 2415 if (ext_encoder) 2416 /* ddc_setup on the dp bridge */ 2417 atombios_external_encoder_setup(encoder, ext_encoder, 2418 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2419 2420 } 2421 2422 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2423 { 2424 struct radeon_device *rdev = encoder->dev->dev_private; 2425 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2426 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2427 2428 if ((radeon_encoder->active_device & 2429 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2430 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2431 ENCODER_OBJECT_ID_NONE)) { 2432 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2433 if (dig) { 2434 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2435 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2436 if (rdev->family >= CHIP_R600) 2437 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2438 else 2439 /* RS600/690/740 have only 1 afmt block */ 2440 dig->afmt = rdev->mode_info.afmt[0]; 2441 } 2442 } 2443 } 2444 2445 radeon_atom_output_lock(encoder, true); 2446 2447 if (connector) { 2448 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2449 2450 /* select the clock/data port if it uses a router */ 2451 if (radeon_connector->router.cd_valid) 2452 radeon_router_select_cd_port(radeon_connector); 2453 2454 /* turn eDP panel on for mode set */ 2455 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2456 atombios_set_edp_panel_power(connector, 2457 ATOM_TRANSMITTER_ACTION_POWER_ON); 2458 } 2459 2460 /* this is needed for the pll/ss setup to work correctly in some cases */ 2461 atombios_set_encoder_crtc_source(encoder); 2462 } 2463 2464 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2465 { 2466 /* need to call this here as we need the crtc set up */ 2467 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2468 radeon_atom_output_lock(encoder, false); 2469 } 2470 2471 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2472 { 2473 struct drm_device *dev = encoder->dev; 2474 struct radeon_device *rdev = dev->dev_private; 2475 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2476 struct radeon_encoder_atom_dig *dig; 2477 2478 /* check for pre-DCE3 cards with shared encoders; 2479 * can't really use the links individually, so don't disable 2480 * the encoder if it's in use by another connector 2481 */ 2482 if (!ASIC_IS_DCE3(rdev)) { 2483 struct drm_encoder *other_encoder; 2484 struct radeon_encoder *other_radeon_encoder; 2485 2486 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2487 other_radeon_encoder = to_radeon_encoder(other_encoder); 2488 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2489 drm_helper_encoder_in_use(other_encoder)) 2490 goto disable_done; 2491 } 2492 } 2493 2494 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2495 2496 switch (radeon_encoder->encoder_id) { 2497 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2499 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2500 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2501 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2502 break; 2503 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2504 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2505 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2506 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2508 /* handled in dpms */ 2509 break; 2510 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2511 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2513 atombios_dvo_setup(encoder, ATOM_DISABLE); 2514 break; 2515 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2516 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2517 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2518 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2519 atombios_dac_setup(encoder, ATOM_DISABLE); 2520 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2521 atombios_tv_setup(encoder, ATOM_DISABLE); 2522 break; 2523 } 2524 2525 disable_done: 2526 if (radeon_encoder_is_digital(encoder)) { 2527 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2528 if (rdev->asic->display.hdmi_enable) 2529 radeon_hdmi_enable(rdev, encoder, false); 2530 } 2531 dig = radeon_encoder->enc_priv; 2532 dig->dig_encoder = -1; 2533 } 2534 radeon_encoder->active_device = 0; 2535 } 2536 2537 /* these are handled by the primary encoders */ 2538 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2539 { 2540 2541 } 2542 2543 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2544 { 2545 2546 } 2547 2548 static void 2549 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2550 struct drm_display_mode *mode, 2551 struct drm_display_mode *adjusted_mode) 2552 { 2553 2554 } 2555 2556 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2557 { 2558 2559 } 2560 2561 static void 2562 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2563 { 2564 2565 } 2566 2567 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2568 const struct drm_display_mode *mode, 2569 struct drm_display_mode *adjusted_mode) 2570 { 2571 return true; 2572 } 2573 2574 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2575 .dpms = radeon_atom_ext_dpms, 2576 .mode_fixup = radeon_atom_ext_mode_fixup, 2577 .prepare = radeon_atom_ext_prepare, 2578 .mode_set = radeon_atom_ext_mode_set, 2579 .commit = radeon_atom_ext_commit, 2580 .disable = radeon_atom_ext_disable, 2581 /* no detect for TMDS/LVDS yet */ 2582 }; 2583 2584 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2585 .dpms = radeon_atom_encoder_dpms, 2586 .mode_fixup = radeon_atom_mode_fixup, 2587 .prepare = radeon_atom_encoder_prepare, 2588 .mode_set = radeon_atom_encoder_mode_set, 2589 .commit = radeon_atom_encoder_commit, 2590 .disable = radeon_atom_encoder_disable, 2591 .detect = radeon_atom_dig_detect, 2592 }; 2593 2594 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2595 .dpms = radeon_atom_encoder_dpms, 2596 .mode_fixup = radeon_atom_mode_fixup, 2597 .prepare = radeon_atom_encoder_prepare, 2598 .mode_set = radeon_atom_encoder_mode_set, 2599 .commit = radeon_atom_encoder_commit, 2600 .detect = radeon_atom_dac_detect, 2601 }; 2602 2603 void radeon_enc_destroy(struct drm_encoder *encoder) 2604 { 2605 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2607 radeon_atom_backlight_exit(radeon_encoder); 2608 kfree(radeon_encoder->enc_priv); 2609 drm_encoder_cleanup(encoder); 2610 kfree(radeon_encoder); 2611 } 2612 2613 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2614 .destroy = radeon_enc_destroy, 2615 }; 2616 2617 static struct radeon_encoder_atom_dac * 2618 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2619 { 2620 struct drm_device *dev = radeon_encoder->base.dev; 2621 struct radeon_device *rdev = dev->dev_private; 2622 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2623 2624 if (!dac) 2625 return NULL; 2626 2627 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2628 return dac; 2629 } 2630 2631 static struct radeon_encoder_atom_dig * 2632 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2633 { 2634 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2635 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2636 2637 if (!dig) 2638 return NULL; 2639 2640 /* coherent mode by default */ 2641 dig->coherent_mode = true; 2642 dig->dig_encoder = -1; 2643 2644 if (encoder_enum == 2) 2645 dig->linkb = true; 2646 else 2647 dig->linkb = false; 2648 2649 return dig; 2650 } 2651 2652 void 2653 radeon_add_atom_encoder(struct drm_device *dev, 2654 uint32_t encoder_enum, 2655 uint32_t supported_device, 2656 u16 caps) 2657 { 2658 struct radeon_device *rdev = dev->dev_private; 2659 struct drm_encoder *encoder; 2660 struct radeon_encoder *radeon_encoder; 2661 2662 /* see if we already added it */ 2663 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2664 radeon_encoder = to_radeon_encoder(encoder); 2665 if (radeon_encoder->encoder_enum == encoder_enum) { 2666 radeon_encoder->devices |= supported_device; 2667 return; 2668 } 2669 2670 } 2671 2672 /* add a new one */ 2673 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2674 if (!radeon_encoder) 2675 return; 2676 2677 encoder = &radeon_encoder->base; 2678 switch (rdev->num_crtc) { 2679 case 1: 2680 encoder->possible_crtcs = 0x1; 2681 break; 2682 case 2: 2683 default: 2684 encoder->possible_crtcs = 0x3; 2685 break; 2686 case 4: 2687 encoder->possible_crtcs = 0xf; 2688 break; 2689 case 6: 2690 encoder->possible_crtcs = 0x3f; 2691 break; 2692 } 2693 2694 radeon_encoder->enc_priv = NULL; 2695 2696 radeon_encoder->encoder_enum = encoder_enum; 2697 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2698 radeon_encoder->devices = supported_device; 2699 radeon_encoder->rmx_type = RMX_OFF; 2700 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2701 radeon_encoder->is_ext_encoder = false; 2702 radeon_encoder->caps = caps; 2703 2704 switch (radeon_encoder->encoder_id) { 2705 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2706 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2707 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2708 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2709 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2710 radeon_encoder->rmx_type = RMX_FULL; 2711 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2712 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2713 } else { 2714 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2715 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2716 } 2717 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2718 break; 2719 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2720 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2721 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2722 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2723 break; 2724 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2725 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2727 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2728 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2729 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2730 break; 2731 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2733 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2734 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2735 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2738 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2739 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2740 radeon_encoder->rmx_type = RMX_FULL; 2741 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2742 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2743 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2744 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2745 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2746 } else { 2747 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2748 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2749 } 2750 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2751 break; 2752 case ENCODER_OBJECT_ID_SI170B: 2753 case ENCODER_OBJECT_ID_CH7303: 2754 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2755 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2756 case ENCODER_OBJECT_ID_TITFP513: 2757 case ENCODER_OBJECT_ID_VT1623: 2758 case ENCODER_OBJECT_ID_HDMI_SI1930: 2759 case ENCODER_OBJECT_ID_TRAVIS: 2760 case ENCODER_OBJECT_ID_NUTMEG: 2761 /* these are handled by the primary encoders */ 2762 radeon_encoder->is_ext_encoder = true; 2763 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2764 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2765 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2766 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2767 else 2768 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2769 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2770 break; 2771 } 2772 } 2773