1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "atom.h" 32 33 static u8 34 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 35 { 36 u8 backlight_level; 37 u32 bios_2_scratch; 38 39 if (rdev->family >= CHIP_R600) 40 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 41 else 42 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 43 44 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 45 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 46 47 return backlight_level; 48 } 49 50 static void 51 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 52 u8 backlight_level) 53 { 54 u32 bios_2_scratch; 55 56 if (rdev->family >= CHIP_R600) 57 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 58 else 59 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 60 61 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 62 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 63 ATOM_S2_CURRENT_BL_LEVEL_MASK); 64 65 if (rdev->family >= CHIP_R600) 66 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 67 else 68 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 69 } 70 71 u8 72 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 73 { 74 struct drm_device *dev = radeon_encoder->base.dev; 75 struct radeon_device *rdev = dev->dev_private; 76 77 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 78 return 0; 79 80 return radeon_atom_get_backlight_level_from_reg(rdev); 81 } 82 83 void 84 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 85 { 86 struct drm_encoder *encoder = &radeon_encoder->base; 87 struct drm_device *dev = radeon_encoder->base.dev; 88 struct radeon_device *rdev = dev->dev_private; 89 struct radeon_encoder_atom_dig *dig; 90 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 91 int index; 92 93 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 94 return; 95 96 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 97 radeon_encoder->enc_priv) { 98 dig = radeon_encoder->enc_priv; 99 dig->backlight_level = level; 100 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 101 102 switch (radeon_encoder->encoder_id) { 103 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 104 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 105 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 106 if (dig->backlight_level == 0) { 107 args.ucAction = ATOM_LCD_BLOFF; 108 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 109 } else { 110 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 112 args.ucAction = ATOM_LCD_BLON; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 } 115 break; 116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 117 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 120 if (dig->backlight_level == 0) 121 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 122 else { 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 125 } 126 break; 127 default: 128 break; 129 } 130 } 131 } 132 133 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 134 135 static u8 radeon_atom_bl_level(struct backlight_device *bd) 136 { 137 u8 level; 138 139 /* Convert brightness to hardware level */ 140 if (bd->props.brightness < 0) 141 level = 0; 142 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 143 level = RADEON_MAX_BL_LEVEL; 144 else 145 level = bd->props.brightness; 146 147 return level; 148 } 149 150 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 151 { 152 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 153 struct radeon_encoder *radeon_encoder = pdata->encoder; 154 155 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 156 157 return 0; 158 } 159 160 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 161 { 162 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 163 struct radeon_encoder *radeon_encoder = pdata->encoder; 164 struct drm_device *dev = radeon_encoder->base.dev; 165 struct radeon_device *rdev = dev->dev_private; 166 167 return radeon_atom_get_backlight_level_from_reg(rdev); 168 } 169 170 static const struct backlight_ops radeon_atom_backlight_ops = { 171 .get_brightness = radeon_atom_backlight_get_brightness, 172 .update_status = radeon_atom_backlight_update_status, 173 }; 174 175 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 176 struct drm_connector *drm_connector) 177 { 178 struct drm_device *dev = radeon_encoder->base.dev; 179 struct radeon_device *rdev = dev->dev_private; 180 struct backlight_device *bd; 181 struct backlight_properties props; 182 struct radeon_backlight_privdata *pdata; 183 struct radeon_encoder_atom_dig *dig; 184 char bl_name[16]; 185 186 /* Mac laptops with multiple GPUs use the gmux driver for backlight 187 * so don't register a backlight device 188 */ 189 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 190 (rdev->pdev->device == 0x6741)) 191 return; 192 193 if (!radeon_encoder->enc_priv) 194 return; 195 196 if (!rdev->is_atom_bios) 197 return; 198 199 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 200 return; 201 202 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), 203 M_DRM, M_WAITOK); 204 if (!pdata) { 205 DRM_ERROR("Memory allocation failed\n"); 206 goto error; 207 } 208 209 memset(&props, 0, sizeof(props)); 210 props.max_brightness = RADEON_MAX_BL_LEVEL; 211 props.type = BACKLIGHT_RAW; 212 snprintf(bl_name, sizeof(bl_name), 213 "radeon_bl%d", dev->primary->index); 214 bd = backlight_device_register(bl_name, drm_connector->kdev, 215 pdata, &radeon_atom_backlight_ops, &props); 216 if (IS_ERR(bd)) { 217 DRM_ERROR("Backlight registration failed\n"); 218 goto error; 219 } 220 221 pdata->encoder = radeon_encoder; 222 223 dig = radeon_encoder->enc_priv; 224 dig->bl_dev = bd; 225 226 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 227 /* Set a reasonable default here if the level is 0 otherwise 228 * fbdev will attempt to turn the backlight on after console 229 * unblanking and it will try and restore 0 which turns the backlight 230 * off again. 231 */ 232 if (bd->props.brightness == 0) 233 bd->props.brightness = RADEON_MAX_BL_LEVEL; 234 bd->props.power = FB_BLANK_UNBLANK; 235 backlight_update_status(bd); 236 237 DRM_INFO("radeon atom DIG backlight initialized\n"); 238 239 return; 240 241 error: 242 kfree(pdata); 243 return; 244 } 245 246 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 247 { 248 struct drm_device *dev = radeon_encoder->base.dev; 249 struct radeon_device *rdev = dev->dev_private; 250 struct backlight_device *bd = NULL; 251 struct radeon_encoder_atom_dig *dig; 252 253 if (!radeon_encoder->enc_priv) 254 return; 255 256 if (!rdev->is_atom_bios) 257 return; 258 259 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 260 return; 261 262 dig = radeon_encoder->enc_priv; 263 bd = dig->bl_dev; 264 dig->bl_dev = NULL; 265 266 if (bd) { 267 struct radeon_legacy_backlight_privdata *pdata; 268 269 pdata = bl_get_data(bd); 270 backlight_device_unregister(bd); 271 kfree(pdata); 272 273 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 274 } 275 } 276 277 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 278 279 /* 280 * Read max backlight level 281 */ 282 static int 283 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 284 { 285 int err, val; 286 287 val = RADEON_MAX_BL_LEVEL; 288 err = sysctl_handle_int(oidp, &val, 0, req); 289 return(err); 290 } 291 292 /* 293 * Read/write backlight level 294 */ 295 static int 296 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 297 { 298 struct radeon_encoder *encoder; 299 struct radeon_encoder_atom_dig *dig; 300 int err, val; 301 302 encoder = (struct radeon_encoder *)arg1; 303 dig = encoder->enc_priv; 304 val = dig->backlight_level; 305 306 err = sysctl_handle_int(oidp, &val, 0, req); 307 if (err != 0 || req->newptr == NULL) { 308 return(err); 309 } 310 if (dig->backlight_level != val && val >= 0 && 311 val <= RADEON_MAX_BL_LEVEL) { 312 atombios_set_backlight_level(encoder, val); 313 } 314 315 return(err); 316 } 317 318 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 319 struct drm_connector *drm_connector) 320 { 321 struct drm_device *dev = radeon_encoder->base.dev; 322 struct radeon_device *rdev = dev->dev_private; 323 struct radeon_encoder_atom_dig *dig; 324 325 if (!radeon_encoder->enc_priv) 326 return; 327 328 if (!rdev->is_atom_bios) 329 return; 330 331 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 332 return; 333 334 dig = radeon_encoder->enc_priv; 335 dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 336 337 DRM_INFO("radeon atom DIG backlight initialized\n"); 338 339 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 340 OID_AUTO, "backlight_max", 341 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 342 radeon_encoder, sizeof(int), 343 sysctl_backlight_max, 344 "I", "Max backlight level"); 345 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 346 OID_AUTO, "backlight_level", 347 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 348 radeon_encoder, sizeof(int), 349 sysctl_backlight_handler, 350 "I", "Backlight level"); 351 return; 352 } 353 354 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 355 { 356 } 357 358 #endif 359 360 361 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 362 { 363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 364 switch (radeon_encoder->encoder_id) { 365 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 366 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 368 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 369 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 370 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 371 case ENCODER_OBJECT_ID_INTERNAL_DDI: 372 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 375 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 376 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 377 return true; 378 default: 379 return false; 380 } 381 } 382 383 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 384 const struct drm_display_mode *mode, 385 struct drm_display_mode *adjusted_mode) 386 { 387 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 388 struct drm_device *dev = encoder->dev; 389 struct radeon_device *rdev = dev->dev_private; 390 391 /* set the active encoder to connector routing */ 392 radeon_encoder_set_active_device(encoder); 393 drm_mode_set_crtcinfo(adjusted_mode, 0); 394 395 /* hw bug */ 396 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 397 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 398 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 399 400 /* get the native mode for scaling */ 401 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 402 radeon_panel_mode_fixup(encoder, adjusted_mode); 403 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 404 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 405 if (tv_dac) { 406 if (tv_dac->tv_std == TV_STD_NTSC || 407 tv_dac->tv_std == TV_STD_NTSC_J || 408 tv_dac->tv_std == TV_STD_PAL_M) 409 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 410 else 411 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 412 } 413 } else if (radeon_encoder->rmx_type != RMX_OFF) { 414 radeon_panel_mode_fixup(encoder, adjusted_mode); 415 } 416 417 if (ASIC_IS_DCE3(rdev) && 418 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 419 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 420 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 421 radeon_dp_set_link_config(connector, adjusted_mode); 422 } 423 424 return true; 425 } 426 427 static void 428 atombios_dac_setup(struct drm_encoder *encoder, int action) 429 { 430 struct drm_device *dev = encoder->dev; 431 struct radeon_device *rdev = dev->dev_private; 432 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 433 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 434 int index = 0; 435 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 436 437 memset(&args, 0, sizeof(args)); 438 439 switch (radeon_encoder->encoder_id) { 440 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 441 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 442 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 443 break; 444 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 446 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 447 break; 448 } 449 450 args.ucAction = action; 451 452 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 453 args.ucDacStandard = ATOM_DAC1_PS2; 454 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 455 args.ucDacStandard = ATOM_DAC1_CV; 456 else { 457 switch (dac_info->tv_std) { 458 case TV_STD_PAL: 459 case TV_STD_PAL_M: 460 case TV_STD_SCART_PAL: 461 case TV_STD_SECAM: 462 case TV_STD_PAL_CN: 463 args.ucDacStandard = ATOM_DAC1_PAL; 464 break; 465 case TV_STD_NTSC: 466 case TV_STD_NTSC_J: 467 case TV_STD_PAL_60: 468 default: 469 args.ucDacStandard = ATOM_DAC1_NTSC; 470 break; 471 } 472 } 473 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 474 475 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 476 477 } 478 479 static void 480 atombios_tv_setup(struct drm_encoder *encoder, int action) 481 { 482 struct drm_device *dev = encoder->dev; 483 struct radeon_device *rdev = dev->dev_private; 484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 485 TV_ENCODER_CONTROL_PS_ALLOCATION args; 486 int index = 0; 487 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 488 489 memset(&args, 0, sizeof(args)); 490 491 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 492 493 args.sTVEncoder.ucAction = action; 494 495 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 496 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 497 else { 498 switch (dac_info->tv_std) { 499 case TV_STD_NTSC: 500 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 501 break; 502 case TV_STD_PAL: 503 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 504 break; 505 case TV_STD_PAL_M: 506 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 507 break; 508 case TV_STD_PAL_60: 509 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 510 break; 511 case TV_STD_NTSC_J: 512 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 513 break; 514 case TV_STD_SCART_PAL: 515 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 516 break; 517 case TV_STD_SECAM: 518 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 519 break; 520 case TV_STD_PAL_CN: 521 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 522 break; 523 default: 524 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 525 break; 526 } 527 } 528 529 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 530 531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 532 533 } 534 535 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 536 { 537 int bpc = 8; 538 539 if (encoder->crtc) { 540 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 541 bpc = radeon_crtc->bpc; 542 } 543 544 switch (bpc) { 545 case 0: 546 return PANEL_BPC_UNDEFINE; 547 case 6: 548 return PANEL_6BIT_PER_COLOR; 549 case 8: 550 default: 551 return PANEL_8BIT_PER_COLOR; 552 case 10: 553 return PANEL_10BIT_PER_COLOR; 554 case 12: 555 return PANEL_12BIT_PER_COLOR; 556 case 16: 557 return PANEL_16BIT_PER_COLOR; 558 } 559 } 560 561 union dvo_encoder_control { 562 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 563 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 564 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 565 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 566 }; 567 568 void 569 atombios_dvo_setup(struct drm_encoder *encoder, int action) 570 { 571 struct drm_device *dev = encoder->dev; 572 struct radeon_device *rdev = dev->dev_private; 573 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 574 union dvo_encoder_control args; 575 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 576 uint8_t frev, crev; 577 578 memset(&args, 0, sizeof(args)); 579 580 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 581 return; 582 583 /* some R4xx chips have the wrong frev */ 584 if (rdev->family <= CHIP_RV410) 585 frev = 1; 586 587 switch (frev) { 588 case 1: 589 switch (crev) { 590 case 1: 591 /* R4xx, R5xx */ 592 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 593 594 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 595 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 596 597 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 598 break; 599 case 2: 600 /* RS600/690/740 */ 601 args.dvo.sDVOEncoder.ucAction = action; 602 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 603 /* DFP1, CRT1, TV1 depending on the type of port */ 604 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 605 606 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 607 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 608 break; 609 case 3: 610 /* R6xx */ 611 args.dvo_v3.ucAction = action; 612 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 613 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 614 break; 615 case 4: 616 /* DCE8 */ 617 args.dvo_v4.ucAction = action; 618 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 619 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 620 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 621 break; 622 default: 623 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 624 break; 625 } 626 break; 627 default: 628 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 629 break; 630 } 631 632 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 633 } 634 635 union lvds_encoder_control { 636 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 637 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 638 }; 639 640 void 641 atombios_digital_setup(struct drm_encoder *encoder, int action) 642 { 643 struct drm_device *dev = encoder->dev; 644 struct radeon_device *rdev = dev->dev_private; 645 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 646 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 647 union lvds_encoder_control args; 648 int index = 0; 649 int hdmi_detected = 0; 650 uint8_t frev, crev; 651 652 if (!dig) 653 return; 654 655 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 656 hdmi_detected = 1; 657 658 memset(&args, 0, sizeof(args)); 659 660 switch (radeon_encoder->encoder_id) { 661 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 662 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 663 break; 664 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 665 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 666 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 667 break; 668 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 669 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 670 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 671 else 672 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 673 break; 674 } 675 676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 677 return; 678 679 switch (frev) { 680 case 1: 681 case 2: 682 switch (crev) { 683 case 1: 684 args.v1.ucMisc = 0; 685 args.v1.ucAction = action; 686 if (hdmi_detected) 687 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 688 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 689 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 690 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 691 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 692 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 693 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 694 } else { 695 if (dig->linkb) 696 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 697 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 698 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 699 /*if (pScrn->rgbBits == 8) */ 700 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 701 } 702 break; 703 case 2: 704 case 3: 705 args.v2.ucMisc = 0; 706 args.v2.ucAction = action; 707 if (crev == 3) { 708 if (dig->coherent_mode) 709 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 710 } 711 if (hdmi_detected) 712 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 713 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 714 args.v2.ucTruncate = 0; 715 args.v2.ucSpatial = 0; 716 args.v2.ucTemporal = 0; 717 args.v2.ucFRC = 0; 718 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 719 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 720 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 721 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 722 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 723 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 724 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 725 } 726 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 727 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 728 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 729 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 730 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 731 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 732 } 733 } else { 734 if (dig->linkb) 735 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 736 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 737 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 738 } 739 break; 740 default: 741 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 742 break; 743 } 744 break; 745 default: 746 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 747 break; 748 } 749 750 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 751 } 752 753 int 754 atombios_get_encoder_mode(struct drm_encoder *encoder) 755 { 756 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 757 struct drm_connector *connector; 758 struct radeon_connector *radeon_connector; 759 struct radeon_connector_atom_dig *dig_connector; 760 761 /* dp bridges are always DP */ 762 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 763 return ATOM_ENCODER_MODE_DP; 764 765 /* DVO is always DVO */ 766 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 767 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 768 return ATOM_ENCODER_MODE_DVO; 769 770 connector = radeon_get_connector_for_encoder(encoder); 771 /* if we don't have an active device yet, just use one of 772 * the connectors tied to the encoder. 773 */ 774 if (!connector) 775 connector = radeon_get_connector_for_encoder_init(encoder); 776 radeon_connector = to_radeon_connector(connector); 777 778 switch (connector->connector_type) { 779 case DRM_MODE_CONNECTOR_DVII: 780 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 781 if (radeon_audio != 0) { 782 if (radeon_connector->use_digital && 783 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 784 return ATOM_ENCODER_MODE_HDMI; 785 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 786 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 787 return ATOM_ENCODER_MODE_HDMI; 788 else if (radeon_connector->use_digital) 789 return ATOM_ENCODER_MODE_DVI; 790 else 791 return ATOM_ENCODER_MODE_CRT; 792 } else if (radeon_connector->use_digital) { 793 return ATOM_ENCODER_MODE_DVI; 794 } else { 795 return ATOM_ENCODER_MODE_CRT; 796 } 797 break; 798 case DRM_MODE_CONNECTOR_DVID: 799 case DRM_MODE_CONNECTOR_HDMIA: 800 default: 801 if (radeon_audio != 0) { 802 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 803 return ATOM_ENCODER_MODE_HDMI; 804 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 805 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 806 return ATOM_ENCODER_MODE_HDMI; 807 else 808 return ATOM_ENCODER_MODE_DVI; 809 } else { 810 return ATOM_ENCODER_MODE_DVI; 811 } 812 break; 813 case DRM_MODE_CONNECTOR_LVDS: 814 return ATOM_ENCODER_MODE_LVDS; 815 break; 816 case DRM_MODE_CONNECTOR_DisplayPort: 817 dig_connector = radeon_connector->con_priv; 818 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 819 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 820 return ATOM_ENCODER_MODE_DP; 821 } else if (radeon_audio != 0) { 822 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 823 return ATOM_ENCODER_MODE_HDMI; 824 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 825 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 826 return ATOM_ENCODER_MODE_HDMI; 827 else 828 return ATOM_ENCODER_MODE_DVI; 829 } else { 830 return ATOM_ENCODER_MODE_DVI; 831 } 832 break; 833 case DRM_MODE_CONNECTOR_eDP: 834 return ATOM_ENCODER_MODE_DP; 835 case DRM_MODE_CONNECTOR_DVIA: 836 case DRM_MODE_CONNECTOR_VGA: 837 return ATOM_ENCODER_MODE_CRT; 838 break; 839 case DRM_MODE_CONNECTOR_Composite: 840 case DRM_MODE_CONNECTOR_SVIDEO: 841 case DRM_MODE_CONNECTOR_9PinDIN: 842 /* fix me */ 843 return ATOM_ENCODER_MODE_TV; 844 /*return ATOM_ENCODER_MODE_CV;*/ 845 break; 846 } 847 } 848 849 /* 850 * DIG Encoder/Transmitter Setup 851 * 852 * DCE 3.0/3.1 853 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 854 * Supports up to 3 digital outputs 855 * - 2 DIG encoder blocks. 856 * DIG1 can drive UNIPHY link A or link B 857 * DIG2 can drive UNIPHY link B or LVTMA 858 * 859 * DCE 3.2 860 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 861 * Supports up to 5 digital outputs 862 * - 2 DIG encoder blocks. 863 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 864 * 865 * DCE 4.0/5.0/6.0 866 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 867 * Supports up to 6 digital outputs 868 * - 6 DIG encoder blocks. 869 * - DIG to PHY mapping is hardcoded 870 * DIG1 drives UNIPHY0 link A, A+B 871 * DIG2 drives UNIPHY0 link B 872 * DIG3 drives UNIPHY1 link A, A+B 873 * DIG4 drives UNIPHY1 link B 874 * DIG5 drives UNIPHY2 link A, A+B 875 * DIG6 drives UNIPHY2 link B 876 * 877 * DCE 4.1 878 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 879 * Supports up to 6 digital outputs 880 * - 2 DIG encoder blocks. 881 * llano 882 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 883 * ontario 884 * DIG1 drives UNIPHY0/1/2 link A 885 * DIG2 drives UNIPHY0/1/2 link B 886 * 887 * Routing 888 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 889 * Examples: 890 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 891 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 892 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 893 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 894 */ 895 896 union dig_encoder_control { 897 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 898 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 899 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 900 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 901 }; 902 903 void 904 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 905 { 906 struct drm_device *dev = encoder->dev; 907 struct radeon_device *rdev = dev->dev_private; 908 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 909 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 910 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 911 union dig_encoder_control args; 912 int index = 0; 913 uint8_t frev, crev; 914 int dp_clock = 0; 915 int dp_lane_count = 0; 916 int hpd_id = RADEON_HPD_NONE; 917 918 if (connector) { 919 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 920 struct radeon_connector_atom_dig *dig_connector = 921 radeon_connector->con_priv; 922 923 dp_clock = dig_connector->dp_clock; 924 dp_lane_count = dig_connector->dp_lane_count; 925 hpd_id = radeon_connector->hpd.hpd; 926 } 927 928 /* no dig encoder assigned */ 929 if (dig->dig_encoder == -1) 930 return; 931 932 memset(&args, 0, sizeof(args)); 933 934 if (ASIC_IS_DCE4(rdev)) 935 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 936 else { 937 if (dig->dig_encoder) 938 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 939 else 940 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 941 } 942 943 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 944 return; 945 946 switch (frev) { 947 case 1: 948 switch (crev) { 949 case 1: 950 args.v1.ucAction = action; 951 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 952 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 953 args.v3.ucPanelMode = panel_mode; 954 else 955 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 956 957 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 958 args.v1.ucLaneNum = dp_lane_count; 959 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 960 args.v1.ucLaneNum = 8; 961 else 962 args.v1.ucLaneNum = 4; 963 964 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 965 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 966 switch (radeon_encoder->encoder_id) { 967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 968 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 969 break; 970 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 971 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 972 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 973 break; 974 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 975 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 976 break; 977 } 978 if (dig->linkb) 979 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 980 else 981 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 982 break; 983 case 2: 984 case 3: 985 args.v3.ucAction = action; 986 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 987 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 988 args.v3.ucPanelMode = panel_mode; 989 else 990 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 991 992 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 993 args.v3.ucLaneNum = dp_lane_count; 994 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 995 args.v3.ucLaneNum = 8; 996 else 997 args.v3.ucLaneNum = 4; 998 999 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 1000 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1001 args.v3.acConfig.ucDigSel = dig->dig_encoder; 1002 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 1003 break; 1004 case 4: 1005 args.v4.ucAction = action; 1006 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1007 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 1008 args.v4.ucPanelMode = panel_mode; 1009 else 1010 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 1011 1012 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 1013 args.v4.ucLaneNum = dp_lane_count; 1014 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1015 args.v4.ucLaneNum = 8; 1016 else 1017 args.v4.ucLaneNum = 4; 1018 1019 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 1020 if (dp_clock == 540000) 1021 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 1022 else if (dp_clock == 324000) 1023 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 1024 else if (dp_clock == 270000) 1025 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 1026 else 1027 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 1028 } 1029 args.v4.acConfig.ucDigSel = dig->dig_encoder; 1030 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 1031 if (hpd_id == RADEON_HPD_NONE) 1032 args.v4.ucHPD_ID = 0; 1033 else 1034 args.v4.ucHPD_ID = hpd_id + 1; 1035 break; 1036 default: 1037 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1038 break; 1039 } 1040 break; 1041 default: 1042 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1043 break; 1044 } 1045 1046 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1047 1048 } 1049 1050 union dig_transmitter_control { 1051 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1052 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1053 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1054 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1055 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1056 }; 1057 1058 void 1059 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1060 { 1061 struct drm_device *dev = encoder->dev; 1062 struct radeon_device *rdev = dev->dev_private; 1063 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1064 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1065 struct drm_connector *connector; 1066 union dig_transmitter_control args; 1067 int index = 0; 1068 uint8_t frev, crev; 1069 bool is_dp = false; 1070 int pll_id = 0; 1071 int dp_clock = 0; 1072 int dp_lane_count = 0; 1073 int connector_object_id = 0; 1074 int igp_lane_info = 0; 1075 int dig_encoder = dig->dig_encoder; 1076 int hpd_id = RADEON_HPD_NONE; 1077 1078 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1079 connector = radeon_get_connector_for_encoder_init(encoder); 1080 /* just needed to avoid bailing in the encoder check. the encoder 1081 * isn't used for init 1082 */ 1083 dig_encoder = 0; 1084 } else 1085 connector = radeon_get_connector_for_encoder(encoder); 1086 1087 if (connector) { 1088 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1089 struct radeon_connector_atom_dig *dig_connector = 1090 radeon_connector->con_priv; 1091 1092 hpd_id = radeon_connector->hpd.hpd; 1093 dp_clock = dig_connector->dp_clock; 1094 dp_lane_count = dig_connector->dp_lane_count; 1095 connector_object_id = 1096 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1097 igp_lane_info = dig_connector->igp_lane_info; 1098 } 1099 1100 if (encoder->crtc) { 1101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1102 pll_id = radeon_crtc->pll_id; 1103 } 1104 1105 /* no dig encoder assigned */ 1106 if (dig_encoder == -1) 1107 return; 1108 1109 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1110 is_dp = true; 1111 1112 memset(&args, 0, sizeof(args)); 1113 1114 switch (radeon_encoder->encoder_id) { 1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1116 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1117 break; 1118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1122 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1123 break; 1124 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1125 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1126 break; 1127 } 1128 1129 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1130 return; 1131 1132 switch (frev) { 1133 case 1: 1134 switch (crev) { 1135 case 1: 1136 args.v1.ucAction = action; 1137 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1138 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1139 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1140 args.v1.asMode.ucLaneSel = lane_num; 1141 args.v1.asMode.ucLaneSet = lane_set; 1142 } else { 1143 if (is_dp) 1144 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1146 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1147 else 1148 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1149 } 1150 1151 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1152 1153 if (dig_encoder) 1154 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1155 else 1156 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1157 1158 if ((rdev->flags & RADEON_IS_IGP) && 1159 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1160 if (is_dp || 1161 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1162 if (igp_lane_info & 0x1) 1163 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1164 else if (igp_lane_info & 0x2) 1165 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1166 else if (igp_lane_info & 0x4) 1167 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1168 else if (igp_lane_info & 0x8) 1169 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1170 } else { 1171 if (igp_lane_info & 0x3) 1172 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1173 else if (igp_lane_info & 0xc) 1174 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1175 } 1176 } 1177 1178 if (dig->linkb) 1179 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1180 else 1181 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1182 1183 if (is_dp) 1184 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1185 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1186 if (dig->coherent_mode) 1187 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1188 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1189 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1190 } 1191 break; 1192 case 2: 1193 args.v2.ucAction = action; 1194 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1195 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1196 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1197 args.v2.asMode.ucLaneSel = lane_num; 1198 args.v2.asMode.ucLaneSet = lane_set; 1199 } else { 1200 if (is_dp) 1201 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1202 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1203 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1204 else 1205 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1206 } 1207 1208 args.v2.acConfig.ucEncoderSel = dig_encoder; 1209 if (dig->linkb) 1210 args.v2.acConfig.ucLinkSel = 1; 1211 1212 switch (radeon_encoder->encoder_id) { 1213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1214 args.v2.acConfig.ucTransmitterSel = 0; 1215 break; 1216 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1217 args.v2.acConfig.ucTransmitterSel = 1; 1218 break; 1219 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1220 args.v2.acConfig.ucTransmitterSel = 2; 1221 break; 1222 } 1223 1224 if (is_dp) { 1225 args.v2.acConfig.fCoherentMode = 1; 1226 args.v2.acConfig.fDPConnector = 1; 1227 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1228 if (dig->coherent_mode) 1229 args.v2.acConfig.fCoherentMode = 1; 1230 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1231 args.v2.acConfig.fDualLinkConnector = 1; 1232 } 1233 break; 1234 case 3: 1235 args.v3.ucAction = action; 1236 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1237 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1238 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1239 args.v3.asMode.ucLaneSel = lane_num; 1240 args.v3.asMode.ucLaneSet = lane_set; 1241 } else { 1242 if (is_dp) 1243 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1244 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1245 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1246 else 1247 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1248 } 1249 1250 if (is_dp) 1251 args.v3.ucLaneNum = dp_lane_count; 1252 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1253 args.v3.ucLaneNum = 8; 1254 else 1255 args.v3.ucLaneNum = 4; 1256 1257 if (dig->linkb) 1258 args.v3.acConfig.ucLinkSel = 1; 1259 if (dig_encoder & 1) 1260 args.v3.acConfig.ucEncoderSel = 1; 1261 1262 /* Select the PLL for the PHY 1263 * DP PHY should be clocked from external src if there is 1264 * one. 1265 */ 1266 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1267 if (is_dp && rdev->clock.dp_extclk) 1268 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1269 else 1270 args.v3.acConfig.ucRefClkSource = pll_id; 1271 1272 switch (radeon_encoder->encoder_id) { 1273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1274 args.v3.acConfig.ucTransmitterSel = 0; 1275 break; 1276 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1277 args.v3.acConfig.ucTransmitterSel = 1; 1278 break; 1279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1280 args.v3.acConfig.ucTransmitterSel = 2; 1281 break; 1282 } 1283 1284 if (is_dp) 1285 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1286 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1287 if (dig->coherent_mode) 1288 args.v3.acConfig.fCoherentMode = 1; 1289 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1290 args.v3.acConfig.fDualLinkConnector = 1; 1291 } 1292 break; 1293 case 4: 1294 args.v4.ucAction = action; 1295 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1296 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1297 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1298 args.v4.asMode.ucLaneSel = lane_num; 1299 args.v4.asMode.ucLaneSet = lane_set; 1300 } else { 1301 if (is_dp) 1302 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1303 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1304 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1305 else 1306 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1307 } 1308 1309 if (is_dp) 1310 args.v4.ucLaneNum = dp_lane_count; 1311 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1312 args.v4.ucLaneNum = 8; 1313 else 1314 args.v4.ucLaneNum = 4; 1315 1316 if (dig->linkb) 1317 args.v4.acConfig.ucLinkSel = 1; 1318 if (dig_encoder & 1) 1319 args.v4.acConfig.ucEncoderSel = 1; 1320 1321 /* Select the PLL for the PHY 1322 * DP PHY should be clocked from external src if there is 1323 * one. 1324 */ 1325 /* On DCE5 DCPLL usually generates the DP ref clock */ 1326 if (is_dp) { 1327 if (rdev->clock.dp_extclk) 1328 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1329 else 1330 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1331 } else 1332 args.v4.acConfig.ucRefClkSource = pll_id; 1333 1334 switch (radeon_encoder->encoder_id) { 1335 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1336 args.v4.acConfig.ucTransmitterSel = 0; 1337 break; 1338 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1339 args.v4.acConfig.ucTransmitterSel = 1; 1340 break; 1341 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1342 args.v4.acConfig.ucTransmitterSel = 2; 1343 break; 1344 } 1345 1346 if (is_dp) 1347 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1348 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1349 if (dig->coherent_mode) 1350 args.v4.acConfig.fCoherentMode = 1; 1351 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1352 args.v4.acConfig.fDualLinkConnector = 1; 1353 } 1354 break; 1355 case 5: 1356 args.v5.ucAction = action; 1357 if (is_dp) 1358 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1359 else 1360 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1361 1362 switch (radeon_encoder->encoder_id) { 1363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1364 if (dig->linkb) 1365 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1366 else 1367 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1368 break; 1369 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1370 if (dig->linkb) 1371 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1372 else 1373 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1374 break; 1375 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1376 if (dig->linkb) 1377 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1378 else 1379 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1380 break; 1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1382 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1383 break; 1384 } 1385 if (is_dp) 1386 args.v5.ucLaneNum = dp_lane_count; 1387 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1388 args.v5.ucLaneNum = 8; 1389 else 1390 args.v5.ucLaneNum = 4; 1391 args.v5.ucConnObjId = connector_object_id; 1392 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1393 1394 if (is_dp && rdev->clock.dp_extclk) 1395 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1396 else 1397 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1398 1399 if (is_dp) 1400 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1401 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1402 if (dig->coherent_mode) 1403 args.v5.asConfig.ucCoherentMode = 1; 1404 } 1405 if (hpd_id == RADEON_HPD_NONE) 1406 args.v5.asConfig.ucHPDSel = 0; 1407 else 1408 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1409 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1410 args.v5.ucDPLaneSet = lane_set; 1411 break; 1412 default: 1413 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1414 break; 1415 } 1416 break; 1417 default: 1418 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1419 break; 1420 } 1421 1422 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1423 } 1424 1425 bool 1426 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1427 { 1428 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1429 struct drm_device *dev = radeon_connector->base.dev; 1430 struct radeon_device *rdev = dev->dev_private; 1431 union dig_transmitter_control args; 1432 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1433 uint8_t frev, crev; 1434 1435 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1436 goto done; 1437 1438 if (!ASIC_IS_DCE4(rdev)) 1439 goto done; 1440 1441 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1442 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1443 goto done; 1444 1445 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1446 goto done; 1447 1448 memset(&args, 0, sizeof(args)); 1449 1450 args.v1.ucAction = action; 1451 1452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1453 1454 /* wait for the panel to power up */ 1455 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1456 int i; 1457 1458 for (i = 0; i < 300; i++) { 1459 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1460 return true; 1461 mdelay(1); 1462 } 1463 return false; 1464 } 1465 done: 1466 return true; 1467 } 1468 1469 union external_encoder_control { 1470 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1471 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1472 }; 1473 1474 static void 1475 atombios_external_encoder_setup(struct drm_encoder *encoder, 1476 struct drm_encoder *ext_encoder, 1477 int action) 1478 { 1479 struct drm_device *dev = encoder->dev; 1480 struct radeon_device *rdev = dev->dev_private; 1481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1482 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1483 union external_encoder_control args; 1484 struct drm_connector *connector; 1485 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1486 u8 frev, crev; 1487 int dp_clock = 0; 1488 int dp_lane_count = 0; 1489 int connector_object_id = 0; 1490 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1491 1492 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1493 connector = radeon_get_connector_for_encoder_init(encoder); 1494 else 1495 connector = radeon_get_connector_for_encoder(encoder); 1496 1497 if (connector) { 1498 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1499 struct radeon_connector_atom_dig *dig_connector = 1500 radeon_connector->con_priv; 1501 1502 dp_clock = dig_connector->dp_clock; 1503 dp_lane_count = dig_connector->dp_lane_count; 1504 connector_object_id = 1505 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1506 } 1507 1508 memset(&args, 0, sizeof(args)); 1509 1510 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1511 return; 1512 1513 switch (frev) { 1514 case 1: 1515 /* no params on frev 1 */ 1516 break; 1517 case 2: 1518 switch (crev) { 1519 case 1: 1520 case 2: 1521 args.v1.sDigEncoder.ucAction = action; 1522 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1523 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1524 1525 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1526 if (dp_clock == 270000) 1527 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1528 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1529 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1530 args.v1.sDigEncoder.ucLaneNum = 8; 1531 else 1532 args.v1.sDigEncoder.ucLaneNum = 4; 1533 break; 1534 case 3: 1535 args.v3.sExtEncoder.ucAction = action; 1536 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1537 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1538 else 1539 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1540 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1541 1542 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1543 if (dp_clock == 270000) 1544 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1545 else if (dp_clock == 540000) 1546 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1547 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1548 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1549 args.v3.sExtEncoder.ucLaneNum = 8; 1550 else 1551 args.v3.sExtEncoder.ucLaneNum = 4; 1552 switch (ext_enum) { 1553 case GRAPH_OBJECT_ENUM_ID1: 1554 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1555 break; 1556 case GRAPH_OBJECT_ENUM_ID2: 1557 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1558 break; 1559 case GRAPH_OBJECT_ENUM_ID3: 1560 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1561 break; 1562 } 1563 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1564 break; 1565 default: 1566 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1567 return; 1568 } 1569 break; 1570 default: 1571 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1572 return; 1573 } 1574 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1575 } 1576 1577 static void 1578 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1579 { 1580 struct drm_device *dev = encoder->dev; 1581 struct radeon_device *rdev = dev->dev_private; 1582 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1583 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1584 ENABLE_YUV_PS_ALLOCATION args; 1585 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1586 uint32_t temp, reg; 1587 1588 memset(&args, 0, sizeof(args)); 1589 1590 if (rdev->family >= CHIP_R600) 1591 reg = R600_BIOS_3_SCRATCH; 1592 else 1593 reg = RADEON_BIOS_3_SCRATCH; 1594 1595 /* XXX: fix up scratch reg handling */ 1596 temp = RREG32(reg); 1597 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1598 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1599 (radeon_crtc->crtc_id << 18))); 1600 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1601 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1602 else 1603 WREG32(reg, 0); 1604 1605 if (enable) 1606 args.ucEnable = ATOM_ENABLE; 1607 args.ucCRTC = radeon_crtc->crtc_id; 1608 1609 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1610 1611 WREG32(reg, temp); 1612 } 1613 1614 static void 1615 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1616 { 1617 struct drm_device *dev = encoder->dev; 1618 struct radeon_device *rdev = dev->dev_private; 1619 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1620 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1621 int index = 0; 1622 1623 memset(&args, 0, sizeof(args)); 1624 1625 switch (radeon_encoder->encoder_id) { 1626 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1628 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1629 break; 1630 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1631 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1632 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1633 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1634 break; 1635 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1636 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1637 break; 1638 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1640 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1641 else 1642 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1643 break; 1644 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1645 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1646 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1647 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1648 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1649 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1650 else 1651 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1652 break; 1653 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1655 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1656 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1657 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1658 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1659 else 1660 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1661 break; 1662 default: 1663 return; 1664 } 1665 1666 switch (mode) { 1667 case DRM_MODE_DPMS_ON: 1668 args.ucAction = ATOM_ENABLE; 1669 /* workaround for DVOOutputControl on some RS690 systems */ 1670 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1671 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1672 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1673 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1674 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1675 } else 1676 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1677 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1678 args.ucAction = ATOM_LCD_BLON; 1679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1680 } 1681 break; 1682 case DRM_MODE_DPMS_STANDBY: 1683 case DRM_MODE_DPMS_SUSPEND: 1684 case DRM_MODE_DPMS_OFF: 1685 args.ucAction = ATOM_DISABLE; 1686 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1687 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1688 args.ucAction = ATOM_LCD_BLOFF; 1689 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1690 } 1691 break; 1692 } 1693 } 1694 1695 static void 1696 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1697 { 1698 struct drm_device *dev = encoder->dev; 1699 struct radeon_device *rdev = dev->dev_private; 1700 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1701 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1702 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1703 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1704 struct radeon_connector *radeon_connector = NULL; 1705 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1706 bool travis_quirk = false; 1707 1708 if (connector) { 1709 radeon_connector = to_radeon_connector(connector); 1710 radeon_dig_connector = radeon_connector->con_priv; 1711 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1712 ENCODER_OBJECT_ID_TRAVIS) && 1713 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1714 !ASIC_IS_DCE5(rdev)) 1715 travis_quirk = true; 1716 } 1717 1718 switch (mode) { 1719 case DRM_MODE_DPMS_ON: 1720 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1721 if (!connector) 1722 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1723 else 1724 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1725 1726 /* setup and enable the encoder */ 1727 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1728 atombios_dig_encoder_setup(encoder, 1729 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1730 dig->panel_mode); 1731 if (ext_encoder) { 1732 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1733 atombios_external_encoder_setup(encoder, ext_encoder, 1734 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1735 } 1736 } else if (ASIC_IS_DCE4(rdev)) { 1737 /* setup and enable the encoder */ 1738 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1739 } else { 1740 /* setup and enable the encoder and transmitter */ 1741 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1742 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1743 } 1744 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1745 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1746 atombios_set_edp_panel_power(connector, 1747 ATOM_TRANSMITTER_ACTION_POWER_ON); 1748 radeon_dig_connector->edp_on = true; 1749 } 1750 } 1751 /* enable the transmitter */ 1752 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1753 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1754 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1755 radeon_dp_link_train(encoder, connector); 1756 if (ASIC_IS_DCE4(rdev)) 1757 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1758 } 1759 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1760 atombios_dig_transmitter_setup(encoder, 1761 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1762 if (ext_encoder) 1763 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1764 break; 1765 case DRM_MODE_DPMS_STANDBY: 1766 case DRM_MODE_DPMS_SUSPEND: 1767 case DRM_MODE_DPMS_OFF: 1768 if (ASIC_IS_DCE4(rdev)) { 1769 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1770 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1771 } 1772 if (ext_encoder) 1773 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1774 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1775 atombios_dig_transmitter_setup(encoder, 1776 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1777 1778 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1779 connector && !travis_quirk) 1780 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1781 if (ASIC_IS_DCE4(rdev)) { 1782 /* disable the transmitter */ 1783 atombios_dig_transmitter_setup(encoder, 1784 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1785 } else { 1786 /* disable the encoder and transmitter */ 1787 atombios_dig_transmitter_setup(encoder, 1788 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1789 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1790 } 1791 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1792 if (travis_quirk) 1793 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1794 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1795 atombios_set_edp_panel_power(connector, 1796 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1797 radeon_dig_connector->edp_on = false; 1798 } 1799 } 1800 break; 1801 } 1802 } 1803 1804 static void 1805 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1806 { 1807 struct drm_device *dev = encoder->dev; 1808 struct radeon_device *rdev = dev->dev_private; 1809 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1810 1811 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1812 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1813 radeon_encoder->active_device); 1814 switch (radeon_encoder->encoder_id) { 1815 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1816 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1817 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1818 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1819 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1820 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1821 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1822 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1823 radeon_atom_encoder_dpms_avivo(encoder, mode); 1824 break; 1825 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1826 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1828 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1829 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1830 radeon_atom_encoder_dpms_dig(encoder, mode); 1831 break; 1832 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1833 if (ASIC_IS_DCE5(rdev)) { 1834 switch (mode) { 1835 case DRM_MODE_DPMS_ON: 1836 atombios_dvo_setup(encoder, ATOM_ENABLE); 1837 break; 1838 case DRM_MODE_DPMS_STANDBY: 1839 case DRM_MODE_DPMS_SUSPEND: 1840 case DRM_MODE_DPMS_OFF: 1841 atombios_dvo_setup(encoder, ATOM_DISABLE); 1842 break; 1843 } 1844 } else if (ASIC_IS_DCE3(rdev)) 1845 radeon_atom_encoder_dpms_dig(encoder, mode); 1846 else 1847 radeon_atom_encoder_dpms_avivo(encoder, mode); 1848 break; 1849 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1850 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1851 if (ASIC_IS_DCE5(rdev)) { 1852 switch (mode) { 1853 case DRM_MODE_DPMS_ON: 1854 atombios_dac_setup(encoder, ATOM_ENABLE); 1855 break; 1856 case DRM_MODE_DPMS_STANDBY: 1857 case DRM_MODE_DPMS_SUSPEND: 1858 case DRM_MODE_DPMS_OFF: 1859 atombios_dac_setup(encoder, ATOM_DISABLE); 1860 break; 1861 } 1862 } else 1863 radeon_atom_encoder_dpms_avivo(encoder, mode); 1864 break; 1865 default: 1866 return; 1867 } 1868 1869 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1870 1871 } 1872 1873 union crtc_source_param { 1874 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1875 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1876 }; 1877 1878 static void 1879 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1880 { 1881 struct drm_device *dev = encoder->dev; 1882 struct radeon_device *rdev = dev->dev_private; 1883 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1884 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1885 union crtc_source_param args; 1886 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1887 uint8_t frev, crev; 1888 struct radeon_encoder_atom_dig *dig; 1889 1890 memset(&args, 0, sizeof(args)); 1891 1892 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1893 return; 1894 1895 switch (frev) { 1896 case 1: 1897 switch (crev) { 1898 case 1: 1899 default: 1900 if (ASIC_IS_AVIVO(rdev)) 1901 args.v1.ucCRTC = radeon_crtc->crtc_id; 1902 else { 1903 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1904 args.v1.ucCRTC = radeon_crtc->crtc_id; 1905 } else { 1906 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1907 } 1908 } 1909 switch (radeon_encoder->encoder_id) { 1910 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1912 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1913 break; 1914 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1915 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1916 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1917 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1918 else 1919 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1920 break; 1921 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1922 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1923 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1924 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1925 break; 1926 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1927 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1928 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1929 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1930 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1931 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1932 else 1933 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1934 break; 1935 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1936 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1937 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1938 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1939 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1940 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1941 else 1942 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1943 break; 1944 } 1945 break; 1946 case 2: 1947 args.v2.ucCRTC = radeon_crtc->crtc_id; 1948 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1949 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1950 1951 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1952 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1953 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1954 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1955 else 1956 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1957 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1958 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1959 } else { 1960 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1961 } 1962 switch (radeon_encoder->encoder_id) { 1963 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1965 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1966 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1967 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1968 dig = radeon_encoder->enc_priv; 1969 switch (dig->dig_encoder) { 1970 case 0: 1971 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1972 break; 1973 case 1: 1974 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1975 break; 1976 case 2: 1977 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1978 break; 1979 case 3: 1980 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1981 break; 1982 case 4: 1983 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1984 break; 1985 case 5: 1986 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1987 break; 1988 case 6: 1989 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1990 break; 1991 } 1992 break; 1993 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1994 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1995 break; 1996 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1997 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1998 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1999 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2000 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2001 else 2002 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 2003 break; 2004 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2005 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2006 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2007 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2008 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2009 else 2010 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 2011 break; 2012 } 2013 break; 2014 } 2015 break; 2016 default: 2017 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2018 return; 2019 } 2020 2021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2022 2023 /* update scratch regs with new routing */ 2024 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2025 } 2026 2027 static void 2028 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2029 struct drm_display_mode *mode) 2030 { 2031 struct drm_device *dev = encoder->dev; 2032 struct radeon_device *rdev = dev->dev_private; 2033 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2034 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2035 2036 /* Funky macbooks */ 2037 if ((dev->pdev->device == 0x71C5) && 2038 (dev->pdev->subsystem_vendor == 0x106b) && 2039 (dev->pdev->subsystem_device == 0x0080)) { 2040 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2041 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2042 2043 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2044 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2045 2046 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2047 } 2048 } 2049 2050 /* set scaler clears this on some chips */ 2051 if (ASIC_IS_AVIVO(rdev) && 2052 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2053 if (ASIC_IS_DCE8(rdev)) { 2054 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2055 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2056 CIK_INTERLEAVE_EN); 2057 else 2058 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2059 } else if (ASIC_IS_DCE4(rdev)) { 2060 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2061 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2062 EVERGREEN_INTERLEAVE_EN); 2063 else 2064 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2065 } else { 2066 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2067 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2068 AVIVO_D1MODE_INTERLEAVE_EN); 2069 else 2070 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2071 } 2072 } 2073 } 2074 2075 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 2076 { 2077 struct drm_device *dev = encoder->dev; 2078 struct radeon_device *rdev = dev->dev_private; 2079 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2080 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2081 struct drm_encoder *test_encoder; 2082 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2083 uint32_t dig_enc_in_use = 0; 2084 2085 if (ASIC_IS_DCE6(rdev)) { 2086 /* DCE6 */ 2087 switch (radeon_encoder->encoder_id) { 2088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2089 if (dig->linkb) 2090 return 1; 2091 else 2092 return 0; 2093 break; 2094 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2095 if (dig->linkb) 2096 return 3; 2097 else 2098 return 2; 2099 break; 2100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2101 if (dig->linkb) 2102 return 5; 2103 else 2104 return 4; 2105 break; 2106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2107 return 6; 2108 break; 2109 } 2110 } else if (ASIC_IS_DCE4(rdev)) { 2111 /* DCE4/5 */ 2112 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2113 /* ontario follows DCE4 */ 2114 if (rdev->family == CHIP_PALM) { 2115 if (dig->linkb) 2116 return 1; 2117 else 2118 return 0; 2119 } else 2120 /* llano follows DCE3.2 */ 2121 return radeon_crtc->crtc_id; 2122 } else { 2123 switch (radeon_encoder->encoder_id) { 2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2125 if (dig->linkb) 2126 return 1; 2127 else 2128 return 0; 2129 break; 2130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2131 if (dig->linkb) 2132 return 3; 2133 else 2134 return 2; 2135 break; 2136 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2137 if (dig->linkb) 2138 return 5; 2139 else 2140 return 4; 2141 break; 2142 } 2143 } 2144 } 2145 2146 /* on DCE32 and encoder can driver any block so just crtc id */ 2147 if (ASIC_IS_DCE32(rdev)) { 2148 return radeon_crtc->crtc_id; 2149 } 2150 2151 /* on DCE3 - LVTMA can only be driven by DIGB */ 2152 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2153 struct radeon_encoder *radeon_test_encoder; 2154 2155 if (encoder == test_encoder) 2156 continue; 2157 2158 if (!radeon_encoder_is_digital(test_encoder)) 2159 continue; 2160 2161 radeon_test_encoder = to_radeon_encoder(test_encoder); 2162 dig = radeon_test_encoder->enc_priv; 2163 2164 if (dig->dig_encoder >= 0) 2165 dig_enc_in_use |= (1 << dig->dig_encoder); 2166 } 2167 2168 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2169 if (dig_enc_in_use & 0x2) 2170 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2171 return 1; 2172 } 2173 if (!(dig_enc_in_use & 1)) 2174 return 0; 2175 return 1; 2176 } 2177 2178 /* This only needs to be called once at startup */ 2179 void 2180 radeon_atom_encoder_init(struct radeon_device *rdev) 2181 { 2182 struct drm_device *dev = rdev->ddev; 2183 struct drm_encoder *encoder; 2184 2185 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2186 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2187 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2188 2189 switch (radeon_encoder->encoder_id) { 2190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2192 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2193 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2194 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2195 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2196 break; 2197 default: 2198 break; 2199 } 2200 2201 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2202 atombios_external_encoder_setup(encoder, ext_encoder, 2203 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2204 } 2205 } 2206 2207 static void 2208 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2209 struct drm_display_mode *mode, 2210 struct drm_display_mode *adjusted_mode) 2211 { 2212 struct drm_device *dev = encoder->dev; 2213 struct radeon_device *rdev = dev->dev_private; 2214 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2215 2216 radeon_encoder->pixel_clock = adjusted_mode->clock; 2217 2218 /* need to call this here rather than in prepare() since we need some crtc info */ 2219 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2220 2221 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2222 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2223 atombios_yuv_setup(encoder, true); 2224 else 2225 atombios_yuv_setup(encoder, false); 2226 } 2227 2228 switch (radeon_encoder->encoder_id) { 2229 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2230 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2231 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2232 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2233 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2234 break; 2235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2236 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2237 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2239 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2240 /* handled in dpms */ 2241 break; 2242 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2243 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2244 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2245 atombios_dvo_setup(encoder, ATOM_ENABLE); 2246 break; 2247 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2248 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2249 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2250 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2251 atombios_dac_setup(encoder, ATOM_ENABLE); 2252 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2253 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2254 atombios_tv_setup(encoder, ATOM_ENABLE); 2255 else 2256 atombios_tv_setup(encoder, ATOM_DISABLE); 2257 } 2258 break; 2259 } 2260 2261 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2262 2263 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2264 if (rdev->asic->display.hdmi_enable) 2265 radeon_hdmi_enable(rdev, encoder, true); 2266 if (rdev->asic->display.hdmi_setmode) 2267 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2268 } 2269 } 2270 2271 static bool 2272 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2273 { 2274 struct drm_device *dev = encoder->dev; 2275 struct radeon_device *rdev = dev->dev_private; 2276 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2277 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2278 2279 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2280 ATOM_DEVICE_CV_SUPPORT | 2281 ATOM_DEVICE_CRT_SUPPORT)) { 2282 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2283 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2284 uint8_t frev, crev; 2285 2286 memset(&args, 0, sizeof(args)); 2287 2288 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2289 return false; 2290 2291 args.sDacload.ucMisc = 0; 2292 2293 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2294 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2295 args.sDacload.ucDacType = ATOM_DAC_A; 2296 else 2297 args.sDacload.ucDacType = ATOM_DAC_B; 2298 2299 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2300 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2301 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2302 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2303 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2304 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2305 if (crev >= 3) 2306 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2307 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2308 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2309 if (crev >= 3) 2310 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2311 } 2312 2313 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2314 2315 return true; 2316 } else 2317 return false; 2318 } 2319 2320 static enum drm_connector_status 2321 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2322 { 2323 struct drm_device *dev = encoder->dev; 2324 struct radeon_device *rdev = dev->dev_private; 2325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2326 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2327 uint32_t bios_0_scratch; 2328 2329 if (!atombios_dac_load_detect(encoder, connector)) { 2330 DRM_DEBUG_KMS("detect returned false \n"); 2331 return connector_status_unknown; 2332 } 2333 2334 if (rdev->family >= CHIP_R600) 2335 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2336 else 2337 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2338 2339 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2340 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2341 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2342 return connector_status_connected; 2343 } 2344 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2345 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2346 return connector_status_connected; 2347 } 2348 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2349 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2350 return connector_status_connected; 2351 } 2352 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2353 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2354 return connector_status_connected; /* CTV */ 2355 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2356 return connector_status_connected; /* STV */ 2357 } 2358 return connector_status_disconnected; 2359 } 2360 2361 static enum drm_connector_status 2362 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2363 { 2364 struct drm_device *dev = encoder->dev; 2365 struct radeon_device *rdev = dev->dev_private; 2366 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2367 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2368 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2369 u32 bios_0_scratch; 2370 2371 if (!ASIC_IS_DCE4(rdev)) 2372 return connector_status_unknown; 2373 2374 if (!ext_encoder) 2375 return connector_status_unknown; 2376 2377 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2378 return connector_status_unknown; 2379 2380 /* load detect on the dp bridge */ 2381 atombios_external_encoder_setup(encoder, ext_encoder, 2382 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2383 2384 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2385 2386 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2387 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2388 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2389 return connector_status_connected; 2390 } 2391 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2392 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2393 return connector_status_connected; 2394 } 2395 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2396 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2397 return connector_status_connected; 2398 } 2399 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2400 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2401 return connector_status_connected; /* CTV */ 2402 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2403 return connector_status_connected; /* STV */ 2404 } 2405 return connector_status_disconnected; 2406 } 2407 2408 void 2409 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2410 { 2411 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2412 2413 if (ext_encoder) 2414 /* ddc_setup on the dp bridge */ 2415 atombios_external_encoder_setup(encoder, ext_encoder, 2416 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2417 2418 } 2419 2420 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2421 { 2422 struct radeon_device *rdev = encoder->dev->dev_private; 2423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2424 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2425 2426 if ((radeon_encoder->active_device & 2427 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2428 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2429 ENCODER_OBJECT_ID_NONE)) { 2430 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2431 if (dig) { 2432 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2433 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2434 if (rdev->family >= CHIP_R600) 2435 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2436 else 2437 /* RS600/690/740 have only 1 afmt block */ 2438 dig->afmt = rdev->mode_info.afmt[0]; 2439 } 2440 } 2441 } 2442 2443 radeon_atom_output_lock(encoder, true); 2444 2445 if (connector) { 2446 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2447 2448 /* select the clock/data port if it uses a router */ 2449 if (radeon_connector->router.cd_valid) 2450 radeon_router_select_cd_port(radeon_connector); 2451 2452 /* turn eDP panel on for mode set */ 2453 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2454 atombios_set_edp_panel_power(connector, 2455 ATOM_TRANSMITTER_ACTION_POWER_ON); 2456 } 2457 2458 /* this is needed for the pll/ss setup to work correctly in some cases */ 2459 atombios_set_encoder_crtc_source(encoder); 2460 /* set up the FMT blocks */ 2461 if (ASIC_IS_DCE8(rdev)) 2462 dce8_program_fmt(encoder); 2463 else if (ASIC_IS_DCE4(rdev)) 2464 dce4_program_fmt(encoder); 2465 else if (ASIC_IS_DCE3(rdev)) 2466 dce3_program_fmt(encoder); 2467 else if (ASIC_IS_AVIVO(rdev)) 2468 avivo_program_fmt(encoder); 2469 } 2470 2471 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2472 { 2473 /* need to call this here as we need the crtc set up */ 2474 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2475 radeon_atom_output_lock(encoder, false); 2476 } 2477 2478 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2479 { 2480 struct drm_device *dev = encoder->dev; 2481 struct radeon_device *rdev = dev->dev_private; 2482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2483 struct radeon_encoder_atom_dig *dig; 2484 2485 /* check for pre-DCE3 cards with shared encoders; 2486 * can't really use the links individually, so don't disable 2487 * the encoder if it's in use by another connector 2488 */ 2489 if (!ASIC_IS_DCE3(rdev)) { 2490 struct drm_encoder *other_encoder; 2491 struct radeon_encoder *other_radeon_encoder; 2492 2493 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2494 other_radeon_encoder = to_radeon_encoder(other_encoder); 2495 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2496 drm_helper_encoder_in_use(other_encoder)) 2497 goto disable_done; 2498 } 2499 } 2500 2501 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2502 2503 switch (radeon_encoder->encoder_id) { 2504 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2505 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2506 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2507 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2508 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2509 break; 2510 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2511 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2512 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2513 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2514 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2515 /* handled in dpms */ 2516 break; 2517 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2518 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2519 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2520 atombios_dvo_setup(encoder, ATOM_DISABLE); 2521 break; 2522 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2524 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2525 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2526 atombios_dac_setup(encoder, ATOM_DISABLE); 2527 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2528 atombios_tv_setup(encoder, ATOM_DISABLE); 2529 break; 2530 } 2531 2532 disable_done: 2533 if (radeon_encoder_is_digital(encoder)) { 2534 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2535 if (rdev->asic->display.hdmi_enable) 2536 radeon_hdmi_enable(rdev, encoder, false); 2537 } 2538 dig = radeon_encoder->enc_priv; 2539 dig->dig_encoder = -1; 2540 } 2541 radeon_encoder->active_device = 0; 2542 } 2543 2544 /* these are handled by the primary encoders */ 2545 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2546 { 2547 2548 } 2549 2550 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2551 { 2552 2553 } 2554 2555 static void 2556 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2557 struct drm_display_mode *mode, 2558 struct drm_display_mode *adjusted_mode) 2559 { 2560 2561 } 2562 2563 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2564 { 2565 2566 } 2567 2568 static void 2569 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2570 { 2571 2572 } 2573 2574 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2575 const struct drm_display_mode *mode, 2576 struct drm_display_mode *adjusted_mode) 2577 { 2578 return true; 2579 } 2580 2581 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2582 .dpms = radeon_atom_ext_dpms, 2583 .mode_fixup = radeon_atom_ext_mode_fixup, 2584 .prepare = radeon_atom_ext_prepare, 2585 .mode_set = radeon_atom_ext_mode_set, 2586 .commit = radeon_atom_ext_commit, 2587 .disable = radeon_atom_ext_disable, 2588 /* no detect for TMDS/LVDS yet */ 2589 }; 2590 2591 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2592 .dpms = radeon_atom_encoder_dpms, 2593 .mode_fixup = radeon_atom_mode_fixup, 2594 .prepare = radeon_atom_encoder_prepare, 2595 .mode_set = radeon_atom_encoder_mode_set, 2596 .commit = radeon_atom_encoder_commit, 2597 .disable = radeon_atom_encoder_disable, 2598 .detect = radeon_atom_dig_detect, 2599 }; 2600 2601 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2602 .dpms = radeon_atom_encoder_dpms, 2603 .mode_fixup = radeon_atom_mode_fixup, 2604 .prepare = radeon_atom_encoder_prepare, 2605 .mode_set = radeon_atom_encoder_mode_set, 2606 .commit = radeon_atom_encoder_commit, 2607 .detect = radeon_atom_dac_detect, 2608 }; 2609 2610 void radeon_enc_destroy(struct drm_encoder *encoder) 2611 { 2612 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2613 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2614 radeon_atom_backlight_exit(radeon_encoder); 2615 kfree(radeon_encoder->enc_priv); 2616 drm_encoder_cleanup(encoder); 2617 kfree(radeon_encoder); 2618 } 2619 2620 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2621 .destroy = radeon_enc_destroy, 2622 }; 2623 2624 static struct radeon_encoder_atom_dac * 2625 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2626 { 2627 struct drm_device *dev = radeon_encoder->base.dev; 2628 struct radeon_device *rdev = dev->dev_private; 2629 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2630 2631 if (!dac) 2632 return NULL; 2633 2634 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2635 return dac; 2636 } 2637 2638 static struct radeon_encoder_atom_dig * 2639 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2640 { 2641 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2642 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2643 2644 if (!dig) 2645 return NULL; 2646 2647 /* coherent mode by default */ 2648 dig->coherent_mode = true; 2649 dig->dig_encoder = -1; 2650 2651 if (encoder_enum == 2) 2652 dig->linkb = true; 2653 else 2654 dig->linkb = false; 2655 2656 return dig; 2657 } 2658 2659 void 2660 radeon_add_atom_encoder(struct drm_device *dev, 2661 uint32_t encoder_enum, 2662 uint32_t supported_device, 2663 u16 caps) 2664 { 2665 struct radeon_device *rdev = dev->dev_private; 2666 struct drm_encoder *encoder; 2667 struct radeon_encoder *radeon_encoder; 2668 2669 /* see if we already added it */ 2670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2671 radeon_encoder = to_radeon_encoder(encoder); 2672 if (radeon_encoder->encoder_enum == encoder_enum) { 2673 radeon_encoder->devices |= supported_device; 2674 return; 2675 } 2676 2677 } 2678 2679 /* add a new one */ 2680 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2681 if (!radeon_encoder) 2682 return; 2683 2684 encoder = &radeon_encoder->base; 2685 switch (rdev->num_crtc) { 2686 case 1: 2687 encoder->possible_crtcs = 0x1; 2688 break; 2689 case 2: 2690 default: 2691 encoder->possible_crtcs = 0x3; 2692 break; 2693 case 4: 2694 encoder->possible_crtcs = 0xf; 2695 break; 2696 case 6: 2697 encoder->possible_crtcs = 0x3f; 2698 break; 2699 } 2700 2701 radeon_encoder->enc_priv = NULL; 2702 2703 radeon_encoder->encoder_enum = encoder_enum; 2704 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2705 radeon_encoder->devices = supported_device; 2706 radeon_encoder->rmx_type = RMX_OFF; 2707 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2708 radeon_encoder->is_ext_encoder = false; 2709 radeon_encoder->caps = caps; 2710 2711 switch (radeon_encoder->encoder_id) { 2712 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2713 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2714 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2715 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2716 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2717 radeon_encoder->rmx_type = RMX_FULL; 2718 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2719 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2720 } else { 2721 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2722 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2723 } 2724 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2725 break; 2726 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2727 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2728 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2729 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2730 break; 2731 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2734 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2735 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2736 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2737 break; 2738 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2739 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2740 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2741 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2742 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2745 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2746 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2747 radeon_encoder->rmx_type = RMX_FULL; 2748 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2749 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2750 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2751 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2752 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2753 } else { 2754 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2755 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2756 } 2757 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2758 break; 2759 case ENCODER_OBJECT_ID_SI170B: 2760 case ENCODER_OBJECT_ID_CH7303: 2761 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2762 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2763 case ENCODER_OBJECT_ID_TITFP513: 2764 case ENCODER_OBJECT_ID_VT1623: 2765 case ENCODER_OBJECT_ID_HDMI_SI1930: 2766 case ENCODER_OBJECT_ID_TRAVIS: 2767 case ENCODER_OBJECT_ID_NUTMEG: 2768 /* these are handled by the primary encoders */ 2769 radeon_encoder->is_ext_encoder = true; 2770 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2771 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2772 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2773 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2774 else 2775 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2776 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2777 break; 2778 } 2779 } 2780