1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_audio.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 34 static u8 35 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 36 { 37 u8 backlight_level; 38 u32 bios_2_scratch; 39 40 if (rdev->family >= CHIP_R600) 41 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 42 else 43 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 44 45 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 46 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 47 48 return backlight_level; 49 } 50 51 static void 52 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 53 u8 backlight_level) 54 { 55 u32 bios_2_scratch; 56 57 if (rdev->family >= CHIP_R600) 58 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 59 else 60 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 61 62 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 63 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 64 ATOM_S2_CURRENT_BL_LEVEL_MASK); 65 66 if (rdev->family >= CHIP_R600) 67 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 68 else 69 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 70 } 71 72 u8 73 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 74 { 75 struct drm_device *dev = radeon_encoder->base.dev; 76 struct radeon_device *rdev = dev->dev_private; 77 78 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 79 return 0; 80 81 return radeon_atom_get_backlight_level_from_reg(rdev); 82 } 83 84 void 85 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 86 { 87 struct drm_encoder *encoder = &radeon_encoder->base; 88 struct drm_device *dev = radeon_encoder->base.dev; 89 struct radeon_device *rdev = dev->dev_private; 90 struct radeon_encoder_atom_dig *dig; 91 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 92 int index; 93 94 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 95 return; 96 97 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 98 radeon_encoder->enc_priv) { 99 dig = radeon_encoder->enc_priv; 100 dig->backlight_level = level; 101 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 102 103 switch (radeon_encoder->encoder_id) { 104 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 105 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 106 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 107 if (dig->backlight_level == 0) { 108 args.ucAction = ATOM_LCD_BLOFF; 109 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 110 } else { 111 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 112 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 113 args.ucAction = ATOM_LCD_BLON; 114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 115 } 116 break; 117 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 122 if (dig->backlight_level == 0) 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 124 else { 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 127 } 128 break; 129 default: 130 break; 131 } 132 } 133 } 134 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 136 137 static u8 radeon_atom_bl_level(struct backlight_device *bd) 138 { 139 u8 level; 140 141 /* Convert brightness to hardware level */ 142 if (bd->props.brightness < 0) 143 level = 0; 144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 145 level = RADEON_MAX_BL_LEVEL; 146 else 147 level = bd->props.brightness; 148 149 return level; 150 } 151 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 153 { 154 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 155 struct radeon_encoder *radeon_encoder = pdata->encoder; 156 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 158 159 return 0; 160 } 161 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 163 { 164 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 165 struct radeon_encoder *radeon_encoder = pdata->encoder; 166 struct drm_device *dev = radeon_encoder->base.dev; 167 struct radeon_device *rdev = dev->dev_private; 168 169 return radeon_atom_get_backlight_level_from_reg(rdev); 170 } 171 172 static const struct backlight_ops radeon_atom_backlight_ops = { 173 .get_brightness = radeon_atom_backlight_get_brightness, 174 .update_status = radeon_atom_backlight_update_status, 175 }; 176 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 178 struct drm_connector *drm_connector) 179 { 180 struct drm_device *dev = radeon_encoder->base.dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct backlight_device *bd; 183 struct backlight_properties props; 184 struct radeon_backlight_privdata *pdata; 185 struct radeon_encoder_atom_dig *dig; 186 char bl_name[16]; 187 188 /* Mac laptops with multiple GPUs use the gmux driver for backlight 189 * so don't register a backlight device 190 */ 191 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 192 (rdev->pdev->device == 0x6741)) 193 return; 194 195 if (!radeon_encoder->enc_priv) 196 return; 197 198 if (!rdev->is_atom_bios) 199 return; 200 201 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 202 return; 203 204 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), 205 M_DRM, M_WAITOK); 206 if (!pdata) { 207 DRM_ERROR("Memory allocation failed\n"); 208 goto error; 209 } 210 211 memset(&props, 0, sizeof(props)); 212 props.max_brightness = RADEON_MAX_BL_LEVEL; 213 props.type = BACKLIGHT_RAW; 214 snprintf(bl_name, sizeof(bl_name), 215 "radeon_bl%d", dev->primary->index); 216 bd = backlight_device_register(bl_name, drm_connector->kdev, 217 pdata, &radeon_atom_backlight_ops, &props); 218 if (IS_ERR(bd)) { 219 DRM_ERROR("Backlight registration failed\n"); 220 goto error; 221 } 222 223 pdata->encoder = radeon_encoder; 224 225 dig = radeon_encoder->enc_priv; 226 dig->bl_dev = bd; 227 228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 229 /* Set a reasonable default here if the level is 0 otherwise 230 * fbdev will attempt to turn the backlight on after console 231 * unblanking and it will try and restore 0 which turns the backlight 232 * off again. 233 */ 234 if (bd->props.brightness == 0) 235 bd->props.brightness = RADEON_MAX_BL_LEVEL; 236 bd->props.power = FB_BLANK_UNBLANK; 237 backlight_update_status(bd); 238 239 DRM_INFO("radeon atom DIG backlight initialized\n"); 240 rdev->mode_info.bl_encoder = radeon_encoder; 241 242 return; 243 244 error: 245 kfree(pdata); 246 return; 247 } 248 249 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 250 { 251 struct drm_device *dev = radeon_encoder->base.dev; 252 struct radeon_device *rdev = dev->dev_private; 253 struct backlight_device *bd = NULL; 254 struct radeon_encoder_atom_dig *dig; 255 256 if (!radeon_encoder->enc_priv) 257 return; 258 259 if (!rdev->is_atom_bios) 260 return; 261 262 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 263 return; 264 265 dig = radeon_encoder->enc_priv; 266 bd = dig->bl_dev; 267 dig->bl_dev = NULL; 268 269 if (bd) { 270 struct radeon_legacy_backlight_privdata *pdata; 271 272 pdata = bl_get_data(bd); 273 backlight_device_unregister(bd); 274 kfree(pdata); 275 276 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 277 } 278 } 279 280 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 281 282 /* 283 * Read max backlight level 284 */ 285 static int 286 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 287 { 288 int err, val; 289 290 val = RADEON_MAX_BL_LEVEL; 291 err = sysctl_handle_int(oidp, &val, 0, req); 292 return(err); 293 } 294 295 /* 296 * Read/write backlight level 297 */ 298 static int 299 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 300 { 301 struct radeon_encoder *encoder; 302 struct radeon_encoder_atom_dig *dig; 303 int err, val; 304 305 encoder = (struct radeon_encoder *)arg1; 306 dig = encoder->enc_priv; 307 val = dig->backlight_level; 308 309 err = sysctl_handle_int(oidp, &val, 0, req); 310 if (err != 0 || req->newptr == NULL) { 311 return(err); 312 } 313 if (dig->backlight_level != val && val >= 0 && 314 val <= RADEON_MAX_BL_LEVEL) { 315 atombios_set_backlight_level(encoder, val); 316 } 317 318 return(err); 319 } 320 321 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 322 struct drm_connector *drm_connector) 323 { 324 struct drm_device *dev = radeon_encoder->base.dev; 325 struct radeon_device *rdev = dev->dev_private; 326 struct radeon_encoder_atom_dig *dig; 327 328 if (!radeon_encoder->enc_priv) 329 return; 330 331 if (!rdev->is_atom_bios) 332 return; 333 334 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 335 return; 336 337 dig = radeon_encoder->enc_priv; 338 dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 339 340 DRM_INFO("radeon atom DIG backlight initialized\n"); 341 rdev->mode_info.bl_encoder = radeon_encoder; 342 343 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 344 OID_AUTO, "backlight_max", 345 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 346 radeon_encoder, sizeof(int), 347 sysctl_backlight_max, 348 "I", "Max backlight level"); 349 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 350 OID_AUTO, "backlight_level", 351 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 352 radeon_encoder, sizeof(int), 353 sysctl_backlight_handler, 354 "I", "Backlight level"); 355 return; 356 } 357 358 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 359 { 360 } 361 362 #endif 363 364 365 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 366 const struct drm_display_mode *mode, 367 struct drm_display_mode *adjusted_mode) 368 { 369 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 370 struct drm_device *dev = encoder->dev; 371 struct radeon_device *rdev = dev->dev_private; 372 373 /* set the active encoder to connector routing */ 374 radeon_encoder_set_active_device(encoder); 375 drm_mode_set_crtcinfo(adjusted_mode, 0); 376 377 /* hw bug */ 378 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 379 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 380 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 381 382 /* vertical FP must be at least 1 */ 383 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 384 adjusted_mode->crtc_vsync_start++; 385 386 /* get the native mode for scaling */ 387 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 388 radeon_panel_mode_fixup(encoder, adjusted_mode); 389 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 390 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 391 if (tv_dac) { 392 if (tv_dac->tv_std == TV_STD_NTSC || 393 tv_dac->tv_std == TV_STD_NTSC_J || 394 tv_dac->tv_std == TV_STD_PAL_M) 395 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 396 else 397 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 398 } 399 } else if (radeon_encoder->rmx_type != RMX_OFF) { 400 radeon_panel_mode_fixup(encoder, adjusted_mode); 401 } 402 403 if (ASIC_IS_DCE3(rdev) && 404 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 405 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 406 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 407 radeon_dp_set_link_config(connector, adjusted_mode); 408 } 409 410 return true; 411 } 412 413 static void 414 atombios_dac_setup(struct drm_encoder *encoder, int action) 415 { 416 struct drm_device *dev = encoder->dev; 417 struct radeon_device *rdev = dev->dev_private; 418 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 419 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 420 int index = 0; 421 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 422 423 memset(&args, 0, sizeof(args)); 424 425 switch (radeon_encoder->encoder_id) { 426 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 427 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 428 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 429 break; 430 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 431 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 432 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 433 break; 434 } 435 436 args.ucAction = action; 437 438 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 439 args.ucDacStandard = ATOM_DAC1_PS2; 440 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 441 args.ucDacStandard = ATOM_DAC1_CV; 442 else { 443 switch (dac_info->tv_std) { 444 case TV_STD_PAL: 445 case TV_STD_PAL_M: 446 case TV_STD_SCART_PAL: 447 case TV_STD_SECAM: 448 case TV_STD_PAL_CN: 449 args.ucDacStandard = ATOM_DAC1_PAL; 450 break; 451 case TV_STD_NTSC: 452 case TV_STD_NTSC_J: 453 case TV_STD_PAL_60: 454 default: 455 args.ucDacStandard = ATOM_DAC1_NTSC; 456 break; 457 } 458 } 459 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 460 461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 462 463 } 464 465 static void 466 atombios_tv_setup(struct drm_encoder *encoder, int action) 467 { 468 struct drm_device *dev = encoder->dev; 469 struct radeon_device *rdev = dev->dev_private; 470 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 471 TV_ENCODER_CONTROL_PS_ALLOCATION args; 472 int index = 0; 473 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 474 475 memset(&args, 0, sizeof(args)); 476 477 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 478 479 args.sTVEncoder.ucAction = action; 480 481 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 482 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 483 else { 484 switch (dac_info->tv_std) { 485 case TV_STD_NTSC: 486 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 487 break; 488 case TV_STD_PAL: 489 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 490 break; 491 case TV_STD_PAL_M: 492 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 493 break; 494 case TV_STD_PAL_60: 495 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 496 break; 497 case TV_STD_NTSC_J: 498 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 499 break; 500 case TV_STD_SCART_PAL: 501 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 502 break; 503 case TV_STD_SECAM: 504 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 505 break; 506 case TV_STD_PAL_CN: 507 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 508 break; 509 default: 510 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 511 break; 512 } 513 } 514 515 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 516 517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 518 519 } 520 521 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 522 { 523 int bpc = 8; 524 525 if (encoder->crtc) { 526 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 527 bpc = radeon_crtc->bpc; 528 } 529 530 switch (bpc) { 531 case 0: 532 return PANEL_BPC_UNDEFINE; 533 case 6: 534 return PANEL_6BIT_PER_COLOR; 535 case 8: 536 default: 537 return PANEL_8BIT_PER_COLOR; 538 case 10: 539 return PANEL_10BIT_PER_COLOR; 540 case 12: 541 return PANEL_12BIT_PER_COLOR; 542 case 16: 543 return PANEL_16BIT_PER_COLOR; 544 } 545 } 546 547 union dvo_encoder_control { 548 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 549 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 550 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 551 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 552 }; 553 554 void 555 atombios_dvo_setup(struct drm_encoder *encoder, int action) 556 { 557 struct drm_device *dev = encoder->dev; 558 struct radeon_device *rdev = dev->dev_private; 559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 560 union dvo_encoder_control args; 561 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 562 uint8_t frev, crev; 563 564 memset(&args, 0, sizeof(args)); 565 566 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 567 return; 568 569 /* some R4xx chips have the wrong frev */ 570 if (rdev->family <= CHIP_RV410) 571 frev = 1; 572 573 switch (frev) { 574 case 1: 575 switch (crev) { 576 case 1: 577 /* R4xx, R5xx */ 578 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 579 580 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 581 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 582 583 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 584 break; 585 case 2: 586 /* RS600/690/740 */ 587 args.dvo.sDVOEncoder.ucAction = action; 588 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 589 /* DFP1, CRT1, TV1 depending on the type of port */ 590 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 591 592 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 593 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 594 break; 595 case 3: 596 /* R6xx */ 597 args.dvo_v3.ucAction = action; 598 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 599 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 600 break; 601 case 4: 602 /* DCE8 */ 603 args.dvo_v4.ucAction = action; 604 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 605 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 606 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 607 break; 608 default: 609 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 610 break; 611 } 612 break; 613 default: 614 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 615 break; 616 } 617 618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 619 } 620 621 union lvds_encoder_control { 622 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 623 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 624 }; 625 626 void 627 atombios_digital_setup(struct drm_encoder *encoder, int action) 628 { 629 struct drm_device *dev = encoder->dev; 630 struct radeon_device *rdev = dev->dev_private; 631 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 633 union lvds_encoder_control args; 634 int index = 0; 635 int hdmi_detected = 0; 636 uint8_t frev, crev; 637 638 if (!dig) 639 return; 640 641 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 642 hdmi_detected = 1; 643 644 memset(&args, 0, sizeof(args)); 645 646 switch (radeon_encoder->encoder_id) { 647 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 648 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 649 break; 650 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 652 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 653 break; 654 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 655 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 656 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 657 else 658 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 659 break; 660 } 661 662 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 663 return; 664 665 switch (frev) { 666 case 1: 667 case 2: 668 switch (crev) { 669 case 1: 670 args.v1.ucMisc = 0; 671 args.v1.ucAction = action; 672 if (hdmi_detected) 673 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 674 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 675 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 676 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 677 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 678 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 679 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 680 } else { 681 if (dig->linkb) 682 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 683 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 684 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 685 /*if (pScrn->rgbBits == 8) */ 686 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 687 } 688 break; 689 case 2: 690 case 3: 691 args.v2.ucMisc = 0; 692 args.v2.ucAction = action; 693 if (crev == 3) { 694 if (dig->coherent_mode) 695 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 696 } 697 if (hdmi_detected) 698 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 699 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 700 args.v2.ucTruncate = 0; 701 args.v2.ucSpatial = 0; 702 args.v2.ucTemporal = 0; 703 args.v2.ucFRC = 0; 704 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 705 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 706 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 707 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 708 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 709 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 710 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 711 } 712 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 713 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 714 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 715 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 716 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 717 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 718 } 719 } else { 720 if (dig->linkb) 721 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 722 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 723 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 724 } 725 break; 726 default: 727 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 728 break; 729 } 730 break; 731 default: 732 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 733 break; 734 } 735 736 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 737 } 738 739 int 740 atombios_get_encoder_mode(struct drm_encoder *encoder) 741 { 742 struct drm_device *dev = encoder->dev; 743 struct radeon_device *rdev = dev->dev_private; 744 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 745 struct drm_connector *connector; 746 struct radeon_connector *radeon_connector; 747 struct radeon_connector_atom_dig *dig_connector; 748 749 /* dp bridges are always DP */ 750 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 751 return ATOM_ENCODER_MODE_DP; 752 753 /* DVO is always DVO */ 754 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 755 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 756 return ATOM_ENCODER_MODE_DVO; 757 758 connector = radeon_get_connector_for_encoder(encoder); 759 /* if we don't have an active device yet, just use one of 760 * the connectors tied to the encoder. 761 */ 762 if (!connector) 763 connector = radeon_get_connector_for_encoder_init(encoder); 764 radeon_connector = to_radeon_connector(connector); 765 766 switch (connector->connector_type) { 767 case DRM_MODE_CONNECTOR_DVII: 768 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 769 if (radeon_audio != 0) { 770 if (radeon_connector->use_digital && 771 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 772 return ATOM_ENCODER_MODE_HDMI; 773 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 774 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 775 return ATOM_ENCODER_MODE_HDMI; 776 else if (radeon_connector->use_digital) 777 return ATOM_ENCODER_MODE_DVI; 778 else 779 return ATOM_ENCODER_MODE_CRT; 780 } else if (radeon_connector->use_digital) { 781 return ATOM_ENCODER_MODE_DVI; 782 } else { 783 return ATOM_ENCODER_MODE_CRT; 784 } 785 break; 786 case DRM_MODE_CONNECTOR_DVID: 787 case DRM_MODE_CONNECTOR_HDMIA: 788 default: 789 if (radeon_audio != 0) { 790 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 791 return ATOM_ENCODER_MODE_HDMI; 792 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 793 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 794 return ATOM_ENCODER_MODE_HDMI; 795 else 796 return ATOM_ENCODER_MODE_DVI; 797 } else { 798 return ATOM_ENCODER_MODE_DVI; 799 } 800 break; 801 case DRM_MODE_CONNECTOR_LVDS: 802 return ATOM_ENCODER_MODE_LVDS; 803 break; 804 case DRM_MODE_CONNECTOR_DisplayPort: 805 dig_connector = radeon_connector->con_priv; 806 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 807 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 808 if (radeon_audio != 0 && 809 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 810 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 811 return ATOM_ENCODER_MODE_DP_AUDIO; 812 return ATOM_ENCODER_MODE_DP; 813 } else if (radeon_audio != 0) { 814 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 815 return ATOM_ENCODER_MODE_HDMI; 816 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 817 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 818 return ATOM_ENCODER_MODE_HDMI; 819 else 820 return ATOM_ENCODER_MODE_DVI; 821 } else { 822 return ATOM_ENCODER_MODE_DVI; 823 } 824 break; 825 case DRM_MODE_CONNECTOR_eDP: 826 if (radeon_audio != 0 && 827 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 828 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 829 return ATOM_ENCODER_MODE_DP_AUDIO; 830 return ATOM_ENCODER_MODE_DP; 831 case DRM_MODE_CONNECTOR_DVIA: 832 case DRM_MODE_CONNECTOR_VGA: 833 return ATOM_ENCODER_MODE_CRT; 834 break; 835 case DRM_MODE_CONNECTOR_Composite: 836 case DRM_MODE_CONNECTOR_SVIDEO: 837 case DRM_MODE_CONNECTOR_9PinDIN: 838 /* fix me */ 839 return ATOM_ENCODER_MODE_TV; 840 /*return ATOM_ENCODER_MODE_CV;*/ 841 break; 842 } 843 } 844 845 /* 846 * DIG Encoder/Transmitter Setup 847 * 848 * DCE 3.0/3.1 849 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 850 * Supports up to 3 digital outputs 851 * - 2 DIG encoder blocks. 852 * DIG1 can drive UNIPHY link A or link B 853 * DIG2 can drive UNIPHY link B or LVTMA 854 * 855 * DCE 3.2 856 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 857 * Supports up to 5 digital outputs 858 * - 2 DIG encoder blocks. 859 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 860 * 861 * DCE 4.0/5.0/6.0 862 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 863 * Supports up to 6 digital outputs 864 * - 6 DIG encoder blocks. 865 * - DIG to PHY mapping is hardcoded 866 * DIG1 drives UNIPHY0 link A, A+B 867 * DIG2 drives UNIPHY0 link B 868 * DIG3 drives UNIPHY1 link A, A+B 869 * DIG4 drives UNIPHY1 link B 870 * DIG5 drives UNIPHY2 link A, A+B 871 * DIG6 drives UNIPHY2 link B 872 * 873 * DCE 4.1 874 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 875 * Supports up to 6 digital outputs 876 * - 2 DIG encoder blocks. 877 * llano 878 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 879 * ontario 880 * DIG1 drives UNIPHY0/1/2 link A 881 * DIG2 drives UNIPHY0/1/2 link B 882 * 883 * Routing 884 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 885 * Examples: 886 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 887 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 888 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 889 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 890 */ 891 892 union dig_encoder_control { 893 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 894 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 895 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 896 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 897 }; 898 899 void 900 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 901 { 902 struct drm_device *dev = encoder->dev; 903 struct radeon_device *rdev = dev->dev_private; 904 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 905 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 906 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 907 union dig_encoder_control args; 908 int index = 0; 909 uint8_t frev, crev; 910 int dp_clock = 0; 911 int dp_lane_count = 0; 912 int hpd_id = RADEON_HPD_NONE; 913 914 if (connector) { 915 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 916 struct radeon_connector_atom_dig *dig_connector = 917 radeon_connector->con_priv; 918 919 dp_clock = dig_connector->dp_clock; 920 dp_lane_count = dig_connector->dp_lane_count; 921 hpd_id = radeon_connector->hpd.hpd; 922 } 923 924 /* no dig encoder assigned */ 925 if (dig->dig_encoder == -1) 926 return; 927 928 memset(&args, 0, sizeof(args)); 929 930 if (ASIC_IS_DCE4(rdev)) 931 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 932 else { 933 if (dig->dig_encoder) 934 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 935 else 936 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 937 } 938 939 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 940 return; 941 942 switch (frev) { 943 case 1: 944 switch (crev) { 945 case 1: 946 args.v1.ucAction = action; 947 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 948 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 949 args.v3.ucPanelMode = panel_mode; 950 else 951 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 952 953 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 954 args.v1.ucLaneNum = dp_lane_count; 955 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 956 args.v1.ucLaneNum = 8; 957 else 958 args.v1.ucLaneNum = 4; 959 960 switch (radeon_encoder->encoder_id) { 961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 962 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 963 break; 964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 965 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 966 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 967 break; 968 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 969 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 970 break; 971 } 972 if (dig->linkb) 973 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 974 else 975 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 976 977 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 978 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 979 980 break; 981 case 2: 982 case 3: 983 args.v3.ucAction = action; 984 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 985 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 986 args.v3.ucPanelMode = panel_mode; 987 else 988 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 989 990 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 991 args.v3.ucLaneNum = dp_lane_count; 992 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 993 args.v3.ucLaneNum = 8; 994 else 995 args.v3.ucLaneNum = 4; 996 997 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 998 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 999 if (enc_override != -1) 1000 args.v3.acConfig.ucDigSel = enc_override; 1001 else 1002 args.v3.acConfig.ucDigSel = dig->dig_encoder; 1003 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 1004 break; 1005 case 4: 1006 args.v4.ucAction = action; 1007 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1008 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 1009 args.v4.ucPanelMode = panel_mode; 1010 else 1011 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 1012 1013 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 1014 args.v4.ucLaneNum = dp_lane_count; 1015 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1016 args.v4.ucLaneNum = 8; 1017 else 1018 args.v4.ucLaneNum = 4; 1019 1020 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 1021 if (dp_clock == 540000) 1022 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 1023 else if (dp_clock == 324000) 1024 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 1025 else if (dp_clock == 270000) 1026 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 1027 else 1028 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 1029 } 1030 1031 if (enc_override != -1) 1032 args.v4.acConfig.ucDigSel = enc_override; 1033 else 1034 args.v4.acConfig.ucDigSel = dig->dig_encoder; 1035 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 1036 if (hpd_id == RADEON_HPD_NONE) 1037 args.v4.ucHPD_ID = 0; 1038 else 1039 args.v4.ucHPD_ID = hpd_id + 1; 1040 break; 1041 default: 1042 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1043 break; 1044 } 1045 break; 1046 default: 1047 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1048 break; 1049 } 1050 1051 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1052 1053 } 1054 1055 void 1056 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 1057 { 1058 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1059 } 1060 1061 union dig_transmitter_control { 1062 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1063 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1064 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1065 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1066 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1067 }; 1068 1069 void 1070 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1071 { 1072 struct drm_device *dev = encoder->dev; 1073 struct radeon_device *rdev = dev->dev_private; 1074 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1075 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1076 struct drm_connector *connector; 1077 union dig_transmitter_control args; 1078 int index = 0; 1079 uint8_t frev, crev; 1080 bool is_dp = false; 1081 int pll_id = 0; 1082 int dp_clock = 0; 1083 int dp_lane_count = 0; 1084 int connector_object_id = 0; 1085 int igp_lane_info = 0; 1086 int dig_encoder = dig->dig_encoder; 1087 int hpd_id = RADEON_HPD_NONE; 1088 1089 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1090 connector = radeon_get_connector_for_encoder_init(encoder); 1091 /* just needed to avoid bailing in the encoder check. the encoder 1092 * isn't used for init 1093 */ 1094 dig_encoder = 0; 1095 } else 1096 connector = radeon_get_connector_for_encoder(encoder); 1097 1098 if (connector) { 1099 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1100 struct radeon_connector_atom_dig *dig_connector = 1101 radeon_connector->con_priv; 1102 1103 hpd_id = radeon_connector->hpd.hpd; 1104 dp_clock = dig_connector->dp_clock; 1105 dp_lane_count = dig_connector->dp_lane_count; 1106 connector_object_id = 1107 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1108 igp_lane_info = dig_connector->igp_lane_info; 1109 } 1110 1111 if (encoder->crtc) { 1112 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1113 pll_id = radeon_crtc->pll_id; 1114 } 1115 1116 /* no dig encoder assigned */ 1117 if (dig_encoder == -1) 1118 return; 1119 1120 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1121 is_dp = true; 1122 1123 memset(&args, 0, sizeof(args)); 1124 1125 switch (radeon_encoder->encoder_id) { 1126 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1127 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1128 break; 1129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1133 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1134 break; 1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1136 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1137 break; 1138 } 1139 1140 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1141 return; 1142 1143 switch (frev) { 1144 case 1: 1145 switch (crev) { 1146 case 1: 1147 args.v1.ucAction = action; 1148 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1149 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1150 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1151 args.v1.asMode.ucLaneSel = lane_num; 1152 args.v1.asMode.ucLaneSet = lane_set; 1153 } else { 1154 if (is_dp) 1155 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1156 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1157 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1158 else 1159 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1160 } 1161 1162 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1163 1164 if (dig_encoder) 1165 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1166 else 1167 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1168 1169 if ((rdev->flags & RADEON_IS_IGP) && 1170 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1171 if (is_dp || 1172 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1173 if (igp_lane_info & 0x1) 1174 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1175 else if (igp_lane_info & 0x2) 1176 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1177 else if (igp_lane_info & 0x4) 1178 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1179 else if (igp_lane_info & 0x8) 1180 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1181 } else { 1182 if (igp_lane_info & 0x3) 1183 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1184 else if (igp_lane_info & 0xc) 1185 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1186 } 1187 } 1188 1189 if (dig->linkb) 1190 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1191 else 1192 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1193 1194 if (is_dp) 1195 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1196 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1197 if (dig->coherent_mode) 1198 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1199 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1200 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1201 } 1202 break; 1203 case 2: 1204 args.v2.ucAction = action; 1205 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1206 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1207 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1208 args.v2.asMode.ucLaneSel = lane_num; 1209 args.v2.asMode.ucLaneSet = lane_set; 1210 } else { 1211 if (is_dp) 1212 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1213 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1214 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1215 else 1216 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1217 } 1218 1219 args.v2.acConfig.ucEncoderSel = dig_encoder; 1220 if (dig->linkb) 1221 args.v2.acConfig.ucLinkSel = 1; 1222 1223 switch (radeon_encoder->encoder_id) { 1224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1225 args.v2.acConfig.ucTransmitterSel = 0; 1226 break; 1227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1228 args.v2.acConfig.ucTransmitterSel = 1; 1229 break; 1230 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1231 args.v2.acConfig.ucTransmitterSel = 2; 1232 break; 1233 } 1234 1235 if (is_dp) { 1236 args.v2.acConfig.fCoherentMode = 1; 1237 args.v2.acConfig.fDPConnector = 1; 1238 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1239 if (dig->coherent_mode) 1240 args.v2.acConfig.fCoherentMode = 1; 1241 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1242 args.v2.acConfig.fDualLinkConnector = 1; 1243 } 1244 break; 1245 case 3: 1246 args.v3.ucAction = action; 1247 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1248 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1249 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1250 args.v3.asMode.ucLaneSel = lane_num; 1251 args.v3.asMode.ucLaneSet = lane_set; 1252 } else { 1253 if (is_dp) 1254 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1255 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1256 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1257 else 1258 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1259 } 1260 1261 if (is_dp) 1262 args.v3.ucLaneNum = dp_lane_count; 1263 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1264 args.v3.ucLaneNum = 8; 1265 else 1266 args.v3.ucLaneNum = 4; 1267 1268 if (dig->linkb) 1269 args.v3.acConfig.ucLinkSel = 1; 1270 if (dig_encoder & 1) 1271 args.v3.acConfig.ucEncoderSel = 1; 1272 1273 /* Select the PLL for the PHY 1274 * DP PHY should be clocked from external src if there is 1275 * one. 1276 */ 1277 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1278 if (is_dp && rdev->clock.dp_extclk) 1279 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1280 else 1281 args.v3.acConfig.ucRefClkSource = pll_id; 1282 1283 switch (radeon_encoder->encoder_id) { 1284 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1285 args.v3.acConfig.ucTransmitterSel = 0; 1286 break; 1287 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1288 args.v3.acConfig.ucTransmitterSel = 1; 1289 break; 1290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1291 args.v3.acConfig.ucTransmitterSel = 2; 1292 break; 1293 } 1294 1295 if (is_dp) 1296 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1297 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1298 if (dig->coherent_mode) 1299 args.v3.acConfig.fCoherentMode = 1; 1300 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1301 args.v3.acConfig.fDualLinkConnector = 1; 1302 } 1303 break; 1304 case 4: 1305 args.v4.ucAction = action; 1306 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1307 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1308 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1309 args.v4.asMode.ucLaneSel = lane_num; 1310 args.v4.asMode.ucLaneSet = lane_set; 1311 } else { 1312 if (is_dp) 1313 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1314 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1315 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1316 else 1317 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1318 } 1319 1320 if (is_dp) 1321 args.v4.ucLaneNum = dp_lane_count; 1322 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1323 args.v4.ucLaneNum = 8; 1324 else 1325 args.v4.ucLaneNum = 4; 1326 1327 if (dig->linkb) 1328 args.v4.acConfig.ucLinkSel = 1; 1329 if (dig_encoder & 1) 1330 args.v4.acConfig.ucEncoderSel = 1; 1331 1332 /* Select the PLL for the PHY 1333 * DP PHY should be clocked from external src if there is 1334 * one. 1335 */ 1336 /* On DCE5 DCPLL usually generates the DP ref clock */ 1337 if (is_dp) { 1338 if (rdev->clock.dp_extclk) 1339 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1340 else 1341 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1342 } else 1343 args.v4.acConfig.ucRefClkSource = pll_id; 1344 1345 switch (radeon_encoder->encoder_id) { 1346 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1347 args.v4.acConfig.ucTransmitterSel = 0; 1348 break; 1349 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1350 args.v4.acConfig.ucTransmitterSel = 1; 1351 break; 1352 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1353 args.v4.acConfig.ucTransmitterSel = 2; 1354 break; 1355 } 1356 1357 if (is_dp) 1358 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1359 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1360 if (dig->coherent_mode) 1361 args.v4.acConfig.fCoherentMode = 1; 1362 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1363 args.v4.acConfig.fDualLinkConnector = 1; 1364 } 1365 break; 1366 case 5: 1367 args.v5.ucAction = action; 1368 if (is_dp) 1369 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1370 else 1371 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1372 1373 switch (radeon_encoder->encoder_id) { 1374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1375 if (dig->linkb) 1376 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1377 else 1378 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1379 break; 1380 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1381 if (dig->linkb) 1382 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1383 else 1384 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1385 break; 1386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1387 if (dig->linkb) 1388 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1389 else 1390 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1391 break; 1392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1393 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1394 break; 1395 } 1396 if (is_dp) 1397 args.v5.ucLaneNum = dp_lane_count; 1398 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1399 args.v5.ucLaneNum = 8; 1400 else 1401 args.v5.ucLaneNum = 4; 1402 args.v5.ucConnObjId = connector_object_id; 1403 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1404 1405 if (is_dp && rdev->clock.dp_extclk) 1406 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1407 else 1408 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1409 1410 if (is_dp) 1411 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1412 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1413 if (dig->coherent_mode) 1414 args.v5.asConfig.ucCoherentMode = 1; 1415 } 1416 if (hpd_id == RADEON_HPD_NONE) 1417 args.v5.asConfig.ucHPDSel = 0; 1418 else 1419 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1420 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1421 args.v5.ucDPLaneSet = lane_set; 1422 break; 1423 default: 1424 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1425 break; 1426 } 1427 break; 1428 default: 1429 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1430 break; 1431 } 1432 1433 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1434 } 1435 1436 void 1437 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1438 { 1439 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1440 } 1441 1442 bool 1443 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1444 { 1445 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1446 struct drm_device *dev = radeon_connector->base.dev; 1447 struct radeon_device *rdev = dev->dev_private; 1448 union dig_transmitter_control args; 1449 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1450 uint8_t frev, crev; 1451 1452 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1453 goto done; 1454 1455 if (!ASIC_IS_DCE4(rdev)) 1456 goto done; 1457 1458 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1459 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1460 goto done; 1461 1462 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1463 goto done; 1464 1465 memset(&args, 0, sizeof(args)); 1466 1467 args.v1.ucAction = action; 1468 1469 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1470 1471 /* wait for the panel to power up */ 1472 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1473 int i; 1474 1475 for (i = 0; i < 300; i++) { 1476 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1477 return true; 1478 mdelay(1); 1479 } 1480 return false; 1481 } 1482 done: 1483 return true; 1484 } 1485 1486 union external_encoder_control { 1487 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1488 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1489 }; 1490 1491 static void 1492 atombios_external_encoder_setup(struct drm_encoder *encoder, 1493 struct drm_encoder *ext_encoder, 1494 int action) 1495 { 1496 struct drm_device *dev = encoder->dev; 1497 struct radeon_device *rdev = dev->dev_private; 1498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1499 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1500 union external_encoder_control args; 1501 struct drm_connector *connector; 1502 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1503 u8 frev, crev; 1504 int dp_clock = 0; 1505 int dp_lane_count = 0; 1506 int connector_object_id = 0; 1507 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1508 1509 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1510 connector = radeon_get_connector_for_encoder_init(encoder); 1511 else 1512 connector = radeon_get_connector_for_encoder(encoder); 1513 1514 if (connector) { 1515 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1516 struct radeon_connector_atom_dig *dig_connector = 1517 radeon_connector->con_priv; 1518 1519 dp_clock = dig_connector->dp_clock; 1520 dp_lane_count = dig_connector->dp_lane_count; 1521 connector_object_id = 1522 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1523 } 1524 1525 memset(&args, 0, sizeof(args)); 1526 1527 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1528 return; 1529 1530 switch (frev) { 1531 case 1: 1532 /* no params on frev 1 */ 1533 break; 1534 case 2: 1535 switch (crev) { 1536 case 1: 1537 case 2: 1538 args.v1.sDigEncoder.ucAction = action; 1539 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1540 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1541 1542 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1543 if (dp_clock == 270000) 1544 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1545 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1546 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1547 args.v1.sDigEncoder.ucLaneNum = 8; 1548 else 1549 args.v1.sDigEncoder.ucLaneNum = 4; 1550 break; 1551 case 3: 1552 args.v3.sExtEncoder.ucAction = action; 1553 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1554 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1555 else 1556 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1557 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1558 1559 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1560 if (dp_clock == 270000) 1561 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1562 else if (dp_clock == 540000) 1563 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1564 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1565 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1566 args.v3.sExtEncoder.ucLaneNum = 8; 1567 else 1568 args.v3.sExtEncoder.ucLaneNum = 4; 1569 switch (ext_enum) { 1570 case GRAPH_OBJECT_ENUM_ID1: 1571 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1572 break; 1573 case GRAPH_OBJECT_ENUM_ID2: 1574 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1575 break; 1576 case GRAPH_OBJECT_ENUM_ID3: 1577 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1578 break; 1579 } 1580 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1581 break; 1582 default: 1583 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1584 return; 1585 } 1586 break; 1587 default: 1588 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1589 return; 1590 } 1591 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1592 } 1593 1594 static void 1595 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1596 { 1597 struct drm_device *dev = encoder->dev; 1598 struct radeon_device *rdev = dev->dev_private; 1599 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1600 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1601 ENABLE_YUV_PS_ALLOCATION args; 1602 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1603 uint32_t temp, reg; 1604 1605 memset(&args, 0, sizeof(args)); 1606 1607 if (rdev->family >= CHIP_R600) 1608 reg = R600_BIOS_3_SCRATCH; 1609 else 1610 reg = RADEON_BIOS_3_SCRATCH; 1611 1612 /* XXX: fix up scratch reg handling */ 1613 temp = RREG32(reg); 1614 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1615 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1616 (radeon_crtc->crtc_id << 18))); 1617 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1618 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1619 else 1620 WREG32(reg, 0); 1621 1622 if (enable) 1623 args.ucEnable = ATOM_ENABLE; 1624 args.ucCRTC = radeon_crtc->crtc_id; 1625 1626 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1627 1628 WREG32(reg, temp); 1629 } 1630 1631 static void 1632 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1633 { 1634 struct drm_device *dev = encoder->dev; 1635 struct radeon_device *rdev = dev->dev_private; 1636 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1637 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1638 int index = 0; 1639 1640 memset(&args, 0, sizeof(args)); 1641 1642 switch (radeon_encoder->encoder_id) { 1643 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1644 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1645 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1646 break; 1647 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1648 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1649 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1650 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1651 break; 1652 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1653 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1654 break; 1655 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1656 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1657 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1658 else 1659 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1660 break; 1661 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1663 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1664 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1665 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1666 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1667 else 1668 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1669 break; 1670 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1671 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1672 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1673 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1674 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1675 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1676 else 1677 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1678 break; 1679 default: 1680 return; 1681 } 1682 1683 switch (mode) { 1684 case DRM_MODE_DPMS_ON: 1685 args.ucAction = ATOM_ENABLE; 1686 /* workaround for DVOOutputControl on some RS690 systems */ 1687 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1688 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1689 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1690 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1691 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1692 } else 1693 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1694 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1695 if (rdev->mode_info.bl_encoder) { 1696 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1697 1698 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1699 } else { 1700 args.ucAction = ATOM_LCD_BLON; 1701 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1702 } 1703 } 1704 break; 1705 case DRM_MODE_DPMS_STANDBY: 1706 case DRM_MODE_DPMS_SUSPEND: 1707 case DRM_MODE_DPMS_OFF: 1708 args.ucAction = ATOM_DISABLE; 1709 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1710 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1711 args.ucAction = ATOM_LCD_BLOFF; 1712 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1713 } 1714 break; 1715 } 1716 } 1717 1718 static void 1719 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1720 { 1721 struct drm_device *dev = encoder->dev; 1722 struct radeon_device *rdev = dev->dev_private; 1723 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1724 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1725 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1726 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1727 struct radeon_connector *radeon_connector = NULL; 1728 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1729 bool travis_quirk = false; 1730 1731 if (connector) { 1732 radeon_connector = to_radeon_connector(connector); 1733 radeon_dig_connector = radeon_connector->con_priv; 1734 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1735 ENCODER_OBJECT_ID_TRAVIS) && 1736 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1737 !ASIC_IS_DCE5(rdev)) 1738 travis_quirk = true; 1739 } 1740 1741 switch (mode) { 1742 case DRM_MODE_DPMS_ON: 1743 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1744 if (!connector) 1745 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1746 else 1747 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1748 1749 /* setup and enable the encoder */ 1750 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1751 atombios_dig_encoder_setup(encoder, 1752 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1753 dig->panel_mode); 1754 if (ext_encoder) { 1755 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1756 atombios_external_encoder_setup(encoder, ext_encoder, 1757 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1758 } 1759 } else if (ASIC_IS_DCE4(rdev)) { 1760 /* setup and enable the encoder */ 1761 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1762 } else { 1763 /* setup and enable the encoder and transmitter */ 1764 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1765 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1766 } 1767 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1768 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1769 atombios_set_edp_panel_power(connector, 1770 ATOM_TRANSMITTER_ACTION_POWER_ON); 1771 radeon_dig_connector->edp_on = true; 1772 } 1773 } 1774 /* enable the transmitter */ 1775 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1776 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1777 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1778 radeon_dp_link_train(encoder, connector); 1779 if (ASIC_IS_DCE4(rdev)) 1780 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1781 } 1782 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1783 if (rdev->mode_info.bl_encoder) 1784 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1785 else 1786 atombios_dig_transmitter_setup(encoder, 1787 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1788 } 1789 if (ext_encoder) 1790 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1791 break; 1792 case DRM_MODE_DPMS_STANDBY: 1793 case DRM_MODE_DPMS_SUSPEND: 1794 case DRM_MODE_DPMS_OFF: 1795 if (ASIC_IS_DCE4(rdev)) { 1796 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1797 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1798 } 1799 if (ext_encoder) 1800 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1801 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1802 atombios_dig_transmitter_setup(encoder, 1803 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1804 1805 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1806 connector && !travis_quirk) 1807 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1808 if (ASIC_IS_DCE4(rdev)) { 1809 /* disable the transmitter */ 1810 atombios_dig_transmitter_setup(encoder, 1811 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1812 } else { 1813 /* disable the encoder and transmitter */ 1814 atombios_dig_transmitter_setup(encoder, 1815 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1816 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1817 } 1818 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1819 if (travis_quirk) 1820 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1821 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1822 atombios_set_edp_panel_power(connector, 1823 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1824 radeon_dig_connector->edp_on = false; 1825 } 1826 } 1827 break; 1828 } 1829 } 1830 1831 static void 1832 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1833 { 1834 struct drm_device *dev = encoder->dev; 1835 struct radeon_device *rdev = dev->dev_private; 1836 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1837 int encoder_mode = atombios_get_encoder_mode(encoder); 1838 1839 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1840 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1841 radeon_encoder->active_device); 1842 1843 if ((radeon_audio != 0) && 1844 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1845 ENCODER_MODE_IS_DP(encoder_mode))) 1846 radeon_audio_dpms(encoder, mode); 1847 1848 switch (radeon_encoder->encoder_id) { 1849 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1850 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1851 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1852 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1853 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1854 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1855 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1856 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1857 radeon_atom_encoder_dpms_avivo(encoder, mode); 1858 break; 1859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1860 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1861 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1863 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1864 radeon_atom_encoder_dpms_dig(encoder, mode); 1865 break; 1866 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1867 if (ASIC_IS_DCE5(rdev)) { 1868 switch (mode) { 1869 case DRM_MODE_DPMS_ON: 1870 atombios_dvo_setup(encoder, ATOM_ENABLE); 1871 break; 1872 case DRM_MODE_DPMS_STANDBY: 1873 case DRM_MODE_DPMS_SUSPEND: 1874 case DRM_MODE_DPMS_OFF: 1875 atombios_dvo_setup(encoder, ATOM_DISABLE); 1876 break; 1877 } 1878 } else if (ASIC_IS_DCE3(rdev)) 1879 radeon_atom_encoder_dpms_dig(encoder, mode); 1880 else 1881 radeon_atom_encoder_dpms_avivo(encoder, mode); 1882 break; 1883 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1885 if (ASIC_IS_DCE5(rdev)) { 1886 switch (mode) { 1887 case DRM_MODE_DPMS_ON: 1888 atombios_dac_setup(encoder, ATOM_ENABLE); 1889 break; 1890 case DRM_MODE_DPMS_STANDBY: 1891 case DRM_MODE_DPMS_SUSPEND: 1892 case DRM_MODE_DPMS_OFF: 1893 atombios_dac_setup(encoder, ATOM_DISABLE); 1894 break; 1895 } 1896 } else 1897 radeon_atom_encoder_dpms_avivo(encoder, mode); 1898 break; 1899 default: 1900 return; 1901 } 1902 1903 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1904 1905 } 1906 1907 union crtc_source_param { 1908 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1909 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1910 }; 1911 1912 static void 1913 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1914 { 1915 struct drm_device *dev = encoder->dev; 1916 struct radeon_device *rdev = dev->dev_private; 1917 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1918 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1919 union crtc_source_param args; 1920 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1921 uint8_t frev, crev; 1922 struct radeon_encoder_atom_dig *dig; 1923 1924 memset(&args, 0, sizeof(args)); 1925 1926 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1927 return; 1928 1929 switch (frev) { 1930 case 1: 1931 switch (crev) { 1932 case 1: 1933 default: 1934 if (ASIC_IS_AVIVO(rdev)) 1935 args.v1.ucCRTC = radeon_crtc->crtc_id; 1936 else { 1937 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1938 args.v1.ucCRTC = radeon_crtc->crtc_id; 1939 } else { 1940 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1941 } 1942 } 1943 switch (radeon_encoder->encoder_id) { 1944 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1945 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1946 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1947 break; 1948 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1949 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1950 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1951 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1952 else 1953 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1954 break; 1955 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1956 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1957 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1958 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1959 break; 1960 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1961 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1962 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1963 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1964 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1965 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1966 else 1967 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1968 break; 1969 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1970 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1971 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1972 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1973 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1974 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1975 else 1976 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1977 break; 1978 } 1979 break; 1980 case 2: 1981 args.v2.ucCRTC = radeon_crtc->crtc_id; 1982 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1983 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1984 1985 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1986 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1987 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1988 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1989 else 1990 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1991 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1992 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1993 } else { 1994 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1995 } 1996 switch (radeon_encoder->encoder_id) { 1997 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1998 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2001 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2002 dig = radeon_encoder->enc_priv; 2003 switch (dig->dig_encoder) { 2004 case 0: 2005 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2006 break; 2007 case 1: 2008 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2009 break; 2010 case 2: 2011 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2012 break; 2013 case 3: 2014 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2015 break; 2016 case 4: 2017 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2018 break; 2019 case 5: 2020 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2021 break; 2022 case 6: 2023 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2024 break; 2025 } 2026 break; 2027 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2028 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 2029 break; 2030 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2031 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2032 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2033 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2034 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2035 else 2036 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 2037 break; 2038 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2039 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2040 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2041 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2042 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2043 else 2044 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 2045 break; 2046 } 2047 break; 2048 } 2049 break; 2050 default: 2051 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2052 return; 2053 } 2054 2055 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2056 2057 /* update scratch regs with new routing */ 2058 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2059 } 2060 2061 static void 2062 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2063 struct drm_display_mode *mode) 2064 { 2065 struct drm_device *dev = encoder->dev; 2066 struct radeon_device *rdev = dev->dev_private; 2067 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2068 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2069 2070 /* Funky macbooks */ 2071 if ((dev->pdev->device == 0x71C5) && 2072 (dev->pdev->subsystem_vendor == 0x106b) && 2073 (dev->pdev->subsystem_device == 0x0080)) { 2074 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2075 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2076 2077 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2078 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2079 2080 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2081 } 2082 } 2083 2084 /* set scaler clears this on some chips */ 2085 if (ASIC_IS_AVIVO(rdev) && 2086 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2087 if (ASIC_IS_DCE8(rdev)) { 2088 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2089 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2090 CIK_INTERLEAVE_EN); 2091 else 2092 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2093 } else if (ASIC_IS_DCE4(rdev)) { 2094 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2095 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2096 EVERGREEN_INTERLEAVE_EN); 2097 else 2098 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2099 } else { 2100 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2101 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2102 AVIVO_D1MODE_INTERLEAVE_EN); 2103 else 2104 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2105 } 2106 } 2107 } 2108 2109 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2110 { 2111 if (enc_idx < 0) 2112 return; 2113 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2114 } 2115 2116 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2117 { 2118 struct drm_device *dev = encoder->dev; 2119 struct radeon_device *rdev = dev->dev_private; 2120 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2121 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2122 struct drm_encoder *test_encoder; 2123 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2124 uint32_t dig_enc_in_use = 0; 2125 int enc_idx = -1; 2126 2127 if (fe_idx >= 0) { 2128 enc_idx = fe_idx; 2129 goto assigned; 2130 } 2131 if (ASIC_IS_DCE6(rdev)) { 2132 /* DCE6 */ 2133 switch (radeon_encoder->encoder_id) { 2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2135 if (dig->linkb) 2136 enc_idx = 1; 2137 else 2138 enc_idx = 0; 2139 break; 2140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2141 if (dig->linkb) 2142 enc_idx = 3; 2143 else 2144 enc_idx = 2; 2145 break; 2146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2147 if (dig->linkb) 2148 enc_idx = 5; 2149 else 2150 enc_idx = 4; 2151 break; 2152 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2153 enc_idx = 6; 2154 break; 2155 } 2156 goto assigned; 2157 } else if (ASIC_IS_DCE4(rdev)) { 2158 /* DCE4/5 */ 2159 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2160 /* ontario follows DCE4 */ 2161 if (rdev->family == CHIP_PALM) { 2162 if (dig->linkb) 2163 enc_idx = 1; 2164 else 2165 enc_idx = 0; 2166 } else 2167 /* llano follows DCE3.2 */ 2168 enc_idx = radeon_crtc->crtc_id; 2169 } else { 2170 switch (radeon_encoder->encoder_id) { 2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2172 if (dig->linkb) 2173 enc_idx = 1; 2174 else 2175 enc_idx = 0; 2176 break; 2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2178 if (dig->linkb) 2179 enc_idx = 3; 2180 else 2181 enc_idx = 2; 2182 break; 2183 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2184 if (dig->linkb) 2185 enc_idx = 5; 2186 else 2187 enc_idx = 4; 2188 break; 2189 } 2190 } 2191 goto assigned; 2192 } 2193 2194 /* on DCE32 and encoder can driver any block so just crtc id */ 2195 if (ASIC_IS_DCE32(rdev)) { 2196 enc_idx = radeon_crtc->crtc_id; 2197 goto assigned; 2198 } 2199 2200 /* on DCE3 - LVTMA can only be driven by DIGB */ 2201 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2202 struct radeon_encoder *radeon_test_encoder; 2203 2204 if (encoder == test_encoder) 2205 continue; 2206 2207 if (!radeon_encoder_is_digital(test_encoder)) 2208 continue; 2209 2210 radeon_test_encoder = to_radeon_encoder(test_encoder); 2211 dig = radeon_test_encoder->enc_priv; 2212 2213 if (dig->dig_encoder >= 0) 2214 dig_enc_in_use |= (1 << dig->dig_encoder); 2215 } 2216 2217 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2218 if (dig_enc_in_use & 0x2) 2219 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2220 return 1; 2221 } 2222 if (!(dig_enc_in_use & 1)) 2223 return 0; 2224 return 1; 2225 2226 assigned: 2227 if (enc_idx == -1) { 2228 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2229 return 0; 2230 } 2231 if (rdev->mode_info.active_encoders & (1 << enc_idx)) { 2232 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2233 } 2234 rdev->mode_info.active_encoders |= (1 << enc_idx); 2235 return enc_idx; 2236 } 2237 2238 /* This only needs to be called once at startup */ 2239 void 2240 radeon_atom_encoder_init(struct radeon_device *rdev) 2241 { 2242 struct drm_device *dev = rdev->ddev; 2243 struct drm_encoder *encoder; 2244 2245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2246 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2247 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2248 2249 switch (radeon_encoder->encoder_id) { 2250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2252 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2254 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2255 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2256 break; 2257 default: 2258 break; 2259 } 2260 2261 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2262 atombios_external_encoder_setup(encoder, ext_encoder, 2263 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2264 } 2265 } 2266 2267 static void 2268 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2269 struct drm_display_mode *mode, 2270 struct drm_display_mode *adjusted_mode) 2271 { 2272 struct drm_device *dev = encoder->dev; 2273 struct radeon_device *rdev = dev->dev_private; 2274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2275 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2276 int encoder_mode; 2277 2278 radeon_encoder->pixel_clock = adjusted_mode->clock; 2279 2280 /* need to call this here rather than in prepare() since we need some crtc info */ 2281 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2282 2283 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2284 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2285 atombios_yuv_setup(encoder, true); 2286 else 2287 atombios_yuv_setup(encoder, false); 2288 } 2289 2290 switch (radeon_encoder->encoder_id) { 2291 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2293 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2294 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2295 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2296 break; 2297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2302 /* handled in dpms */ 2303 break; 2304 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2305 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2306 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2307 atombios_dvo_setup(encoder, ATOM_ENABLE); 2308 break; 2309 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2310 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2311 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2312 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2313 atombios_dac_setup(encoder, ATOM_ENABLE); 2314 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2315 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2316 atombios_tv_setup(encoder, ATOM_ENABLE); 2317 else 2318 atombios_tv_setup(encoder, ATOM_DISABLE); 2319 } 2320 break; 2321 } 2322 2323 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2324 2325 encoder_mode = atombios_get_encoder_mode(encoder); 2326 if (connector && (radeon_audio != 0) && 2327 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2328 ENCODER_MODE_IS_DP(encoder_mode))) 2329 radeon_audio_mode_set(encoder, adjusted_mode); 2330 } 2331 2332 static bool 2333 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2334 { 2335 struct drm_device *dev = encoder->dev; 2336 struct radeon_device *rdev = dev->dev_private; 2337 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2338 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2339 2340 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2341 ATOM_DEVICE_CV_SUPPORT | 2342 ATOM_DEVICE_CRT_SUPPORT)) { 2343 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2344 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2345 uint8_t frev, crev; 2346 2347 memset(&args, 0, sizeof(args)); 2348 2349 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2350 return false; 2351 2352 args.sDacload.ucMisc = 0; 2353 2354 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2355 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2356 args.sDacload.ucDacType = ATOM_DAC_A; 2357 else 2358 args.sDacload.ucDacType = ATOM_DAC_B; 2359 2360 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2361 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2362 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2363 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2364 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2365 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2366 if (crev >= 3) 2367 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2368 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2369 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2370 if (crev >= 3) 2371 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2372 } 2373 2374 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2375 2376 return true; 2377 } else 2378 return false; 2379 } 2380 2381 static enum drm_connector_status 2382 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2383 { 2384 struct drm_device *dev = encoder->dev; 2385 struct radeon_device *rdev = dev->dev_private; 2386 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2387 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2388 uint32_t bios_0_scratch; 2389 2390 if (!atombios_dac_load_detect(encoder, connector)) { 2391 DRM_DEBUG_KMS("detect returned false \n"); 2392 return connector_status_unknown; 2393 } 2394 2395 if (rdev->family >= CHIP_R600) 2396 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2397 else 2398 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2399 2400 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2401 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2402 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2403 return connector_status_connected; 2404 } 2405 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2406 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2407 return connector_status_connected; 2408 } 2409 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2410 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2411 return connector_status_connected; 2412 } 2413 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2414 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2415 return connector_status_connected; /* CTV */ 2416 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2417 return connector_status_connected; /* STV */ 2418 } 2419 return connector_status_disconnected; 2420 } 2421 2422 static enum drm_connector_status 2423 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2424 { 2425 struct drm_device *dev = encoder->dev; 2426 struct radeon_device *rdev = dev->dev_private; 2427 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2428 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2429 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2430 u32 bios_0_scratch; 2431 2432 if (!ASIC_IS_DCE4(rdev)) 2433 return connector_status_unknown; 2434 2435 if (!ext_encoder) 2436 return connector_status_unknown; 2437 2438 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2439 return connector_status_unknown; 2440 2441 /* load detect on the dp bridge */ 2442 atombios_external_encoder_setup(encoder, ext_encoder, 2443 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2444 2445 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2446 2447 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2448 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2449 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2450 return connector_status_connected; 2451 } 2452 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2453 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2454 return connector_status_connected; 2455 } 2456 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2457 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2458 return connector_status_connected; 2459 } 2460 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2461 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2462 return connector_status_connected; /* CTV */ 2463 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2464 return connector_status_connected; /* STV */ 2465 } 2466 return connector_status_disconnected; 2467 } 2468 2469 void 2470 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2471 { 2472 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2473 2474 if (ext_encoder) 2475 /* ddc_setup on the dp bridge */ 2476 atombios_external_encoder_setup(encoder, ext_encoder, 2477 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2478 2479 } 2480 2481 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2482 { 2483 struct radeon_device *rdev = encoder->dev->dev_private; 2484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2485 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2486 2487 if ((radeon_encoder->active_device & 2488 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2489 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2490 ENCODER_OBJECT_ID_NONE)) { 2491 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2492 if (dig) { 2493 if (dig->dig_encoder >= 0) 2494 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2495 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2496 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2497 if (rdev->family >= CHIP_R600) 2498 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2499 else 2500 /* RS600/690/740 have only 1 afmt block */ 2501 dig->afmt = rdev->mode_info.afmt[0]; 2502 } 2503 } 2504 } 2505 2506 radeon_atom_output_lock(encoder, true); 2507 2508 if (connector) { 2509 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2510 2511 /* select the clock/data port if it uses a router */ 2512 if (radeon_connector->router.cd_valid) 2513 radeon_router_select_cd_port(radeon_connector); 2514 2515 /* turn eDP panel on for mode set */ 2516 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2517 atombios_set_edp_panel_power(connector, 2518 ATOM_TRANSMITTER_ACTION_POWER_ON); 2519 } 2520 2521 /* this is needed for the pll/ss setup to work correctly in some cases */ 2522 atombios_set_encoder_crtc_source(encoder); 2523 /* set up the FMT blocks */ 2524 if (ASIC_IS_DCE8(rdev)) 2525 dce8_program_fmt(encoder); 2526 else if (ASIC_IS_DCE4(rdev)) 2527 dce4_program_fmt(encoder); 2528 else if (ASIC_IS_DCE3(rdev)) 2529 dce3_program_fmt(encoder); 2530 else if (ASIC_IS_AVIVO(rdev)) 2531 avivo_program_fmt(encoder); 2532 } 2533 2534 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2535 { 2536 /* need to call this here as we need the crtc set up */ 2537 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2538 radeon_atom_output_lock(encoder, false); 2539 } 2540 2541 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2542 { 2543 struct drm_device *dev = encoder->dev; 2544 struct radeon_device *rdev = dev->dev_private; 2545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2546 struct radeon_encoder_atom_dig *dig; 2547 2548 /* check for pre-DCE3 cards with shared encoders; 2549 * can't really use the links individually, so don't disable 2550 * the encoder if it's in use by another connector 2551 */ 2552 if (!ASIC_IS_DCE3(rdev)) { 2553 struct drm_encoder *other_encoder; 2554 struct radeon_encoder *other_radeon_encoder; 2555 2556 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2557 other_radeon_encoder = to_radeon_encoder(other_encoder); 2558 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2559 drm_helper_encoder_in_use(other_encoder)) 2560 goto disable_done; 2561 } 2562 } 2563 2564 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2565 2566 switch (radeon_encoder->encoder_id) { 2567 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2568 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2569 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2570 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2571 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2572 break; 2573 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2574 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2575 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2576 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2578 /* handled in dpms */ 2579 break; 2580 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2581 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2583 atombios_dvo_setup(encoder, ATOM_DISABLE); 2584 break; 2585 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2587 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2589 atombios_dac_setup(encoder, ATOM_DISABLE); 2590 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2591 atombios_tv_setup(encoder, ATOM_DISABLE); 2592 break; 2593 } 2594 2595 disable_done: 2596 if (radeon_encoder_is_digital(encoder)) { 2597 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2598 if (rdev->asic->display.hdmi_enable) 2599 radeon_hdmi_enable(rdev, encoder, false); 2600 } 2601 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2602 dig = radeon_encoder->enc_priv; 2603 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2604 dig->dig_encoder = -1; 2605 radeon_encoder->active_device = 0; 2606 } 2607 } else 2608 radeon_encoder->active_device = 0; 2609 } 2610 2611 /* these are handled by the primary encoders */ 2612 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2613 { 2614 2615 } 2616 2617 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2618 { 2619 2620 } 2621 2622 static void 2623 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2624 struct drm_display_mode *mode, 2625 struct drm_display_mode *adjusted_mode) 2626 { 2627 2628 } 2629 2630 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2631 { 2632 2633 } 2634 2635 static void 2636 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2637 { 2638 2639 } 2640 2641 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2642 const struct drm_display_mode *mode, 2643 struct drm_display_mode *adjusted_mode) 2644 { 2645 return true; 2646 } 2647 2648 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2649 .dpms = radeon_atom_ext_dpms, 2650 .mode_fixup = radeon_atom_ext_mode_fixup, 2651 .prepare = radeon_atom_ext_prepare, 2652 .mode_set = radeon_atom_ext_mode_set, 2653 .commit = radeon_atom_ext_commit, 2654 .disable = radeon_atom_ext_disable, 2655 /* no detect for TMDS/LVDS yet */ 2656 }; 2657 2658 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2659 .dpms = radeon_atom_encoder_dpms, 2660 .mode_fixup = radeon_atom_mode_fixup, 2661 .prepare = radeon_atom_encoder_prepare, 2662 .mode_set = radeon_atom_encoder_mode_set, 2663 .commit = radeon_atom_encoder_commit, 2664 .disable = radeon_atom_encoder_disable, 2665 .detect = radeon_atom_dig_detect, 2666 }; 2667 2668 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2669 .dpms = radeon_atom_encoder_dpms, 2670 .mode_fixup = radeon_atom_mode_fixup, 2671 .prepare = radeon_atom_encoder_prepare, 2672 .mode_set = radeon_atom_encoder_mode_set, 2673 .commit = radeon_atom_encoder_commit, 2674 .detect = radeon_atom_dac_detect, 2675 }; 2676 2677 void radeon_enc_destroy(struct drm_encoder *encoder) 2678 { 2679 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2680 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2681 radeon_atom_backlight_exit(radeon_encoder); 2682 kfree(radeon_encoder->enc_priv); 2683 drm_encoder_cleanup(encoder); 2684 kfree(radeon_encoder); 2685 } 2686 2687 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2688 .destroy = radeon_enc_destroy, 2689 }; 2690 2691 static struct radeon_encoder_atom_dac * 2692 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2693 { 2694 struct drm_device *dev = radeon_encoder->base.dev; 2695 struct radeon_device *rdev = dev->dev_private; 2696 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2697 2698 if (!dac) 2699 return NULL; 2700 2701 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2702 return dac; 2703 } 2704 2705 static struct radeon_encoder_atom_dig * 2706 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2707 { 2708 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2709 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2710 2711 if (!dig) 2712 return NULL; 2713 2714 /* coherent mode by default */ 2715 dig->coherent_mode = true; 2716 dig->dig_encoder = -1; 2717 2718 if (encoder_enum == 2) 2719 dig->linkb = true; 2720 else 2721 dig->linkb = false; 2722 2723 return dig; 2724 } 2725 2726 void 2727 radeon_add_atom_encoder(struct drm_device *dev, 2728 uint32_t encoder_enum, 2729 uint32_t supported_device, 2730 u16 caps) 2731 { 2732 struct radeon_device *rdev = dev->dev_private; 2733 struct drm_encoder *encoder; 2734 struct radeon_encoder *radeon_encoder; 2735 2736 /* see if we already added it */ 2737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2738 radeon_encoder = to_radeon_encoder(encoder); 2739 if (radeon_encoder->encoder_enum == encoder_enum) { 2740 radeon_encoder->devices |= supported_device; 2741 return; 2742 } 2743 2744 } 2745 2746 /* add a new one */ 2747 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2748 if (!radeon_encoder) 2749 return; 2750 2751 encoder = &radeon_encoder->base; 2752 switch (rdev->num_crtc) { 2753 case 1: 2754 encoder->possible_crtcs = 0x1; 2755 break; 2756 case 2: 2757 default: 2758 encoder->possible_crtcs = 0x3; 2759 break; 2760 case 4: 2761 encoder->possible_crtcs = 0xf; 2762 break; 2763 case 6: 2764 encoder->possible_crtcs = 0x3f; 2765 break; 2766 } 2767 2768 radeon_encoder->enc_priv = NULL; 2769 2770 radeon_encoder->encoder_enum = encoder_enum; 2771 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2772 radeon_encoder->devices = supported_device; 2773 radeon_encoder->rmx_type = RMX_OFF; 2774 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2775 radeon_encoder->is_ext_encoder = false; 2776 radeon_encoder->caps = caps; 2777 2778 switch (radeon_encoder->encoder_id) { 2779 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2780 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2781 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2782 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2783 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2784 radeon_encoder->rmx_type = RMX_FULL; 2785 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2786 DRM_MODE_ENCODER_LVDS, NULL); 2787 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2788 } else { 2789 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2790 DRM_MODE_ENCODER_TMDS, NULL); 2791 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2792 } 2793 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2794 break; 2795 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2796 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2797 DRM_MODE_ENCODER_DAC, NULL); 2798 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2799 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2800 break; 2801 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2803 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2804 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2805 DRM_MODE_ENCODER_TVDAC, NULL); 2806 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2807 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2808 break; 2809 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2810 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2811 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2813 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2815 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2816 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2817 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2818 radeon_encoder->rmx_type = RMX_FULL; 2819 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2820 DRM_MODE_ENCODER_LVDS, NULL); 2821 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2822 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2823 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2824 DRM_MODE_ENCODER_DAC, NULL); 2825 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2826 } else { 2827 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2828 DRM_MODE_ENCODER_TMDS, NULL); 2829 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2830 } 2831 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2832 break; 2833 case ENCODER_OBJECT_ID_SI170B: 2834 case ENCODER_OBJECT_ID_CH7303: 2835 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2836 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2837 case ENCODER_OBJECT_ID_TITFP513: 2838 case ENCODER_OBJECT_ID_VT1623: 2839 case ENCODER_OBJECT_ID_HDMI_SI1930: 2840 case ENCODER_OBJECT_ID_TRAVIS: 2841 case ENCODER_OBJECT_ID_NUTMEG: 2842 /* these are handled by the primary encoders */ 2843 radeon_encoder->is_ext_encoder = true; 2844 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2845 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2846 DRM_MODE_ENCODER_LVDS, NULL); 2847 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2848 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2849 DRM_MODE_ENCODER_DAC, NULL); 2850 else 2851 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2852 DRM_MODE_ENCODER_TMDS, NULL); 2853 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2854 break; 2855 } 2856 } 2857