1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_audio.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include <linux/backlight.h> 34 #include <linux/dmi.h> 35 36 static u8 37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 38 { 39 u8 backlight_level; 40 u32 bios_2_scratch; 41 42 if (rdev->family >= CHIP_R600) 43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 44 else 45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 46 47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 49 50 return backlight_level; 51 } 52 53 static void 54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 55 u8 backlight_level) 56 { 57 u32 bios_2_scratch; 58 59 if (rdev->family >= CHIP_R600) 60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 61 else 62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 63 64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 66 ATOM_S2_CURRENT_BL_LEVEL_MASK); 67 68 if (rdev->family >= CHIP_R600) 69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 70 else 71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 72 } 73 74 u8 75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 76 { 77 struct drm_device *dev = radeon_encoder->base.dev; 78 struct radeon_device *rdev = dev->dev_private; 79 80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 81 return 0; 82 83 return radeon_atom_get_backlight_level_from_reg(rdev); 84 } 85 86 void 87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 88 { 89 struct drm_encoder *encoder = &radeon_encoder->base; 90 struct drm_device *dev = radeon_encoder->base.dev; 91 struct radeon_device *rdev = dev->dev_private; 92 struct radeon_encoder_atom_dig *dig; 93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 94 int index; 95 96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 97 return; 98 99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 100 radeon_encoder->enc_priv) { 101 dig = radeon_encoder->enc_priv; 102 dig->backlight_level = level; 103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 104 105 switch (radeon_encoder->encoder_id) { 106 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 109 if (dig->backlight_level == 0) { 110 args.ucAction = ATOM_LCD_BLOFF; 111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 112 } else { 113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 115 args.ucAction = ATOM_LCD_BLON; 116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 117 } 118 break; 119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 124 if (dig->backlight_level == 0) 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 126 else { 127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 128 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 129 } 130 break; 131 default: 132 break; 133 } 134 } 135 } 136 137 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 138 139 #if 0 140 static u8 radeon_atom_bl_level(struct backlight_device *bd) 141 { 142 u8 level; 143 144 /* Convert brightness to hardware level */ 145 if (bd->props.brightness < 0) 146 level = 0; 147 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 148 level = RADEON_MAX_BL_LEVEL; 149 else 150 level = bd->props.brightness; 151 152 return level; 153 } 154 155 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 156 { 157 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 158 struct radeon_encoder *radeon_encoder = pdata->encoder; 159 160 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 161 162 return 0; 163 } 164 165 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 166 { 167 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 168 struct radeon_encoder *radeon_encoder = pdata->encoder; 169 struct drm_device *dev = radeon_encoder->base.dev; 170 struct radeon_device *rdev = dev->dev_private; 171 172 return radeon_atom_get_backlight_level_from_reg(rdev); 173 } 174 175 static const struct backlight_ops radeon_atom_backlight_ops = { 176 .get_brightness = radeon_atom_backlight_get_brightness, 177 .update_status = radeon_atom_backlight_update_status, 178 }; 179 #endif 180 181 /* 182 * Read max backlight level 183 */ 184 static int 185 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 186 { 187 int err, val; 188 189 val = RADEON_MAX_BL_LEVEL; 190 err = sysctl_handle_int(oidp, &val, 0, req); 191 return(err); 192 } 193 194 /* 195 * Read/write backlight level 196 */ 197 static int 198 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 199 { 200 struct radeon_encoder *encoder; 201 struct radeon_encoder_atom_dig *dig; 202 int err, val; 203 204 encoder = (struct radeon_encoder *)arg1; 205 dig = encoder->enc_priv; 206 val = dig->backlight_level; 207 208 err = sysctl_handle_int(oidp, &val, 0, req); 209 if (err != 0 || req->newptr == NULL) { 210 return(err); 211 } 212 if (dig->backlight_level != val && val >= 0 && 213 val <= RADEON_MAX_BL_LEVEL) { 214 atombios_set_backlight_level(encoder, val); 215 } 216 217 return(err); 218 } 219 220 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 221 struct drm_connector *drm_connector) 222 { 223 struct drm_device *dev = radeon_encoder->base.dev; 224 struct radeon_device *rdev = dev->dev_private; 225 #if 0 226 struct backlight_device *bd; 227 #endif 228 struct backlight_properties props; 229 struct radeon_backlight_privdata *pdata; 230 struct radeon_encoder_atom_dig *dig; 231 char bl_name[16]; 232 233 /* Mac laptops with multiple GPUs use the gmux driver for backlight 234 * so don't register a backlight device 235 */ 236 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 237 (rdev->pdev->device == 0x6741)) 238 return; 239 240 if (!radeon_encoder->enc_priv) 241 return; 242 243 if (!rdev->is_atom_bios) 244 return; 245 246 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 247 return; 248 249 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), M_DRM, 250 GFP_KERNEL); 251 if (!pdata) { 252 DRM_ERROR("Memory allocation failed\n"); 253 goto error; 254 } 255 256 memset(&props, 0, sizeof(props)); 257 props.max_brightness = RADEON_MAX_BL_LEVEL; 258 props.type = BACKLIGHT_RAW; 259 snprintf(bl_name, sizeof(bl_name), 260 "radeon_bl%d", dev->primary->index); 261 #if 0 262 bd = backlight_device_register(bl_name, drm_connector->kdev, 263 pdata, &radeon_atom_backlight_ops, &props); 264 if (IS_ERR(bd)) { 265 DRM_ERROR("Backlight registration failed\n"); 266 goto error; 267 } 268 #endif 269 270 pdata->encoder = radeon_encoder; 271 272 dig = radeon_encoder->enc_priv; 273 #if 0 274 dig->bl_dev = bd; 275 276 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 277 /* Set a reasonable default here if the level is 0 otherwise 278 * fbdev will attempt to turn the backlight on after console 279 * unblanking and it will try and restore 0 which turns the backlight 280 * off again. 281 */ 282 if (bd->props.brightness == 0) 283 bd->props.brightness = RADEON_MAX_BL_LEVEL; 284 bd->props.power = FB_BLANK_UNBLANK; 285 backlight_update_status(bd); 286 #endif 287 288 DRM_INFO("radeon atom DIG backlight initialized\n"); 289 rdev->mode_info.bl_encoder = radeon_encoder; 290 291 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 292 OID_AUTO, "backlight_max", 293 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 294 radeon_encoder, sizeof(int), 295 sysctl_backlight_max, 296 "I", "Max backlight level"); 297 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 298 OID_AUTO, "backlight_level", 299 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 300 radeon_encoder, sizeof(int), 301 sysctl_backlight_handler, 302 "I", "Backlight level"); 303 304 return; 305 306 error: 307 kfree(pdata); 308 return; 309 } 310 311 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 312 { 313 #if 0 314 struct drm_device *dev = radeon_encoder->base.dev; 315 struct radeon_device *rdev = dev->dev_private; 316 struct backlight_device *bd = NULL; 317 struct radeon_encoder_atom_dig *dig; 318 319 if (!radeon_encoder->enc_priv) 320 return; 321 322 if (!rdev->is_atom_bios) 323 return; 324 325 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 326 return; 327 328 dig = radeon_encoder->enc_priv; 329 bd = dig->bl_dev; 330 dig->bl_dev = NULL; 331 332 if (bd) { 333 struct radeon_legacy_backlight_privdata *pdata; 334 335 pdata = bl_get_data(bd); 336 backlight_device_unregister(bd); 337 kfree(pdata); 338 339 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 340 } 341 #endif 342 } 343 344 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 345 346 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 347 { 348 } 349 350 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 351 { 352 } 353 354 #endif 355 356 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 357 const struct drm_display_mode *mode, 358 struct drm_display_mode *adjusted_mode) 359 { 360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 361 struct drm_device *dev = encoder->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 364 /* set the active encoder to connector routing */ 365 radeon_encoder_set_active_device(encoder); 366 drm_mode_set_crtcinfo(adjusted_mode, 0); 367 368 /* hw bug */ 369 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 370 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 371 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 372 373 /* vertical FP must be at least 1 */ 374 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 375 adjusted_mode->crtc_vsync_start++; 376 377 /* get the native mode for scaling */ 378 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 379 radeon_panel_mode_fixup(encoder, adjusted_mode); 380 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 381 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 382 if (tv_dac) { 383 if (tv_dac->tv_std == TV_STD_NTSC || 384 tv_dac->tv_std == TV_STD_NTSC_J || 385 tv_dac->tv_std == TV_STD_PAL_M) 386 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 387 else 388 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 389 } 390 } else if (radeon_encoder->rmx_type != RMX_OFF) { 391 radeon_panel_mode_fixup(encoder, adjusted_mode); 392 } 393 394 if (ASIC_IS_DCE3(rdev) && 395 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 396 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 397 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 398 radeon_dp_set_link_config(connector, adjusted_mode); 399 } 400 401 return true; 402 } 403 404 static void 405 atombios_dac_setup(struct drm_encoder *encoder, int action) 406 { 407 struct drm_device *dev = encoder->dev; 408 struct radeon_device *rdev = dev->dev_private; 409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 410 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 411 int index = 0; 412 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 413 414 memset(&args, 0, sizeof(args)); 415 416 switch (radeon_encoder->encoder_id) { 417 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 418 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 419 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 420 break; 421 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 423 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 424 break; 425 } 426 427 args.ucAction = action; 428 429 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 430 args.ucDacStandard = ATOM_DAC1_PS2; 431 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 432 args.ucDacStandard = ATOM_DAC1_CV; 433 else { 434 switch (dac_info->tv_std) { 435 case TV_STD_PAL: 436 case TV_STD_PAL_M: 437 case TV_STD_SCART_PAL: 438 case TV_STD_SECAM: 439 case TV_STD_PAL_CN: 440 args.ucDacStandard = ATOM_DAC1_PAL; 441 break; 442 case TV_STD_NTSC: 443 case TV_STD_NTSC_J: 444 case TV_STD_PAL_60: 445 default: 446 args.ucDacStandard = ATOM_DAC1_NTSC; 447 break; 448 } 449 } 450 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 451 452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 453 454 } 455 456 static void 457 atombios_tv_setup(struct drm_encoder *encoder, int action) 458 { 459 struct drm_device *dev = encoder->dev; 460 struct radeon_device *rdev = dev->dev_private; 461 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 462 TV_ENCODER_CONTROL_PS_ALLOCATION args; 463 int index = 0; 464 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 465 466 memset(&args, 0, sizeof(args)); 467 468 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 469 470 args.sTVEncoder.ucAction = action; 471 472 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 473 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 474 else { 475 switch (dac_info->tv_std) { 476 case TV_STD_NTSC: 477 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 478 break; 479 case TV_STD_PAL: 480 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 481 break; 482 case TV_STD_PAL_M: 483 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 484 break; 485 case TV_STD_PAL_60: 486 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 487 break; 488 case TV_STD_NTSC_J: 489 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 490 break; 491 case TV_STD_SCART_PAL: 492 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 493 break; 494 case TV_STD_SECAM: 495 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 496 break; 497 case TV_STD_PAL_CN: 498 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 499 break; 500 default: 501 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 502 break; 503 } 504 } 505 506 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 507 508 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 509 510 } 511 512 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 513 { 514 int bpc = 8; 515 516 if (encoder->crtc) { 517 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 518 bpc = radeon_crtc->bpc; 519 } 520 521 switch (bpc) { 522 case 0: 523 return PANEL_BPC_UNDEFINE; 524 case 6: 525 return PANEL_6BIT_PER_COLOR; 526 case 8: 527 default: 528 return PANEL_8BIT_PER_COLOR; 529 case 10: 530 return PANEL_10BIT_PER_COLOR; 531 case 12: 532 return PANEL_12BIT_PER_COLOR; 533 case 16: 534 return PANEL_16BIT_PER_COLOR; 535 } 536 } 537 538 union dvo_encoder_control { 539 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 540 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 541 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 542 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 543 }; 544 545 void 546 atombios_dvo_setup(struct drm_encoder *encoder, int action) 547 { 548 struct drm_device *dev = encoder->dev; 549 struct radeon_device *rdev = dev->dev_private; 550 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 551 union dvo_encoder_control args; 552 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 553 uint8_t frev, crev; 554 555 memset(&args, 0, sizeof(args)); 556 557 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 558 return; 559 560 /* some R4xx chips have the wrong frev */ 561 if (rdev->family <= CHIP_RV410) 562 frev = 1; 563 564 switch (frev) { 565 case 1: 566 switch (crev) { 567 case 1: 568 /* R4xx, R5xx */ 569 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 570 571 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 572 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 573 574 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 575 break; 576 case 2: 577 /* RS600/690/740 */ 578 args.dvo.sDVOEncoder.ucAction = action; 579 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 580 /* DFP1, CRT1, TV1 depending on the type of port */ 581 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 582 583 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 584 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 585 break; 586 case 3: 587 /* R6xx */ 588 args.dvo_v3.ucAction = action; 589 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 590 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 591 break; 592 case 4: 593 /* DCE8 */ 594 args.dvo_v4.ucAction = action; 595 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 596 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 597 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 598 break; 599 default: 600 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 601 break; 602 } 603 break; 604 default: 605 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 606 break; 607 } 608 609 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 610 } 611 612 union lvds_encoder_control { 613 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 614 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 615 }; 616 617 void 618 atombios_digital_setup(struct drm_encoder *encoder, int action) 619 { 620 struct drm_device *dev = encoder->dev; 621 struct radeon_device *rdev = dev->dev_private; 622 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 623 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 624 union lvds_encoder_control args; 625 int index = 0; 626 int hdmi_detected = 0; 627 uint8_t frev, crev; 628 629 if (!dig) 630 return; 631 632 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 633 hdmi_detected = 1; 634 635 memset(&args, 0, sizeof(args)); 636 637 switch (radeon_encoder->encoder_id) { 638 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 639 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 640 break; 641 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 642 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 643 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 644 break; 645 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 646 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 647 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 648 else 649 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 650 break; 651 } 652 653 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 654 return; 655 656 switch (frev) { 657 case 1: 658 case 2: 659 switch (crev) { 660 case 1: 661 args.v1.ucMisc = 0; 662 args.v1.ucAction = action; 663 if (hdmi_detected) 664 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 665 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 666 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 667 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 668 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 669 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 670 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 671 } else { 672 if (dig->linkb) 673 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 674 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 675 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 676 /*if (pScrn->rgbBits == 8) */ 677 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 678 } 679 break; 680 case 2: 681 case 3: 682 args.v2.ucMisc = 0; 683 args.v2.ucAction = action; 684 if (crev == 3) { 685 if (dig->coherent_mode) 686 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 687 } 688 if (hdmi_detected) 689 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 690 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 691 args.v2.ucTruncate = 0; 692 args.v2.ucSpatial = 0; 693 args.v2.ucTemporal = 0; 694 args.v2.ucFRC = 0; 695 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 696 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 697 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 698 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 699 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 700 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 701 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 702 } 703 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 704 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 705 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 706 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 707 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 708 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 709 } 710 } else { 711 if (dig->linkb) 712 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 713 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 714 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 715 } 716 break; 717 default: 718 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 719 break; 720 } 721 break; 722 default: 723 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 724 break; 725 } 726 727 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 728 } 729 730 int 731 atombios_get_encoder_mode(struct drm_encoder *encoder) 732 { 733 struct drm_device *dev = encoder->dev; 734 struct radeon_device *rdev = dev->dev_private; 735 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 736 struct drm_connector *connector; 737 struct radeon_connector *radeon_connector; 738 struct radeon_connector_atom_dig *dig_connector; 739 struct radeon_encoder_atom_dig *dig_enc; 740 741 if (radeon_encoder_is_digital(encoder)) { 742 dig_enc = radeon_encoder->enc_priv; 743 if (dig_enc->active_mst_links) 744 return ATOM_ENCODER_MODE_DP_MST; 745 } 746 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 747 return ATOM_ENCODER_MODE_DP_MST; 748 /* dp bridges are always DP */ 749 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 750 return ATOM_ENCODER_MODE_DP; 751 752 /* DVO is always DVO */ 753 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 754 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 755 return ATOM_ENCODER_MODE_DVO; 756 757 connector = radeon_get_connector_for_encoder(encoder); 758 /* if we don't have an active device yet, just use one of 759 * the connectors tied to the encoder. 760 */ 761 if (!connector) 762 connector = radeon_get_connector_for_encoder_init(encoder); 763 radeon_connector = to_radeon_connector(connector); 764 765 switch (connector->connector_type) { 766 case DRM_MODE_CONNECTOR_DVII: 767 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 768 if (radeon_audio != 0) { 769 if (radeon_connector->use_digital && 770 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 771 return ATOM_ENCODER_MODE_HDMI; 772 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 773 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 774 return ATOM_ENCODER_MODE_HDMI; 775 else if (radeon_connector->use_digital) 776 return ATOM_ENCODER_MODE_DVI; 777 else 778 return ATOM_ENCODER_MODE_CRT; 779 } else if (radeon_connector->use_digital) { 780 return ATOM_ENCODER_MODE_DVI; 781 } else { 782 return ATOM_ENCODER_MODE_CRT; 783 } 784 break; 785 case DRM_MODE_CONNECTOR_DVID: 786 case DRM_MODE_CONNECTOR_HDMIA: 787 default: 788 if (radeon_audio != 0) { 789 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 790 return ATOM_ENCODER_MODE_HDMI; 791 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 792 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 793 return ATOM_ENCODER_MODE_HDMI; 794 else 795 return ATOM_ENCODER_MODE_DVI; 796 } else { 797 return ATOM_ENCODER_MODE_DVI; 798 } 799 break; 800 case DRM_MODE_CONNECTOR_LVDS: 801 return ATOM_ENCODER_MODE_LVDS; 802 break; 803 case DRM_MODE_CONNECTOR_DisplayPort: 804 dig_connector = radeon_connector->con_priv; 805 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 806 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 807 if (radeon_audio != 0 && 808 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 809 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 810 return ATOM_ENCODER_MODE_DP_AUDIO; 811 return ATOM_ENCODER_MODE_DP; 812 } else if (radeon_audio != 0) { 813 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 814 return ATOM_ENCODER_MODE_HDMI; 815 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 816 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 817 return ATOM_ENCODER_MODE_HDMI; 818 else 819 return ATOM_ENCODER_MODE_DVI; 820 } else { 821 return ATOM_ENCODER_MODE_DVI; 822 } 823 break; 824 case DRM_MODE_CONNECTOR_eDP: 825 if (radeon_audio != 0 && 826 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 827 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 828 return ATOM_ENCODER_MODE_DP_AUDIO; 829 return ATOM_ENCODER_MODE_DP; 830 case DRM_MODE_CONNECTOR_DVIA: 831 case DRM_MODE_CONNECTOR_VGA: 832 return ATOM_ENCODER_MODE_CRT; 833 break; 834 case DRM_MODE_CONNECTOR_Composite: 835 case DRM_MODE_CONNECTOR_SVIDEO: 836 case DRM_MODE_CONNECTOR_9PinDIN: 837 /* fix me */ 838 return ATOM_ENCODER_MODE_TV; 839 /*return ATOM_ENCODER_MODE_CV;*/ 840 break; 841 } 842 } 843 844 /* 845 * DIG Encoder/Transmitter Setup 846 * 847 * DCE 3.0/3.1 848 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 849 * Supports up to 3 digital outputs 850 * - 2 DIG encoder blocks. 851 * DIG1 can drive UNIPHY link A or link B 852 * DIG2 can drive UNIPHY link B or LVTMA 853 * 854 * DCE 3.2 855 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 856 * Supports up to 5 digital outputs 857 * - 2 DIG encoder blocks. 858 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 859 * 860 * DCE 4.0/5.0/6.0 861 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 862 * Supports up to 6 digital outputs 863 * - 6 DIG encoder blocks. 864 * - DIG to PHY mapping is hardcoded 865 * DIG1 drives UNIPHY0 link A, A+B 866 * DIG2 drives UNIPHY0 link B 867 * DIG3 drives UNIPHY1 link A, A+B 868 * DIG4 drives UNIPHY1 link B 869 * DIG5 drives UNIPHY2 link A, A+B 870 * DIG6 drives UNIPHY2 link B 871 * 872 * DCE 4.1 873 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 874 * Supports up to 6 digital outputs 875 * - 2 DIG encoder blocks. 876 * llano 877 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 878 * ontario 879 * DIG1 drives UNIPHY0/1/2 link A 880 * DIG2 drives UNIPHY0/1/2 link B 881 * 882 * Routing 883 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 884 * Examples: 885 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 886 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 887 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 888 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 889 */ 890 891 union dig_encoder_control { 892 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 893 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 894 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 895 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 896 }; 897 898 void 899 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 900 { 901 struct drm_device *dev = encoder->dev; 902 struct radeon_device *rdev = dev->dev_private; 903 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 904 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 905 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 906 union dig_encoder_control args; 907 int index = 0; 908 uint8_t frev, crev; 909 int dp_clock = 0; 910 int dp_lane_count = 0; 911 int hpd_id = RADEON_HPD_NONE; 912 913 if (connector) { 914 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 915 struct radeon_connector_atom_dig *dig_connector = 916 radeon_connector->con_priv; 917 918 dp_clock = dig_connector->dp_clock; 919 dp_lane_count = dig_connector->dp_lane_count; 920 hpd_id = radeon_connector->hpd.hpd; 921 } 922 923 /* no dig encoder assigned */ 924 if (dig->dig_encoder == -1) 925 return; 926 927 memset(&args, 0, sizeof(args)); 928 929 if (ASIC_IS_DCE4(rdev)) 930 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 931 else { 932 if (dig->dig_encoder) 933 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 934 else 935 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 936 } 937 938 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 939 return; 940 941 switch (frev) { 942 case 1: 943 switch (crev) { 944 case 1: 945 args.v1.ucAction = action; 946 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 947 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 948 args.v3.ucPanelMode = panel_mode; 949 else 950 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 951 952 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 953 args.v1.ucLaneNum = dp_lane_count; 954 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 955 args.v1.ucLaneNum = 8; 956 else 957 args.v1.ucLaneNum = 4; 958 959 switch (radeon_encoder->encoder_id) { 960 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 961 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 962 break; 963 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 964 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 965 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 966 break; 967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 968 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 969 break; 970 } 971 if (dig->linkb) 972 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 973 else 974 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 975 976 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 977 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 978 979 break; 980 case 2: 981 case 3: 982 args.v3.ucAction = action; 983 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 984 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 985 args.v3.ucPanelMode = panel_mode; 986 else 987 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 988 989 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 990 args.v3.ucLaneNum = dp_lane_count; 991 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 992 args.v3.ucLaneNum = 8; 993 else 994 args.v3.ucLaneNum = 4; 995 996 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 997 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 998 if (enc_override != -1) 999 args.v3.acConfig.ucDigSel = enc_override; 1000 else 1001 args.v3.acConfig.ucDigSel = dig->dig_encoder; 1002 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 1003 break; 1004 case 4: 1005 args.v4.ucAction = action; 1006 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1007 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 1008 args.v4.ucPanelMode = panel_mode; 1009 else 1010 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 1011 1012 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 1013 args.v4.ucLaneNum = dp_lane_count; 1014 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1015 args.v4.ucLaneNum = 8; 1016 else 1017 args.v4.ucLaneNum = 4; 1018 1019 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 1020 if (dp_clock == 540000) 1021 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 1022 else if (dp_clock == 324000) 1023 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 1024 else if (dp_clock == 270000) 1025 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 1026 else 1027 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 1028 } 1029 1030 if (enc_override != -1) 1031 args.v4.acConfig.ucDigSel = enc_override; 1032 else 1033 args.v4.acConfig.ucDigSel = dig->dig_encoder; 1034 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 1035 if (hpd_id == RADEON_HPD_NONE) 1036 args.v4.ucHPD_ID = 0; 1037 else 1038 args.v4.ucHPD_ID = hpd_id + 1; 1039 break; 1040 default: 1041 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1042 break; 1043 } 1044 break; 1045 default: 1046 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1047 break; 1048 } 1049 1050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1051 1052 } 1053 1054 void 1055 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 1056 { 1057 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1058 } 1059 1060 union dig_transmitter_control { 1061 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1062 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1063 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1064 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1065 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1066 }; 1067 1068 void 1069 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1070 { 1071 struct drm_device *dev = encoder->dev; 1072 struct radeon_device *rdev = dev->dev_private; 1073 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1074 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1075 struct drm_connector *connector; 1076 union dig_transmitter_control args; 1077 int index = 0; 1078 uint8_t frev, crev; 1079 bool is_dp = false; 1080 int pll_id = 0; 1081 int dp_clock = 0; 1082 int dp_lane_count = 0; 1083 int connector_object_id = 0; 1084 int igp_lane_info = 0; 1085 int dig_encoder = dig->dig_encoder; 1086 int hpd_id = RADEON_HPD_NONE; 1087 1088 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1089 connector = radeon_get_connector_for_encoder_init(encoder); 1090 /* just needed to avoid bailing in the encoder check. the encoder 1091 * isn't used for init 1092 */ 1093 dig_encoder = 0; 1094 } else 1095 connector = radeon_get_connector_for_encoder(encoder); 1096 1097 if (connector) { 1098 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1099 struct radeon_connector_atom_dig *dig_connector = 1100 radeon_connector->con_priv; 1101 1102 hpd_id = radeon_connector->hpd.hpd; 1103 dp_clock = dig_connector->dp_clock; 1104 dp_lane_count = dig_connector->dp_lane_count; 1105 connector_object_id = 1106 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1107 igp_lane_info = dig_connector->igp_lane_info; 1108 } 1109 1110 if (encoder->crtc) { 1111 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1112 pll_id = radeon_crtc->pll_id; 1113 } 1114 1115 /* no dig encoder assigned */ 1116 if (dig_encoder == -1) 1117 return; 1118 1119 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1120 is_dp = true; 1121 1122 memset(&args, 0, sizeof(args)); 1123 1124 switch (radeon_encoder->encoder_id) { 1125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1126 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1127 break; 1128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1132 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1133 break; 1134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1135 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1136 break; 1137 } 1138 1139 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1140 return; 1141 1142 switch (frev) { 1143 case 1: 1144 switch (crev) { 1145 case 1: 1146 args.v1.ucAction = action; 1147 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1148 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1149 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1150 args.v1.asMode.ucLaneSel = lane_num; 1151 args.v1.asMode.ucLaneSet = lane_set; 1152 } else { 1153 if (is_dp) 1154 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1155 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1156 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1157 else 1158 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1159 } 1160 1161 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1162 1163 if (dig_encoder) 1164 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1165 else 1166 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1167 1168 if ((rdev->flags & RADEON_IS_IGP) && 1169 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1170 if (is_dp || 1171 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1172 if (igp_lane_info & 0x1) 1173 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1174 else if (igp_lane_info & 0x2) 1175 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1176 else if (igp_lane_info & 0x4) 1177 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1178 else if (igp_lane_info & 0x8) 1179 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1180 } else { 1181 if (igp_lane_info & 0x3) 1182 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1183 else if (igp_lane_info & 0xc) 1184 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1185 } 1186 } 1187 1188 if (dig->linkb) 1189 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1190 else 1191 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1192 1193 if (is_dp) 1194 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1195 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1196 if (dig->coherent_mode) 1197 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1198 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1199 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1200 } 1201 break; 1202 case 2: 1203 args.v2.ucAction = action; 1204 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1205 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1206 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1207 args.v2.asMode.ucLaneSel = lane_num; 1208 args.v2.asMode.ucLaneSet = lane_set; 1209 } else { 1210 if (is_dp) 1211 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1212 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1213 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1214 else 1215 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1216 } 1217 1218 args.v2.acConfig.ucEncoderSel = dig_encoder; 1219 if (dig->linkb) 1220 args.v2.acConfig.ucLinkSel = 1; 1221 1222 switch (radeon_encoder->encoder_id) { 1223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1224 args.v2.acConfig.ucTransmitterSel = 0; 1225 break; 1226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1227 args.v2.acConfig.ucTransmitterSel = 1; 1228 break; 1229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1230 args.v2.acConfig.ucTransmitterSel = 2; 1231 break; 1232 } 1233 1234 if (is_dp) { 1235 args.v2.acConfig.fCoherentMode = 1; 1236 args.v2.acConfig.fDPConnector = 1; 1237 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1238 if (dig->coherent_mode) 1239 args.v2.acConfig.fCoherentMode = 1; 1240 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1241 args.v2.acConfig.fDualLinkConnector = 1; 1242 } 1243 break; 1244 case 3: 1245 args.v3.ucAction = action; 1246 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1247 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1248 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1249 args.v3.asMode.ucLaneSel = lane_num; 1250 args.v3.asMode.ucLaneSet = lane_set; 1251 } else { 1252 if (is_dp) 1253 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1254 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1255 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1256 else 1257 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1258 } 1259 1260 if (is_dp) 1261 args.v3.ucLaneNum = dp_lane_count; 1262 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1263 args.v3.ucLaneNum = 8; 1264 else 1265 args.v3.ucLaneNum = 4; 1266 1267 if (dig->linkb) 1268 args.v3.acConfig.ucLinkSel = 1; 1269 if (dig_encoder & 1) 1270 args.v3.acConfig.ucEncoderSel = 1; 1271 1272 /* Select the PLL for the PHY 1273 * DP PHY should be clocked from external src if there is 1274 * one. 1275 */ 1276 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1277 if (is_dp && rdev->clock.dp_extclk) 1278 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1279 else 1280 args.v3.acConfig.ucRefClkSource = pll_id; 1281 1282 switch (radeon_encoder->encoder_id) { 1283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1284 args.v3.acConfig.ucTransmitterSel = 0; 1285 break; 1286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1287 args.v3.acConfig.ucTransmitterSel = 1; 1288 break; 1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1290 args.v3.acConfig.ucTransmitterSel = 2; 1291 break; 1292 } 1293 1294 if (is_dp) 1295 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1296 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1297 if (dig->coherent_mode) 1298 args.v3.acConfig.fCoherentMode = 1; 1299 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1300 args.v3.acConfig.fDualLinkConnector = 1; 1301 } 1302 break; 1303 case 4: 1304 args.v4.ucAction = action; 1305 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1306 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1307 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1308 args.v4.asMode.ucLaneSel = lane_num; 1309 args.v4.asMode.ucLaneSet = lane_set; 1310 } else { 1311 if (is_dp) 1312 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1313 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1314 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1315 else 1316 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1317 } 1318 1319 if (is_dp) 1320 args.v4.ucLaneNum = dp_lane_count; 1321 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1322 args.v4.ucLaneNum = 8; 1323 else 1324 args.v4.ucLaneNum = 4; 1325 1326 if (dig->linkb) 1327 args.v4.acConfig.ucLinkSel = 1; 1328 if (dig_encoder & 1) 1329 args.v4.acConfig.ucEncoderSel = 1; 1330 1331 /* Select the PLL for the PHY 1332 * DP PHY should be clocked from external src if there is 1333 * one. 1334 */ 1335 /* On DCE5 DCPLL usually generates the DP ref clock */ 1336 if (is_dp) { 1337 if (rdev->clock.dp_extclk) 1338 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1339 else 1340 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1341 } else 1342 args.v4.acConfig.ucRefClkSource = pll_id; 1343 1344 switch (radeon_encoder->encoder_id) { 1345 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1346 args.v4.acConfig.ucTransmitterSel = 0; 1347 break; 1348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1349 args.v4.acConfig.ucTransmitterSel = 1; 1350 break; 1351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1352 args.v4.acConfig.ucTransmitterSel = 2; 1353 break; 1354 } 1355 1356 if (is_dp) 1357 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1358 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1359 if (dig->coherent_mode) 1360 args.v4.acConfig.fCoherentMode = 1; 1361 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1362 args.v4.acConfig.fDualLinkConnector = 1; 1363 } 1364 break; 1365 case 5: 1366 args.v5.ucAction = action; 1367 if (is_dp) 1368 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1369 else 1370 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1371 1372 switch (radeon_encoder->encoder_id) { 1373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1374 if (dig->linkb) 1375 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1376 else 1377 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1378 break; 1379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1380 if (dig->linkb) 1381 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1382 else 1383 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1384 break; 1385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1386 if (dig->linkb) 1387 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1388 else 1389 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1390 break; 1391 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1392 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1393 break; 1394 } 1395 if (is_dp) 1396 args.v5.ucLaneNum = dp_lane_count; 1397 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1398 args.v5.ucLaneNum = 8; 1399 else 1400 args.v5.ucLaneNum = 4; 1401 args.v5.ucConnObjId = connector_object_id; 1402 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1403 1404 if (is_dp && rdev->clock.dp_extclk) 1405 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1406 else 1407 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1408 1409 if (is_dp) 1410 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1411 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1412 if (dig->coherent_mode) 1413 args.v5.asConfig.ucCoherentMode = 1; 1414 } 1415 if (hpd_id == RADEON_HPD_NONE) 1416 args.v5.asConfig.ucHPDSel = 0; 1417 else 1418 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1419 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1420 args.v5.ucDPLaneSet = lane_set; 1421 break; 1422 default: 1423 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1424 break; 1425 } 1426 break; 1427 default: 1428 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1429 break; 1430 } 1431 1432 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1433 } 1434 1435 void 1436 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1437 { 1438 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1439 } 1440 1441 bool 1442 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1443 { 1444 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1445 struct drm_device *dev = radeon_connector->base.dev; 1446 struct radeon_device *rdev = dev->dev_private; 1447 union dig_transmitter_control args; 1448 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1449 uint8_t frev, crev; 1450 1451 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1452 goto done; 1453 1454 if (!ASIC_IS_DCE4(rdev)) 1455 goto done; 1456 1457 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1458 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1459 goto done; 1460 1461 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1462 goto done; 1463 1464 memset(&args, 0, sizeof(args)); 1465 1466 args.v1.ucAction = action; 1467 1468 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1469 1470 /* wait for the panel to power up */ 1471 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1472 int i; 1473 1474 for (i = 0; i < 300; i++) { 1475 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1476 return true; 1477 mdelay(1); 1478 } 1479 return false; 1480 } 1481 done: 1482 return true; 1483 } 1484 1485 union external_encoder_control { 1486 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1487 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1488 }; 1489 1490 static void 1491 atombios_external_encoder_setup(struct drm_encoder *encoder, 1492 struct drm_encoder *ext_encoder, 1493 int action) 1494 { 1495 struct drm_device *dev = encoder->dev; 1496 struct radeon_device *rdev = dev->dev_private; 1497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1498 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1499 union external_encoder_control args; 1500 struct drm_connector *connector; 1501 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1502 u8 frev, crev; 1503 int dp_clock = 0; 1504 int dp_lane_count = 0; 1505 int connector_object_id = 0; 1506 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1507 1508 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1509 connector = radeon_get_connector_for_encoder_init(encoder); 1510 else 1511 connector = radeon_get_connector_for_encoder(encoder); 1512 1513 if (connector) { 1514 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1515 struct radeon_connector_atom_dig *dig_connector = 1516 radeon_connector->con_priv; 1517 1518 dp_clock = dig_connector->dp_clock; 1519 dp_lane_count = dig_connector->dp_lane_count; 1520 connector_object_id = 1521 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1522 } 1523 1524 memset(&args, 0, sizeof(args)); 1525 1526 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1527 return; 1528 1529 switch (frev) { 1530 case 1: 1531 /* no params on frev 1 */ 1532 break; 1533 case 2: 1534 switch (crev) { 1535 case 1: 1536 case 2: 1537 args.v1.sDigEncoder.ucAction = action; 1538 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1539 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1540 1541 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1542 if (dp_clock == 270000) 1543 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1544 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1545 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1546 args.v1.sDigEncoder.ucLaneNum = 8; 1547 else 1548 args.v1.sDigEncoder.ucLaneNum = 4; 1549 break; 1550 case 3: 1551 args.v3.sExtEncoder.ucAction = action; 1552 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1553 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1554 else 1555 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1556 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1557 1558 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1559 if (dp_clock == 270000) 1560 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1561 else if (dp_clock == 540000) 1562 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1563 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1564 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1565 args.v3.sExtEncoder.ucLaneNum = 8; 1566 else 1567 args.v3.sExtEncoder.ucLaneNum = 4; 1568 switch (ext_enum) { 1569 case GRAPH_OBJECT_ENUM_ID1: 1570 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1571 break; 1572 case GRAPH_OBJECT_ENUM_ID2: 1573 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1574 break; 1575 case GRAPH_OBJECT_ENUM_ID3: 1576 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1577 break; 1578 } 1579 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1580 break; 1581 default: 1582 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1583 return; 1584 } 1585 break; 1586 default: 1587 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1588 return; 1589 } 1590 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1591 } 1592 1593 static void 1594 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1595 { 1596 struct drm_device *dev = encoder->dev; 1597 struct radeon_device *rdev = dev->dev_private; 1598 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1599 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1600 ENABLE_YUV_PS_ALLOCATION args; 1601 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1602 uint32_t temp, reg; 1603 1604 memset(&args, 0, sizeof(args)); 1605 1606 if (rdev->family >= CHIP_R600) 1607 reg = R600_BIOS_3_SCRATCH; 1608 else 1609 reg = RADEON_BIOS_3_SCRATCH; 1610 1611 /* XXX: fix up scratch reg handling */ 1612 temp = RREG32(reg); 1613 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1614 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1615 (radeon_crtc->crtc_id << 18))); 1616 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1617 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1618 else 1619 WREG32(reg, 0); 1620 1621 if (enable) 1622 args.ucEnable = ATOM_ENABLE; 1623 args.ucCRTC = radeon_crtc->crtc_id; 1624 1625 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1626 1627 WREG32(reg, temp); 1628 } 1629 1630 static void 1631 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1632 { 1633 struct drm_device *dev = encoder->dev; 1634 struct radeon_device *rdev = dev->dev_private; 1635 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1636 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1637 int index = 0; 1638 1639 memset(&args, 0, sizeof(args)); 1640 1641 switch (radeon_encoder->encoder_id) { 1642 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1644 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1645 break; 1646 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1647 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1649 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1650 break; 1651 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1652 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1653 break; 1654 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1655 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1656 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1657 else 1658 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1659 break; 1660 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1662 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1663 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1664 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1665 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1666 else 1667 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1668 break; 1669 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1670 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1671 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1672 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1673 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1674 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1675 else 1676 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1677 break; 1678 default: 1679 return; 1680 } 1681 1682 switch (mode) { 1683 case DRM_MODE_DPMS_ON: 1684 args.ucAction = ATOM_ENABLE; 1685 /* workaround for DVOOutputControl on some RS690 systems */ 1686 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1687 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1688 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1689 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1690 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1691 } else 1692 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1693 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1694 if (rdev->mode_info.bl_encoder) { 1695 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1696 1697 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1698 } else { 1699 args.ucAction = ATOM_LCD_BLON; 1700 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1701 } 1702 } 1703 break; 1704 case DRM_MODE_DPMS_STANDBY: 1705 case DRM_MODE_DPMS_SUSPEND: 1706 case DRM_MODE_DPMS_OFF: 1707 args.ucAction = ATOM_DISABLE; 1708 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1709 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1710 args.ucAction = ATOM_LCD_BLOFF; 1711 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1712 } 1713 break; 1714 } 1715 } 1716 1717 static void 1718 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1719 { 1720 struct drm_device *dev = encoder->dev; 1721 struct radeon_device *rdev = dev->dev_private; 1722 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1723 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1724 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1725 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1726 struct radeon_connector *radeon_connector = NULL; 1727 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1728 bool travis_quirk = false; 1729 1730 if (connector) { 1731 radeon_connector = to_radeon_connector(connector); 1732 radeon_dig_connector = radeon_connector->con_priv; 1733 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1734 ENCODER_OBJECT_ID_TRAVIS) && 1735 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1736 !ASIC_IS_DCE5(rdev)) 1737 travis_quirk = true; 1738 } 1739 1740 switch (mode) { 1741 case DRM_MODE_DPMS_ON: 1742 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1743 if (!connector) 1744 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1745 else 1746 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1747 1748 /* setup and enable the encoder */ 1749 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1750 atombios_dig_encoder_setup(encoder, 1751 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1752 dig->panel_mode); 1753 if (ext_encoder) { 1754 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1755 atombios_external_encoder_setup(encoder, ext_encoder, 1756 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1757 } 1758 } else if (ASIC_IS_DCE4(rdev)) { 1759 /* setup and enable the encoder */ 1760 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1761 } else { 1762 /* setup and enable the encoder and transmitter */ 1763 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1764 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1765 } 1766 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1767 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1768 atombios_set_edp_panel_power(connector, 1769 ATOM_TRANSMITTER_ACTION_POWER_ON); 1770 radeon_dig_connector->edp_on = true; 1771 } 1772 } 1773 /* enable the transmitter */ 1774 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1775 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1776 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1777 radeon_dp_link_train(encoder, connector); 1778 if (ASIC_IS_DCE4(rdev)) 1779 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1780 } 1781 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1782 if (rdev->mode_info.bl_encoder) 1783 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1784 else 1785 atombios_dig_transmitter_setup(encoder, 1786 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1787 } 1788 if (ext_encoder) 1789 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1790 break; 1791 case DRM_MODE_DPMS_STANDBY: 1792 case DRM_MODE_DPMS_SUSPEND: 1793 case DRM_MODE_DPMS_OFF: 1794 1795 /* don't power off encoders with active MST links */ 1796 if (dig->active_mst_links) 1797 return; 1798 1799 if (ASIC_IS_DCE4(rdev)) { 1800 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1801 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1802 } 1803 if (ext_encoder) 1804 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1805 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1806 atombios_dig_transmitter_setup(encoder, 1807 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1808 1809 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1810 connector && !travis_quirk) 1811 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1812 if (ASIC_IS_DCE4(rdev)) { 1813 /* disable the transmitter */ 1814 atombios_dig_transmitter_setup(encoder, 1815 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1816 } else { 1817 /* disable the encoder and transmitter */ 1818 atombios_dig_transmitter_setup(encoder, 1819 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1820 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1821 } 1822 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1823 if (travis_quirk) 1824 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1825 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1826 atombios_set_edp_panel_power(connector, 1827 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1828 radeon_dig_connector->edp_on = false; 1829 } 1830 } 1831 break; 1832 } 1833 } 1834 1835 static void 1836 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1837 { 1838 struct drm_device *dev = encoder->dev; 1839 struct radeon_device *rdev = dev->dev_private; 1840 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1841 int encoder_mode = atombios_get_encoder_mode(encoder); 1842 1843 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1844 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1845 radeon_encoder->active_device); 1846 1847 if ((radeon_audio != 0) && 1848 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1849 ENCODER_MODE_IS_DP(encoder_mode))) 1850 radeon_audio_dpms(encoder, mode); 1851 1852 switch (radeon_encoder->encoder_id) { 1853 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1855 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1856 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1857 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1858 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1859 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1860 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1861 radeon_atom_encoder_dpms_avivo(encoder, mode); 1862 break; 1863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1864 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1868 radeon_atom_encoder_dpms_dig(encoder, mode); 1869 break; 1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1871 if (ASIC_IS_DCE5(rdev)) { 1872 switch (mode) { 1873 case DRM_MODE_DPMS_ON: 1874 atombios_dvo_setup(encoder, ATOM_ENABLE); 1875 break; 1876 case DRM_MODE_DPMS_STANDBY: 1877 case DRM_MODE_DPMS_SUSPEND: 1878 case DRM_MODE_DPMS_OFF: 1879 atombios_dvo_setup(encoder, ATOM_DISABLE); 1880 break; 1881 } 1882 } else if (ASIC_IS_DCE3(rdev)) 1883 radeon_atom_encoder_dpms_dig(encoder, mode); 1884 else 1885 radeon_atom_encoder_dpms_avivo(encoder, mode); 1886 break; 1887 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1889 if (ASIC_IS_DCE5(rdev)) { 1890 switch (mode) { 1891 case DRM_MODE_DPMS_ON: 1892 atombios_dac_setup(encoder, ATOM_ENABLE); 1893 break; 1894 case DRM_MODE_DPMS_STANDBY: 1895 case DRM_MODE_DPMS_SUSPEND: 1896 case DRM_MODE_DPMS_OFF: 1897 atombios_dac_setup(encoder, ATOM_DISABLE); 1898 break; 1899 } 1900 } else 1901 radeon_atom_encoder_dpms_avivo(encoder, mode); 1902 break; 1903 default: 1904 return; 1905 } 1906 1907 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1908 1909 } 1910 1911 union crtc_source_param { 1912 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1913 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1914 }; 1915 1916 static void 1917 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1918 { 1919 struct drm_device *dev = encoder->dev; 1920 struct radeon_device *rdev = dev->dev_private; 1921 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1922 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1923 union crtc_source_param args; 1924 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1925 uint8_t frev, crev; 1926 struct radeon_encoder_atom_dig *dig; 1927 1928 memset(&args, 0, sizeof(args)); 1929 1930 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1931 return; 1932 1933 switch (frev) { 1934 case 1: 1935 switch (crev) { 1936 case 1: 1937 default: 1938 if (ASIC_IS_AVIVO(rdev)) 1939 args.v1.ucCRTC = radeon_crtc->crtc_id; 1940 else { 1941 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1942 args.v1.ucCRTC = radeon_crtc->crtc_id; 1943 } else { 1944 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1945 } 1946 } 1947 switch (radeon_encoder->encoder_id) { 1948 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1949 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1950 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1951 break; 1952 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1953 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1954 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1955 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1956 else 1957 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1958 break; 1959 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1960 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1961 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1962 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1963 break; 1964 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1965 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1966 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1967 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1968 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1969 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1970 else 1971 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1972 break; 1973 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1974 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1975 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1976 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1977 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1978 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1979 else 1980 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1981 break; 1982 } 1983 break; 1984 case 2: 1985 args.v2.ucCRTC = radeon_crtc->crtc_id; 1986 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1987 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1988 1989 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1990 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1991 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1992 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1993 else 1994 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1995 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1996 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1997 } else { 1998 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1999 } 2000 switch (radeon_encoder->encoder_id) { 2001 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2002 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2003 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2005 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2006 dig = radeon_encoder->enc_priv; 2007 switch (dig->dig_encoder) { 2008 case 0: 2009 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2010 break; 2011 case 1: 2012 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2013 break; 2014 case 2: 2015 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2016 break; 2017 case 3: 2018 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2019 break; 2020 case 4: 2021 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2022 break; 2023 case 5: 2024 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2025 break; 2026 case 6: 2027 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2028 break; 2029 } 2030 break; 2031 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2032 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 2033 break; 2034 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2035 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2036 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2037 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2038 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2039 else 2040 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 2041 break; 2042 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2043 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 2044 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2045 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 2046 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 2047 else 2048 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 2049 break; 2050 } 2051 break; 2052 } 2053 break; 2054 default: 2055 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2056 return; 2057 } 2058 2059 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2060 2061 /* update scratch regs with new routing */ 2062 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2063 } 2064 2065 void 2066 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2067 { 2068 struct drm_device *dev = encoder->dev; 2069 struct radeon_device *rdev = dev->dev_private; 2070 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2071 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2072 uint8_t frev, crev; 2073 union crtc_source_param args; 2074 2075 memset(&args, 0, sizeof(args)); 2076 2077 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2078 return; 2079 2080 if (frev != 1 && crev != 2) 2081 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2082 2083 args.v2.ucCRTC = radeon_crtc->crtc_id; 2084 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2085 2086 switch (fe) { 2087 case 0: 2088 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2089 break; 2090 case 1: 2091 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2092 break; 2093 case 2: 2094 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2095 break; 2096 case 3: 2097 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2098 break; 2099 case 4: 2100 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2101 break; 2102 case 5: 2103 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2104 break; 2105 case 6: 2106 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2107 break; 2108 } 2109 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2110 } 2111 2112 static void 2113 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2114 struct drm_display_mode *mode) 2115 { 2116 struct drm_device *dev = encoder->dev; 2117 struct radeon_device *rdev = dev->dev_private; 2118 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2119 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2120 2121 /* Funky macbooks */ 2122 if ((dev->pdev->device == 0x71C5) && 2123 (dev->pdev->subsystem_vendor == 0x106b) && 2124 (dev->pdev->subsystem_device == 0x0080)) { 2125 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2126 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2127 2128 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2129 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2130 2131 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2132 } 2133 } 2134 2135 /* set scaler clears this on some chips */ 2136 if (ASIC_IS_AVIVO(rdev) && 2137 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2138 if (ASIC_IS_DCE8(rdev)) { 2139 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2140 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2141 CIK_INTERLEAVE_EN); 2142 else 2143 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2144 } else if (ASIC_IS_DCE4(rdev)) { 2145 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2146 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2147 EVERGREEN_INTERLEAVE_EN); 2148 else 2149 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2150 } else { 2151 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2152 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2153 AVIVO_D1MODE_INTERLEAVE_EN); 2154 else 2155 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2156 } 2157 } 2158 } 2159 2160 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2161 { 2162 if (enc_idx < 0) 2163 return; 2164 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2165 } 2166 2167 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2168 { 2169 struct drm_device *dev = encoder->dev; 2170 struct radeon_device *rdev = dev->dev_private; 2171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2172 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2173 struct drm_encoder *test_encoder; 2174 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2175 uint32_t dig_enc_in_use = 0; 2176 int enc_idx = -1; 2177 2178 if (fe_idx >= 0) { 2179 enc_idx = fe_idx; 2180 goto assigned; 2181 } 2182 if (ASIC_IS_DCE6(rdev)) { 2183 /* DCE6 */ 2184 switch (radeon_encoder->encoder_id) { 2185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2186 if (dig->linkb) 2187 enc_idx = 1; 2188 else 2189 enc_idx = 0; 2190 break; 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2192 if (dig->linkb) 2193 enc_idx = 3; 2194 else 2195 enc_idx = 2; 2196 break; 2197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2198 if (dig->linkb) 2199 enc_idx = 5; 2200 else 2201 enc_idx = 4; 2202 break; 2203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2204 enc_idx = 6; 2205 break; 2206 } 2207 goto assigned; 2208 } else if (ASIC_IS_DCE4(rdev)) { 2209 /* DCE4/5 */ 2210 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2211 /* ontario follows DCE4 */ 2212 if (rdev->family == CHIP_PALM) { 2213 if (dig->linkb) 2214 enc_idx = 1; 2215 else 2216 enc_idx = 0; 2217 } else 2218 /* llano follows DCE3.2 */ 2219 enc_idx = radeon_crtc->crtc_id; 2220 } else { 2221 switch (radeon_encoder->encoder_id) { 2222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2223 if (dig->linkb) 2224 enc_idx = 1; 2225 else 2226 enc_idx = 0; 2227 break; 2228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2229 if (dig->linkb) 2230 enc_idx = 3; 2231 else 2232 enc_idx = 2; 2233 break; 2234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2235 if (dig->linkb) 2236 enc_idx = 5; 2237 else 2238 enc_idx = 4; 2239 break; 2240 } 2241 } 2242 goto assigned; 2243 } 2244 2245 /* 2246 * On DCE32 any encoder can drive any block so usually just use crtc id, 2247 * but Apple thinks different at least on iMac10,1, so there use linkb, 2248 * otherwise the internal eDP panel will stay dark. 2249 */ 2250 if (ASIC_IS_DCE32(rdev)) { 2251 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) 2252 enc_idx = (dig->linkb) ? 1 : 0; 2253 else 2254 enc_idx = radeon_crtc->crtc_id; 2255 2256 goto assigned; 2257 } 2258 2259 /* on DCE3 - LVTMA can only be driven by DIGB */ 2260 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2261 struct radeon_encoder *radeon_test_encoder; 2262 2263 if (encoder == test_encoder) 2264 continue; 2265 2266 if (!radeon_encoder_is_digital(test_encoder)) 2267 continue; 2268 2269 radeon_test_encoder = to_radeon_encoder(test_encoder); 2270 dig = radeon_test_encoder->enc_priv; 2271 2272 if (dig->dig_encoder >= 0) 2273 dig_enc_in_use |= (1 << dig->dig_encoder); 2274 } 2275 2276 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2277 if (dig_enc_in_use & 0x2) 2278 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2279 return 1; 2280 } 2281 if (!(dig_enc_in_use & 1)) 2282 return 0; 2283 return 1; 2284 2285 assigned: 2286 if (enc_idx == -1) { 2287 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2288 return 0; 2289 } 2290 if (rdev->mode_info.active_encoders & (1 << enc_idx)) { 2291 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2292 } 2293 rdev->mode_info.active_encoders |= (1 << enc_idx); 2294 return enc_idx; 2295 } 2296 2297 /* This only needs to be called once at startup */ 2298 void 2299 radeon_atom_encoder_init(struct radeon_device *rdev) 2300 { 2301 struct drm_device *dev = rdev->ddev; 2302 struct drm_encoder *encoder; 2303 2304 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2305 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2306 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2307 2308 switch (radeon_encoder->encoder_id) { 2309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2312 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2314 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2315 break; 2316 default: 2317 break; 2318 } 2319 2320 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2321 atombios_external_encoder_setup(encoder, ext_encoder, 2322 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2323 } 2324 } 2325 2326 static void 2327 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2328 struct drm_display_mode *mode, 2329 struct drm_display_mode *adjusted_mode) 2330 { 2331 struct drm_device *dev = encoder->dev; 2332 struct radeon_device *rdev = dev->dev_private; 2333 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2334 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2335 int encoder_mode; 2336 2337 radeon_encoder->pixel_clock = adjusted_mode->clock; 2338 2339 /* need to call this here rather than in prepare() since we need some crtc info */ 2340 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2341 2342 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2343 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2344 atombios_yuv_setup(encoder, true); 2345 else 2346 atombios_yuv_setup(encoder, false); 2347 } 2348 2349 switch (radeon_encoder->encoder_id) { 2350 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2351 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2352 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2353 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2354 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2355 break; 2356 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2357 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2358 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2359 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2361 /* handled in dpms */ 2362 break; 2363 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2364 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2365 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2366 atombios_dvo_setup(encoder, ATOM_ENABLE); 2367 break; 2368 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2370 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2372 atombios_dac_setup(encoder, ATOM_ENABLE); 2373 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2374 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2375 atombios_tv_setup(encoder, ATOM_ENABLE); 2376 else 2377 atombios_tv_setup(encoder, ATOM_DISABLE); 2378 } 2379 break; 2380 } 2381 2382 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2383 2384 encoder_mode = atombios_get_encoder_mode(encoder); 2385 if (connector && (radeon_audio != 0) && 2386 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2387 ENCODER_MODE_IS_DP(encoder_mode))) 2388 radeon_audio_mode_set(encoder, adjusted_mode); 2389 } 2390 2391 static bool 2392 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2393 { 2394 struct drm_device *dev = encoder->dev; 2395 struct radeon_device *rdev = dev->dev_private; 2396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2397 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2398 2399 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2400 ATOM_DEVICE_CV_SUPPORT | 2401 ATOM_DEVICE_CRT_SUPPORT)) { 2402 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2403 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2404 uint8_t frev, crev; 2405 2406 memset(&args, 0, sizeof(args)); 2407 2408 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2409 return false; 2410 2411 args.sDacload.ucMisc = 0; 2412 2413 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2414 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2415 args.sDacload.ucDacType = ATOM_DAC_A; 2416 else 2417 args.sDacload.ucDacType = ATOM_DAC_B; 2418 2419 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2420 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2421 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2422 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2423 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2424 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2425 if (crev >= 3) 2426 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2427 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2428 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2429 if (crev >= 3) 2430 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2431 } 2432 2433 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2434 2435 return true; 2436 } else 2437 return false; 2438 } 2439 2440 static enum drm_connector_status 2441 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2442 { 2443 struct drm_device *dev = encoder->dev; 2444 struct radeon_device *rdev = dev->dev_private; 2445 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2446 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2447 uint32_t bios_0_scratch; 2448 2449 if (!atombios_dac_load_detect(encoder, connector)) { 2450 DRM_DEBUG_KMS("detect returned false \n"); 2451 return connector_status_unknown; 2452 } 2453 2454 if (rdev->family >= CHIP_R600) 2455 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2456 else 2457 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2458 2459 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2460 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2461 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2462 return connector_status_connected; 2463 } 2464 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2465 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2466 return connector_status_connected; 2467 } 2468 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2469 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2470 return connector_status_connected; 2471 } 2472 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2473 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2474 return connector_status_connected; /* CTV */ 2475 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2476 return connector_status_connected; /* STV */ 2477 } 2478 return connector_status_disconnected; 2479 } 2480 2481 static enum drm_connector_status 2482 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2483 { 2484 struct drm_device *dev = encoder->dev; 2485 struct radeon_device *rdev = dev->dev_private; 2486 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2487 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2488 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2489 u32 bios_0_scratch; 2490 2491 if (!ASIC_IS_DCE4(rdev)) 2492 return connector_status_unknown; 2493 2494 if (!ext_encoder) 2495 return connector_status_unknown; 2496 2497 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2498 return connector_status_unknown; 2499 2500 /* load detect on the dp bridge */ 2501 atombios_external_encoder_setup(encoder, ext_encoder, 2502 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2503 2504 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2505 2506 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2507 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2508 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2509 return connector_status_connected; 2510 } 2511 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2512 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2513 return connector_status_connected; 2514 } 2515 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2516 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2517 return connector_status_connected; 2518 } 2519 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2520 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2521 return connector_status_connected; /* CTV */ 2522 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2523 return connector_status_connected; /* STV */ 2524 } 2525 return connector_status_disconnected; 2526 } 2527 2528 void 2529 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2530 { 2531 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2532 2533 if (ext_encoder) 2534 /* ddc_setup on the dp bridge */ 2535 atombios_external_encoder_setup(encoder, ext_encoder, 2536 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2537 2538 } 2539 2540 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2541 { 2542 struct radeon_device *rdev = encoder->dev->dev_private; 2543 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2544 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2545 2546 if ((radeon_encoder->active_device & 2547 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2548 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2549 ENCODER_OBJECT_ID_NONE)) { 2550 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2551 if (dig) { 2552 if (dig->dig_encoder >= 0) 2553 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2554 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2555 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2556 if (rdev->family >= CHIP_R600) 2557 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2558 else 2559 /* RS600/690/740 have only 1 afmt block */ 2560 dig->afmt = rdev->mode_info.afmt[0]; 2561 } 2562 } 2563 } 2564 2565 radeon_atom_output_lock(encoder, true); 2566 2567 if (connector) { 2568 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2569 2570 /* select the clock/data port if it uses a router */ 2571 if (radeon_connector->router.cd_valid) 2572 radeon_router_select_cd_port(radeon_connector); 2573 2574 /* turn eDP panel on for mode set */ 2575 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2576 atombios_set_edp_panel_power(connector, 2577 ATOM_TRANSMITTER_ACTION_POWER_ON); 2578 } 2579 2580 /* this is needed for the pll/ss setup to work correctly in some cases */ 2581 atombios_set_encoder_crtc_source(encoder); 2582 /* set up the FMT blocks */ 2583 if (ASIC_IS_DCE8(rdev)) 2584 dce8_program_fmt(encoder); 2585 else if (ASIC_IS_DCE4(rdev)) 2586 dce4_program_fmt(encoder); 2587 else if (ASIC_IS_DCE3(rdev)) 2588 dce3_program_fmt(encoder); 2589 else if (ASIC_IS_AVIVO(rdev)) 2590 avivo_program_fmt(encoder); 2591 } 2592 2593 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2594 { 2595 /* need to call this here as we need the crtc set up */ 2596 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2597 radeon_atom_output_lock(encoder, false); 2598 } 2599 2600 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2601 { 2602 struct drm_device *dev = encoder->dev; 2603 struct radeon_device *rdev = dev->dev_private; 2604 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2605 struct radeon_encoder_atom_dig *dig; 2606 2607 /* check for pre-DCE3 cards with shared encoders; 2608 * can't really use the links individually, so don't disable 2609 * the encoder if it's in use by another connector 2610 */ 2611 if (!ASIC_IS_DCE3(rdev)) { 2612 struct drm_encoder *other_encoder; 2613 struct radeon_encoder *other_radeon_encoder; 2614 2615 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2616 other_radeon_encoder = to_radeon_encoder(other_encoder); 2617 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2618 drm_helper_encoder_in_use(other_encoder)) 2619 goto disable_done; 2620 } 2621 } 2622 2623 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2624 2625 switch (radeon_encoder->encoder_id) { 2626 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2628 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2629 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2630 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2631 break; 2632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2633 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2634 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2635 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2636 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2637 /* handled in dpms */ 2638 break; 2639 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2640 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2642 atombios_dvo_setup(encoder, ATOM_DISABLE); 2643 break; 2644 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2645 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2646 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2648 atombios_dac_setup(encoder, ATOM_DISABLE); 2649 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2650 atombios_tv_setup(encoder, ATOM_DISABLE); 2651 break; 2652 } 2653 2654 disable_done: 2655 if (radeon_encoder_is_digital(encoder)) { 2656 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2657 if (rdev->asic->display.hdmi_enable) 2658 radeon_hdmi_enable(rdev, encoder, false); 2659 } 2660 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2661 dig = radeon_encoder->enc_priv; 2662 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2663 dig->dig_encoder = -1; 2664 radeon_encoder->active_device = 0; 2665 } 2666 } else 2667 radeon_encoder->active_device = 0; 2668 } 2669 2670 /* these are handled by the primary encoders */ 2671 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2672 { 2673 2674 } 2675 2676 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2677 { 2678 2679 } 2680 2681 static void 2682 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2683 struct drm_display_mode *mode, 2684 struct drm_display_mode *adjusted_mode) 2685 { 2686 2687 } 2688 2689 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2690 { 2691 2692 } 2693 2694 static void 2695 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2696 { 2697 2698 } 2699 2700 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2701 .dpms = radeon_atom_ext_dpms, 2702 .prepare = radeon_atom_ext_prepare, 2703 .mode_set = radeon_atom_ext_mode_set, 2704 .commit = radeon_atom_ext_commit, 2705 .disable = radeon_atom_ext_disable, 2706 /* no detect for TMDS/LVDS yet */ 2707 }; 2708 2709 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2710 .dpms = radeon_atom_encoder_dpms, 2711 .mode_fixup = radeon_atom_mode_fixup, 2712 .prepare = radeon_atom_encoder_prepare, 2713 .mode_set = radeon_atom_encoder_mode_set, 2714 .commit = radeon_atom_encoder_commit, 2715 .disable = radeon_atom_encoder_disable, 2716 .detect = radeon_atom_dig_detect, 2717 }; 2718 2719 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2720 .dpms = radeon_atom_encoder_dpms, 2721 .mode_fixup = radeon_atom_mode_fixup, 2722 .prepare = radeon_atom_encoder_prepare, 2723 .mode_set = radeon_atom_encoder_mode_set, 2724 .commit = radeon_atom_encoder_commit, 2725 .detect = radeon_atom_dac_detect, 2726 }; 2727 2728 void radeon_enc_destroy(struct drm_encoder *encoder) 2729 { 2730 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2731 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2732 radeon_atom_backlight_exit(radeon_encoder); 2733 kfree(radeon_encoder->enc_priv); 2734 drm_encoder_cleanup(encoder); 2735 kfree(radeon_encoder); 2736 } 2737 2738 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2739 .destroy = radeon_enc_destroy, 2740 }; 2741 2742 static struct radeon_encoder_atom_dac * 2743 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2744 { 2745 struct drm_device *dev = radeon_encoder->base.dev; 2746 struct radeon_device *rdev = dev->dev_private; 2747 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2748 2749 if (!dac) 2750 return NULL; 2751 2752 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2753 return dac; 2754 } 2755 2756 static struct radeon_encoder_atom_dig * 2757 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2758 { 2759 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2760 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2761 2762 if (!dig) 2763 return NULL; 2764 2765 /* coherent mode by default */ 2766 dig->coherent_mode = true; 2767 dig->dig_encoder = -1; 2768 2769 if (encoder_enum == 2) 2770 dig->linkb = true; 2771 else 2772 dig->linkb = false; 2773 2774 return dig; 2775 } 2776 2777 void 2778 radeon_add_atom_encoder(struct drm_device *dev, 2779 uint32_t encoder_enum, 2780 uint32_t supported_device, 2781 u16 caps) 2782 { 2783 struct radeon_device *rdev = dev->dev_private; 2784 struct drm_encoder *encoder; 2785 struct radeon_encoder *radeon_encoder; 2786 2787 /* see if we already added it */ 2788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2789 radeon_encoder = to_radeon_encoder(encoder); 2790 if (radeon_encoder->encoder_enum == encoder_enum) { 2791 radeon_encoder->devices |= supported_device; 2792 return; 2793 } 2794 2795 } 2796 2797 /* add a new one */ 2798 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2799 if (!radeon_encoder) 2800 return; 2801 2802 encoder = &radeon_encoder->base; 2803 switch (rdev->num_crtc) { 2804 case 1: 2805 encoder->possible_crtcs = 0x1; 2806 break; 2807 case 2: 2808 default: 2809 encoder->possible_crtcs = 0x3; 2810 break; 2811 case 4: 2812 encoder->possible_crtcs = 0xf; 2813 break; 2814 case 6: 2815 encoder->possible_crtcs = 0x3f; 2816 break; 2817 } 2818 2819 radeon_encoder->enc_priv = NULL; 2820 2821 radeon_encoder->encoder_enum = encoder_enum; 2822 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2823 radeon_encoder->devices = supported_device; 2824 radeon_encoder->rmx_type = RMX_OFF; 2825 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2826 radeon_encoder->is_ext_encoder = false; 2827 radeon_encoder->caps = caps; 2828 2829 switch (radeon_encoder->encoder_id) { 2830 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2831 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2832 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2833 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2834 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2835 radeon_encoder->rmx_type = RMX_FULL; 2836 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2837 DRM_MODE_ENCODER_LVDS, NULL); 2838 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2839 } else { 2840 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2841 DRM_MODE_ENCODER_TMDS, NULL); 2842 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2843 } 2844 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2845 break; 2846 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2847 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2848 DRM_MODE_ENCODER_DAC, NULL); 2849 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2850 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2851 break; 2852 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2853 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2855 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2856 DRM_MODE_ENCODER_TVDAC, NULL); 2857 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2858 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2859 break; 2860 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2862 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2864 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2868 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2869 radeon_encoder->rmx_type = RMX_FULL; 2870 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2871 DRM_MODE_ENCODER_LVDS, NULL); 2872 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2873 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2874 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2875 DRM_MODE_ENCODER_DAC, NULL); 2876 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2877 } else { 2878 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2879 DRM_MODE_ENCODER_TMDS, NULL); 2880 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2881 } 2882 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2883 break; 2884 case ENCODER_OBJECT_ID_SI170B: 2885 case ENCODER_OBJECT_ID_CH7303: 2886 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2887 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2888 case ENCODER_OBJECT_ID_TITFP513: 2889 case ENCODER_OBJECT_ID_VT1623: 2890 case ENCODER_OBJECT_ID_HDMI_SI1930: 2891 case ENCODER_OBJECT_ID_TRAVIS: 2892 case ENCODER_OBJECT_ID_NUTMEG: 2893 /* these are handled by the primary encoders */ 2894 radeon_encoder->is_ext_encoder = true; 2895 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2896 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2897 DRM_MODE_ENCODER_LVDS, NULL); 2898 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2899 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2900 DRM_MODE_ENCODER_DAC, NULL); 2901 else 2902 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2903 DRM_MODE_ENCODER_TMDS, NULL); 2904 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2905 break; 2906 } 2907 } 2908