1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "cikd.h" 28 #include "r600_dpm.h" 29 #include "ci_dpm.h" 30 #include "ni_dpm.h" 31 #include "atom.h" 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x40000 40 41 #define VOLTAGE_SCALE 4 42 #define VOLTAGE_VID_OFFSET_SCALE1 625 43 #define VOLTAGE_VID_OFFSET_SCALE2 100 44 45 static const struct ci_pt_defaults defaults_bonaire_xt = 46 { 47 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 48 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 49 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 50 }; 51 52 static const struct ci_pt_defaults defaults_bonaire_pro = 53 { 54 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, 55 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, 56 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } 57 }; 58 59 static const struct ci_pt_defaults defaults_saturn_xt = 60 { 61 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 62 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 63 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 64 }; 65 66 static const struct ci_pt_defaults defaults_saturn_pro = 67 { 68 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, 69 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, 70 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } 71 }; 72 73 static const struct ci_pt_config_reg didt_config_ci[] = 74 { 75 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 76 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 77 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 78 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 79 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 80 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 81 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 82 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 83 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 84 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 85 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 86 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 87 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 88 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 89 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 90 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 91 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 92 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 93 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 94 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 147 { 0xFFFFFFFF } 148 }; 149 150 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 151 struct atom_voltage_table_entry *voltage_table, 152 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 153 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 154 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 155 u32 target_tdp); 156 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 157 158 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 159 { 160 struct ci_power_info *pi = rdev->pm.dpm.priv; 161 162 return pi; 163 } 164 165 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 166 { 167 struct ci_ps *ps = rps->ps_priv; 168 169 return ps; 170 } 171 172 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 173 { 174 struct ci_power_info *pi = ci_get_pi(rdev); 175 176 switch (rdev->ddev->pci_device) { 177 case 0x6650: 178 case 0x6658: 179 case 0x665C: 180 default: 181 pi->powertune_defaults = &defaults_bonaire_xt; 182 break; 183 case 0x6651: 184 case 0x665D: 185 pi->powertune_defaults = &defaults_bonaire_pro; 186 break; 187 case 0x6640: 188 pi->powertune_defaults = &defaults_saturn_xt; 189 break; 190 case 0x6641: 191 pi->powertune_defaults = &defaults_saturn_pro; 192 break; 193 } 194 195 pi->dte_tj_offset = 0; 196 197 pi->caps_power_containment = true; 198 pi->caps_cac = false; 199 pi->caps_sq_ramping = false; 200 pi->caps_db_ramping = false; 201 pi->caps_td_ramping = false; 202 pi->caps_tcp_ramping = false; 203 204 if (pi->caps_power_containment) { 205 pi->caps_cac = true; 206 pi->enable_bapm_feature = true; 207 pi->enable_tdc_limit_feature = true; 208 pi->enable_pkg_pwr_tracking_feature = true; 209 } 210 } 211 212 static u8 ci_convert_to_vid(u16 vddc) 213 { 214 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 215 } 216 217 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 218 { 219 struct ci_power_info *pi = ci_get_pi(rdev); 220 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 221 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 222 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 223 u32 i; 224 225 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 226 return -EINVAL; 227 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 228 return -EINVAL; 229 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 230 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 231 return -EINVAL; 232 233 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 234 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 235 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 236 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 237 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 238 } else { 239 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 240 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 241 } 242 } 243 return 0; 244 } 245 246 static int ci_populate_vddc_vid(struct radeon_device *rdev) 247 { 248 struct ci_power_info *pi = ci_get_pi(rdev); 249 u8 *vid = pi->smc_powertune_table.VddCVid; 250 u32 i; 251 252 if (pi->vddc_voltage_table.count > 8) 253 return -EINVAL; 254 255 for (i = 0; i < pi->vddc_voltage_table.count; i++) 256 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 257 258 return 0; 259 } 260 261 static int ci_populate_svi_load_line(struct radeon_device *rdev) 262 { 263 struct ci_power_info *pi = ci_get_pi(rdev); 264 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 265 266 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 267 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 268 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 269 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 270 271 return 0; 272 } 273 274 static int ci_populate_tdc_limit(struct radeon_device *rdev) 275 { 276 struct ci_power_info *pi = ci_get_pi(rdev); 277 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 278 u16 tdc_limit; 279 280 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 281 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 282 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 283 pt_defaults->tdc_vddc_throttle_release_limit_perc; 284 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 285 286 return 0; 287 } 288 289 static int ci_populate_dw8(struct radeon_device *rdev) 290 { 291 struct ci_power_info *pi = ci_get_pi(rdev); 292 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 293 int ret; 294 295 ret = ci_read_smc_sram_dword(rdev, 296 SMU7_FIRMWARE_HEADER_LOCATION + 297 offsetof(SMU7_Firmware_Header, PmFuseTable) + 298 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 299 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 300 pi->sram_end); 301 if (ret) 302 return -EINVAL; 303 else 304 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 305 306 return 0; 307 } 308 309 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 310 { 311 struct ci_power_info *pi = ci_get_pi(rdev); 312 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 313 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 314 int i, min, max; 315 316 min = max = hi_vid[0]; 317 for (i = 0; i < 8; i++) { 318 if (0 != hi_vid[i]) { 319 if (min > hi_vid[i]) 320 min = hi_vid[i]; 321 if (max < hi_vid[i]) 322 max = hi_vid[i]; 323 } 324 325 if (0 != lo_vid[i]) { 326 if (min > lo_vid[i]) 327 min = lo_vid[i]; 328 if (max < lo_vid[i]) 329 max = lo_vid[i]; 330 } 331 } 332 333 if ((min == 0) || (max == 0)) 334 return -EINVAL; 335 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 336 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 337 338 return 0; 339 } 340 341 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 342 { 343 struct ci_power_info *pi = ci_get_pi(rdev); 344 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; 345 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; 346 struct radeon_cac_tdp_table *cac_tdp_table = 347 rdev->pm.dpm.dyn_state.cac_tdp_table; 348 349 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 350 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 351 352 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 353 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 354 355 return 0; 356 } 357 358 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 359 { 360 struct ci_power_info *pi = ci_get_pi(rdev); 361 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 362 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 363 struct radeon_cac_tdp_table *cac_tdp_table = 364 rdev->pm.dpm.dyn_state.cac_tdp_table; 365 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 366 int i, j, k; 367 const u16 *def1; 368 const u16 *def2; 369 370 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 371 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 372 373 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 374 dpm_table->GpuTjMax = 375 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 376 dpm_table->GpuTjHyst = 8; 377 378 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 379 380 if (ppm) { 381 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 382 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 383 } else { 384 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 385 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 386 } 387 388 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 389 def1 = pt_defaults->bapmti_r; 390 def2 = pt_defaults->bapmti_rc; 391 392 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 393 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 394 for (k = 0; k < SMU7_DTE_SINKS; k++) { 395 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 396 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 397 def1++; 398 def2++; 399 } 400 } 401 } 402 403 return 0; 404 } 405 406 static int ci_populate_pm_base(struct radeon_device *rdev) 407 { 408 struct ci_power_info *pi = ci_get_pi(rdev); 409 u32 pm_fuse_table_offset; 410 int ret; 411 412 if (pi->caps_power_containment) { 413 ret = ci_read_smc_sram_dword(rdev, 414 SMU7_FIRMWARE_HEADER_LOCATION + 415 offsetof(SMU7_Firmware_Header, PmFuseTable), 416 &pm_fuse_table_offset, pi->sram_end); 417 if (ret) 418 return ret; 419 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 420 if (ret) 421 return ret; 422 ret = ci_populate_vddc_vid(rdev); 423 if (ret) 424 return ret; 425 ret = ci_populate_svi_load_line(rdev); 426 if (ret) 427 return ret; 428 ret = ci_populate_tdc_limit(rdev); 429 if (ret) 430 return ret; 431 ret = ci_populate_dw8(rdev); 432 if (ret) 433 return ret; 434 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 435 if (ret) 436 return ret; 437 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 438 if (ret) 439 return ret; 440 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 441 (u8 *)&pi->smc_powertune_table, 442 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 443 if (ret) 444 return ret; 445 } 446 447 return 0; 448 } 449 450 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 451 { 452 struct ci_power_info *pi = ci_get_pi(rdev); 453 u32 data; 454 455 if (pi->caps_sq_ramping) { 456 data = RREG32_DIDT(DIDT_SQ_CTRL0); 457 if (enable) 458 data |= DIDT_CTRL_EN; 459 else 460 data &= ~DIDT_CTRL_EN; 461 WREG32_DIDT(DIDT_SQ_CTRL0, data); 462 } 463 464 if (pi->caps_db_ramping) { 465 data = RREG32_DIDT(DIDT_DB_CTRL0); 466 if (enable) 467 data |= DIDT_CTRL_EN; 468 else 469 data &= ~DIDT_CTRL_EN; 470 WREG32_DIDT(DIDT_DB_CTRL0, data); 471 } 472 473 if (pi->caps_td_ramping) { 474 data = RREG32_DIDT(DIDT_TD_CTRL0); 475 if (enable) 476 data |= DIDT_CTRL_EN; 477 else 478 data &= ~DIDT_CTRL_EN; 479 WREG32_DIDT(DIDT_TD_CTRL0, data); 480 } 481 482 if (pi->caps_tcp_ramping) { 483 data = RREG32_DIDT(DIDT_TCP_CTRL0); 484 if (enable) 485 data |= DIDT_CTRL_EN; 486 else 487 data &= ~DIDT_CTRL_EN; 488 WREG32_DIDT(DIDT_TCP_CTRL0, data); 489 } 490 } 491 492 static int ci_program_pt_config_registers(struct radeon_device *rdev, 493 const struct ci_pt_config_reg *cac_config_regs) 494 { 495 const struct ci_pt_config_reg *config_regs = cac_config_regs; 496 u32 data; 497 u32 cache = 0; 498 499 if (config_regs == NULL) 500 return -EINVAL; 501 502 while (config_regs->offset != 0xFFFFFFFF) { 503 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 504 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 505 } else { 506 switch (config_regs->type) { 507 case CISLANDS_CONFIGREG_SMC_IND: 508 data = RREG32_SMC(config_regs->offset); 509 break; 510 case CISLANDS_CONFIGREG_DIDT_IND: 511 data = RREG32_DIDT(config_regs->offset); 512 break; 513 default: 514 data = RREG32(config_regs->offset << 2); 515 break; 516 } 517 518 data &= ~config_regs->mask; 519 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 520 data |= cache; 521 522 switch (config_regs->type) { 523 case CISLANDS_CONFIGREG_SMC_IND: 524 WREG32_SMC(config_regs->offset, data); 525 break; 526 case CISLANDS_CONFIGREG_DIDT_IND: 527 WREG32_DIDT(config_regs->offset, data); 528 break; 529 default: 530 WREG32(config_regs->offset << 2, data); 531 break; 532 } 533 cache = 0; 534 } 535 config_regs++; 536 } 537 return 0; 538 } 539 540 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 541 { 542 struct ci_power_info *pi = ci_get_pi(rdev); 543 int ret; 544 545 if (pi->caps_sq_ramping || pi->caps_db_ramping || 546 pi->caps_td_ramping || pi->caps_tcp_ramping) { 547 cik_enter_rlc_safe_mode(rdev); 548 549 if (enable) { 550 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 551 if (ret) { 552 cik_exit_rlc_safe_mode(rdev); 553 return ret; 554 } 555 } 556 557 ci_do_enable_didt(rdev, enable); 558 559 cik_exit_rlc_safe_mode(rdev); 560 } 561 562 return 0; 563 } 564 565 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 566 { 567 struct ci_power_info *pi = ci_get_pi(rdev); 568 PPSMC_Result smc_result; 569 int ret = 0; 570 571 if (enable) { 572 pi->power_containment_features = 0; 573 if (pi->caps_power_containment) { 574 if (pi->enable_bapm_feature) { 575 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 576 if (smc_result != PPSMC_Result_OK) 577 ret = -EINVAL; 578 else 579 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 580 } 581 582 if (pi->enable_tdc_limit_feature) { 583 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 584 if (smc_result != PPSMC_Result_OK) 585 ret = -EINVAL; 586 else 587 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 588 } 589 590 if (pi->enable_pkg_pwr_tracking_feature) { 591 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 592 if (smc_result != PPSMC_Result_OK) { 593 ret = -EINVAL; 594 } else { 595 struct radeon_cac_tdp_table *cac_tdp_table = 596 rdev->pm.dpm.dyn_state.cac_tdp_table; 597 u32 default_pwr_limit = 598 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 599 600 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 601 602 ci_set_power_limit(rdev, default_pwr_limit); 603 } 604 } 605 } 606 } else { 607 if (pi->caps_power_containment && pi->power_containment_features) { 608 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 609 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 610 611 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 612 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 613 614 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 615 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 616 pi->power_containment_features = 0; 617 } 618 } 619 620 return ret; 621 } 622 623 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 624 { 625 struct ci_power_info *pi = ci_get_pi(rdev); 626 PPSMC_Result smc_result; 627 int ret = 0; 628 629 if (pi->caps_cac) { 630 if (enable) { 631 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 632 if (smc_result != PPSMC_Result_OK) { 633 ret = -EINVAL; 634 pi->cac_enabled = false; 635 } else { 636 pi->cac_enabled = true; 637 } 638 } else if (pi->cac_enabled) { 639 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 640 pi->cac_enabled = false; 641 } 642 } 643 644 return ret; 645 } 646 647 static int ci_power_control_set_level(struct radeon_device *rdev) 648 { 649 struct ci_power_info *pi = ci_get_pi(rdev); 650 struct radeon_cac_tdp_table *cac_tdp_table = 651 rdev->pm.dpm.dyn_state.cac_tdp_table; 652 s32 adjust_percent; 653 s32 target_tdp; 654 int ret = 0; 655 bool adjust_polarity = false; /* ??? */ 656 657 if (pi->caps_power_containment && 658 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) { 659 adjust_percent = adjust_polarity ? 660 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 661 target_tdp = ((100 + adjust_percent) * 662 (s32)cac_tdp_table->configurable_tdp) / 100; 663 target_tdp *= 256; 664 665 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 666 } 667 668 return ret; 669 } 670 671 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 672 { 673 struct ci_power_info *pi = ci_get_pi(rdev); 674 675 if (pi->uvd_power_gated == gate) 676 return; 677 678 pi->uvd_power_gated = gate; 679 680 ci_update_uvd_dpm(rdev, gate); 681 } 682 683 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 684 { 685 struct ci_power_info *pi = ci_get_pi(rdev); 686 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 687 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 688 689 if (vblank_time < switch_limit) 690 return true; 691 else 692 return false; 693 694 } 695 696 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 697 struct radeon_ps *rps) 698 { 699 struct ci_ps *ps = ci_get_ps(rps); 700 struct ci_power_info *pi = ci_get_pi(rdev); 701 struct radeon_clock_and_voltage_limits *max_limits; 702 bool disable_mclk_switching; 703 u32 sclk, mclk; 704 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 705 int i; 706 707 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 708 ci_dpm_vblank_too_short(rdev)) 709 disable_mclk_switching = true; 710 else 711 disable_mclk_switching = false; 712 713 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 714 pi->battery_state = true; 715 else 716 pi->battery_state = false; 717 718 if (rdev->pm.dpm.ac_power) 719 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 720 else 721 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 722 723 if (rdev->pm.dpm.ac_power == false) { 724 for (i = 0; i < ps->performance_level_count; i++) { 725 if (ps->performance_levels[i].mclk > max_limits->mclk) 726 ps->performance_levels[i].mclk = max_limits->mclk; 727 if (ps->performance_levels[i].sclk > max_limits->sclk) 728 ps->performance_levels[i].sclk = max_limits->sclk; 729 } 730 } 731 732 /* limit clocks to max supported clocks based on voltage dependency tables */ 733 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 734 &max_sclk_vddc); 735 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 736 &max_mclk_vddci); 737 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 738 &max_mclk_vddc); 739 740 for (i = 0; i < ps->performance_level_count; i++) { 741 if (max_sclk_vddc) { 742 if (ps->performance_levels[i].sclk > max_sclk_vddc) 743 ps->performance_levels[i].sclk = max_sclk_vddc; 744 } 745 if (max_mclk_vddci) { 746 if (ps->performance_levels[i].mclk > max_mclk_vddci) 747 ps->performance_levels[i].mclk = max_mclk_vddci; 748 } 749 if (max_mclk_vddc) { 750 if (ps->performance_levels[i].mclk > max_mclk_vddc) 751 ps->performance_levels[i].mclk = max_mclk_vddc; 752 } 753 } 754 755 /* XXX validate the min clocks required for display */ 756 757 if (disable_mclk_switching) { 758 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 759 sclk = ps->performance_levels[0].sclk; 760 } else { 761 mclk = ps->performance_levels[0].mclk; 762 sclk = ps->performance_levels[0].sclk; 763 } 764 765 ps->performance_levels[0].sclk = sclk; 766 ps->performance_levels[0].mclk = mclk; 767 768 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 769 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 770 771 if (disable_mclk_switching) { 772 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 773 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 774 } else { 775 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 776 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 777 } 778 } 779 780 static int ci_set_thermal_temperature_range(struct radeon_device *rdev, 781 int min_temp, int max_temp) 782 { 783 int low_temp = 0 * 1000; 784 int high_temp = 255 * 1000; 785 u32 tmp; 786 787 if (low_temp < min_temp) 788 low_temp = min_temp; 789 if (high_temp > max_temp) 790 high_temp = max_temp; 791 if (high_temp < low_temp) { 792 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 793 return -EINVAL; 794 } 795 796 tmp = RREG32_SMC(CG_THERMAL_INT); 797 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 798 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 799 CI_DIG_THERM_INTL(low_temp / 1000); 800 WREG32_SMC(CG_THERMAL_INT, tmp); 801 802 #if 0 803 /* XXX: need to figure out how to handle this properly */ 804 tmp = RREG32_SMC(CG_THERMAL_CTRL); 805 tmp &= DIG_THERM_DPM_MASK; 806 tmp |= DIG_THERM_DPM(high_temp / 1000); 807 WREG32_SMC(CG_THERMAL_CTRL, tmp); 808 #endif 809 810 return 0; 811 } 812 813 #if 0 814 static int ci_read_smc_soft_register(struct radeon_device *rdev, 815 u16 reg_offset, u32 *value) 816 { 817 struct ci_power_info *pi = ci_get_pi(rdev); 818 819 return ci_read_smc_sram_dword(rdev, 820 pi->soft_regs_start + reg_offset, 821 value, pi->sram_end); 822 } 823 #endif 824 825 static int ci_write_smc_soft_register(struct radeon_device *rdev, 826 u16 reg_offset, u32 value) 827 { 828 struct ci_power_info *pi = ci_get_pi(rdev); 829 830 return ci_write_smc_sram_dword(rdev, 831 pi->soft_regs_start + reg_offset, 832 value, pi->sram_end); 833 } 834 835 static void ci_init_fps_limits(struct radeon_device *rdev) 836 { 837 struct ci_power_info *pi = ci_get_pi(rdev); 838 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 839 840 if (pi->caps_fps) { 841 u16 tmp; 842 843 tmp = 45; 844 table->FpsHighT = cpu_to_be16(tmp); 845 846 tmp = 30; 847 table->FpsLowT = cpu_to_be16(tmp); 848 } 849 } 850 851 static int ci_update_sclk_t(struct radeon_device *rdev) 852 { 853 struct ci_power_info *pi = ci_get_pi(rdev); 854 int ret = 0; 855 u32 low_sclk_interrupt_t = 0; 856 857 if (pi->caps_sclk_throttle_low_notification) { 858 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 859 860 ret = ci_copy_bytes_to_smc(rdev, 861 pi->dpm_table_start + 862 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 863 (u8 *)&low_sclk_interrupt_t, 864 sizeof(u32), pi->sram_end); 865 866 } 867 868 return ret; 869 } 870 871 static void ci_get_leakage_voltages(struct radeon_device *rdev) 872 { 873 struct ci_power_info *pi = ci_get_pi(rdev); 874 u16 leakage_id, virtual_voltage_id; 875 u16 vddc, vddci; 876 int i; 877 878 pi->vddc_leakage.count = 0; 879 pi->vddci_leakage.count = 0; 880 881 if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 882 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 883 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 884 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 885 virtual_voltage_id, 886 leakage_id) == 0) { 887 if (vddc != 0 && vddc != virtual_voltage_id) { 888 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 889 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 890 pi->vddc_leakage.count++; 891 } 892 if (vddci != 0 && vddci != virtual_voltage_id) { 893 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 894 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 895 pi->vddci_leakage.count++; 896 } 897 } 898 } 899 } 900 } 901 902 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 903 { 904 struct ci_power_info *pi = ci_get_pi(rdev); 905 bool want_thermal_protection; 906 enum radeon_dpm_event_src dpm_event_src; 907 u32 tmp; 908 909 switch (sources) { 910 case 0: 911 default: 912 want_thermal_protection = false; 913 break; 914 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 915 want_thermal_protection = true; 916 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 917 break; 918 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 919 want_thermal_protection = true; 920 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 921 break; 922 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 923 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 924 want_thermal_protection = true; 925 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 926 break; 927 } 928 929 if (want_thermal_protection) { 930 #if 0 931 /* XXX: need to figure out how to handle this properly */ 932 tmp = RREG32_SMC(CG_THERMAL_CTRL); 933 tmp &= DPM_EVENT_SRC_MASK; 934 tmp |= DPM_EVENT_SRC(dpm_event_src); 935 WREG32_SMC(CG_THERMAL_CTRL, tmp); 936 #endif 937 938 tmp = RREG32_SMC(GENERAL_PWRMGT); 939 if (pi->thermal_protection) 940 tmp &= ~THERMAL_PROTECTION_DIS; 941 else 942 tmp |= THERMAL_PROTECTION_DIS; 943 WREG32_SMC(GENERAL_PWRMGT, tmp); 944 } else { 945 tmp = RREG32_SMC(GENERAL_PWRMGT); 946 tmp |= THERMAL_PROTECTION_DIS; 947 WREG32_SMC(GENERAL_PWRMGT, tmp); 948 } 949 } 950 951 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 952 enum radeon_dpm_auto_throttle_src source, 953 bool enable) 954 { 955 struct ci_power_info *pi = ci_get_pi(rdev); 956 957 if (enable) { 958 if (!(pi->active_auto_throttle_sources & (1 << source))) { 959 pi->active_auto_throttle_sources |= 1 << source; 960 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 961 } 962 } else { 963 if (pi->active_auto_throttle_sources & (1 << source)) { 964 pi->active_auto_throttle_sources &= ~(1 << source); 965 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 966 } 967 } 968 } 969 970 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 971 { 972 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 973 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 974 } 975 976 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 977 { 978 struct ci_power_info *pi = ci_get_pi(rdev); 979 PPSMC_Result smc_result; 980 981 if (!pi->need_update_smu7_dpm_table) 982 return 0; 983 984 if ((!pi->sclk_dpm_key_disabled) && 985 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 986 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 987 if (smc_result != PPSMC_Result_OK) 988 return -EINVAL; 989 } 990 991 if ((!pi->mclk_dpm_key_disabled) && 992 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 993 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 994 if (smc_result != PPSMC_Result_OK) 995 return -EINVAL; 996 } 997 998 pi->need_update_smu7_dpm_table = 0; 999 return 0; 1000 } 1001 1002 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1003 { 1004 struct ci_power_info *pi = ci_get_pi(rdev); 1005 PPSMC_Result smc_result; 1006 1007 if (enable) { 1008 if (!pi->sclk_dpm_key_disabled) { 1009 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1010 if (smc_result != PPSMC_Result_OK) 1011 return -EINVAL; 1012 } 1013 1014 if (!pi->mclk_dpm_key_disabled) { 1015 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1016 if (smc_result != PPSMC_Result_OK) 1017 return -EINVAL; 1018 1019 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1020 1021 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1022 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1023 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1024 1025 udelay(10); 1026 1027 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1028 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1029 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1030 } 1031 } else { 1032 if (!pi->sclk_dpm_key_disabled) { 1033 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1034 if (smc_result != PPSMC_Result_OK) 1035 return -EINVAL; 1036 } 1037 1038 if (!pi->mclk_dpm_key_disabled) { 1039 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1040 if (smc_result != PPSMC_Result_OK) 1041 return -EINVAL; 1042 } 1043 } 1044 1045 return 0; 1046 } 1047 1048 static int ci_start_dpm(struct radeon_device *rdev) 1049 { 1050 struct ci_power_info *pi = ci_get_pi(rdev); 1051 PPSMC_Result smc_result; 1052 int ret; 1053 u32 tmp; 1054 1055 tmp = RREG32_SMC(GENERAL_PWRMGT); 1056 tmp |= GLOBAL_PWRMGT_EN; 1057 WREG32_SMC(GENERAL_PWRMGT, tmp); 1058 1059 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1060 tmp |= DYNAMIC_PM_EN; 1061 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1062 1063 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1064 1065 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1066 1067 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1068 if (smc_result != PPSMC_Result_OK) 1069 return -EINVAL; 1070 1071 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1072 if (ret) 1073 return ret; 1074 1075 if (!pi->pcie_dpm_key_disabled) { 1076 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1077 if (smc_result != PPSMC_Result_OK) 1078 return -EINVAL; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1085 { 1086 struct ci_power_info *pi = ci_get_pi(rdev); 1087 PPSMC_Result smc_result; 1088 1089 if (!pi->need_update_smu7_dpm_table) 1090 return 0; 1091 1092 if ((!pi->sclk_dpm_key_disabled) && 1093 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1094 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1095 if (smc_result != PPSMC_Result_OK) 1096 return -EINVAL; 1097 } 1098 1099 if ((!pi->mclk_dpm_key_disabled) && 1100 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1101 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1102 if (smc_result != PPSMC_Result_OK) 1103 return -EINVAL; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int ci_stop_dpm(struct radeon_device *rdev) 1110 { 1111 struct ci_power_info *pi = ci_get_pi(rdev); 1112 PPSMC_Result smc_result; 1113 int ret; 1114 u32 tmp; 1115 1116 tmp = RREG32_SMC(GENERAL_PWRMGT); 1117 tmp &= ~GLOBAL_PWRMGT_EN; 1118 WREG32_SMC(GENERAL_PWRMGT, tmp); 1119 1120 tmp = RREG32(SCLK_PWRMGT_CNTL); 1121 tmp &= ~DYNAMIC_PM_EN; 1122 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1123 1124 if (!pi->pcie_dpm_key_disabled) { 1125 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1126 if (smc_result != PPSMC_Result_OK) 1127 return -EINVAL; 1128 } 1129 1130 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1131 if (ret) 1132 return ret; 1133 1134 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1135 if (smc_result != PPSMC_Result_OK) 1136 return -EINVAL; 1137 1138 return 0; 1139 } 1140 1141 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1142 { 1143 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1144 1145 if (enable) 1146 tmp &= ~SCLK_PWRMGT_OFF; 1147 else 1148 tmp |= SCLK_PWRMGT_OFF; 1149 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1150 } 1151 1152 #if 0 1153 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1154 bool ac_power) 1155 { 1156 struct ci_power_info *pi = ci_get_pi(rdev); 1157 struct radeon_cac_tdp_table *cac_tdp_table = 1158 rdev->pm.dpm.dyn_state.cac_tdp_table; 1159 u32 power_limit; 1160 1161 if (ac_power) 1162 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1163 else 1164 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1165 1166 ci_set_power_limit(rdev, power_limit); 1167 1168 if (pi->caps_automatic_dc_transition) { 1169 if (ac_power) 1170 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1171 else 1172 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1173 } 1174 1175 return 0; 1176 } 1177 #endif 1178 1179 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1180 PPSMC_Msg msg, u32 parameter) 1181 { 1182 WREG32(SMC_MSG_ARG_0, parameter); 1183 return ci_send_msg_to_smc(rdev, msg); 1184 } 1185 1186 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1187 PPSMC_Msg msg, u32 *parameter) 1188 { 1189 PPSMC_Result smc_result; 1190 1191 smc_result = ci_send_msg_to_smc(rdev, msg); 1192 1193 if ((smc_result == PPSMC_Result_OK) && parameter) 1194 *parameter = RREG32(SMC_MSG_ARG_0); 1195 1196 return smc_result; 1197 } 1198 1199 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1200 { 1201 struct ci_power_info *pi = ci_get_pi(rdev); 1202 1203 if (!pi->sclk_dpm_key_disabled) { 1204 PPSMC_Result smc_result = 1205 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n); 1206 if (smc_result != PPSMC_Result_OK) 1207 return -EINVAL; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1214 { 1215 struct ci_power_info *pi = ci_get_pi(rdev); 1216 1217 if (!pi->mclk_dpm_key_disabled) { 1218 PPSMC_Result smc_result = 1219 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n); 1220 if (smc_result != PPSMC_Result_OK) 1221 return -EINVAL; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1228 { 1229 struct ci_power_info *pi = ci_get_pi(rdev); 1230 1231 if (!pi->pcie_dpm_key_disabled) { 1232 PPSMC_Result smc_result = 1233 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1234 if (smc_result != PPSMC_Result_OK) 1235 return -EINVAL; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1242 { 1243 struct ci_power_info *pi = ci_get_pi(rdev); 1244 1245 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1246 PPSMC_Result smc_result = 1247 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1248 if (smc_result != PPSMC_Result_OK) 1249 return -EINVAL; 1250 } 1251 1252 return 0; 1253 } 1254 1255 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1256 u32 target_tdp) 1257 { 1258 PPSMC_Result smc_result = 1259 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1260 if (smc_result != PPSMC_Result_OK) 1261 return -EINVAL; 1262 return 0; 1263 } 1264 1265 static int ci_set_boot_state(struct radeon_device *rdev) 1266 { 1267 return ci_enable_sclk_mclk_dpm(rdev, false); 1268 } 1269 1270 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1271 { 1272 u32 sclk_freq; 1273 PPSMC_Result smc_result = 1274 ci_send_msg_to_smc_return_parameter(rdev, 1275 PPSMC_MSG_API_GetSclkFrequency, 1276 &sclk_freq); 1277 if (smc_result != PPSMC_Result_OK) 1278 sclk_freq = 0; 1279 1280 return sclk_freq; 1281 } 1282 1283 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1284 { 1285 u32 mclk_freq; 1286 PPSMC_Result smc_result = 1287 ci_send_msg_to_smc_return_parameter(rdev, 1288 PPSMC_MSG_API_GetMclkFrequency, 1289 &mclk_freq); 1290 if (smc_result != PPSMC_Result_OK) 1291 mclk_freq = 0; 1292 1293 return mclk_freq; 1294 } 1295 1296 static void ci_dpm_start_smc(struct radeon_device *rdev) 1297 { 1298 int i; 1299 1300 ci_program_jump_on_start(rdev); 1301 ci_start_smc_clock(rdev); 1302 ci_start_smc(rdev); 1303 for (i = 0; i < rdev->usec_timeout; i++) { 1304 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1305 break; 1306 } 1307 } 1308 1309 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1310 { 1311 ci_reset_smc(rdev); 1312 ci_stop_smc_clock(rdev); 1313 } 1314 1315 static int ci_process_firmware_header(struct radeon_device *rdev) 1316 { 1317 struct ci_power_info *pi = ci_get_pi(rdev); 1318 u32 tmp; 1319 int ret; 1320 1321 ret = ci_read_smc_sram_dword(rdev, 1322 SMU7_FIRMWARE_HEADER_LOCATION + 1323 offsetof(SMU7_Firmware_Header, DpmTable), 1324 &tmp, pi->sram_end); 1325 if (ret) 1326 return ret; 1327 1328 pi->dpm_table_start = tmp; 1329 1330 ret = ci_read_smc_sram_dword(rdev, 1331 SMU7_FIRMWARE_HEADER_LOCATION + 1332 offsetof(SMU7_Firmware_Header, SoftRegisters), 1333 &tmp, pi->sram_end); 1334 if (ret) 1335 return ret; 1336 1337 pi->soft_regs_start = tmp; 1338 1339 ret = ci_read_smc_sram_dword(rdev, 1340 SMU7_FIRMWARE_HEADER_LOCATION + 1341 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1342 &tmp, pi->sram_end); 1343 if (ret) 1344 return ret; 1345 1346 pi->mc_reg_table_start = tmp; 1347 1348 ret = ci_read_smc_sram_dword(rdev, 1349 SMU7_FIRMWARE_HEADER_LOCATION + 1350 offsetof(SMU7_Firmware_Header, FanTable), 1351 &tmp, pi->sram_end); 1352 if (ret) 1353 return ret; 1354 1355 pi->fan_table_start = tmp; 1356 1357 ret = ci_read_smc_sram_dword(rdev, 1358 SMU7_FIRMWARE_HEADER_LOCATION + 1359 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1360 &tmp, pi->sram_end); 1361 if (ret) 1362 return ret; 1363 1364 pi->arb_table_start = tmp; 1365 1366 return 0; 1367 } 1368 1369 static void ci_read_clock_registers(struct radeon_device *rdev) 1370 { 1371 struct ci_power_info *pi = ci_get_pi(rdev); 1372 1373 pi->clock_registers.cg_spll_func_cntl = 1374 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1375 pi->clock_registers.cg_spll_func_cntl_2 = 1376 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1377 pi->clock_registers.cg_spll_func_cntl_3 = 1378 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1379 pi->clock_registers.cg_spll_func_cntl_4 = 1380 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1381 pi->clock_registers.cg_spll_spread_spectrum = 1382 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1383 pi->clock_registers.cg_spll_spread_spectrum_2 = 1384 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1385 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1386 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1387 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1388 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1389 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1390 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1391 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1392 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1393 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1394 } 1395 1396 static void ci_init_sclk_t(struct radeon_device *rdev) 1397 { 1398 struct ci_power_info *pi = ci_get_pi(rdev); 1399 1400 pi->low_sclk_interrupt_t = 0; 1401 } 1402 1403 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1404 bool enable) 1405 { 1406 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1407 1408 if (enable) 1409 tmp &= ~THERMAL_PROTECTION_DIS; 1410 else 1411 tmp |= THERMAL_PROTECTION_DIS; 1412 WREG32_SMC(GENERAL_PWRMGT, tmp); 1413 } 1414 1415 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1416 { 1417 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1418 1419 tmp |= STATIC_PM_EN; 1420 1421 WREG32_SMC(GENERAL_PWRMGT, tmp); 1422 } 1423 1424 #if 0 1425 static int ci_enter_ulp_state(struct radeon_device *rdev) 1426 { 1427 1428 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1429 1430 udelay(25000); 1431 1432 return 0; 1433 } 1434 1435 static int ci_exit_ulp_state(struct radeon_device *rdev) 1436 { 1437 int i; 1438 1439 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1440 1441 udelay(7000); 1442 1443 for (i = 0; i < rdev->usec_timeout; i++) { 1444 if (RREG32(SMC_RESP_0) == 1) 1445 break; 1446 udelay(1000); 1447 } 1448 1449 return 0; 1450 } 1451 #endif 1452 1453 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1454 bool has_display) 1455 { 1456 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1457 1458 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1459 } 1460 1461 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1462 bool enable) 1463 { 1464 struct ci_power_info *pi = ci_get_pi(rdev); 1465 1466 if (enable) { 1467 if (pi->caps_sclk_ds) { 1468 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1469 return -EINVAL; 1470 } else { 1471 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1472 return -EINVAL; 1473 } 1474 } else { 1475 if (pi->caps_sclk_ds) { 1476 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1477 return -EINVAL; 1478 } 1479 } 1480 1481 return 0; 1482 } 1483 1484 static void ci_program_display_gap(struct radeon_device *rdev) 1485 { 1486 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1487 u32 pre_vbi_time_in_us; 1488 u32 frame_time_in_us; 1489 u32 ref_clock = rdev->clock.spll.reference_freq; 1490 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1491 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1492 1493 tmp &= ~DISP_GAP_MASK; 1494 if (rdev->pm.dpm.new_active_crtc_count > 0) 1495 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1496 else 1497 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1498 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1499 1500 if (refresh_rate == 0) 1501 refresh_rate = 60; 1502 if (vblank_time == 0xffffffff) 1503 vblank_time = 500; 1504 frame_time_in_us = 1000000 / refresh_rate; 1505 pre_vbi_time_in_us = 1506 frame_time_in_us - 200 - vblank_time; 1507 tmp = pre_vbi_time_in_us * (ref_clock / 100); 1508 1509 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 1510 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 1511 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 1512 1513 1514 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 1515 1516 } 1517 1518 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 1519 { 1520 struct ci_power_info *pi = ci_get_pi(rdev); 1521 u32 tmp; 1522 1523 if (enable) { 1524 if (pi->caps_sclk_ss_support) { 1525 tmp = RREG32_SMC(GENERAL_PWRMGT); 1526 tmp |= DYN_SPREAD_SPECTRUM_EN; 1527 WREG32_SMC(GENERAL_PWRMGT, tmp); 1528 } 1529 } else { 1530 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1531 tmp &= ~SSEN; 1532 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 1533 1534 tmp = RREG32_SMC(GENERAL_PWRMGT); 1535 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 1536 WREG32_SMC(GENERAL_PWRMGT, tmp); 1537 } 1538 } 1539 1540 static void ci_program_sstp(struct radeon_device *rdev) 1541 { 1542 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 1543 } 1544 1545 static void ci_enable_display_gap(struct radeon_device *rdev) 1546 { 1547 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1548 1549 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 1550 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 1551 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 1552 1553 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1554 } 1555 1556 static void ci_program_vc(struct radeon_device *rdev) 1557 { 1558 u32 tmp; 1559 1560 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1561 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 1562 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1563 1564 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 1565 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 1566 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 1567 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 1568 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 1569 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 1570 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 1571 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 1572 } 1573 1574 static void ci_clear_vc(struct radeon_device *rdev) 1575 { 1576 u32 tmp; 1577 1578 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1579 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 1580 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1581 1582 WREG32_SMC(CG_FTV_0, 0); 1583 WREG32_SMC(CG_FTV_1, 0); 1584 WREG32_SMC(CG_FTV_2, 0); 1585 WREG32_SMC(CG_FTV_3, 0); 1586 WREG32_SMC(CG_FTV_4, 0); 1587 WREG32_SMC(CG_FTV_5, 0); 1588 WREG32_SMC(CG_FTV_6, 0); 1589 WREG32_SMC(CG_FTV_7, 0); 1590 } 1591 1592 static int ci_upload_firmware(struct radeon_device *rdev) 1593 { 1594 struct ci_power_info *pi = ci_get_pi(rdev); 1595 int i, ret; 1596 1597 for (i = 0; i < rdev->usec_timeout; i++) { 1598 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 1599 break; 1600 } 1601 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 1602 1603 ci_stop_smc_clock(rdev); 1604 ci_reset_smc(rdev); 1605 1606 ret = ci_load_smc_ucode(rdev, pi->sram_end); 1607 1608 return ret; 1609 1610 } 1611 1612 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 1613 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 1614 struct atom_voltage_table *voltage_table) 1615 { 1616 u32 i; 1617 1618 if (voltage_dependency_table == NULL) 1619 return -EINVAL; 1620 1621 voltage_table->mask_low = 0; 1622 voltage_table->phase_delay = 0; 1623 1624 voltage_table->count = voltage_dependency_table->count; 1625 for (i = 0; i < voltage_table->count; i++) { 1626 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 1627 voltage_table->entries[i].smio_low = 0; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int ci_construct_voltage_tables(struct radeon_device *rdev) 1634 { 1635 struct ci_power_info *pi = ci_get_pi(rdev); 1636 int ret; 1637 1638 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1639 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 1640 VOLTAGE_OBJ_GPIO_LUT, 1641 &pi->vddc_voltage_table); 1642 if (ret) 1643 return ret; 1644 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1645 ret = ci_get_svi2_voltage_table(rdev, 1646 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 1647 &pi->vddc_voltage_table); 1648 if (ret) 1649 return ret; 1650 } 1651 1652 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 1653 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 1654 &pi->vddc_voltage_table); 1655 1656 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1657 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 1658 VOLTAGE_OBJ_GPIO_LUT, 1659 &pi->vddci_voltage_table); 1660 if (ret) 1661 return ret; 1662 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1663 ret = ci_get_svi2_voltage_table(rdev, 1664 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 1665 &pi->vddci_voltage_table); 1666 if (ret) 1667 return ret; 1668 } 1669 1670 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 1671 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 1672 &pi->vddci_voltage_table); 1673 1674 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1675 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 1676 VOLTAGE_OBJ_GPIO_LUT, 1677 &pi->mvdd_voltage_table); 1678 if (ret) 1679 return ret; 1680 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1681 ret = ci_get_svi2_voltage_table(rdev, 1682 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 1683 &pi->mvdd_voltage_table); 1684 if (ret) 1685 return ret; 1686 } 1687 1688 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 1689 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 1690 &pi->mvdd_voltage_table); 1691 1692 return 0; 1693 } 1694 1695 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 1696 struct atom_voltage_table_entry *voltage_table, 1697 SMU7_Discrete_VoltageLevel *smc_voltage_table) 1698 { 1699 int ret; 1700 1701 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 1702 &smc_voltage_table->StdVoltageHiSidd, 1703 &smc_voltage_table->StdVoltageLoSidd); 1704 1705 if (ret) { 1706 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 1707 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 1708 } 1709 1710 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 1711 smc_voltage_table->StdVoltageHiSidd = 1712 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 1713 smc_voltage_table->StdVoltageLoSidd = 1714 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 1715 } 1716 1717 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 1718 SMU7_Discrete_DpmTable *table) 1719 { 1720 struct ci_power_info *pi = ci_get_pi(rdev); 1721 unsigned int count; 1722 1723 table->VddcLevelCount = pi->vddc_voltage_table.count; 1724 for (count = 0; count < table->VddcLevelCount; count++) { 1725 ci_populate_smc_voltage_table(rdev, 1726 &pi->vddc_voltage_table.entries[count], 1727 &table->VddcLevel[count]); 1728 1729 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1730 table->VddcLevel[count].Smio |= 1731 pi->vddc_voltage_table.entries[count].smio_low; 1732 else 1733 table->VddcLevel[count].Smio = 0; 1734 } 1735 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 1736 1737 return 0; 1738 } 1739 1740 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 1741 SMU7_Discrete_DpmTable *table) 1742 { 1743 unsigned int count; 1744 struct ci_power_info *pi = ci_get_pi(rdev); 1745 1746 table->VddciLevelCount = pi->vddci_voltage_table.count; 1747 for (count = 0; count < table->VddciLevelCount; count++) { 1748 ci_populate_smc_voltage_table(rdev, 1749 &pi->vddci_voltage_table.entries[count], 1750 &table->VddciLevel[count]); 1751 1752 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1753 table->VddciLevel[count].Smio |= 1754 pi->vddci_voltage_table.entries[count].smio_low; 1755 else 1756 table->VddciLevel[count].Smio = 0; 1757 } 1758 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 1759 1760 return 0; 1761 } 1762 1763 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 1764 SMU7_Discrete_DpmTable *table) 1765 { 1766 struct ci_power_info *pi = ci_get_pi(rdev); 1767 unsigned int count; 1768 1769 table->MvddLevelCount = pi->mvdd_voltage_table.count; 1770 for (count = 0; count < table->MvddLevelCount; count++) { 1771 ci_populate_smc_voltage_table(rdev, 1772 &pi->mvdd_voltage_table.entries[count], 1773 &table->MvddLevel[count]); 1774 1775 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1776 table->MvddLevel[count].Smio |= 1777 pi->mvdd_voltage_table.entries[count].smio_low; 1778 else 1779 table->MvddLevel[count].Smio = 0; 1780 } 1781 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 1782 1783 return 0; 1784 } 1785 1786 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 1787 SMU7_Discrete_DpmTable *table) 1788 { 1789 int ret; 1790 1791 ret = ci_populate_smc_vddc_table(rdev, table); 1792 if (ret) 1793 return ret; 1794 1795 ret = ci_populate_smc_vddci_table(rdev, table); 1796 if (ret) 1797 return ret; 1798 1799 ret = ci_populate_smc_mvdd_table(rdev, table); 1800 if (ret) 1801 return ret; 1802 1803 return 0; 1804 } 1805 1806 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 1807 SMU7_Discrete_VoltageLevel *voltage) 1808 { 1809 struct ci_power_info *pi = ci_get_pi(rdev); 1810 u32 i = 0; 1811 1812 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 1813 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 1814 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 1815 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 1816 break; 1817 } 1818 } 1819 1820 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 1821 return -EINVAL; 1822 } 1823 1824 return -EINVAL; 1825 } 1826 1827 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 1828 struct atom_voltage_table_entry *voltage_table, 1829 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 1830 { 1831 u16 v_index, idx; 1832 bool voltage_found = false; 1833 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 1834 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 1835 1836 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 1837 return -EINVAL; 1838 1839 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 1840 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1841 if (voltage_table->value == 1842 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1843 voltage_found = true; 1844 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1845 idx = v_index; 1846 else 1847 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1848 *std_voltage_lo_sidd = 1849 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1850 *std_voltage_hi_sidd = 1851 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1852 break; 1853 } 1854 } 1855 1856 if (!voltage_found) { 1857 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1858 if (voltage_table->value <= 1859 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1860 voltage_found = true; 1861 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1862 idx = v_index; 1863 else 1864 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1865 *std_voltage_lo_sidd = 1866 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1867 *std_voltage_hi_sidd = 1868 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1869 break; 1870 } 1871 } 1872 } 1873 } 1874 1875 return 0; 1876 } 1877 1878 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 1879 const struct radeon_phase_shedding_limits_table *limits, 1880 u32 sclk, 1881 u32 *phase_shedding) 1882 { 1883 unsigned int i; 1884 1885 *phase_shedding = 1; 1886 1887 for (i = 0; i < limits->count; i++) { 1888 if (sclk < limits->entries[i].sclk) { 1889 *phase_shedding = i; 1890 break; 1891 } 1892 } 1893 } 1894 1895 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 1896 const struct radeon_phase_shedding_limits_table *limits, 1897 u32 mclk, 1898 u32 *phase_shedding) 1899 { 1900 unsigned int i; 1901 1902 *phase_shedding = 1; 1903 1904 for (i = 0; i < limits->count; i++) { 1905 if (mclk < limits->entries[i].mclk) { 1906 *phase_shedding = i; 1907 break; 1908 } 1909 } 1910 } 1911 1912 static int ci_init_arb_table_index(struct radeon_device *rdev) 1913 { 1914 struct ci_power_info *pi = ci_get_pi(rdev); 1915 u32 tmp; 1916 int ret; 1917 1918 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 1919 &tmp, pi->sram_end); 1920 if (ret) 1921 return ret; 1922 1923 tmp &= 0x00FFFFFF; 1924 tmp |= MC_CG_ARB_FREQ_F1 << 24; 1925 1926 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 1927 tmp, pi->sram_end); 1928 } 1929 1930 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 1931 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 1932 u32 clock, u32 *voltage) 1933 { 1934 u32 i = 0; 1935 1936 if (allowed_clock_voltage_table->count == 0) 1937 return -EINVAL; 1938 1939 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 1940 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 1941 *voltage = allowed_clock_voltage_table->entries[i].v; 1942 return 0; 1943 } 1944 } 1945 1946 *voltage = allowed_clock_voltage_table->entries[i-1].v; 1947 1948 return 0; 1949 } 1950 1951 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 1952 u32 sclk, u32 min_sclk_in_sr) 1953 { 1954 u32 i; 1955 u32 tmp; 1956 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 1957 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 1958 1959 if (sclk < min) 1960 return 0; 1961 1962 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 1963 tmp = sclk / (1 << i); 1964 if (tmp >= min || i == 0) 1965 break; 1966 } 1967 1968 return (u8)i; 1969 } 1970 1971 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 1972 { 1973 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 1974 } 1975 1976 static int ci_reset_to_default(struct radeon_device *rdev) 1977 { 1978 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 1979 0 : -EINVAL; 1980 } 1981 1982 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 1983 { 1984 u32 tmp; 1985 1986 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 1987 1988 if (tmp == MC_CG_ARB_FREQ_F0) 1989 return 0; 1990 1991 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 1992 } 1993 1994 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 1995 u32 sclk, 1996 u32 mclk, 1997 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 1998 { 1999 u32 dram_timing; 2000 u32 dram_timing2; 2001 u32 burst_time; 2002 2003 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2004 2005 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2006 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2007 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2008 2009 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2010 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2011 arb_regs->McArbBurstTime = (u8)burst_time; 2012 2013 return 0; 2014 } 2015 2016 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2017 { 2018 struct ci_power_info *pi = ci_get_pi(rdev); 2019 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2020 u32 i, j; 2021 int ret = 0; 2022 2023 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2024 2025 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2026 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2027 ret = ci_populate_memory_timing_parameters(rdev, 2028 pi->dpm_table.sclk_table.dpm_levels[i].value, 2029 pi->dpm_table.mclk_table.dpm_levels[j].value, 2030 &arb_regs.entries[i][j]); 2031 if (ret) 2032 break; 2033 } 2034 } 2035 2036 if (ret == 0) 2037 ret = ci_copy_bytes_to_smc(rdev, 2038 pi->arb_table_start, 2039 (u8 *)&arb_regs, 2040 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2041 pi->sram_end); 2042 2043 return ret; 2044 } 2045 2046 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2047 { 2048 struct ci_power_info *pi = ci_get_pi(rdev); 2049 2050 if (pi->need_update_smu7_dpm_table == 0) 2051 return 0; 2052 2053 return ci_do_program_memory_timing_parameters(rdev); 2054 } 2055 2056 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2057 struct radeon_ps *radeon_boot_state) 2058 { 2059 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2060 struct ci_power_info *pi = ci_get_pi(rdev); 2061 u32 level = 0; 2062 2063 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2064 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2065 boot_state->performance_levels[0].sclk) { 2066 pi->smc_state_table.GraphicsBootLevel = level; 2067 break; 2068 } 2069 } 2070 2071 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2072 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2073 boot_state->performance_levels[0].mclk) { 2074 pi->smc_state_table.MemoryBootLevel = level; 2075 break; 2076 } 2077 } 2078 } 2079 2080 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2081 { 2082 u32 i; 2083 u32 mask_value = 0; 2084 2085 for (i = dpm_table->count; i > 0; i--) { 2086 mask_value = mask_value << 1; 2087 if (dpm_table->dpm_levels[i-1].enabled) 2088 mask_value |= 0x1; 2089 else 2090 mask_value &= 0xFFFFFFFE; 2091 } 2092 2093 return mask_value; 2094 } 2095 2096 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2097 SMU7_Discrete_DpmTable *table) 2098 { 2099 struct ci_power_info *pi = ci_get_pi(rdev); 2100 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2101 u32 i; 2102 2103 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2104 table->LinkLevel[i].PcieGenSpeed = 2105 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2106 table->LinkLevel[i].PcieLaneCount = 2107 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2108 table->LinkLevel[i].EnabledForActivity = 1; 2109 table->LinkLevel[i].DownT = cpu_to_be32(5); 2110 table->LinkLevel[i].UpT = cpu_to_be32(30); 2111 } 2112 2113 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2114 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2115 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2116 } 2117 2118 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2119 SMU7_Discrete_DpmTable *table) 2120 { 2121 u32 count; 2122 struct atom_clock_dividers dividers; 2123 int ret = -EINVAL; 2124 2125 table->UvdLevelCount = 2126 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2127 2128 for (count = 0; count < table->UvdLevelCount; count++) { 2129 table->UvdLevel[count].VclkFrequency = 2130 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2131 table->UvdLevel[count].DclkFrequency = 2132 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2133 table->UvdLevel[count].MinVddc = 2134 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2135 table->UvdLevel[count].MinVddcPhases = 1; 2136 2137 ret = radeon_atom_get_clock_dividers(rdev, 2138 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2139 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2140 if (ret) 2141 return ret; 2142 2143 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2144 2145 ret = radeon_atom_get_clock_dividers(rdev, 2146 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2147 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2148 if (ret) 2149 return ret; 2150 2151 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2152 2153 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2154 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2155 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2156 } 2157 2158 return ret; 2159 } 2160 2161 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2162 SMU7_Discrete_DpmTable *table) 2163 { 2164 u32 count; 2165 struct atom_clock_dividers dividers; 2166 int ret = -EINVAL; 2167 2168 table->VceLevelCount = 2169 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2170 2171 for (count = 0; count < table->VceLevelCount; count++) { 2172 table->VceLevel[count].Frequency = 2173 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2174 table->VceLevel[count].MinVoltage = 2175 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2176 table->VceLevel[count].MinPhases = 1; 2177 2178 ret = radeon_atom_get_clock_dividers(rdev, 2179 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2180 table->VceLevel[count].Frequency, false, ÷rs); 2181 if (ret) 2182 return ret; 2183 2184 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2185 2186 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2187 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2188 } 2189 2190 return ret; 2191 2192 } 2193 2194 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2195 SMU7_Discrete_DpmTable *table) 2196 { 2197 u32 count; 2198 struct atom_clock_dividers dividers; 2199 int ret = -EINVAL; 2200 2201 table->AcpLevelCount = (u8) 2202 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2203 2204 for (count = 0; count < table->AcpLevelCount; count++) { 2205 table->AcpLevel[count].Frequency = 2206 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2207 table->AcpLevel[count].MinVoltage = 2208 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2209 table->AcpLevel[count].MinPhases = 1; 2210 2211 ret = radeon_atom_get_clock_dividers(rdev, 2212 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2213 table->AcpLevel[count].Frequency, false, ÷rs); 2214 if (ret) 2215 return ret; 2216 2217 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2218 2219 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2220 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2221 } 2222 2223 return ret; 2224 } 2225 2226 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2227 SMU7_Discrete_DpmTable *table) 2228 { 2229 u32 count; 2230 struct atom_clock_dividers dividers; 2231 int ret = -EINVAL; 2232 2233 table->SamuLevelCount = 2234 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2235 2236 for (count = 0; count < table->SamuLevelCount; count++) { 2237 table->SamuLevel[count].Frequency = 2238 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2239 table->SamuLevel[count].MinVoltage = 2240 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2241 table->SamuLevel[count].MinPhases = 1; 2242 2243 ret = radeon_atom_get_clock_dividers(rdev, 2244 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2245 table->SamuLevel[count].Frequency, false, ÷rs); 2246 if (ret) 2247 return ret; 2248 2249 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2250 2251 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2252 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2253 } 2254 2255 return ret; 2256 } 2257 2258 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2259 u32 memory_clock, 2260 SMU7_Discrete_MemoryLevel *mclk, 2261 bool strobe_mode, 2262 bool dll_state_on) 2263 { 2264 struct ci_power_info *pi = ci_get_pi(rdev); 2265 u32 dll_cntl = pi->clock_registers.dll_cntl; 2266 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2267 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2268 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2269 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2270 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2271 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2272 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2273 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2274 struct atom_mpll_param mpll_param; 2275 int ret; 2276 2277 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2278 if (ret) 2279 return ret; 2280 2281 mpll_func_cntl &= ~BWCTRL_MASK; 2282 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2283 2284 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2285 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2286 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2287 2288 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2289 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2290 2291 if (pi->mem_gddr5) { 2292 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2293 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2294 YCLK_POST_DIV(mpll_param.post_div); 2295 } 2296 2297 if (pi->caps_mclk_ss_support) { 2298 struct radeon_atom_ss ss; 2299 u32 freq_nom; 2300 u32 tmp; 2301 u32 reference_clock = rdev->clock.mpll.reference_freq; 2302 2303 if (pi->mem_gddr5) 2304 freq_nom = memory_clock * 4; 2305 else 2306 freq_nom = memory_clock * 2; 2307 2308 tmp = (freq_nom / reference_clock); 2309 tmp = tmp * tmp; 2310 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2311 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2312 u32 clks = reference_clock * 5 / ss.rate; 2313 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2314 2315 mpll_ss1 &= ~CLKV_MASK; 2316 mpll_ss1 |= CLKV(clkv); 2317 2318 mpll_ss2 &= ~CLKS_MASK; 2319 mpll_ss2 |= CLKS(clks); 2320 } 2321 } 2322 2323 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2324 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2325 2326 if (dll_state_on) 2327 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2328 else 2329 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2330 2331 mclk->MclkFrequency = memory_clock; 2332 mclk->MpllFuncCntl = mpll_func_cntl; 2333 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2334 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2335 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2336 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2337 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2338 mclk->DllCntl = dll_cntl; 2339 mclk->MpllSs1 = mpll_ss1; 2340 mclk->MpllSs2 = mpll_ss2; 2341 2342 return 0; 2343 } 2344 2345 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2346 u32 memory_clock, 2347 SMU7_Discrete_MemoryLevel *memory_level) 2348 { 2349 struct ci_power_info *pi = ci_get_pi(rdev); 2350 int ret; 2351 bool dll_state_on; 2352 2353 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2354 ret = ci_get_dependency_volt_by_clk(rdev, 2355 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2356 memory_clock, &memory_level->MinVddc); 2357 if (ret) 2358 return ret; 2359 } 2360 2361 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2362 ret = ci_get_dependency_volt_by_clk(rdev, 2363 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2364 memory_clock, &memory_level->MinVddci); 2365 if (ret) 2366 return ret; 2367 } 2368 2369 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2370 ret = ci_get_dependency_volt_by_clk(rdev, 2371 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2372 memory_clock, &memory_level->MinMvdd); 2373 if (ret) 2374 return ret; 2375 } 2376 2377 memory_level->MinVddcPhases = 1; 2378 2379 if (pi->vddc_phase_shed_control) 2380 ci_populate_phase_value_based_on_mclk(rdev, 2381 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2382 memory_clock, 2383 &memory_level->MinVddcPhases); 2384 2385 memory_level->EnabledForThrottle = 1; 2386 memory_level->EnabledForActivity = 1; 2387 memory_level->UpH = 0; 2388 memory_level->DownH = 100; 2389 memory_level->VoltageDownH = 0; 2390 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2391 2392 memory_level->StutterEnable = false; 2393 memory_level->StrobeEnable = false; 2394 memory_level->EdcReadEnable = false; 2395 memory_level->EdcWriteEnable = false; 2396 memory_level->RttEnable = false; 2397 2398 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2399 2400 if (pi->mclk_stutter_mode_threshold && 2401 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2402 (pi->uvd_enabled == false) && 2403 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2404 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2405 memory_level->StutterEnable = true; 2406 2407 if (pi->mclk_strobe_mode_threshold && 2408 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2409 memory_level->StrobeEnable = 1; 2410 2411 if (pi->mem_gddr5) { 2412 memory_level->StrobeRatio = 2413 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2414 if (pi->mclk_edc_enable_threshold && 2415 (memory_clock > pi->mclk_edc_enable_threshold)) 2416 memory_level->EdcReadEnable = true; 2417 2418 if (pi->mclk_edc_wr_enable_threshold && 2419 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2420 memory_level->EdcWriteEnable = true; 2421 2422 if (memory_level->StrobeEnable) { 2423 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2424 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2425 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2426 else 2427 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2428 } else { 2429 dll_state_on = pi->dll_default_on; 2430 } 2431 } else { 2432 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2433 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2434 } 2435 2436 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2437 if (ret) 2438 return ret; 2439 2440 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2441 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2442 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2443 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2444 2445 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2446 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2447 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2448 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2449 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2450 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2451 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2452 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2453 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2454 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2455 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2456 2457 return 0; 2458 } 2459 2460 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2461 SMU7_Discrete_DpmTable *table) 2462 { 2463 struct ci_power_info *pi = ci_get_pi(rdev); 2464 struct atom_clock_dividers dividers; 2465 SMU7_Discrete_VoltageLevel voltage_level; 2466 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2467 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2468 u32 dll_cntl = pi->clock_registers.dll_cntl; 2469 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2470 int ret; 2471 2472 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2473 2474 if (pi->acpi_vddc) 2475 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2476 else 2477 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2478 2479 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2480 2481 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2482 2483 ret = radeon_atom_get_clock_dividers(rdev, 2484 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2485 table->ACPILevel.SclkFrequency, false, ÷rs); 2486 if (ret) 2487 return ret; 2488 2489 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2490 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2491 table->ACPILevel.DeepSleepDivId = 0; 2492 2493 spll_func_cntl &= ~SPLL_PWRON; 2494 spll_func_cntl |= SPLL_RESET; 2495 2496 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2497 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 2498 2499 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 2500 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 2501 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 2502 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 2503 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 2504 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2505 table->ACPILevel.CcPwrDynRm = 0; 2506 table->ACPILevel.CcPwrDynRm1 = 0; 2507 2508 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 2509 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 2510 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 2511 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 2512 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 2513 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 2514 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 2515 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 2516 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 2517 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 2518 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 2519 2520 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 2521 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 2522 2523 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2524 if (pi->acpi_vddci) 2525 table->MemoryACPILevel.MinVddci = 2526 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 2527 else 2528 table->MemoryACPILevel.MinVddci = 2529 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 2530 } 2531 2532 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 2533 table->MemoryACPILevel.MinMvdd = 0; 2534 else 2535 table->MemoryACPILevel.MinMvdd = 2536 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 2537 2538 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 2539 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2540 2541 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 2542 2543 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 2544 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 2545 table->MemoryACPILevel.MpllAdFuncCntl = 2546 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 2547 table->MemoryACPILevel.MpllDqFuncCntl = 2548 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 2549 table->MemoryACPILevel.MpllFuncCntl = 2550 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 2551 table->MemoryACPILevel.MpllFuncCntl_1 = 2552 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 2553 table->MemoryACPILevel.MpllFuncCntl_2 = 2554 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 2555 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 2556 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 2557 2558 table->MemoryACPILevel.EnabledForThrottle = 0; 2559 table->MemoryACPILevel.EnabledForActivity = 0; 2560 table->MemoryACPILevel.UpH = 0; 2561 table->MemoryACPILevel.DownH = 100; 2562 table->MemoryACPILevel.VoltageDownH = 0; 2563 table->MemoryACPILevel.ActivityLevel = 2564 cpu_to_be16((u16)pi->mclk_activity_target); 2565 2566 table->MemoryACPILevel.StutterEnable = false; 2567 table->MemoryACPILevel.StrobeEnable = false; 2568 table->MemoryACPILevel.EdcReadEnable = false; 2569 table->MemoryACPILevel.EdcWriteEnable = false; 2570 table->MemoryACPILevel.RttEnable = false; 2571 2572 return 0; 2573 } 2574 2575 2576 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 2577 { 2578 struct ci_power_info *pi = ci_get_pi(rdev); 2579 struct ci_ulv_parm *ulv = &pi->ulv; 2580 2581 if (ulv->supported) { 2582 if (enable) 2583 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 2584 0 : -EINVAL; 2585 else 2586 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 2587 0 : -EINVAL; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static int ci_populate_ulv_level(struct radeon_device *rdev, 2594 SMU7_Discrete_Ulv *state) 2595 { 2596 struct ci_power_info *pi = ci_get_pi(rdev); 2597 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 2598 2599 state->CcPwrDynRm = 0; 2600 state->CcPwrDynRm1 = 0; 2601 2602 if (ulv_voltage == 0) { 2603 pi->ulv.supported = false; 2604 return 0; 2605 } 2606 2607 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2608 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2609 state->VddcOffset = 0; 2610 else 2611 state->VddcOffset = 2612 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 2613 } else { 2614 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2615 state->VddcOffsetVid = 0; 2616 else 2617 state->VddcOffsetVid = (u8) 2618 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 2619 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2620 } 2621 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 2622 2623 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 2624 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 2625 state->VddcOffset = cpu_to_be16(state->VddcOffset); 2626 2627 return 0; 2628 } 2629 2630 static int ci_calculate_sclk_params(struct radeon_device *rdev, 2631 u32 engine_clock, 2632 SMU7_Discrete_GraphicsLevel *sclk) 2633 { 2634 struct ci_power_info *pi = ci_get_pi(rdev); 2635 struct atom_clock_dividers dividers; 2636 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 2637 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 2638 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 2639 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2640 u32 reference_clock = rdev->clock.spll.reference_freq; 2641 u32 reference_divider; 2642 u32 fbdiv; 2643 int ret; 2644 2645 ret = radeon_atom_get_clock_dividers(rdev, 2646 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2647 engine_clock, false, ÷rs); 2648 if (ret) 2649 return ret; 2650 2651 reference_divider = 1 + dividers.ref_div; 2652 fbdiv = dividers.fb_div & 0x3FFFFFF; 2653 2654 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 2655 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 2656 spll_func_cntl_3 |= SPLL_DITHEN; 2657 2658 if (pi->caps_sclk_ss_support) { 2659 struct radeon_atom_ss ss; 2660 u32 vco_freq = engine_clock * dividers.post_div; 2661 2662 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2663 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 2664 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 2665 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 2666 2667 cg_spll_spread_spectrum &= ~CLK_S_MASK; 2668 cg_spll_spread_spectrum |= CLK_S(clk_s); 2669 cg_spll_spread_spectrum |= SSEN; 2670 2671 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 2672 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 2673 } 2674 } 2675 2676 sclk->SclkFrequency = engine_clock; 2677 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 2678 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 2679 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 2680 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 2681 sclk->SclkDid = (u8)dividers.post_divider; 2682 2683 return 0; 2684 } 2685 2686 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 2687 u32 engine_clock, 2688 u16 sclk_activity_level_t, 2689 SMU7_Discrete_GraphicsLevel *graphic_level) 2690 { 2691 struct ci_power_info *pi = ci_get_pi(rdev); 2692 int ret; 2693 2694 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 2695 if (ret) 2696 return ret; 2697 2698 ret = ci_get_dependency_volt_by_clk(rdev, 2699 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2700 engine_clock, &graphic_level->MinVddc); 2701 if (ret) 2702 return ret; 2703 2704 graphic_level->SclkFrequency = engine_clock; 2705 2706 graphic_level->Flags = 0; 2707 graphic_level->MinVddcPhases = 1; 2708 2709 if (pi->vddc_phase_shed_control) 2710 ci_populate_phase_value_based_on_sclk(rdev, 2711 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2712 engine_clock, 2713 &graphic_level->MinVddcPhases); 2714 2715 graphic_level->ActivityLevel = sclk_activity_level_t; 2716 2717 graphic_level->CcPwrDynRm = 0; 2718 graphic_level->CcPwrDynRm1 = 0; 2719 graphic_level->EnabledForActivity = 1; 2720 graphic_level->EnabledForThrottle = 1; 2721 graphic_level->UpH = 0; 2722 graphic_level->DownH = 0; 2723 graphic_level->VoltageDownH = 0; 2724 graphic_level->PowerThrottle = 0; 2725 2726 if (pi->caps_sclk_ds) 2727 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 2728 engine_clock, 2729 CISLAND_MINIMUM_ENGINE_CLOCK); 2730 2731 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2732 2733 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 2734 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 2735 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 2736 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 2737 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 2738 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 2739 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 2740 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 2741 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 2742 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 2743 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 2744 2745 return 0; 2746 } 2747 2748 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 2749 { 2750 struct ci_power_info *pi = ci_get_pi(rdev); 2751 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2752 u32 level_array_address = pi->dpm_table_start + 2753 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 2754 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 2755 SMU7_MAX_LEVELS_GRAPHICS; 2756 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 2757 u32 i, ret; 2758 2759 memset(levels, 0, level_array_size); 2760 2761 for (i = 0; i < dpm_table->sclk_table.count; i++) { 2762 ret = ci_populate_single_graphic_level(rdev, 2763 dpm_table->sclk_table.dpm_levels[i].value, 2764 (u16)pi->activity_target[i], 2765 &pi->smc_state_table.GraphicsLevel[i]); 2766 if (ret) 2767 return ret; 2768 if (i == (dpm_table->sclk_table.count - 1)) 2769 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 2770 PPSMC_DISPLAY_WATERMARK_HIGH; 2771 } 2772 2773 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 2774 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 2775 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 2776 2777 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2778 (u8 *)levels, level_array_size, 2779 pi->sram_end); 2780 if (ret) 2781 return ret; 2782 2783 return 0; 2784 } 2785 2786 static int ci_populate_ulv_state(struct radeon_device *rdev, 2787 SMU7_Discrete_Ulv *ulv_level) 2788 { 2789 return ci_populate_ulv_level(rdev, ulv_level); 2790 } 2791 2792 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 2793 { 2794 struct ci_power_info *pi = ci_get_pi(rdev); 2795 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2796 u32 level_array_address = pi->dpm_table_start + 2797 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 2798 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 2799 SMU7_MAX_LEVELS_MEMORY; 2800 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 2801 u32 i, ret; 2802 2803 memset(levels, 0, level_array_size); 2804 2805 for (i = 0; i < dpm_table->mclk_table.count; i++) { 2806 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 2807 return -EINVAL; 2808 ret = ci_populate_single_memory_level(rdev, 2809 dpm_table->mclk_table.dpm_levels[i].value, 2810 &pi->smc_state_table.MemoryLevel[i]); 2811 if (ret) 2812 return ret; 2813 } 2814 2815 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 2816 2817 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 2818 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 2819 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 2820 2821 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 2822 PPSMC_DISPLAY_WATERMARK_HIGH; 2823 2824 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2825 (u8 *)levels, level_array_size, 2826 pi->sram_end); 2827 if (ret) 2828 return ret; 2829 2830 return 0; 2831 } 2832 2833 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 2834 struct ci_single_dpm_table* dpm_table, 2835 u32 count) 2836 { 2837 u32 i; 2838 2839 dpm_table->count = count; 2840 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 2841 dpm_table->dpm_levels[i].enabled = false; 2842 } 2843 2844 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, 2845 u32 index, u32 pcie_gen, u32 pcie_lanes) 2846 { 2847 dpm_table->dpm_levels[index].value = pcie_gen; 2848 dpm_table->dpm_levels[index].param1 = pcie_lanes; 2849 dpm_table->dpm_levels[index].enabled = true; 2850 } 2851 2852 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 2853 { 2854 struct ci_power_info *pi = ci_get_pi(rdev); 2855 2856 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 2857 return -EINVAL; 2858 2859 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 2860 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 2861 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 2862 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 2863 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 2864 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 2865 } 2866 2867 ci_reset_single_dpm_table(rdev, 2868 &pi->dpm_table.pcie_speed_table, 2869 SMU7_MAX_LEVELS_LINK); 2870 2871 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 2872 pi->pcie_gen_powersaving.min, 2873 pi->pcie_lane_powersaving.min); 2874 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 2875 pi->pcie_gen_performance.min, 2876 pi->pcie_lane_performance.min); 2877 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 2878 pi->pcie_gen_powersaving.min, 2879 pi->pcie_lane_powersaving.max); 2880 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 2881 pi->pcie_gen_performance.min, 2882 pi->pcie_lane_performance.max); 2883 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 2884 pi->pcie_gen_powersaving.max, 2885 pi->pcie_lane_powersaving.max); 2886 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 2887 pi->pcie_gen_performance.max, 2888 pi->pcie_lane_performance.max); 2889 2890 pi->dpm_table.pcie_speed_table.count = 6; 2891 2892 return 0; 2893 } 2894 2895 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 2896 { 2897 struct ci_power_info *pi = ci_get_pi(rdev); 2898 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 2899 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2900 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 2901 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 2902 struct radeon_cac_leakage_table *std_voltage_table = 2903 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2904 u32 i; 2905 2906 if (allowed_sclk_vddc_table == NULL) 2907 return -EINVAL; 2908 if (allowed_sclk_vddc_table->count < 1) 2909 return -EINVAL; 2910 if (allowed_mclk_table == NULL) 2911 return -EINVAL; 2912 if (allowed_mclk_table->count < 1) 2913 return -EINVAL; 2914 2915 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 2916 2917 ci_reset_single_dpm_table(rdev, 2918 &pi->dpm_table.sclk_table, 2919 SMU7_MAX_LEVELS_GRAPHICS); 2920 ci_reset_single_dpm_table(rdev, 2921 &pi->dpm_table.mclk_table, 2922 SMU7_MAX_LEVELS_MEMORY); 2923 ci_reset_single_dpm_table(rdev, 2924 &pi->dpm_table.vddc_table, 2925 SMU7_MAX_LEVELS_VDDC); 2926 ci_reset_single_dpm_table(rdev, 2927 &pi->dpm_table.vddci_table, 2928 SMU7_MAX_LEVELS_VDDCI); 2929 ci_reset_single_dpm_table(rdev, 2930 &pi->dpm_table.mvdd_table, 2931 SMU7_MAX_LEVELS_MVDD); 2932 2933 pi->dpm_table.sclk_table.count = 0; 2934 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2935 if ((i == 0) || 2936 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 2937 allowed_sclk_vddc_table->entries[i].clk)) { 2938 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 2939 allowed_sclk_vddc_table->entries[i].clk; 2940 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true; 2941 pi->dpm_table.sclk_table.count++; 2942 } 2943 } 2944 2945 pi->dpm_table.mclk_table.count = 0; 2946 for (i = 0; i < allowed_mclk_table->count; i++) { 2947 if ((i==0) || 2948 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 2949 allowed_mclk_table->entries[i].clk)) { 2950 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 2951 allowed_mclk_table->entries[i].clk; 2952 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true; 2953 pi->dpm_table.mclk_table.count++; 2954 } 2955 } 2956 2957 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2958 pi->dpm_table.vddc_table.dpm_levels[i].value = 2959 allowed_sclk_vddc_table->entries[i].v; 2960 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 2961 std_voltage_table->entries[i].leakage; 2962 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 2963 } 2964 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 2965 2966 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 2967 if (allowed_mclk_table) { 2968 for (i = 0; i < allowed_mclk_table->count; i++) { 2969 pi->dpm_table.vddci_table.dpm_levels[i].value = 2970 allowed_mclk_table->entries[i].v; 2971 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 2972 } 2973 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 2974 } 2975 2976 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 2977 if (allowed_mclk_table) { 2978 for (i = 0; i < allowed_mclk_table->count; i++) { 2979 pi->dpm_table.mvdd_table.dpm_levels[i].value = 2980 allowed_mclk_table->entries[i].v; 2981 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 2982 } 2983 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 2984 } 2985 2986 ci_setup_default_pcie_tables(rdev); 2987 2988 return 0; 2989 } 2990 2991 static int ci_find_boot_level(struct ci_single_dpm_table *table, 2992 u32 value, u32 *boot_level) 2993 { 2994 u32 i; 2995 int ret = -EINVAL; 2996 2997 for(i = 0; i < table->count; i++) { 2998 if (value == table->dpm_levels[i].value) { 2999 *boot_level = i; 3000 ret = 0; 3001 } 3002 } 3003 3004 return ret; 3005 } 3006 3007 static int ci_init_smc_table(struct radeon_device *rdev) 3008 { 3009 struct ci_power_info *pi = ci_get_pi(rdev); 3010 struct ci_ulv_parm *ulv = &pi->ulv; 3011 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3012 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3013 int ret; 3014 3015 ret = ci_setup_default_dpm_tables(rdev); 3016 if (ret) 3017 return ret; 3018 3019 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3020 ci_populate_smc_voltage_tables(rdev, table); 3021 3022 ci_init_fps_limits(rdev); 3023 3024 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3025 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3026 3027 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3028 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3029 3030 if (pi->mem_gddr5) 3031 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3032 3033 if (ulv->supported) { 3034 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3035 if (ret) 3036 return ret; 3037 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3038 } 3039 3040 ret = ci_populate_all_graphic_levels(rdev); 3041 if (ret) 3042 return ret; 3043 3044 ret = ci_populate_all_memory_levels(rdev); 3045 if (ret) 3046 return ret; 3047 3048 ci_populate_smc_link_level(rdev, table); 3049 3050 ret = ci_populate_smc_acpi_level(rdev, table); 3051 if (ret) 3052 return ret; 3053 3054 ret = ci_populate_smc_vce_level(rdev, table); 3055 if (ret) 3056 return ret; 3057 3058 ret = ci_populate_smc_acp_level(rdev, table); 3059 if (ret) 3060 return ret; 3061 3062 ret = ci_populate_smc_samu_level(rdev, table); 3063 if (ret) 3064 return ret; 3065 3066 ret = ci_do_program_memory_timing_parameters(rdev); 3067 if (ret) 3068 return ret; 3069 3070 ret = ci_populate_smc_uvd_level(rdev, table); 3071 if (ret) 3072 return ret; 3073 3074 table->UvdBootLevel = 0; 3075 table->VceBootLevel = 0; 3076 table->AcpBootLevel = 0; 3077 table->SamuBootLevel = 0; 3078 table->GraphicsBootLevel = 0; 3079 table->MemoryBootLevel = 0; 3080 3081 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3082 pi->vbios_boot_state.sclk_bootup_value, 3083 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3084 3085 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3086 pi->vbios_boot_state.mclk_bootup_value, 3087 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3088 3089 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3090 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3091 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3092 3093 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3094 3095 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3096 if (ret) 3097 return ret; 3098 3099 table->UVDInterval = 1; 3100 table->VCEInterval = 1; 3101 table->ACPInterval = 1; 3102 table->SAMUInterval = 1; 3103 table->GraphicsVoltageChangeEnable = 1; 3104 table->GraphicsThermThrottleEnable = 1; 3105 table->GraphicsInterval = 1; 3106 table->VoltageInterval = 1; 3107 table->ThermalInterval = 1; 3108 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3109 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3110 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3111 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3112 table->MemoryVoltageChangeEnable = 1; 3113 table->MemoryInterval = 1; 3114 table->VoltageResponseTime = 0; 3115 table->VddcVddciDelta = 4000; 3116 table->PhaseResponseTime = 0; 3117 table->MemoryThermThrottleEnable = 1; 3118 table->PCIeBootLinkLevel = 0; 3119 table->PCIeGenInterval = 1; 3120 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3121 table->SVI2Enable = 1; 3122 else 3123 table->SVI2Enable = 0; 3124 3125 table->ThermGpio = 17; 3126 table->SclkStepSize = 0x4000; 3127 3128 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3129 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3130 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3131 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3132 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3133 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3134 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3135 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3136 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3137 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3138 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3139 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3140 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3141 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3142 3143 ret = ci_copy_bytes_to_smc(rdev, 3144 pi->dpm_table_start + 3145 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3146 (u8 *)&table->SystemFlags, 3147 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3148 pi->sram_end); 3149 if (ret) 3150 return ret; 3151 3152 return 0; 3153 } 3154 3155 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3156 struct ci_single_dpm_table *dpm_table, 3157 u32 low_limit, u32 high_limit) 3158 { 3159 u32 i; 3160 3161 for (i = 0; i < dpm_table->count; i++) { 3162 if ((dpm_table->dpm_levels[i].value < low_limit) || 3163 (dpm_table->dpm_levels[i].value > high_limit)) 3164 dpm_table->dpm_levels[i].enabled = false; 3165 else 3166 dpm_table->dpm_levels[i].enabled = true; 3167 } 3168 } 3169 3170 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3171 u32 speed_low, u32 lanes_low, 3172 u32 speed_high, u32 lanes_high) 3173 { 3174 struct ci_power_info *pi = ci_get_pi(rdev); 3175 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3176 u32 i, j; 3177 3178 for (i = 0; i < pcie_table->count; i++) { 3179 if ((pcie_table->dpm_levels[i].value < speed_low) || 3180 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3181 (pcie_table->dpm_levels[i].value > speed_high) || 3182 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3183 pcie_table->dpm_levels[i].enabled = false; 3184 else 3185 pcie_table->dpm_levels[i].enabled = true; 3186 } 3187 3188 for (i = 0; i < pcie_table->count; i++) { 3189 if (pcie_table->dpm_levels[i].enabled) { 3190 for (j = i + 1; j < pcie_table->count; j++) { 3191 if (pcie_table->dpm_levels[j].enabled) { 3192 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3193 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3194 pcie_table->dpm_levels[j].enabled = false; 3195 } 3196 } 3197 } 3198 } 3199 } 3200 3201 static int ci_trim_dpm_states(struct radeon_device *rdev, 3202 struct radeon_ps *radeon_state) 3203 { 3204 struct ci_ps *state = ci_get_ps(radeon_state); 3205 struct ci_power_info *pi = ci_get_pi(rdev); 3206 u32 high_limit_count; 3207 3208 if (state->performance_level_count < 1) 3209 return -EINVAL; 3210 3211 if (state->performance_level_count == 1) 3212 high_limit_count = 0; 3213 else 3214 high_limit_count = 1; 3215 3216 ci_trim_single_dpm_states(rdev, 3217 &pi->dpm_table.sclk_table, 3218 state->performance_levels[0].sclk, 3219 state->performance_levels[high_limit_count].sclk); 3220 3221 ci_trim_single_dpm_states(rdev, 3222 &pi->dpm_table.mclk_table, 3223 state->performance_levels[0].mclk, 3224 state->performance_levels[high_limit_count].mclk); 3225 3226 ci_trim_pcie_dpm_states(rdev, 3227 state->performance_levels[0].pcie_gen, 3228 state->performance_levels[0].pcie_lane, 3229 state->performance_levels[high_limit_count].pcie_gen, 3230 state->performance_levels[high_limit_count].pcie_lane); 3231 3232 return 0; 3233 } 3234 3235 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3236 { 3237 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3238 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3239 struct radeon_clock_voltage_dependency_table *vddc_table = 3240 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3241 u32 requested_voltage = 0; 3242 u32 i; 3243 3244 if (disp_voltage_table == NULL) 3245 return -EINVAL; 3246 if (!disp_voltage_table->count) 3247 return -EINVAL; 3248 3249 for (i = 0; i < disp_voltage_table->count; i++) { 3250 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3251 requested_voltage = disp_voltage_table->entries[i].v; 3252 } 3253 3254 for (i = 0; i < vddc_table->count; i++) { 3255 if (requested_voltage <= vddc_table->entries[i].v) { 3256 requested_voltage = vddc_table->entries[i].v; 3257 return (ci_send_msg_to_smc_with_parameter(rdev, 3258 PPSMC_MSG_VddC_Request, 3259 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3260 0 : -EINVAL; 3261 } 3262 } 3263 3264 return -EINVAL; 3265 } 3266 3267 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3268 { 3269 struct ci_power_info *pi = ci_get_pi(rdev); 3270 PPSMC_Result result; 3271 3272 if (!pi->sclk_dpm_key_disabled) { 3273 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3274 result = ci_send_msg_to_smc_with_parameter(rdev, 3275 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3276 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3277 if (result != PPSMC_Result_OK) 3278 return -EINVAL; 3279 } 3280 } 3281 3282 if (!pi->mclk_dpm_key_disabled) { 3283 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3284 result = ci_send_msg_to_smc_with_parameter(rdev, 3285 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3286 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3287 if (result != PPSMC_Result_OK) 3288 return -EINVAL; 3289 } 3290 } 3291 3292 if (!pi->pcie_dpm_key_disabled) { 3293 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3294 result = ci_send_msg_to_smc_with_parameter(rdev, 3295 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3296 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3297 if (result != PPSMC_Result_OK) 3298 return -EINVAL; 3299 } 3300 } 3301 3302 ci_apply_disp_minimum_voltage_request(rdev); 3303 3304 return 0; 3305 } 3306 3307 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3308 struct radeon_ps *radeon_state) 3309 { 3310 struct ci_power_info *pi = ci_get_pi(rdev); 3311 struct ci_ps *state = ci_get_ps(radeon_state); 3312 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3313 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3314 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3315 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3316 u32 i; 3317 3318 pi->need_update_smu7_dpm_table = 0; 3319 3320 for (i = 0; i < sclk_table->count; i++) { 3321 if (sclk == sclk_table->dpm_levels[i].value) 3322 break; 3323 } 3324 3325 if (i >= sclk_table->count) { 3326 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3327 } else { 3328 /* XXX check display min clock requirements */ 3329 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK) 3330 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3331 } 3332 3333 for (i = 0; i < mclk_table->count; i++) { 3334 if (mclk == mclk_table->dpm_levels[i].value) 3335 break; 3336 } 3337 3338 if (i >= mclk_table->count) 3339 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3340 3341 if (rdev->pm.dpm.current_active_crtc_count != 3342 rdev->pm.dpm.new_active_crtc_count) 3343 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3344 } 3345 3346 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3347 struct radeon_ps *radeon_state) 3348 { 3349 struct ci_power_info *pi = ci_get_pi(rdev); 3350 struct ci_ps *state = ci_get_ps(radeon_state); 3351 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3352 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3353 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3354 int ret; 3355 3356 if (!pi->need_update_smu7_dpm_table) 3357 return 0; 3358 3359 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3360 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3361 3362 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3363 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3364 3365 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3366 ret = ci_populate_all_graphic_levels(rdev); 3367 if (ret) 3368 return ret; 3369 } 3370 3371 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3372 ret = ci_populate_all_memory_levels(rdev); 3373 if (ret) 3374 return ret; 3375 } 3376 3377 return 0; 3378 } 3379 3380 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3381 { 3382 struct ci_power_info *pi = ci_get_pi(rdev); 3383 const struct radeon_clock_and_voltage_limits *max_limits; 3384 int i; 3385 3386 if (rdev->pm.dpm.ac_power) 3387 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3388 else 3389 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3390 3391 if (enable) { 3392 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3393 3394 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3395 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3396 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3397 3398 if (!pi->caps_uvd_dpm) 3399 break; 3400 } 3401 } 3402 3403 ci_send_msg_to_smc_with_parameter(rdev, 3404 PPSMC_MSG_UVDDPM_SetEnabledMask, 3405 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3406 3407 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3408 pi->uvd_enabled = true; 3409 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3410 ci_send_msg_to_smc_with_parameter(rdev, 3411 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3412 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3413 } 3414 } else { 3415 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3416 pi->uvd_enabled = false; 3417 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3418 ci_send_msg_to_smc_with_parameter(rdev, 3419 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3420 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3421 } 3422 } 3423 3424 return (ci_send_msg_to_smc(rdev, enable ? 3425 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3426 0 : -EINVAL; 3427 } 3428 3429 #if 0 3430 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3431 { 3432 struct ci_power_info *pi = ci_get_pi(rdev); 3433 const struct radeon_clock_and_voltage_limits *max_limits; 3434 int i; 3435 3436 if (rdev->pm.dpm.ac_power) 3437 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3438 else 3439 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3440 3441 if (enable) { 3442 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3443 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3444 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3445 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3446 3447 if (!pi->caps_vce_dpm) 3448 break; 3449 } 3450 } 3451 3452 ci_send_msg_to_smc_with_parameter(rdev, 3453 PPSMC_MSG_VCEDPM_SetEnabledMask, 3454 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3455 } 3456 3457 return (ci_send_msg_to_smc(rdev, enable ? 3458 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 3459 0 : -EINVAL; 3460 } 3461 3462 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 3463 { 3464 struct ci_power_info *pi = ci_get_pi(rdev); 3465 const struct radeon_clock_and_voltage_limits *max_limits; 3466 int i; 3467 3468 if (rdev->pm.dpm.ac_power) 3469 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3470 else 3471 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3472 3473 if (enable) { 3474 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 3475 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3476 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3477 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 3478 3479 if (!pi->caps_samu_dpm) 3480 break; 3481 } 3482 } 3483 3484 ci_send_msg_to_smc_with_parameter(rdev, 3485 PPSMC_MSG_SAMUDPM_SetEnabledMask, 3486 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 3487 } 3488 return (ci_send_msg_to_smc(rdev, enable ? 3489 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 3490 0 : -EINVAL; 3491 } 3492 3493 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 3494 { 3495 struct ci_power_info *pi = ci_get_pi(rdev); 3496 const struct radeon_clock_and_voltage_limits *max_limits; 3497 int i; 3498 3499 if (rdev->pm.dpm.ac_power) 3500 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3501 else 3502 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3503 3504 if (enable) { 3505 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 3506 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3507 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3508 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 3509 3510 if (!pi->caps_acp_dpm) 3511 break; 3512 } 3513 } 3514 3515 ci_send_msg_to_smc_with_parameter(rdev, 3516 PPSMC_MSG_ACPDPM_SetEnabledMask, 3517 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 3518 } 3519 3520 return (ci_send_msg_to_smc(rdev, enable ? 3521 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 3522 0 : -EINVAL; 3523 } 3524 #endif 3525 3526 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 3527 { 3528 struct ci_power_info *pi = ci_get_pi(rdev); 3529 u32 tmp; 3530 3531 if (!gate) { 3532 if (pi->caps_uvd_dpm || 3533 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 3534 pi->smc_state_table.UvdBootLevel = 0; 3535 else 3536 pi->smc_state_table.UvdBootLevel = 3537 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 3538 3539 tmp = RREG32_SMC(DPM_TABLE_475); 3540 tmp &= ~UvdBootLevel_MASK; 3541 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 3542 WREG32_SMC(DPM_TABLE_475, tmp); 3543 } 3544 3545 return ci_enable_uvd_dpm(rdev, !gate); 3546 } 3547 3548 #if 0 3549 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 3550 { 3551 u8 i; 3552 u32 min_evclk = 30000; /* ??? */ 3553 struct radeon_vce_clock_voltage_dependency_table *table = 3554 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3555 3556 for (i = 0; i < table->count; i++) { 3557 if (table->entries[i].evclk >= min_evclk) 3558 return i; 3559 } 3560 3561 return table->count - 1; 3562 } 3563 3564 static int ci_update_vce_dpm(struct radeon_device *rdev, 3565 struct radeon_ps *radeon_new_state, 3566 struct radeon_ps *radeon_current_state) 3567 { 3568 struct ci_power_info *pi = ci_get_pi(rdev); 3569 bool new_vce_clock_non_zero = (radeon_new_state->evclk != 0); 3570 bool old_vce_clock_non_zero = (radeon_current_state->evclk != 0); 3571 int ret = 0; 3572 u32 tmp; 3573 3574 if (new_vce_clock_non_zero != old_vce_clock_non_zero) { 3575 if (new_vce_clock_non_zero) { 3576 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 3577 3578 tmp = RREG32_SMC(DPM_TABLE_475); 3579 tmp &= ~VceBootLevel_MASK; 3580 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 3581 WREG32_SMC(DPM_TABLE_475, tmp); 3582 3583 ret = ci_enable_vce_dpm(rdev, true); 3584 } else { 3585 ret = ci_enable_vce_dpm(rdev, false); 3586 } 3587 } 3588 return ret; 3589 } 3590 3591 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 3592 { 3593 return ci_enable_samu_dpm(rdev, gate); 3594 } 3595 3596 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 3597 { 3598 struct ci_power_info *pi = ci_get_pi(rdev); 3599 u32 tmp; 3600 3601 if (!gate) { 3602 pi->smc_state_table.AcpBootLevel = 0; 3603 3604 tmp = RREG32_SMC(DPM_TABLE_475); 3605 tmp &= ~AcpBootLevel_MASK; 3606 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 3607 WREG32_SMC(DPM_TABLE_475, tmp); 3608 } 3609 3610 return ci_enable_acp_dpm(rdev, !gate); 3611 } 3612 #endif 3613 3614 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 3615 struct radeon_ps *radeon_state) 3616 { 3617 struct ci_power_info *pi = ci_get_pi(rdev); 3618 int ret; 3619 3620 ret = ci_trim_dpm_states(rdev, radeon_state); 3621 if (ret) 3622 return ret; 3623 3624 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3625 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 3626 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3627 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 3628 pi->last_mclk_dpm_enable_mask = 3629 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3630 if (pi->uvd_enabled) { 3631 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 3632 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3633 } 3634 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 3635 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 3636 3637 return 0; 3638 } 3639 3640 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 3641 u32 level_mask) 3642 { 3643 u32 level = 0; 3644 3645 while ((level_mask & (1 << level)) == 0) 3646 level++; 3647 3648 return level; 3649 } 3650 3651 3652 int ci_dpm_force_performance_level(struct radeon_device *rdev, 3653 enum radeon_dpm_forced_level level) 3654 { 3655 struct ci_power_info *pi = ci_get_pi(rdev); 3656 PPSMC_Result smc_result; 3657 u32 tmp, levels, i; 3658 int ret; 3659 3660 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3661 if ((!pi->sclk_dpm_key_disabled) && 3662 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3663 levels = 0; 3664 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 3665 while (tmp >>= 1) 3666 levels++; 3667 if (levels) { 3668 ret = ci_dpm_force_state_sclk(rdev, levels); 3669 if (ret) 3670 return ret; 3671 for (i = 0; i < rdev->usec_timeout; i++) { 3672 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3673 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3674 if (tmp == levels) 3675 break; 3676 udelay(1); 3677 } 3678 } 3679 } 3680 if ((!pi->mclk_dpm_key_disabled) && 3681 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3682 levels = 0; 3683 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3684 while (tmp >>= 1) 3685 levels++; 3686 if (levels) { 3687 ret = ci_dpm_force_state_mclk(rdev, levels); 3688 if (ret) 3689 return ret; 3690 for (i = 0; i < rdev->usec_timeout; i++) { 3691 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3692 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3693 if (tmp == levels) 3694 break; 3695 udelay(1); 3696 } 3697 } 3698 } 3699 if ((!pi->pcie_dpm_key_disabled) && 3700 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3701 levels = 0; 3702 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 3703 while (tmp >>= 1) 3704 levels++; 3705 if (levels) { 3706 ret = ci_dpm_force_state_pcie(rdev, level); 3707 if (ret) 3708 return ret; 3709 for (i = 0; i < rdev->usec_timeout; i++) { 3710 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3711 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3712 if (tmp == levels) 3713 break; 3714 udelay(1); 3715 } 3716 } 3717 } 3718 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3719 if ((!pi->sclk_dpm_key_disabled) && 3720 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3721 levels = ci_get_lowest_enabled_level(rdev, 3722 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3723 ret = ci_dpm_force_state_sclk(rdev, levels); 3724 if (ret) 3725 return ret; 3726 for (i = 0; i < rdev->usec_timeout; i++) { 3727 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3728 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3729 if (tmp == levels) 3730 break; 3731 udelay(1); 3732 } 3733 } 3734 if ((!pi->mclk_dpm_key_disabled) && 3735 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3736 levels = ci_get_lowest_enabled_level(rdev, 3737 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3738 ret = ci_dpm_force_state_mclk(rdev, levels); 3739 if (ret) 3740 return ret; 3741 for (i = 0; i < rdev->usec_timeout; i++) { 3742 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3743 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3744 if (tmp == levels) 3745 break; 3746 udelay(1); 3747 } 3748 } 3749 if ((!pi->pcie_dpm_key_disabled) && 3750 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3751 levels = ci_get_lowest_enabled_level(rdev, 3752 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3753 ret = ci_dpm_force_state_pcie(rdev, levels); 3754 if (ret) 3755 return ret; 3756 for (i = 0; i < rdev->usec_timeout; i++) { 3757 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3758 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3759 if (tmp == levels) 3760 break; 3761 udelay(1); 3762 } 3763 } 3764 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3765 if (!pi->sclk_dpm_key_disabled) { 3766 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel); 3767 if (smc_result != PPSMC_Result_OK) 3768 return -EINVAL; 3769 } 3770 if (!pi->mclk_dpm_key_disabled) { 3771 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel); 3772 if (smc_result != PPSMC_Result_OK) 3773 return -EINVAL; 3774 } 3775 if (!pi->pcie_dpm_key_disabled) { 3776 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel); 3777 if (smc_result != PPSMC_Result_OK) 3778 return -EINVAL; 3779 } 3780 } 3781 3782 rdev->pm.dpm.forced_level = level; 3783 3784 return 0; 3785 } 3786 3787 static int ci_set_mc_special_registers(struct radeon_device *rdev, 3788 struct ci_mc_reg_table *table) 3789 { 3790 struct ci_power_info *pi = ci_get_pi(rdev); 3791 u8 i, j, k; 3792 u32 temp_reg; 3793 3794 for (i = 0, j = table->last; i < table->last; i++) { 3795 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3796 return -EINVAL; 3797 switch(table->mc_reg_address[i].s1 << 2) { 3798 case MC_SEQ_MISC1: 3799 temp_reg = RREG32(MC_PMG_CMD_EMRS); 3800 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 3801 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3802 for (k = 0; k < table->num_entries; k++) { 3803 table->mc_reg_table_entry[k].mc_data[j] = 3804 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 3805 } 3806 j++; 3807 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3808 return -EINVAL; 3809 3810 temp_reg = RREG32(MC_PMG_CMD_MRS); 3811 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 3812 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3813 for (k = 0; k < table->num_entries; k++) { 3814 table->mc_reg_table_entry[k].mc_data[j] = 3815 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3816 if (!pi->mem_gddr5) 3817 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 3818 } 3819 j++; 3820 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3821 return -EINVAL; 3822 3823 if (!pi->mem_gddr5) { 3824 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 3825 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 3826 for (k = 0; k < table->num_entries; k++) { 3827 table->mc_reg_table_entry[k].mc_data[j] = 3828 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 3829 } 3830 j++; 3831 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3832 return -EINVAL; 3833 } 3834 break; 3835 case MC_SEQ_RESERVE_M: 3836 temp_reg = RREG32(MC_PMG_CMD_MRS1); 3837 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 3838 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3839 for (k = 0; k < table->num_entries; k++) { 3840 table->mc_reg_table_entry[k].mc_data[j] = 3841 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3842 } 3843 j++; 3844 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3845 return -EINVAL; 3846 break; 3847 default: 3848 break; 3849 } 3850 3851 } 3852 3853 table->last = j; 3854 3855 return 0; 3856 } 3857 3858 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 3859 { 3860 bool result = true; 3861 3862 switch(in_reg) { 3863 case MC_SEQ_RAS_TIMING >> 2: 3864 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 3865 break; 3866 case MC_SEQ_DLL_STBY >> 2: 3867 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 3868 break; 3869 case MC_SEQ_G5PDX_CMD0 >> 2: 3870 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 3871 break; 3872 case MC_SEQ_G5PDX_CMD1 >> 2: 3873 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 3874 break; 3875 case MC_SEQ_G5PDX_CTRL >> 2: 3876 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 3877 break; 3878 case MC_SEQ_CAS_TIMING >> 2: 3879 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 3880 break; 3881 case MC_SEQ_MISC_TIMING >> 2: 3882 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 3883 break; 3884 case MC_SEQ_MISC_TIMING2 >> 2: 3885 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 3886 break; 3887 case MC_SEQ_PMG_DVS_CMD >> 2: 3888 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 3889 break; 3890 case MC_SEQ_PMG_DVS_CTL >> 2: 3891 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 3892 break; 3893 case MC_SEQ_RD_CTL_D0 >> 2: 3894 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 3895 break; 3896 case MC_SEQ_RD_CTL_D1 >> 2: 3897 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 3898 break; 3899 case MC_SEQ_WR_CTL_D0 >> 2: 3900 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 3901 break; 3902 case MC_SEQ_WR_CTL_D1 >> 2: 3903 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 3904 break; 3905 case MC_PMG_CMD_EMRS >> 2: 3906 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3907 break; 3908 case MC_PMG_CMD_MRS >> 2: 3909 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3910 break; 3911 case MC_PMG_CMD_MRS1 >> 2: 3912 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3913 break; 3914 case MC_SEQ_PMG_TIMING >> 2: 3915 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 3916 break; 3917 case MC_PMG_CMD_MRS2 >> 2: 3918 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 3919 break; 3920 case MC_SEQ_WR_CTL_2 >> 2: 3921 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 3922 break; 3923 default: 3924 result = false; 3925 break; 3926 } 3927 3928 return result; 3929 } 3930 3931 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 3932 { 3933 u8 i, j; 3934 3935 for (i = 0; i < table->last; i++) { 3936 for (j = 1; j < table->num_entries; j++) { 3937 if (table->mc_reg_table_entry[j-1].mc_data[i] != 3938 table->mc_reg_table_entry[j].mc_data[i]) { 3939 table->valid_flag |= 1 << i; 3940 break; 3941 } 3942 } 3943 } 3944 } 3945 3946 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 3947 { 3948 u32 i; 3949 u16 address; 3950 3951 for (i = 0; i < table->last; i++) { 3952 table->mc_reg_address[i].s0 = 3953 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 3954 address : table->mc_reg_address[i].s1; 3955 } 3956 } 3957 3958 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 3959 struct ci_mc_reg_table *ci_table) 3960 { 3961 u8 i, j; 3962 3963 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3964 return -EINVAL; 3965 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 3966 return -EINVAL; 3967 3968 for (i = 0; i < table->last; i++) 3969 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 3970 3971 ci_table->last = table->last; 3972 3973 for (i = 0; i < table->num_entries; i++) { 3974 ci_table->mc_reg_table_entry[i].mclk_max = 3975 table->mc_reg_table_entry[i].mclk_max; 3976 for (j = 0; j < table->last; j++) 3977 ci_table->mc_reg_table_entry[i].mc_data[j] = 3978 table->mc_reg_table_entry[i].mc_data[j]; 3979 } 3980 ci_table->num_entries = table->num_entries; 3981 3982 return 0; 3983 } 3984 3985 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 3986 { 3987 struct ci_power_info *pi = ci_get_pi(rdev); 3988 struct atom_mc_reg_table *table; 3989 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 3990 u8 module_index = rv770_get_memory_module_index(rdev); 3991 int ret; 3992 3993 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 3994 if (!table) 3995 return -ENOMEM; 3996 3997 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 3998 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 3999 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4000 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4001 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4002 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4003 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4004 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4005 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4006 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4007 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4008 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4009 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4010 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4011 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4012 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4013 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4014 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4015 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4016 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4017 4018 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4019 if (ret) 4020 goto init_mc_done; 4021 4022 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4023 if (ret) 4024 goto init_mc_done; 4025 4026 ci_set_s0_mc_reg_index(ci_table); 4027 4028 ret = ci_set_mc_special_registers(rdev, ci_table); 4029 if (ret) 4030 goto init_mc_done; 4031 4032 ci_set_valid_flag(ci_table); 4033 4034 init_mc_done: 4035 kfree(table); 4036 4037 return ret; 4038 } 4039 4040 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4041 SMU7_Discrete_MCRegisters *mc_reg_table) 4042 { 4043 struct ci_power_info *pi = ci_get_pi(rdev); 4044 u32 i, j; 4045 4046 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4047 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4048 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4049 return -EINVAL; 4050 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4051 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4052 i++; 4053 } 4054 } 4055 4056 mc_reg_table->last = (u8)i; 4057 4058 return 0; 4059 } 4060 4061 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4062 SMU7_Discrete_MCRegisterSet *data, 4063 u32 num_entries, u32 valid_flag) 4064 { 4065 u32 i, j; 4066 4067 for (i = 0, j = 0; j < num_entries; j++) { 4068 if (valid_flag & (1 << j)) { 4069 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4070 i++; 4071 } 4072 } 4073 } 4074 4075 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4076 const u32 memory_clock, 4077 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4078 { 4079 struct ci_power_info *pi = ci_get_pi(rdev); 4080 u32 i = 0; 4081 4082 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { 4083 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4084 break; 4085 } 4086 4087 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4088 --i; 4089 4090 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4091 mc_reg_table_data, pi->mc_reg_table.last, 4092 pi->mc_reg_table.valid_flag); 4093 } 4094 4095 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4096 SMU7_Discrete_MCRegisters *mc_reg_table) 4097 { 4098 struct ci_power_info *pi = ci_get_pi(rdev); 4099 u32 i; 4100 4101 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4102 ci_convert_mc_reg_table_entry_to_smc(rdev, 4103 pi->dpm_table.mclk_table.dpm_levels[i].value, 4104 &mc_reg_table->data[i]); 4105 } 4106 4107 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4108 { 4109 struct ci_power_info *pi = ci_get_pi(rdev); 4110 int ret; 4111 4112 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4113 4114 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4115 if (ret) 4116 return ret; 4117 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4118 4119 return ci_copy_bytes_to_smc(rdev, 4120 pi->mc_reg_table_start, 4121 (u8 *)&pi->smc_mc_reg_table, 4122 sizeof(SMU7_Discrete_MCRegisters), 4123 pi->sram_end); 4124 } 4125 4126 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4127 { 4128 struct ci_power_info *pi = ci_get_pi(rdev); 4129 4130 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4131 return 0; 4132 4133 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4134 4135 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4136 4137 return ci_copy_bytes_to_smc(rdev, 4138 pi->mc_reg_table_start + 4139 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4140 (u8 *)&pi->smc_mc_reg_table.data[0], 4141 sizeof(SMU7_Discrete_MCRegisterSet) * 4142 pi->dpm_table.mclk_table.count, 4143 pi->sram_end); 4144 } 4145 4146 static void ci_enable_voltage_control(struct radeon_device *rdev) 4147 { 4148 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4149 4150 tmp |= VOLT_PWRMGT_EN; 4151 WREG32_SMC(GENERAL_PWRMGT, tmp); 4152 } 4153 4154 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4155 struct radeon_ps *radeon_state) 4156 { 4157 struct ci_ps *state = ci_get_ps(radeon_state); 4158 int i; 4159 u16 pcie_speed, max_speed = 0; 4160 4161 for (i = 0; i < state->performance_level_count; i++) { 4162 pcie_speed = state->performance_levels[i].pcie_gen; 4163 if (max_speed < pcie_speed) 4164 max_speed = pcie_speed; 4165 } 4166 4167 return max_speed; 4168 } 4169 4170 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4171 { 4172 u32 speed_cntl = 0; 4173 4174 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4175 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4176 4177 return (u16)speed_cntl; 4178 } 4179 4180 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4181 { 4182 u32 link_width = 0; 4183 4184 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4185 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4186 4187 switch (link_width) { 4188 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4189 return 1; 4190 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4191 return 2; 4192 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4193 return 4; 4194 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4195 return 8; 4196 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4197 /* not actually supported */ 4198 return 12; 4199 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4200 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4201 default: 4202 return 16; 4203 } 4204 } 4205 4206 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4207 struct radeon_ps *radeon_new_state, 4208 struct radeon_ps *radeon_current_state) 4209 { 4210 struct ci_power_info *pi = ci_get_pi(rdev); 4211 enum radeon_pcie_gen target_link_speed = 4212 ci_get_maximum_link_speed(rdev, radeon_new_state); 4213 enum radeon_pcie_gen current_link_speed; 4214 4215 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4216 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4217 else 4218 current_link_speed = pi->force_pcie_gen; 4219 4220 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4221 pi->pspp_notify_required = false; 4222 if (target_link_speed > current_link_speed) { 4223 switch (target_link_speed) { 4224 #ifdef CONFIG_ACPI 4225 case RADEON_PCIE_GEN3: 4226 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4227 break; 4228 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4229 if (current_link_speed == RADEON_PCIE_GEN2) 4230 break; 4231 case RADEON_PCIE_GEN2: 4232 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4233 break; 4234 #endif 4235 default: 4236 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4237 break; 4238 } 4239 } else { 4240 if (target_link_speed < current_link_speed) 4241 pi->pspp_notify_required = true; 4242 } 4243 } 4244 4245 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4246 struct radeon_ps *radeon_new_state, 4247 struct radeon_ps *radeon_current_state) 4248 { 4249 struct ci_power_info *pi = ci_get_pi(rdev); 4250 enum radeon_pcie_gen target_link_speed = 4251 ci_get_maximum_link_speed(rdev, radeon_new_state); 4252 u8 request; 4253 4254 if (pi->pspp_notify_required) { 4255 if (target_link_speed == RADEON_PCIE_GEN3) 4256 request = PCIE_PERF_REQ_PECI_GEN3; 4257 else if (target_link_speed == RADEON_PCIE_GEN2) 4258 request = PCIE_PERF_REQ_PECI_GEN2; 4259 else 4260 request = PCIE_PERF_REQ_PECI_GEN1; 4261 4262 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4263 (ci_get_current_pcie_speed(rdev) > 0)) 4264 return; 4265 4266 #ifdef CONFIG_ACPI 4267 radeon_acpi_pcie_performance_request(rdev, request, false); 4268 #endif 4269 } 4270 } 4271 4272 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4273 { 4274 struct ci_power_info *pi = ci_get_pi(rdev); 4275 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4276 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4277 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4278 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4279 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4280 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4281 4282 if (allowed_sclk_vddc_table == NULL) 4283 return -EINVAL; 4284 if (allowed_sclk_vddc_table->count < 1) 4285 return -EINVAL; 4286 if (allowed_mclk_vddc_table == NULL) 4287 return -EINVAL; 4288 if (allowed_mclk_vddc_table->count < 1) 4289 return -EINVAL; 4290 if (allowed_mclk_vddci_table == NULL) 4291 return -EINVAL; 4292 if (allowed_mclk_vddci_table->count < 1) 4293 return -EINVAL; 4294 4295 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4296 pi->max_vddc_in_pp_table = 4297 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4298 4299 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4300 pi->max_vddci_in_pp_table = 4301 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4302 4303 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4304 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4305 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4306 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4307 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4308 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4309 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4310 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4311 4312 return 0; 4313 } 4314 4315 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4316 { 4317 struct ci_power_info *pi = ci_get_pi(rdev); 4318 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4319 u32 leakage_index; 4320 4321 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4322 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4323 *vddc = leakage_table->actual_voltage[leakage_index]; 4324 break; 4325 } 4326 } 4327 } 4328 4329 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4330 { 4331 struct ci_power_info *pi = ci_get_pi(rdev); 4332 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4333 u32 leakage_index; 4334 4335 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4336 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4337 *vddci = leakage_table->actual_voltage[leakage_index]; 4338 break; 4339 } 4340 } 4341 } 4342 4343 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4344 struct radeon_clock_voltage_dependency_table *table) 4345 { 4346 u32 i; 4347 4348 if (table) { 4349 for (i = 0; i < table->count; i++) 4350 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4351 } 4352 } 4353 4354 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4355 struct radeon_clock_voltage_dependency_table *table) 4356 { 4357 u32 i; 4358 4359 if (table) { 4360 for (i = 0; i < table->count; i++) 4361 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4362 } 4363 } 4364 4365 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4366 struct radeon_vce_clock_voltage_dependency_table *table) 4367 { 4368 u32 i; 4369 4370 if (table) { 4371 for (i = 0; i < table->count; i++) 4372 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4373 } 4374 } 4375 4376 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4377 struct radeon_uvd_clock_voltage_dependency_table *table) 4378 { 4379 u32 i; 4380 4381 if (table) { 4382 for (i = 0; i < table->count; i++) 4383 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4384 } 4385 } 4386 4387 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 4388 struct radeon_phase_shedding_limits_table *table) 4389 { 4390 u32 i; 4391 4392 if (table) { 4393 for (i = 0; i < table->count; i++) 4394 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 4395 } 4396 } 4397 4398 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 4399 struct radeon_clock_and_voltage_limits *table) 4400 { 4401 if (table) { 4402 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 4403 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 4404 } 4405 } 4406 4407 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 4408 struct radeon_cac_leakage_table *table) 4409 { 4410 u32 i; 4411 4412 if (table) { 4413 for (i = 0; i < table->count; i++) 4414 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 4415 } 4416 } 4417 4418 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 4419 { 4420 4421 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4422 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 4423 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4424 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 4425 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4426 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 4427 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 4428 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 4429 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4430 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 4431 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4432 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 4433 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4434 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 4435 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4436 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 4437 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 4438 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 4439 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4440 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 4441 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4442 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 4443 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 4444 &rdev->pm.dpm.dyn_state.cac_leakage_table); 4445 4446 } 4447 4448 static void ci_get_memory_type(struct radeon_device *rdev) 4449 { 4450 struct ci_power_info *pi = ci_get_pi(rdev); 4451 u32 tmp; 4452 4453 tmp = RREG32(MC_SEQ_MISC0); 4454 4455 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 4456 MC_SEQ_MISC0_GDDR5_VALUE) 4457 pi->mem_gddr5 = true; 4458 else 4459 pi->mem_gddr5 = false; 4460 4461 } 4462 4463 static void ci_update_current_ps(struct radeon_device *rdev, 4464 struct radeon_ps *rps) 4465 { 4466 struct ci_ps *new_ps = ci_get_ps(rps); 4467 struct ci_power_info *pi = ci_get_pi(rdev); 4468 4469 pi->current_rps = *rps; 4470 pi->current_ps = *new_ps; 4471 pi->current_rps.ps_priv = &pi->current_ps; 4472 } 4473 4474 static void ci_update_requested_ps(struct radeon_device *rdev, 4475 struct radeon_ps *rps) 4476 { 4477 struct ci_ps *new_ps = ci_get_ps(rps); 4478 struct ci_power_info *pi = ci_get_pi(rdev); 4479 4480 pi->requested_rps = *rps; 4481 pi->requested_ps = *new_ps; 4482 pi->requested_rps.ps_priv = &pi->requested_ps; 4483 } 4484 4485 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 4486 { 4487 struct ci_power_info *pi = ci_get_pi(rdev); 4488 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 4489 struct radeon_ps *new_ps = &requested_ps; 4490 4491 ci_update_requested_ps(rdev, new_ps); 4492 4493 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 4494 4495 return 0; 4496 } 4497 4498 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 4499 { 4500 struct ci_power_info *pi = ci_get_pi(rdev); 4501 struct radeon_ps *new_ps = &pi->requested_rps; 4502 4503 ci_update_current_ps(rdev, new_ps); 4504 } 4505 4506 4507 void ci_dpm_setup_asic(struct radeon_device *rdev) 4508 { 4509 ci_read_clock_registers(rdev); 4510 ci_get_memory_type(rdev); 4511 ci_enable_acpi_power_management(rdev); 4512 ci_init_sclk_t(rdev); 4513 } 4514 4515 int ci_dpm_enable(struct radeon_device *rdev) 4516 { 4517 struct ci_power_info *pi = ci_get_pi(rdev); 4518 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4519 int ret; 4520 4521 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 4522 RADEON_CG_BLOCK_MC | 4523 RADEON_CG_BLOCK_SDMA | 4524 RADEON_CG_BLOCK_BIF | 4525 RADEON_CG_BLOCK_UVD | 4526 RADEON_CG_BLOCK_HDP), false); 4527 4528 if (ci_is_smc_running(rdev)) 4529 return -EINVAL; 4530 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 4531 ci_enable_voltage_control(rdev); 4532 ret = ci_construct_voltage_tables(rdev); 4533 if (ret) { 4534 DRM_ERROR("ci_construct_voltage_tables failed\n"); 4535 return ret; 4536 } 4537 } 4538 if (pi->caps_dynamic_ac_timing) { 4539 ret = ci_initialize_mc_reg_table(rdev); 4540 if (ret) 4541 pi->caps_dynamic_ac_timing = false; 4542 } 4543 if (pi->dynamic_ss) 4544 ci_enable_spread_spectrum(rdev, true); 4545 if (pi->thermal_protection) 4546 ci_enable_thermal_protection(rdev, true); 4547 ci_program_sstp(rdev); 4548 ci_enable_display_gap(rdev); 4549 ci_program_vc(rdev); 4550 ret = ci_upload_firmware(rdev); 4551 if (ret) { 4552 DRM_ERROR("ci_upload_firmware failed\n"); 4553 return ret; 4554 } 4555 ret = ci_process_firmware_header(rdev); 4556 if (ret) { 4557 DRM_ERROR("ci_process_firmware_header failed\n"); 4558 return ret; 4559 } 4560 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 4561 if (ret) { 4562 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 4563 return ret; 4564 } 4565 ret = ci_init_smc_table(rdev); 4566 if (ret) { 4567 DRM_ERROR("ci_init_smc_table failed\n"); 4568 return ret; 4569 } 4570 ret = ci_init_arb_table_index(rdev); 4571 if (ret) { 4572 DRM_ERROR("ci_init_arb_table_index failed\n"); 4573 return ret; 4574 } 4575 if (pi->caps_dynamic_ac_timing) { 4576 ret = ci_populate_initial_mc_reg_table(rdev); 4577 if (ret) { 4578 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 4579 return ret; 4580 } 4581 } 4582 ret = ci_populate_pm_base(rdev); 4583 if (ret) { 4584 DRM_ERROR("ci_populate_pm_base failed\n"); 4585 return ret; 4586 } 4587 ci_dpm_start_smc(rdev); 4588 ci_enable_vr_hot_gpio_interrupt(rdev); 4589 ret = ci_notify_smc_display_change(rdev, false); 4590 if (ret) { 4591 DRM_ERROR("ci_notify_smc_display_change failed\n"); 4592 return ret; 4593 } 4594 ci_enable_sclk_control(rdev, true); 4595 ret = ci_enable_ulv(rdev, true); 4596 if (ret) { 4597 DRM_ERROR("ci_enable_ulv failed\n"); 4598 return ret; 4599 } 4600 ret = ci_enable_ds_master_switch(rdev, true); 4601 if (ret) { 4602 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 4603 return ret; 4604 } 4605 ret = ci_start_dpm(rdev); 4606 if (ret) { 4607 DRM_ERROR("ci_start_dpm failed\n"); 4608 return ret; 4609 } 4610 ret = ci_enable_didt(rdev, true); 4611 if (ret) { 4612 DRM_ERROR("ci_enable_didt failed\n"); 4613 return ret; 4614 } 4615 ret = ci_enable_smc_cac(rdev, true); 4616 if (ret) { 4617 DRM_ERROR("ci_enable_smc_cac failed\n"); 4618 return ret; 4619 } 4620 ret = ci_enable_power_containment(rdev, true); 4621 if (ret) { 4622 DRM_ERROR("ci_enable_power_containment failed\n"); 4623 return ret; 4624 } 4625 if (rdev->irq.installed && 4626 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 4627 #if 0 4628 PPSMC_Result result; 4629 #endif 4630 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 4631 if (ret) { 4632 DRM_ERROR("ci_set_thermal_temperature_range failed\n"); 4633 return ret; 4634 } 4635 rdev->irq.dpm_thermal = true; 4636 radeon_irq_set(rdev); 4637 #if 0 4638 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 4639 4640 if (result != PPSMC_Result_OK) 4641 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 4642 #endif 4643 } 4644 4645 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 4646 4647 ci_dpm_powergate_uvd(rdev, true); 4648 4649 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 4650 RADEON_CG_BLOCK_MC | 4651 RADEON_CG_BLOCK_SDMA | 4652 RADEON_CG_BLOCK_BIF | 4653 RADEON_CG_BLOCK_UVD | 4654 RADEON_CG_BLOCK_HDP), true); 4655 4656 ci_update_current_ps(rdev, boot_ps); 4657 4658 return 0; 4659 } 4660 4661 void ci_dpm_disable(struct radeon_device *rdev) 4662 { 4663 struct ci_power_info *pi = ci_get_pi(rdev); 4664 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4665 4666 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 4667 RADEON_CG_BLOCK_MC | 4668 RADEON_CG_BLOCK_SDMA | 4669 RADEON_CG_BLOCK_UVD | 4670 RADEON_CG_BLOCK_HDP), false); 4671 4672 ci_dpm_powergate_uvd(rdev, false); 4673 4674 if (!ci_is_smc_running(rdev)) 4675 return; 4676 4677 if (pi->thermal_protection) 4678 ci_enable_thermal_protection(rdev, false); 4679 ci_enable_power_containment(rdev, false); 4680 ci_enable_smc_cac(rdev, false); 4681 ci_enable_didt(rdev, false); 4682 ci_enable_spread_spectrum(rdev, false); 4683 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 4684 ci_stop_dpm(rdev); 4685 ci_enable_ds_master_switch(rdev, true); 4686 ci_enable_ulv(rdev, false); 4687 ci_clear_vc(rdev); 4688 ci_reset_to_default(rdev); 4689 ci_dpm_stop_smc(rdev); 4690 ci_force_switch_to_arb_f0(rdev); 4691 4692 ci_update_current_ps(rdev, boot_ps); 4693 } 4694 4695 int ci_dpm_set_power_state(struct radeon_device *rdev) 4696 { 4697 struct ci_power_info *pi = ci_get_pi(rdev); 4698 struct radeon_ps *new_ps = &pi->requested_rps; 4699 struct radeon_ps *old_ps = &pi->current_rps; 4700 int ret; 4701 4702 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 4703 RADEON_CG_BLOCK_MC | 4704 RADEON_CG_BLOCK_SDMA | 4705 RADEON_CG_BLOCK_BIF | 4706 RADEON_CG_BLOCK_UVD | 4707 RADEON_CG_BLOCK_HDP), false); 4708 4709 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 4710 if (pi->pcie_performance_request) 4711 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 4712 ret = ci_freeze_sclk_mclk_dpm(rdev); 4713 if (ret) { 4714 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 4715 return ret; 4716 } 4717 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 4718 if (ret) { 4719 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 4720 return ret; 4721 } 4722 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 4723 if (ret) { 4724 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 4725 return ret; 4726 } 4727 #if 0 4728 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 4729 if (ret) { 4730 DRM_ERROR("ci_update_vce_dpm failed\n"); 4731 return ret; 4732 } 4733 #endif 4734 ret = ci_update_sclk_t(rdev); 4735 if (ret) { 4736 DRM_ERROR("ci_update_sclk_t failed\n"); 4737 return ret; 4738 } 4739 if (pi->caps_dynamic_ac_timing) { 4740 ret = ci_update_and_upload_mc_reg_table(rdev); 4741 if (ret) { 4742 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 4743 return ret; 4744 } 4745 } 4746 ret = ci_program_memory_timing_parameters(rdev); 4747 if (ret) { 4748 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 4749 return ret; 4750 } 4751 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 4752 if (ret) { 4753 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 4754 return ret; 4755 } 4756 ret = ci_upload_dpm_level_enable_mask(rdev); 4757 if (ret) { 4758 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 4759 return ret; 4760 } 4761 if (pi->pcie_performance_request) 4762 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 4763 4764 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 4765 RADEON_CG_BLOCK_MC | 4766 RADEON_CG_BLOCK_SDMA | 4767 RADEON_CG_BLOCK_BIF | 4768 RADEON_CG_BLOCK_UVD | 4769 RADEON_CG_BLOCK_HDP), true); 4770 4771 return 0; 4772 } 4773 4774 static int __unused ci_dpm_power_control_set_level(struct radeon_device *rdev) 4775 { 4776 return ci_power_control_set_level(rdev); 4777 } 4778 4779 static void __unused ci_dpm_reset_asic(struct radeon_device *rdev) 4780 { 4781 ci_set_boot_state(rdev); 4782 } 4783 4784 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 4785 { 4786 ci_program_display_gap(rdev); 4787 } 4788 4789 union power_info { 4790 struct _ATOM_POWERPLAY_INFO info; 4791 struct _ATOM_POWERPLAY_INFO_V2 info_2; 4792 struct _ATOM_POWERPLAY_INFO_V3 info_3; 4793 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 4794 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 4795 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 4796 }; 4797 4798 union pplib_clock_info { 4799 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 4800 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 4801 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 4802 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 4803 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 4804 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 4805 }; 4806 4807 union pplib_power_state { 4808 struct _ATOM_PPLIB_STATE v1; 4809 struct _ATOM_PPLIB_STATE_V2 v2; 4810 }; 4811 4812 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 4813 struct radeon_ps *rps, 4814 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 4815 u8 table_rev) 4816 { 4817 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 4818 rps->class = le16_to_cpu(non_clock_info->usClassification); 4819 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 4820 4821 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 4822 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 4823 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 4824 } else { 4825 rps->vclk = 0; 4826 rps->dclk = 0; 4827 } 4828 4829 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 4830 rdev->pm.dpm.boot_ps = rps; 4831 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 4832 rdev->pm.dpm.uvd_ps = rps; 4833 } 4834 4835 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 4836 struct radeon_ps *rps, int index, 4837 union pplib_clock_info *clock_info) 4838 { 4839 struct ci_power_info *pi = ci_get_pi(rdev); 4840 struct ci_ps *ps = ci_get_ps(rps); 4841 struct ci_pl *pl = &ps->performance_levels[index]; 4842 4843 ps->performance_level_count = index + 1; 4844 4845 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 4846 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 4847 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 4848 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 4849 4850 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 4851 pi->sys_pcie_mask, 4852 pi->vbios_boot_state.pcie_gen_bootup_value, 4853 clock_info->ci.ucPCIEGen); 4854 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 4855 pi->vbios_boot_state.pcie_lane_bootup_value, 4856 le16_to_cpu(clock_info->ci.usPCIELane)); 4857 4858 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 4859 pi->acpi_pcie_gen = pl->pcie_gen; 4860 } 4861 4862 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 4863 pi->ulv.supported = true; 4864 pi->ulv.pl = *pl; 4865 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 4866 } 4867 4868 /* patch up boot state */ 4869 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 4870 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 4871 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 4872 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 4873 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 4874 } 4875 4876 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 4877 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 4878 pi->use_pcie_powersaving_levels = true; 4879 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 4880 pi->pcie_gen_powersaving.max = pl->pcie_gen; 4881 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 4882 pi->pcie_gen_powersaving.min = pl->pcie_gen; 4883 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 4884 pi->pcie_lane_powersaving.max = pl->pcie_lane; 4885 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 4886 pi->pcie_lane_powersaving.min = pl->pcie_lane; 4887 break; 4888 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 4889 pi->use_pcie_performance_levels = true; 4890 if (pi->pcie_gen_performance.max < pl->pcie_gen) 4891 pi->pcie_gen_performance.max = pl->pcie_gen; 4892 if (pi->pcie_gen_performance.min > pl->pcie_gen) 4893 pi->pcie_gen_performance.min = pl->pcie_gen; 4894 if (pi->pcie_lane_performance.max < pl->pcie_lane) 4895 pi->pcie_lane_performance.max = pl->pcie_lane; 4896 if (pi->pcie_lane_performance.min > pl->pcie_lane) 4897 pi->pcie_lane_performance.min = pl->pcie_lane; 4898 break; 4899 default: 4900 break; 4901 } 4902 } 4903 4904 static int ci_parse_power_table(struct radeon_device *rdev) 4905 { 4906 struct radeon_mode_info *mode_info = &rdev->mode_info; 4907 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 4908 union pplib_power_state *power_state; 4909 int i, j, k, non_clock_array_index, clock_array_index; 4910 union pplib_clock_info *clock_info; 4911 struct _StateArray *state_array; 4912 struct _ClockInfoArray *clock_info_array; 4913 struct _NonClockInfoArray *non_clock_info_array; 4914 union power_info *power_info; 4915 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 4916 u16 data_offset; 4917 u8 frev, crev; 4918 u8 *power_state_offset; 4919 struct ci_ps *ps; 4920 4921 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 4922 &frev, &crev, &data_offset)) 4923 return -EINVAL; 4924 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 4925 4926 state_array = (struct _StateArray *) 4927 (mode_info->atom_context->bios + data_offset + 4928 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 4929 clock_info_array = (struct _ClockInfoArray *) 4930 (mode_info->atom_context->bios + data_offset + 4931 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 4932 non_clock_info_array = (struct _NonClockInfoArray *) 4933 (mode_info->atom_context->bios + data_offset + 4934 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 4935 4936 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 4937 state_array->ucNumEntries, GFP_KERNEL); 4938 if (!rdev->pm.dpm.ps) 4939 return -ENOMEM; 4940 power_state_offset = (u8 *)state_array->states; 4941 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 4942 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 4943 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 4944 for (i = 0; i < state_array->ucNumEntries; i++) { 4945 u8 *idx; 4946 power_state = (union pplib_power_state *)power_state_offset; 4947 non_clock_array_index = power_state->v2.nonClockInfoIndex; 4948 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 4949 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 4950 if (!rdev->pm.power_state[i].clock_info) 4951 return -EINVAL; 4952 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); 4953 if (ps == NULL) { 4954 kfree(rdev->pm.dpm.ps); 4955 return -ENOMEM; 4956 } 4957 rdev->pm.dpm.ps[i].ps_priv = ps; 4958 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 4959 non_clock_info, 4960 non_clock_info_array->ucEntrySize); 4961 k = 0; 4962 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 4963 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 4964 clock_array_index = idx[j]; 4965 if (clock_array_index >= clock_info_array->ucNumEntries) 4966 continue; 4967 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 4968 break; 4969 clock_info = (union pplib_clock_info *) 4970 ((u8 *)&clock_info_array->clockInfo[0] + 4971 (clock_array_index * clock_info_array->ucEntrySize)); 4972 ci_parse_pplib_clock_info(rdev, 4973 &rdev->pm.dpm.ps[i], k, 4974 clock_info); 4975 k++; 4976 } 4977 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 4978 } 4979 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 4980 return 0; 4981 } 4982 4983 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 4984 struct ci_vbios_boot_state *boot_state) 4985 { 4986 struct radeon_mode_info *mode_info = &rdev->mode_info; 4987 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 4988 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 4989 u8 frev, crev; 4990 u16 data_offset; 4991 4992 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 4993 &frev, &crev, &data_offset)) { 4994 firmware_info = 4995 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 4996 data_offset); 4997 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 4998 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 4999 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5000 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5001 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5002 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5003 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5004 5005 return 0; 5006 } 5007 return -EINVAL; 5008 } 5009 5010 void ci_dpm_fini(struct radeon_device *rdev) 5011 { 5012 int i; 5013 5014 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5015 kfree(rdev->pm.dpm.ps[i].ps_priv); 5016 } 5017 kfree(rdev->pm.dpm.ps); 5018 kfree(rdev->pm.dpm.priv); 5019 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5020 r600_free_extended_power_table(rdev); 5021 } 5022 5023 int ci_dpm_init(struct radeon_device *rdev) 5024 { 5025 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5026 u16 data_offset, size; 5027 u8 frev, crev; 5028 struct ci_power_info *pi; 5029 int ret; 5030 u32 mask; 5031 5032 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5033 if (pi == NULL) 5034 return -ENOMEM; 5035 rdev->pm.dpm.priv = pi; 5036 5037 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 5038 if (ret) 5039 pi->sys_pcie_mask = 0; 5040 else 5041 pi->sys_pcie_mask = mask; 5042 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5043 5044 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5045 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5046 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5047 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5048 5049 pi->pcie_lane_performance.max = 0; 5050 pi->pcie_lane_performance.min = 16; 5051 pi->pcie_lane_powersaving.max = 0; 5052 pi->pcie_lane_powersaving.min = 16; 5053 5054 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5055 if (ret) { 5056 ci_dpm_fini(rdev); 5057 return ret; 5058 } 5059 ret = ci_parse_power_table(rdev); 5060 if (ret) { 5061 ci_dpm_fini(rdev); 5062 return ret; 5063 } 5064 ret = r600_parse_extended_power_table(rdev); 5065 if (ret) { 5066 ci_dpm_fini(rdev); 5067 return ret; 5068 } 5069 5070 pi->dll_default_on = false; 5071 pi->sram_end = SMC_RAM_END; 5072 5073 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5074 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5075 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5076 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5077 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5078 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5079 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5080 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5081 5082 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5083 5084 pi->sclk_dpm_key_disabled = 0; 5085 pi->mclk_dpm_key_disabled = 0; 5086 pi->pcie_dpm_key_disabled = 0; 5087 5088 pi->caps_sclk_ds = true; 5089 5090 pi->mclk_strobe_mode_threshold = 40000; 5091 pi->mclk_stutter_mode_threshold = 40000; 5092 pi->mclk_edc_enable_threshold = 40000; 5093 pi->mclk_edc_wr_enable_threshold = 40000; 5094 5095 ci_initialize_powertune_defaults(rdev); 5096 5097 pi->caps_fps = false; 5098 5099 pi->caps_sclk_throttle_low_notification = false; 5100 5101 pi->caps_uvd_dpm = true; 5102 5103 ci_get_leakage_voltages(rdev); 5104 ci_patch_dependency_tables_with_leakage(rdev); 5105 ci_set_private_data_variables_based_on_pptable(rdev); 5106 5107 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5108 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 5109 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5110 ci_dpm_fini(rdev); 5111 return -ENOMEM; 5112 } 5113 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5114 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5115 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5116 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5117 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5118 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5119 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5120 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5121 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5122 5123 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5124 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5125 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5126 5127 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5128 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5129 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5130 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5131 5132 pi->thermal_temp_setting.temperature_low = 99500; 5133 pi->thermal_temp_setting.temperature_high = 100000; 5134 pi->thermal_temp_setting.temperature_shutdown = 104000; 5135 5136 pi->uvd_enabled = false; 5137 5138 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5139 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5140 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5141 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5142 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5143 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5144 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5145 5146 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5147 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5148 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5149 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5150 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5151 else 5152 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5153 } 5154 5155 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5156 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5157 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5158 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5159 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5160 else 5161 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5162 } 5163 5164 pi->vddc_phase_shed_control = true; 5165 5166 #if defined(CONFIG_ACPI) 5167 pi->pcie_performance_request = 5168 radeon_acpi_is_pcie_performance_request_supported(rdev); 5169 #else 5170 pi->pcie_performance_request = false; 5171 #endif 5172 5173 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5174 &frev, &crev, &data_offset)) { 5175 pi->caps_sclk_ss_support = true; 5176 pi->caps_mclk_ss_support = true; 5177 pi->dynamic_ss = true; 5178 } else { 5179 pi->caps_sclk_ss_support = false; 5180 pi->caps_mclk_ss_support = false; 5181 pi->dynamic_ss = true; 5182 } 5183 5184 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5185 pi->thermal_protection = true; 5186 else 5187 pi->thermal_protection = false; 5188 5189 pi->caps_dynamic_ac_timing = true; 5190 5191 pi->uvd_power_gated = false; 5192 5193 /* make sure dc limits are valid */ 5194 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5195 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5196 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5197 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5198 5199 return 0; 5200 } 5201 5202 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5203 struct seq_file *m) 5204 { 5205 u32 sclk = ci_get_average_sclk_freq(rdev); 5206 u32 mclk = ci_get_average_mclk_freq(rdev); 5207 5208 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5209 sclk, mclk); 5210 } 5211 5212 void ci_dpm_print_power_state(struct radeon_device *rdev, 5213 struct radeon_ps *rps) 5214 { 5215 struct ci_ps *ps = ci_get_ps(rps); 5216 struct ci_pl *pl; 5217 int i; 5218 5219 r600_dpm_print_class_info(rps->class, rps->class2); 5220 r600_dpm_print_cap_info(rps->caps); 5221 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5222 for (i = 0; i < ps->performance_level_count; i++) { 5223 pl = &ps->performance_levels[i]; 5224 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5225 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5226 } 5227 r600_dpm_print_ps_status(rdev, rps); 5228 } 5229 5230 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5231 { 5232 struct ci_power_info *pi = ci_get_pi(rdev); 5233 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5234 5235 if (low) 5236 return requested_state->performance_levels[0].sclk; 5237 else 5238 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5239 } 5240 5241 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5242 { 5243 struct ci_power_info *pi = ci_get_pi(rdev); 5244 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5245 5246 if (low) 5247 return requested_state->performance_levels[0].mclk; 5248 else 5249 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5250 } 5251