1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include "radeon_ucode.h" 29 #include "cikd.h" 30 #include "r600_dpm.h" 31 #include "ci_dpm.h" 32 #include "ni_dpm.h" 33 #include "atom.h" 34 #include <linux/seq_file.h> 35 36 #define MC_CG_ARB_FREQ_F0 0x0a 37 #define MC_CG_ARB_FREQ_F1 0x0b 38 #define MC_CG_ARB_FREQ_F2 0x0c 39 #define MC_CG_ARB_FREQ_F3 0x0d 40 41 #define SMC_RAM_END 0x40000 42 43 #define VOLTAGE_SCALE 4 44 #define VOLTAGE_VID_OFFSET_SCALE1 625 45 #define VOLTAGE_VID_OFFSET_SCALE2 100 46 47 static const struct ci_pt_defaults defaults_hawaii_xt = 48 { 49 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 50 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 51 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 52 }; 53 54 static const struct ci_pt_defaults defaults_hawaii_pro = 55 { 56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 57 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 58 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 59 }; 60 61 static const struct ci_pt_defaults defaults_bonaire_xt = 62 { 63 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 66 }; 67 68 static const struct ci_pt_defaults defaults_bonaire_pro = 69 { 70 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, 71 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, 72 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } 73 }; 74 75 static const struct ci_pt_defaults defaults_saturn_xt = 76 { 77 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 78 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 79 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 80 }; 81 82 static const struct ci_pt_defaults defaults_saturn_pro = 83 { 84 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, 85 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, 86 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } 87 }; 88 89 static const struct ci_pt_config_reg didt_config_ci[] = 90 { 91 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 92 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 93 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 94 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 147 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 148 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 149 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 150 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 151 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 152 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 153 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 154 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 155 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 156 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 157 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 158 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 159 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 160 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 161 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 162 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 163 { 0xFFFFFFFF } 164 }; 165 166 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 167 struct atom_voltage_table_entry *voltage_table, 168 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 169 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 170 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 171 u32 target_tdp); 172 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 173 174 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 175 { 176 struct ci_power_info *pi = rdev->pm.dpm.priv; 177 178 return pi; 179 } 180 181 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 182 { 183 struct ci_ps *ps = rps->ps_priv; 184 185 return ps; 186 } 187 188 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 189 { 190 struct ci_power_info *pi = ci_get_pi(rdev); 191 192 switch (rdev->pdev->device) { 193 case 0x6649: 194 case 0x6650: 195 case 0x6651: 196 case 0x6658: 197 case 0x665C: 198 case 0x665D: 199 default: 200 pi->powertune_defaults = &defaults_bonaire_xt; 201 break; 202 case 0x6640: 203 case 0x6641: 204 case 0x6646: 205 case 0x6647: 206 pi->powertune_defaults = &defaults_saturn_xt; 207 break; 208 case 0x67B8: 209 case 0x67B0: 210 pi->powertune_defaults = &defaults_hawaii_xt; 211 break; 212 case 0x67BA: 213 case 0x67B1: 214 pi->powertune_defaults = &defaults_hawaii_pro; 215 break; 216 case 0x67A0: 217 case 0x67A1: 218 case 0x67A2: 219 case 0x67A8: 220 case 0x67A9: 221 case 0x67AA: 222 case 0x67B9: 223 case 0x67BE: 224 pi->powertune_defaults = &defaults_bonaire_xt; 225 break; 226 } 227 228 pi->dte_tj_offset = 0; 229 230 pi->caps_power_containment = true; 231 pi->caps_cac = false; 232 pi->caps_sq_ramping = false; 233 pi->caps_db_ramping = false; 234 pi->caps_td_ramping = false; 235 pi->caps_tcp_ramping = false; 236 237 if (pi->caps_power_containment) { 238 pi->caps_cac = true; 239 pi->enable_bapm_feature = true; 240 pi->enable_tdc_limit_feature = true; 241 pi->enable_pkg_pwr_tracking_feature = true; 242 } 243 } 244 245 static u8 ci_convert_to_vid(u16 vddc) 246 { 247 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 248 } 249 250 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 251 { 252 struct ci_power_info *pi = ci_get_pi(rdev); 253 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 254 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 255 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 256 u32 i; 257 258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 259 return -EINVAL; 260 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 261 return -EINVAL; 262 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 263 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 264 return -EINVAL; 265 266 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 267 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 268 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 269 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 270 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 271 } else { 272 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 273 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 274 } 275 } 276 return 0; 277 } 278 279 static int ci_populate_vddc_vid(struct radeon_device *rdev) 280 { 281 struct ci_power_info *pi = ci_get_pi(rdev); 282 u8 *vid = pi->smc_powertune_table.VddCVid; 283 u32 i; 284 285 if (pi->vddc_voltage_table.count > 8) 286 return -EINVAL; 287 288 for (i = 0; i < pi->vddc_voltage_table.count; i++) 289 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 290 291 return 0; 292 } 293 294 static int ci_populate_svi_load_line(struct radeon_device *rdev) 295 { 296 struct ci_power_info *pi = ci_get_pi(rdev); 297 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 298 299 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 300 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 301 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 302 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 303 304 return 0; 305 } 306 307 static int ci_populate_tdc_limit(struct radeon_device *rdev) 308 { 309 struct ci_power_info *pi = ci_get_pi(rdev); 310 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 311 u16 tdc_limit; 312 313 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 314 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 315 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 316 pt_defaults->tdc_vddc_throttle_release_limit_perc; 317 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 318 319 return 0; 320 } 321 322 static int ci_populate_dw8(struct radeon_device *rdev) 323 { 324 struct ci_power_info *pi = ci_get_pi(rdev); 325 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 326 int ret; 327 328 ret = ci_read_smc_sram_dword(rdev, 329 SMU7_FIRMWARE_HEADER_LOCATION + 330 offsetof(SMU7_Firmware_Header, PmFuseTable) + 331 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 332 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 333 pi->sram_end); 334 if (ret) 335 return -EINVAL; 336 else 337 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 338 339 return 0; 340 } 341 342 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 343 { 344 struct ci_power_info *pi = ci_get_pi(rdev); 345 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 346 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 347 int i, min, max; 348 349 min = max = hi_vid[0]; 350 for (i = 0; i < 8; i++) { 351 if (0 != hi_vid[i]) { 352 if (min > hi_vid[i]) 353 min = hi_vid[i]; 354 if (max < hi_vid[i]) 355 max = hi_vid[i]; 356 } 357 358 if (0 != lo_vid[i]) { 359 if (min > lo_vid[i]) 360 min = lo_vid[i]; 361 if (max < lo_vid[i]) 362 max = lo_vid[i]; 363 } 364 } 365 366 if ((min == 0) || (max == 0)) 367 return -EINVAL; 368 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 369 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 370 371 return 0; 372 } 373 374 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 375 { 376 struct ci_power_info *pi = ci_get_pi(rdev); 377 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; 378 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; 379 struct radeon_cac_tdp_table *cac_tdp_table = 380 rdev->pm.dpm.dyn_state.cac_tdp_table; 381 382 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 383 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 384 385 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 386 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 387 388 return 0; 389 } 390 391 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 392 { 393 struct ci_power_info *pi = ci_get_pi(rdev); 394 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 395 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 396 struct radeon_cac_tdp_table *cac_tdp_table = 397 rdev->pm.dpm.dyn_state.cac_tdp_table; 398 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 399 int i, j, k; 400 const u16 *def1; 401 const u16 *def2; 402 403 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 404 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 405 406 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 407 dpm_table->GpuTjMax = 408 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 409 dpm_table->GpuTjHyst = 8; 410 411 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 412 413 if (ppm) { 414 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 415 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 416 } else { 417 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 418 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 419 } 420 421 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 422 def1 = pt_defaults->bapmti_r; 423 def2 = pt_defaults->bapmti_rc; 424 425 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 426 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 427 for (k = 0; k < SMU7_DTE_SINKS; k++) { 428 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 429 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 430 def1++; 431 def2++; 432 } 433 } 434 } 435 436 return 0; 437 } 438 439 static int ci_populate_pm_base(struct radeon_device *rdev) 440 { 441 struct ci_power_info *pi = ci_get_pi(rdev); 442 u32 pm_fuse_table_offset; 443 int ret; 444 445 if (pi->caps_power_containment) { 446 ret = ci_read_smc_sram_dword(rdev, 447 SMU7_FIRMWARE_HEADER_LOCATION + 448 offsetof(SMU7_Firmware_Header, PmFuseTable), 449 &pm_fuse_table_offset, pi->sram_end); 450 if (ret) 451 return ret; 452 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 453 if (ret) 454 return ret; 455 ret = ci_populate_vddc_vid(rdev); 456 if (ret) 457 return ret; 458 ret = ci_populate_svi_load_line(rdev); 459 if (ret) 460 return ret; 461 ret = ci_populate_tdc_limit(rdev); 462 if (ret) 463 return ret; 464 ret = ci_populate_dw8(rdev); 465 if (ret) 466 return ret; 467 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 468 if (ret) 469 return ret; 470 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 471 if (ret) 472 return ret; 473 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 474 (u8 *)&pi->smc_powertune_table, 475 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 476 if (ret) 477 return ret; 478 } 479 480 return 0; 481 } 482 483 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 484 { 485 struct ci_power_info *pi = ci_get_pi(rdev); 486 u32 data; 487 488 if (pi->caps_sq_ramping) { 489 data = RREG32_DIDT(DIDT_SQ_CTRL0); 490 if (enable) 491 data |= DIDT_CTRL_EN; 492 else 493 data &= ~DIDT_CTRL_EN; 494 WREG32_DIDT(DIDT_SQ_CTRL0, data); 495 } 496 497 if (pi->caps_db_ramping) { 498 data = RREG32_DIDT(DIDT_DB_CTRL0); 499 if (enable) 500 data |= DIDT_CTRL_EN; 501 else 502 data &= ~DIDT_CTRL_EN; 503 WREG32_DIDT(DIDT_DB_CTRL0, data); 504 } 505 506 if (pi->caps_td_ramping) { 507 data = RREG32_DIDT(DIDT_TD_CTRL0); 508 if (enable) 509 data |= DIDT_CTRL_EN; 510 else 511 data &= ~DIDT_CTRL_EN; 512 WREG32_DIDT(DIDT_TD_CTRL0, data); 513 } 514 515 if (pi->caps_tcp_ramping) { 516 data = RREG32_DIDT(DIDT_TCP_CTRL0); 517 if (enable) 518 data |= DIDT_CTRL_EN; 519 else 520 data &= ~DIDT_CTRL_EN; 521 WREG32_DIDT(DIDT_TCP_CTRL0, data); 522 } 523 } 524 525 static int ci_program_pt_config_registers(struct radeon_device *rdev, 526 const struct ci_pt_config_reg *cac_config_regs) 527 { 528 const struct ci_pt_config_reg *config_regs = cac_config_regs; 529 u32 data; 530 u32 cache = 0; 531 532 if (config_regs == NULL) 533 return -EINVAL; 534 535 while (config_regs->offset != 0xFFFFFFFF) { 536 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 537 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 538 } else { 539 switch (config_regs->type) { 540 case CISLANDS_CONFIGREG_SMC_IND: 541 data = RREG32_SMC(config_regs->offset); 542 break; 543 case CISLANDS_CONFIGREG_DIDT_IND: 544 data = RREG32_DIDT(config_regs->offset); 545 break; 546 default: 547 data = RREG32(config_regs->offset << 2); 548 break; 549 } 550 551 data &= ~config_regs->mask; 552 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 553 data |= cache; 554 555 switch (config_regs->type) { 556 case CISLANDS_CONFIGREG_SMC_IND: 557 WREG32_SMC(config_regs->offset, data); 558 break; 559 case CISLANDS_CONFIGREG_DIDT_IND: 560 WREG32_DIDT(config_regs->offset, data); 561 break; 562 default: 563 WREG32(config_regs->offset << 2, data); 564 break; 565 } 566 cache = 0; 567 } 568 config_regs++; 569 } 570 return 0; 571 } 572 573 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 574 { 575 struct ci_power_info *pi = ci_get_pi(rdev); 576 int ret; 577 578 if (pi->caps_sq_ramping || pi->caps_db_ramping || 579 pi->caps_td_ramping || pi->caps_tcp_ramping) { 580 cik_enter_rlc_safe_mode(rdev); 581 582 if (enable) { 583 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 584 if (ret) { 585 cik_exit_rlc_safe_mode(rdev); 586 return ret; 587 } 588 } 589 590 ci_do_enable_didt(rdev, enable); 591 592 cik_exit_rlc_safe_mode(rdev); 593 } 594 595 return 0; 596 } 597 598 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 599 { 600 struct ci_power_info *pi = ci_get_pi(rdev); 601 PPSMC_Result smc_result; 602 int ret = 0; 603 604 if (enable) { 605 pi->power_containment_features = 0; 606 if (pi->caps_power_containment) { 607 if (pi->enable_bapm_feature) { 608 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 609 if (smc_result != PPSMC_Result_OK) 610 ret = -EINVAL; 611 else 612 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 613 } 614 615 if (pi->enable_tdc_limit_feature) { 616 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 617 if (smc_result != PPSMC_Result_OK) 618 ret = -EINVAL; 619 else 620 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 621 } 622 623 if (pi->enable_pkg_pwr_tracking_feature) { 624 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 625 if (smc_result != PPSMC_Result_OK) { 626 ret = -EINVAL; 627 } else { 628 struct radeon_cac_tdp_table *cac_tdp_table = 629 rdev->pm.dpm.dyn_state.cac_tdp_table; 630 u32 default_pwr_limit = 631 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 632 633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 634 635 ci_set_power_limit(rdev, default_pwr_limit); 636 } 637 } 638 } 639 } else { 640 if (pi->caps_power_containment && pi->power_containment_features) { 641 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 642 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 643 644 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 645 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 646 647 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 648 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 649 pi->power_containment_features = 0; 650 } 651 } 652 653 return ret; 654 } 655 656 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 657 { 658 struct ci_power_info *pi = ci_get_pi(rdev); 659 PPSMC_Result smc_result; 660 int ret = 0; 661 662 if (pi->caps_cac) { 663 if (enable) { 664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 665 if (smc_result != PPSMC_Result_OK) { 666 ret = -EINVAL; 667 pi->cac_enabled = false; 668 } else { 669 pi->cac_enabled = true; 670 } 671 } else if (pi->cac_enabled) { 672 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 673 pi->cac_enabled = false; 674 } 675 } 676 677 return ret; 678 } 679 680 static int ci_power_control_set_level(struct radeon_device *rdev) 681 { 682 struct ci_power_info *pi = ci_get_pi(rdev); 683 struct radeon_cac_tdp_table *cac_tdp_table = 684 rdev->pm.dpm.dyn_state.cac_tdp_table; 685 s32 adjust_percent; 686 s32 target_tdp; 687 int ret = 0; 688 bool adjust_polarity = false; /* ??? */ 689 690 if (pi->caps_power_containment && 691 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) { 692 adjust_percent = adjust_polarity ? 693 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 694 target_tdp = ((100 + adjust_percent) * 695 (s32)cac_tdp_table->configurable_tdp) / 100; 696 target_tdp *= 256; 697 698 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 699 } 700 701 return ret; 702 } 703 704 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 705 { 706 struct ci_power_info *pi = ci_get_pi(rdev); 707 708 if (pi->uvd_power_gated == gate) 709 return; 710 711 pi->uvd_power_gated = gate; 712 713 ci_update_uvd_dpm(rdev, gate); 714 } 715 716 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 717 { 718 struct ci_power_info *pi = ci_get_pi(rdev); 719 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 720 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 721 722 if (vblank_time < switch_limit) 723 return true; 724 else 725 return false; 726 727 } 728 729 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 730 struct radeon_ps *rps) 731 { 732 struct ci_ps *ps = ci_get_ps(rps); 733 struct ci_power_info *pi = ci_get_pi(rdev); 734 struct radeon_clock_and_voltage_limits *max_limits; 735 bool disable_mclk_switching; 736 u32 sclk, mclk; 737 int i; 738 739 if (rps->vce_active) { 740 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 741 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 742 } else { 743 rps->evclk = 0; 744 rps->ecclk = 0; 745 } 746 747 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 748 ci_dpm_vblank_too_short(rdev)) 749 disable_mclk_switching = true; 750 else 751 disable_mclk_switching = false; 752 753 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 754 pi->battery_state = true; 755 else 756 pi->battery_state = false; 757 758 if (rdev->pm.dpm.ac_power) 759 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 760 else 761 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 762 763 if (rdev->pm.dpm.ac_power == false) { 764 for (i = 0; i < ps->performance_level_count; i++) { 765 if (ps->performance_levels[i].mclk > max_limits->mclk) 766 ps->performance_levels[i].mclk = max_limits->mclk; 767 if (ps->performance_levels[i].sclk > max_limits->sclk) 768 ps->performance_levels[i].sclk = max_limits->sclk; 769 } 770 } 771 772 /* XXX validate the min clocks required for display */ 773 774 if (disable_mclk_switching) { 775 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 776 sclk = ps->performance_levels[0].sclk; 777 } else { 778 mclk = ps->performance_levels[0].mclk; 779 sclk = ps->performance_levels[0].sclk; 780 } 781 782 if (rps->vce_active) { 783 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 784 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 785 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 786 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 787 } 788 789 ps->performance_levels[0].sclk = sclk; 790 ps->performance_levels[0].mclk = mclk; 791 792 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 793 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 794 795 if (disable_mclk_switching) { 796 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 797 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 798 } else { 799 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 800 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 801 } 802 } 803 804 static int ci_set_thermal_temperature_range(struct radeon_device *rdev, 805 int min_temp, int max_temp) 806 { 807 int low_temp = 0 * 1000; 808 int high_temp = 255 * 1000; 809 u32 tmp; 810 811 if (low_temp < min_temp) 812 low_temp = min_temp; 813 if (high_temp > max_temp) 814 high_temp = max_temp; 815 if (high_temp < low_temp) { 816 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 817 return -EINVAL; 818 } 819 820 tmp = RREG32_SMC(CG_THERMAL_INT); 821 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 822 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 823 CI_DIG_THERM_INTL(low_temp / 1000); 824 WREG32_SMC(CG_THERMAL_INT, tmp); 825 826 #if 0 827 /* XXX: need to figure out how to handle this properly */ 828 tmp = RREG32_SMC(CG_THERMAL_CTRL); 829 tmp &= DIG_THERM_DPM_MASK; 830 tmp |= DIG_THERM_DPM(high_temp / 1000); 831 WREG32_SMC(CG_THERMAL_CTRL, tmp); 832 #endif 833 834 rdev->pm.dpm.thermal.min_temp = low_temp; 835 rdev->pm.dpm.thermal.max_temp = high_temp; 836 837 return 0; 838 } 839 840 #if 0 841 static int ci_read_smc_soft_register(struct radeon_device *rdev, 842 u16 reg_offset, u32 *value) 843 { 844 struct ci_power_info *pi = ci_get_pi(rdev); 845 846 return ci_read_smc_sram_dword(rdev, 847 pi->soft_regs_start + reg_offset, 848 value, pi->sram_end); 849 } 850 #endif 851 852 static int ci_write_smc_soft_register(struct radeon_device *rdev, 853 u16 reg_offset, u32 value) 854 { 855 struct ci_power_info *pi = ci_get_pi(rdev); 856 857 return ci_write_smc_sram_dword(rdev, 858 pi->soft_regs_start + reg_offset, 859 value, pi->sram_end); 860 } 861 862 static void ci_init_fps_limits(struct radeon_device *rdev) 863 { 864 struct ci_power_info *pi = ci_get_pi(rdev); 865 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 866 867 if (pi->caps_fps) { 868 u16 tmp; 869 870 tmp = 45; 871 table->FpsHighT = cpu_to_be16(tmp); 872 873 tmp = 30; 874 table->FpsLowT = cpu_to_be16(tmp); 875 } 876 } 877 878 static int ci_update_sclk_t(struct radeon_device *rdev) 879 { 880 struct ci_power_info *pi = ci_get_pi(rdev); 881 int ret = 0; 882 u32 low_sclk_interrupt_t = 0; 883 884 if (pi->caps_sclk_throttle_low_notification) { 885 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 886 887 ret = ci_copy_bytes_to_smc(rdev, 888 pi->dpm_table_start + 889 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 890 (u8 *)&low_sclk_interrupt_t, 891 sizeof(u32), pi->sram_end); 892 893 } 894 895 return ret; 896 } 897 898 static void ci_get_leakage_voltages(struct radeon_device *rdev) 899 { 900 struct ci_power_info *pi = ci_get_pi(rdev); 901 u16 leakage_id, virtual_voltage_id; 902 u16 vddc, vddci; 903 int i; 904 905 pi->vddc_leakage.count = 0; 906 pi->vddci_leakage.count = 0; 907 908 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 909 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 910 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 911 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) 912 continue; 913 if (vddc != 0 && vddc != virtual_voltage_id) { 914 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 915 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 916 pi->vddc_leakage.count++; 917 } 918 } 919 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 920 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 921 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 922 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 923 virtual_voltage_id, 924 leakage_id) == 0) { 925 if (vddc != 0 && vddc != virtual_voltage_id) { 926 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 927 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 928 pi->vddc_leakage.count++; 929 } 930 if (vddci != 0 && vddci != virtual_voltage_id) { 931 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 932 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 933 pi->vddci_leakage.count++; 934 } 935 } 936 } 937 } 938 } 939 940 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 941 { 942 struct ci_power_info *pi = ci_get_pi(rdev); 943 bool want_thermal_protection; 944 enum radeon_dpm_event_src dpm_event_src; 945 u32 tmp; 946 947 switch (sources) { 948 case 0: 949 default: 950 want_thermal_protection = false; 951 break; 952 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 953 want_thermal_protection = true; 954 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 955 break; 956 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 957 want_thermal_protection = true; 958 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 959 break; 960 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 961 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 962 want_thermal_protection = true; 963 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 964 break; 965 } 966 967 if (want_thermal_protection) { 968 #if 0 969 /* XXX: need to figure out how to handle this properly */ 970 tmp = RREG32_SMC(CG_THERMAL_CTRL); 971 tmp &= DPM_EVENT_SRC_MASK; 972 tmp |= DPM_EVENT_SRC(dpm_event_src); 973 WREG32_SMC(CG_THERMAL_CTRL, tmp); 974 #endif 975 976 tmp = RREG32_SMC(GENERAL_PWRMGT); 977 if (pi->thermal_protection) 978 tmp &= ~THERMAL_PROTECTION_DIS; 979 else 980 tmp |= THERMAL_PROTECTION_DIS; 981 WREG32_SMC(GENERAL_PWRMGT, tmp); 982 } else { 983 tmp = RREG32_SMC(GENERAL_PWRMGT); 984 tmp |= THERMAL_PROTECTION_DIS; 985 WREG32_SMC(GENERAL_PWRMGT, tmp); 986 } 987 } 988 989 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 990 enum radeon_dpm_auto_throttle_src source, 991 bool enable) 992 { 993 struct ci_power_info *pi = ci_get_pi(rdev); 994 995 if (enable) { 996 if (!(pi->active_auto_throttle_sources & (1 << source))) { 997 pi->active_auto_throttle_sources |= 1 << source; 998 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 999 } 1000 } else { 1001 if (pi->active_auto_throttle_sources & (1 << source)) { 1002 pi->active_auto_throttle_sources &= ~(1 << source); 1003 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1004 } 1005 } 1006 } 1007 1008 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 1009 { 1010 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1011 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 1012 } 1013 1014 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 1015 { 1016 struct ci_power_info *pi = ci_get_pi(rdev); 1017 PPSMC_Result smc_result; 1018 1019 if (!pi->need_update_smu7_dpm_table) 1020 return 0; 1021 1022 if ((!pi->sclk_dpm_key_disabled) && 1023 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1024 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 1025 if (smc_result != PPSMC_Result_OK) 1026 return -EINVAL; 1027 } 1028 1029 if ((!pi->mclk_dpm_key_disabled) && 1030 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1031 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 1032 if (smc_result != PPSMC_Result_OK) 1033 return -EINVAL; 1034 } 1035 1036 pi->need_update_smu7_dpm_table = 0; 1037 return 0; 1038 } 1039 1040 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1041 { 1042 struct ci_power_info *pi = ci_get_pi(rdev); 1043 PPSMC_Result smc_result; 1044 1045 if (enable) { 1046 if (!pi->sclk_dpm_key_disabled) { 1047 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1048 if (smc_result != PPSMC_Result_OK) 1049 return -EINVAL; 1050 } 1051 1052 if (!pi->mclk_dpm_key_disabled) { 1053 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1054 if (smc_result != PPSMC_Result_OK) 1055 return -EINVAL; 1056 1057 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1058 1059 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1060 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1061 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1062 1063 udelay(10); 1064 1065 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1066 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1067 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1068 } 1069 } else { 1070 if (!pi->sclk_dpm_key_disabled) { 1071 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1072 if (smc_result != PPSMC_Result_OK) 1073 return -EINVAL; 1074 } 1075 1076 if (!pi->mclk_dpm_key_disabled) { 1077 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1078 if (smc_result != PPSMC_Result_OK) 1079 return -EINVAL; 1080 } 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int ci_start_dpm(struct radeon_device *rdev) 1087 { 1088 struct ci_power_info *pi = ci_get_pi(rdev); 1089 PPSMC_Result smc_result; 1090 int ret; 1091 u32 tmp; 1092 1093 tmp = RREG32_SMC(GENERAL_PWRMGT); 1094 tmp |= GLOBAL_PWRMGT_EN; 1095 WREG32_SMC(GENERAL_PWRMGT, tmp); 1096 1097 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1098 tmp |= DYNAMIC_PM_EN; 1099 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1100 1101 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1102 1103 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1104 1105 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1106 if (smc_result != PPSMC_Result_OK) 1107 return -EINVAL; 1108 1109 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1110 if (ret) 1111 return ret; 1112 1113 if (!pi->pcie_dpm_key_disabled) { 1114 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1115 if (smc_result != PPSMC_Result_OK) 1116 return -EINVAL; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1123 { 1124 struct ci_power_info *pi = ci_get_pi(rdev); 1125 PPSMC_Result smc_result; 1126 1127 if (!pi->need_update_smu7_dpm_table) 1128 return 0; 1129 1130 if ((!pi->sclk_dpm_key_disabled) && 1131 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1132 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1133 if (smc_result != PPSMC_Result_OK) 1134 return -EINVAL; 1135 } 1136 1137 if ((!pi->mclk_dpm_key_disabled) && 1138 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1139 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1140 if (smc_result != PPSMC_Result_OK) 1141 return -EINVAL; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static int ci_stop_dpm(struct radeon_device *rdev) 1148 { 1149 struct ci_power_info *pi = ci_get_pi(rdev); 1150 PPSMC_Result smc_result; 1151 int ret; 1152 u32 tmp; 1153 1154 tmp = RREG32_SMC(GENERAL_PWRMGT); 1155 tmp &= ~GLOBAL_PWRMGT_EN; 1156 WREG32_SMC(GENERAL_PWRMGT, tmp); 1157 1158 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1159 tmp &= ~DYNAMIC_PM_EN; 1160 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1161 1162 if (!pi->pcie_dpm_key_disabled) { 1163 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1164 if (smc_result != PPSMC_Result_OK) 1165 return -EINVAL; 1166 } 1167 1168 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1169 if (ret) 1170 return ret; 1171 1172 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1173 if (smc_result != PPSMC_Result_OK) 1174 return -EINVAL; 1175 1176 return 0; 1177 } 1178 1179 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1180 { 1181 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1182 1183 if (enable) 1184 tmp &= ~SCLK_PWRMGT_OFF; 1185 else 1186 tmp |= SCLK_PWRMGT_OFF; 1187 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1188 } 1189 1190 #if 0 1191 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1192 bool ac_power) 1193 { 1194 struct ci_power_info *pi = ci_get_pi(rdev); 1195 struct radeon_cac_tdp_table *cac_tdp_table = 1196 rdev->pm.dpm.dyn_state.cac_tdp_table; 1197 u32 power_limit; 1198 1199 if (ac_power) 1200 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1201 else 1202 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1203 1204 ci_set_power_limit(rdev, power_limit); 1205 1206 if (pi->caps_automatic_dc_transition) { 1207 if (ac_power) 1208 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1209 else 1210 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1211 } 1212 1213 return 0; 1214 } 1215 #endif 1216 1217 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1218 PPSMC_Msg msg, u32 parameter) 1219 { 1220 WREG32(SMC_MSG_ARG_0, parameter); 1221 return ci_send_msg_to_smc(rdev, msg); 1222 } 1223 1224 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1225 PPSMC_Msg msg, u32 *parameter) 1226 { 1227 PPSMC_Result smc_result; 1228 1229 smc_result = ci_send_msg_to_smc(rdev, msg); 1230 1231 if ((smc_result == PPSMC_Result_OK) && parameter) 1232 *parameter = RREG32(SMC_MSG_ARG_0); 1233 1234 return smc_result; 1235 } 1236 1237 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1238 { 1239 struct ci_power_info *pi = ci_get_pi(rdev); 1240 1241 if (!pi->sclk_dpm_key_disabled) { 1242 PPSMC_Result smc_result = 1243 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n); 1244 if (smc_result != PPSMC_Result_OK) 1245 return -EINVAL; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1252 { 1253 struct ci_power_info *pi = ci_get_pi(rdev); 1254 1255 if (!pi->mclk_dpm_key_disabled) { 1256 PPSMC_Result smc_result = 1257 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n); 1258 if (smc_result != PPSMC_Result_OK) 1259 return -EINVAL; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1266 { 1267 struct ci_power_info *pi = ci_get_pi(rdev); 1268 1269 if (!pi->pcie_dpm_key_disabled) { 1270 PPSMC_Result smc_result = 1271 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1272 if (smc_result != PPSMC_Result_OK) 1273 return -EINVAL; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1280 { 1281 struct ci_power_info *pi = ci_get_pi(rdev); 1282 1283 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1284 PPSMC_Result smc_result = 1285 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1286 if (smc_result != PPSMC_Result_OK) 1287 return -EINVAL; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1294 u32 target_tdp) 1295 { 1296 PPSMC_Result smc_result = 1297 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1298 if (smc_result != PPSMC_Result_OK) 1299 return -EINVAL; 1300 return 0; 1301 } 1302 1303 #if 0 1304 static int ci_set_boot_state(struct radeon_device *rdev) 1305 { 1306 return ci_enable_sclk_mclk_dpm(rdev, false); 1307 } 1308 #endif 1309 1310 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1311 { 1312 u32 sclk_freq; 1313 PPSMC_Result smc_result = 1314 ci_send_msg_to_smc_return_parameter(rdev, 1315 PPSMC_MSG_API_GetSclkFrequency, 1316 &sclk_freq); 1317 if (smc_result != PPSMC_Result_OK) 1318 sclk_freq = 0; 1319 1320 return sclk_freq; 1321 } 1322 1323 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1324 { 1325 u32 mclk_freq; 1326 PPSMC_Result smc_result = 1327 ci_send_msg_to_smc_return_parameter(rdev, 1328 PPSMC_MSG_API_GetMclkFrequency, 1329 &mclk_freq); 1330 if (smc_result != PPSMC_Result_OK) 1331 mclk_freq = 0; 1332 1333 return mclk_freq; 1334 } 1335 1336 static void ci_dpm_start_smc(struct radeon_device *rdev) 1337 { 1338 int i; 1339 1340 ci_program_jump_on_start(rdev); 1341 ci_start_smc_clock(rdev); 1342 ci_start_smc(rdev); 1343 for (i = 0; i < rdev->usec_timeout; i++) { 1344 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1345 break; 1346 } 1347 } 1348 1349 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1350 { 1351 ci_reset_smc(rdev); 1352 ci_stop_smc_clock(rdev); 1353 } 1354 1355 static int ci_process_firmware_header(struct radeon_device *rdev) 1356 { 1357 struct ci_power_info *pi = ci_get_pi(rdev); 1358 u32 tmp; 1359 int ret; 1360 1361 ret = ci_read_smc_sram_dword(rdev, 1362 SMU7_FIRMWARE_HEADER_LOCATION + 1363 offsetof(SMU7_Firmware_Header, DpmTable), 1364 &tmp, pi->sram_end); 1365 if (ret) 1366 return ret; 1367 1368 pi->dpm_table_start = tmp; 1369 1370 ret = ci_read_smc_sram_dword(rdev, 1371 SMU7_FIRMWARE_HEADER_LOCATION + 1372 offsetof(SMU7_Firmware_Header, SoftRegisters), 1373 &tmp, pi->sram_end); 1374 if (ret) 1375 return ret; 1376 1377 pi->soft_regs_start = tmp; 1378 1379 ret = ci_read_smc_sram_dword(rdev, 1380 SMU7_FIRMWARE_HEADER_LOCATION + 1381 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1382 &tmp, pi->sram_end); 1383 if (ret) 1384 return ret; 1385 1386 pi->mc_reg_table_start = tmp; 1387 1388 ret = ci_read_smc_sram_dword(rdev, 1389 SMU7_FIRMWARE_HEADER_LOCATION + 1390 offsetof(SMU7_Firmware_Header, FanTable), 1391 &tmp, pi->sram_end); 1392 if (ret) 1393 return ret; 1394 1395 pi->fan_table_start = tmp; 1396 1397 ret = ci_read_smc_sram_dword(rdev, 1398 SMU7_FIRMWARE_HEADER_LOCATION + 1399 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1400 &tmp, pi->sram_end); 1401 if (ret) 1402 return ret; 1403 1404 pi->arb_table_start = tmp; 1405 1406 return 0; 1407 } 1408 1409 static void ci_read_clock_registers(struct radeon_device *rdev) 1410 { 1411 struct ci_power_info *pi = ci_get_pi(rdev); 1412 1413 pi->clock_registers.cg_spll_func_cntl = 1414 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1415 pi->clock_registers.cg_spll_func_cntl_2 = 1416 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1417 pi->clock_registers.cg_spll_func_cntl_3 = 1418 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1419 pi->clock_registers.cg_spll_func_cntl_4 = 1420 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1421 pi->clock_registers.cg_spll_spread_spectrum = 1422 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1423 pi->clock_registers.cg_spll_spread_spectrum_2 = 1424 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1425 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1426 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1427 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1428 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1429 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1430 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1431 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1432 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1433 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1434 } 1435 1436 static void ci_init_sclk_t(struct radeon_device *rdev) 1437 { 1438 struct ci_power_info *pi = ci_get_pi(rdev); 1439 1440 pi->low_sclk_interrupt_t = 0; 1441 } 1442 1443 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1444 bool enable) 1445 { 1446 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1447 1448 if (enable) 1449 tmp &= ~THERMAL_PROTECTION_DIS; 1450 else 1451 tmp |= THERMAL_PROTECTION_DIS; 1452 WREG32_SMC(GENERAL_PWRMGT, tmp); 1453 } 1454 1455 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1456 { 1457 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1458 1459 tmp |= STATIC_PM_EN; 1460 1461 WREG32_SMC(GENERAL_PWRMGT, tmp); 1462 } 1463 1464 #if 0 1465 static int ci_enter_ulp_state(struct radeon_device *rdev) 1466 { 1467 1468 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1469 1470 udelay(25000); 1471 1472 return 0; 1473 } 1474 1475 static int ci_exit_ulp_state(struct radeon_device *rdev) 1476 { 1477 int i; 1478 1479 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1480 1481 udelay(7000); 1482 1483 for (i = 0; i < rdev->usec_timeout; i++) { 1484 if (RREG32(SMC_RESP_0) == 1) 1485 break; 1486 udelay(1000); 1487 } 1488 1489 return 0; 1490 } 1491 #endif 1492 1493 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1494 bool has_display) 1495 { 1496 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1497 1498 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1499 } 1500 1501 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1502 bool enable) 1503 { 1504 struct ci_power_info *pi = ci_get_pi(rdev); 1505 1506 if (enable) { 1507 if (pi->caps_sclk_ds) { 1508 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1509 return -EINVAL; 1510 } else { 1511 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1512 return -EINVAL; 1513 } 1514 } else { 1515 if (pi->caps_sclk_ds) { 1516 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1517 return -EINVAL; 1518 } 1519 } 1520 1521 return 0; 1522 } 1523 1524 static void ci_program_display_gap(struct radeon_device *rdev) 1525 { 1526 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1527 u32 pre_vbi_time_in_us; 1528 u32 frame_time_in_us; 1529 u32 ref_clock = rdev->clock.spll.reference_freq; 1530 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1531 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1532 1533 tmp &= ~DISP_GAP_MASK; 1534 if (rdev->pm.dpm.new_active_crtc_count > 0) 1535 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1536 else 1537 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1538 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1539 1540 if (refresh_rate == 0) 1541 refresh_rate = 60; 1542 if (vblank_time == 0xffffffff) 1543 vblank_time = 500; 1544 frame_time_in_us = 1000000 / refresh_rate; 1545 pre_vbi_time_in_us = 1546 frame_time_in_us - 200 - vblank_time; 1547 tmp = pre_vbi_time_in_us * (ref_clock / 100); 1548 1549 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 1550 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 1551 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 1552 1553 1554 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 1555 1556 } 1557 1558 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 1559 { 1560 struct ci_power_info *pi = ci_get_pi(rdev); 1561 u32 tmp; 1562 1563 if (enable) { 1564 if (pi->caps_sclk_ss_support) { 1565 tmp = RREG32_SMC(GENERAL_PWRMGT); 1566 tmp |= DYN_SPREAD_SPECTRUM_EN; 1567 WREG32_SMC(GENERAL_PWRMGT, tmp); 1568 } 1569 } else { 1570 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1571 tmp &= ~SSEN; 1572 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 1573 1574 tmp = RREG32_SMC(GENERAL_PWRMGT); 1575 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 1576 WREG32_SMC(GENERAL_PWRMGT, tmp); 1577 } 1578 } 1579 1580 static void ci_program_sstp(struct radeon_device *rdev) 1581 { 1582 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 1583 } 1584 1585 static void ci_enable_display_gap(struct radeon_device *rdev) 1586 { 1587 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1588 1589 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 1590 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 1591 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 1592 1593 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1594 } 1595 1596 static void ci_program_vc(struct radeon_device *rdev) 1597 { 1598 u32 tmp; 1599 1600 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1601 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 1602 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1603 1604 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 1605 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 1606 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 1607 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 1608 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 1609 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 1610 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 1611 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 1612 } 1613 1614 static void ci_clear_vc(struct radeon_device *rdev) 1615 { 1616 u32 tmp; 1617 1618 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1619 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 1620 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1621 1622 WREG32_SMC(CG_FTV_0, 0); 1623 WREG32_SMC(CG_FTV_1, 0); 1624 WREG32_SMC(CG_FTV_2, 0); 1625 WREG32_SMC(CG_FTV_3, 0); 1626 WREG32_SMC(CG_FTV_4, 0); 1627 WREG32_SMC(CG_FTV_5, 0); 1628 WREG32_SMC(CG_FTV_6, 0); 1629 WREG32_SMC(CG_FTV_7, 0); 1630 } 1631 1632 static int ci_upload_firmware(struct radeon_device *rdev) 1633 { 1634 struct ci_power_info *pi = ci_get_pi(rdev); 1635 int i, ret; 1636 1637 for (i = 0; i < rdev->usec_timeout; i++) { 1638 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 1639 break; 1640 } 1641 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 1642 1643 ci_stop_smc_clock(rdev); 1644 ci_reset_smc(rdev); 1645 1646 ret = ci_load_smc_ucode(rdev, pi->sram_end); 1647 1648 return ret; 1649 1650 } 1651 1652 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 1653 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 1654 struct atom_voltage_table *voltage_table) 1655 { 1656 u32 i; 1657 1658 if (voltage_dependency_table == NULL) 1659 return -EINVAL; 1660 1661 voltage_table->mask_low = 0; 1662 voltage_table->phase_delay = 0; 1663 1664 voltage_table->count = voltage_dependency_table->count; 1665 for (i = 0; i < voltage_table->count; i++) { 1666 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 1667 voltage_table->entries[i].smio_low = 0; 1668 } 1669 1670 return 0; 1671 } 1672 1673 static int ci_construct_voltage_tables(struct radeon_device *rdev) 1674 { 1675 struct ci_power_info *pi = ci_get_pi(rdev); 1676 int ret; 1677 1678 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1679 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 1680 VOLTAGE_OBJ_GPIO_LUT, 1681 &pi->vddc_voltage_table); 1682 if (ret) 1683 return ret; 1684 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1685 ret = ci_get_svi2_voltage_table(rdev, 1686 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 1687 &pi->vddc_voltage_table); 1688 if (ret) 1689 return ret; 1690 } 1691 1692 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 1693 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 1694 &pi->vddc_voltage_table); 1695 1696 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1697 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 1698 VOLTAGE_OBJ_GPIO_LUT, 1699 &pi->vddci_voltage_table); 1700 if (ret) 1701 return ret; 1702 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1703 ret = ci_get_svi2_voltage_table(rdev, 1704 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 1705 &pi->vddci_voltage_table); 1706 if (ret) 1707 return ret; 1708 } 1709 1710 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 1711 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 1712 &pi->vddci_voltage_table); 1713 1714 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1715 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 1716 VOLTAGE_OBJ_GPIO_LUT, 1717 &pi->mvdd_voltage_table); 1718 if (ret) 1719 return ret; 1720 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1721 ret = ci_get_svi2_voltage_table(rdev, 1722 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 1723 &pi->mvdd_voltage_table); 1724 if (ret) 1725 return ret; 1726 } 1727 1728 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 1729 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 1730 &pi->mvdd_voltage_table); 1731 1732 return 0; 1733 } 1734 1735 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 1736 struct atom_voltage_table_entry *voltage_table, 1737 SMU7_Discrete_VoltageLevel *smc_voltage_table) 1738 { 1739 int ret; 1740 1741 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 1742 &smc_voltage_table->StdVoltageHiSidd, 1743 &smc_voltage_table->StdVoltageLoSidd); 1744 1745 if (ret) { 1746 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 1747 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 1748 } 1749 1750 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 1751 smc_voltage_table->StdVoltageHiSidd = 1752 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 1753 smc_voltage_table->StdVoltageLoSidd = 1754 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 1755 } 1756 1757 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 1758 SMU7_Discrete_DpmTable *table) 1759 { 1760 struct ci_power_info *pi = ci_get_pi(rdev); 1761 unsigned int count; 1762 1763 table->VddcLevelCount = pi->vddc_voltage_table.count; 1764 for (count = 0; count < table->VddcLevelCount; count++) { 1765 ci_populate_smc_voltage_table(rdev, 1766 &pi->vddc_voltage_table.entries[count], 1767 &table->VddcLevel[count]); 1768 1769 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1770 table->VddcLevel[count].Smio |= 1771 pi->vddc_voltage_table.entries[count].smio_low; 1772 else 1773 table->VddcLevel[count].Smio = 0; 1774 } 1775 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 1776 1777 return 0; 1778 } 1779 1780 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 1781 SMU7_Discrete_DpmTable *table) 1782 { 1783 unsigned int count; 1784 struct ci_power_info *pi = ci_get_pi(rdev); 1785 1786 table->VddciLevelCount = pi->vddci_voltage_table.count; 1787 for (count = 0; count < table->VddciLevelCount; count++) { 1788 ci_populate_smc_voltage_table(rdev, 1789 &pi->vddci_voltage_table.entries[count], 1790 &table->VddciLevel[count]); 1791 1792 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1793 table->VddciLevel[count].Smio |= 1794 pi->vddci_voltage_table.entries[count].smio_low; 1795 else 1796 table->VddciLevel[count].Smio = 0; 1797 } 1798 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 1799 1800 return 0; 1801 } 1802 1803 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 1804 SMU7_Discrete_DpmTable *table) 1805 { 1806 struct ci_power_info *pi = ci_get_pi(rdev); 1807 unsigned int count; 1808 1809 table->MvddLevelCount = pi->mvdd_voltage_table.count; 1810 for (count = 0; count < table->MvddLevelCount; count++) { 1811 ci_populate_smc_voltage_table(rdev, 1812 &pi->mvdd_voltage_table.entries[count], 1813 &table->MvddLevel[count]); 1814 1815 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1816 table->MvddLevel[count].Smio |= 1817 pi->mvdd_voltage_table.entries[count].smio_low; 1818 else 1819 table->MvddLevel[count].Smio = 0; 1820 } 1821 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 1822 1823 return 0; 1824 } 1825 1826 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 1827 SMU7_Discrete_DpmTable *table) 1828 { 1829 int ret; 1830 1831 ret = ci_populate_smc_vddc_table(rdev, table); 1832 if (ret) 1833 return ret; 1834 1835 ret = ci_populate_smc_vddci_table(rdev, table); 1836 if (ret) 1837 return ret; 1838 1839 ret = ci_populate_smc_mvdd_table(rdev, table); 1840 if (ret) 1841 return ret; 1842 1843 return 0; 1844 } 1845 1846 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 1847 SMU7_Discrete_VoltageLevel *voltage) 1848 { 1849 struct ci_power_info *pi = ci_get_pi(rdev); 1850 u32 i = 0; 1851 1852 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 1853 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 1854 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 1855 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 1856 break; 1857 } 1858 } 1859 1860 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 1861 return -EINVAL; 1862 } 1863 1864 return -EINVAL; 1865 } 1866 1867 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 1868 struct atom_voltage_table_entry *voltage_table, 1869 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 1870 { 1871 u16 v_index, idx; 1872 bool voltage_found = false; 1873 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 1874 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 1875 1876 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 1877 return -EINVAL; 1878 1879 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 1880 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1881 if (voltage_table->value == 1882 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1883 voltage_found = true; 1884 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1885 idx = v_index; 1886 else 1887 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1888 *std_voltage_lo_sidd = 1889 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1890 *std_voltage_hi_sidd = 1891 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1892 break; 1893 } 1894 } 1895 1896 if (!voltage_found) { 1897 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1898 if (voltage_table->value <= 1899 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1900 voltage_found = true; 1901 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1902 idx = v_index; 1903 else 1904 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1905 *std_voltage_lo_sidd = 1906 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1907 *std_voltage_hi_sidd = 1908 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1909 break; 1910 } 1911 } 1912 } 1913 } 1914 1915 return 0; 1916 } 1917 1918 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 1919 const struct radeon_phase_shedding_limits_table *limits, 1920 u32 sclk, 1921 u32 *phase_shedding) 1922 { 1923 unsigned int i; 1924 1925 *phase_shedding = 1; 1926 1927 for (i = 0; i < limits->count; i++) { 1928 if (sclk < limits->entries[i].sclk) { 1929 *phase_shedding = i; 1930 break; 1931 } 1932 } 1933 } 1934 1935 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 1936 const struct radeon_phase_shedding_limits_table *limits, 1937 u32 mclk, 1938 u32 *phase_shedding) 1939 { 1940 unsigned int i; 1941 1942 *phase_shedding = 1; 1943 1944 for (i = 0; i < limits->count; i++) { 1945 if (mclk < limits->entries[i].mclk) { 1946 *phase_shedding = i; 1947 break; 1948 } 1949 } 1950 } 1951 1952 static int ci_init_arb_table_index(struct radeon_device *rdev) 1953 { 1954 struct ci_power_info *pi = ci_get_pi(rdev); 1955 u32 tmp; 1956 int ret; 1957 1958 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 1959 &tmp, pi->sram_end); 1960 if (ret) 1961 return ret; 1962 1963 tmp &= 0x00FFFFFF; 1964 tmp |= MC_CG_ARB_FREQ_F1 << 24; 1965 1966 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 1967 tmp, pi->sram_end); 1968 } 1969 1970 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 1971 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 1972 u32 clock, u32 *voltage) 1973 { 1974 u32 i = 0; 1975 1976 if (allowed_clock_voltage_table->count == 0) 1977 return -EINVAL; 1978 1979 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 1980 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 1981 *voltage = allowed_clock_voltage_table->entries[i].v; 1982 return 0; 1983 } 1984 } 1985 1986 *voltage = allowed_clock_voltage_table->entries[i-1].v; 1987 1988 return 0; 1989 } 1990 1991 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 1992 u32 sclk, u32 min_sclk_in_sr) 1993 { 1994 u32 i; 1995 u32 tmp; 1996 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 1997 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 1998 1999 if (sclk < min) 2000 return 0; 2001 2002 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 2003 tmp = sclk / (1 << i); 2004 if (tmp >= min || i == 0) 2005 break; 2006 } 2007 2008 return (u8)i; 2009 } 2010 2011 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 2012 { 2013 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2014 } 2015 2016 static int ci_reset_to_default(struct radeon_device *rdev) 2017 { 2018 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 2019 0 : -EINVAL; 2020 } 2021 2022 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 2023 { 2024 u32 tmp; 2025 2026 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 2027 2028 if (tmp == MC_CG_ARB_FREQ_F0) 2029 return 0; 2030 2031 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 2032 } 2033 2034 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 2035 u32 sclk, 2036 u32 mclk, 2037 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2038 { 2039 u32 dram_timing; 2040 u32 dram_timing2; 2041 u32 burst_time; 2042 2043 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2044 2045 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2046 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2047 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2048 2049 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2050 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2051 arb_regs->McArbBurstTime = (u8)burst_time; 2052 2053 return 0; 2054 } 2055 2056 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2057 { 2058 struct ci_power_info *pi = ci_get_pi(rdev); 2059 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2060 u32 i, j; 2061 int ret = 0; 2062 2063 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2064 2065 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2066 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2067 ret = ci_populate_memory_timing_parameters(rdev, 2068 pi->dpm_table.sclk_table.dpm_levels[i].value, 2069 pi->dpm_table.mclk_table.dpm_levels[j].value, 2070 &arb_regs.entries[i][j]); 2071 if (ret) 2072 break; 2073 } 2074 } 2075 2076 if (ret == 0) 2077 ret = ci_copy_bytes_to_smc(rdev, 2078 pi->arb_table_start, 2079 (u8 *)&arb_regs, 2080 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2081 pi->sram_end); 2082 2083 return ret; 2084 } 2085 2086 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2087 { 2088 struct ci_power_info *pi = ci_get_pi(rdev); 2089 2090 if (pi->need_update_smu7_dpm_table == 0) 2091 return 0; 2092 2093 return ci_do_program_memory_timing_parameters(rdev); 2094 } 2095 2096 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2097 struct radeon_ps *radeon_boot_state) 2098 { 2099 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2100 struct ci_power_info *pi = ci_get_pi(rdev); 2101 u32 level = 0; 2102 2103 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2104 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2105 boot_state->performance_levels[0].sclk) { 2106 pi->smc_state_table.GraphicsBootLevel = level; 2107 break; 2108 } 2109 } 2110 2111 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2112 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2113 boot_state->performance_levels[0].mclk) { 2114 pi->smc_state_table.MemoryBootLevel = level; 2115 break; 2116 } 2117 } 2118 } 2119 2120 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2121 { 2122 u32 i; 2123 u32 mask_value = 0; 2124 2125 for (i = dpm_table->count; i > 0; i--) { 2126 mask_value = mask_value << 1; 2127 if (dpm_table->dpm_levels[i-1].enabled) 2128 mask_value |= 0x1; 2129 else 2130 mask_value &= 0xFFFFFFFE; 2131 } 2132 2133 return mask_value; 2134 } 2135 2136 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2137 SMU7_Discrete_DpmTable *table) 2138 { 2139 struct ci_power_info *pi = ci_get_pi(rdev); 2140 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2141 u32 i; 2142 2143 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2144 table->LinkLevel[i].PcieGenSpeed = 2145 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2146 table->LinkLevel[i].PcieLaneCount = 2147 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2148 table->LinkLevel[i].EnabledForActivity = 1; 2149 table->LinkLevel[i].DownT = cpu_to_be32(5); 2150 table->LinkLevel[i].UpT = cpu_to_be32(30); 2151 } 2152 2153 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2154 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2155 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2156 } 2157 2158 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2159 SMU7_Discrete_DpmTable *table) 2160 { 2161 u32 count; 2162 struct atom_clock_dividers dividers; 2163 int ret = -EINVAL; 2164 2165 table->UvdLevelCount = 2166 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2167 2168 for (count = 0; count < table->UvdLevelCount; count++) { 2169 table->UvdLevel[count].VclkFrequency = 2170 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2171 table->UvdLevel[count].DclkFrequency = 2172 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2173 table->UvdLevel[count].MinVddc = 2174 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2175 table->UvdLevel[count].MinVddcPhases = 1; 2176 2177 ret = radeon_atom_get_clock_dividers(rdev, 2178 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2179 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2180 if (ret) 2181 return ret; 2182 2183 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2184 2185 ret = radeon_atom_get_clock_dividers(rdev, 2186 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2187 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2188 if (ret) 2189 return ret; 2190 2191 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2192 2193 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2194 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2195 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2196 } 2197 2198 return ret; 2199 } 2200 2201 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2202 SMU7_Discrete_DpmTable *table) 2203 { 2204 u32 count; 2205 struct atom_clock_dividers dividers; 2206 int ret = -EINVAL; 2207 2208 table->VceLevelCount = 2209 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2210 2211 for (count = 0; count < table->VceLevelCount; count++) { 2212 table->VceLevel[count].Frequency = 2213 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2214 table->VceLevel[count].MinVoltage = 2215 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2216 table->VceLevel[count].MinPhases = 1; 2217 2218 ret = radeon_atom_get_clock_dividers(rdev, 2219 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2220 table->VceLevel[count].Frequency, false, ÷rs); 2221 if (ret) 2222 return ret; 2223 2224 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2225 2226 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2227 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2228 } 2229 2230 return ret; 2231 2232 } 2233 2234 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2235 SMU7_Discrete_DpmTable *table) 2236 { 2237 u32 count; 2238 struct atom_clock_dividers dividers; 2239 int ret = -EINVAL; 2240 2241 table->AcpLevelCount = (u8) 2242 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2243 2244 for (count = 0; count < table->AcpLevelCount; count++) { 2245 table->AcpLevel[count].Frequency = 2246 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2247 table->AcpLevel[count].MinVoltage = 2248 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2249 table->AcpLevel[count].MinPhases = 1; 2250 2251 ret = radeon_atom_get_clock_dividers(rdev, 2252 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2253 table->AcpLevel[count].Frequency, false, ÷rs); 2254 if (ret) 2255 return ret; 2256 2257 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2258 2259 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2260 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2261 } 2262 2263 return ret; 2264 } 2265 2266 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2267 SMU7_Discrete_DpmTable *table) 2268 { 2269 u32 count; 2270 struct atom_clock_dividers dividers; 2271 int ret = -EINVAL; 2272 2273 table->SamuLevelCount = 2274 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2275 2276 for (count = 0; count < table->SamuLevelCount; count++) { 2277 table->SamuLevel[count].Frequency = 2278 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2279 table->SamuLevel[count].MinVoltage = 2280 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2281 table->SamuLevel[count].MinPhases = 1; 2282 2283 ret = radeon_atom_get_clock_dividers(rdev, 2284 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2285 table->SamuLevel[count].Frequency, false, ÷rs); 2286 if (ret) 2287 return ret; 2288 2289 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2290 2291 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2292 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2293 } 2294 2295 return ret; 2296 } 2297 2298 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2299 u32 memory_clock, 2300 SMU7_Discrete_MemoryLevel *mclk, 2301 bool strobe_mode, 2302 bool dll_state_on) 2303 { 2304 struct ci_power_info *pi = ci_get_pi(rdev); 2305 u32 dll_cntl = pi->clock_registers.dll_cntl; 2306 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2307 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2308 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2309 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2310 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2311 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2312 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2313 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2314 struct atom_mpll_param mpll_param; 2315 int ret; 2316 2317 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2318 if (ret) 2319 return ret; 2320 2321 mpll_func_cntl &= ~BWCTRL_MASK; 2322 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2323 2324 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2325 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2326 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2327 2328 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2329 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2330 2331 if (pi->mem_gddr5) { 2332 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2333 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2334 YCLK_POST_DIV(mpll_param.post_div); 2335 } 2336 2337 if (pi->caps_mclk_ss_support) { 2338 struct radeon_atom_ss ss; 2339 u32 freq_nom; 2340 u32 tmp; 2341 u32 reference_clock = rdev->clock.mpll.reference_freq; 2342 2343 if (pi->mem_gddr5) 2344 freq_nom = memory_clock * 4; 2345 else 2346 freq_nom = memory_clock * 2; 2347 2348 tmp = (freq_nom / reference_clock); 2349 tmp = tmp * tmp; 2350 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2351 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2352 u32 clks = reference_clock * 5 / ss.rate; 2353 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2354 2355 mpll_ss1 &= ~CLKV_MASK; 2356 mpll_ss1 |= CLKV(clkv); 2357 2358 mpll_ss2 &= ~CLKS_MASK; 2359 mpll_ss2 |= CLKS(clks); 2360 } 2361 } 2362 2363 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2364 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2365 2366 if (dll_state_on) 2367 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2368 else 2369 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2370 2371 mclk->MclkFrequency = memory_clock; 2372 mclk->MpllFuncCntl = mpll_func_cntl; 2373 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2374 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2375 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2376 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2377 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2378 mclk->DllCntl = dll_cntl; 2379 mclk->MpllSs1 = mpll_ss1; 2380 mclk->MpllSs2 = mpll_ss2; 2381 2382 return 0; 2383 } 2384 2385 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2386 u32 memory_clock, 2387 SMU7_Discrete_MemoryLevel *memory_level) 2388 { 2389 struct ci_power_info *pi = ci_get_pi(rdev); 2390 int ret; 2391 bool dll_state_on; 2392 2393 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2394 ret = ci_get_dependency_volt_by_clk(rdev, 2395 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2396 memory_clock, &memory_level->MinVddc); 2397 if (ret) 2398 return ret; 2399 } 2400 2401 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2402 ret = ci_get_dependency_volt_by_clk(rdev, 2403 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2404 memory_clock, &memory_level->MinVddci); 2405 if (ret) 2406 return ret; 2407 } 2408 2409 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2410 ret = ci_get_dependency_volt_by_clk(rdev, 2411 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2412 memory_clock, &memory_level->MinMvdd); 2413 if (ret) 2414 return ret; 2415 } 2416 2417 memory_level->MinVddcPhases = 1; 2418 2419 if (pi->vddc_phase_shed_control) 2420 ci_populate_phase_value_based_on_mclk(rdev, 2421 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2422 memory_clock, 2423 &memory_level->MinVddcPhases); 2424 2425 memory_level->EnabledForThrottle = 1; 2426 memory_level->EnabledForActivity = 1; 2427 memory_level->UpH = 0; 2428 memory_level->DownH = 100; 2429 memory_level->VoltageDownH = 0; 2430 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2431 2432 memory_level->StutterEnable = false; 2433 memory_level->StrobeEnable = false; 2434 memory_level->EdcReadEnable = false; 2435 memory_level->EdcWriteEnable = false; 2436 memory_level->RttEnable = false; 2437 2438 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2439 2440 if (pi->mclk_stutter_mode_threshold && 2441 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2442 (pi->uvd_enabled == false) && 2443 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2444 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2445 memory_level->StutterEnable = true; 2446 2447 if (pi->mclk_strobe_mode_threshold && 2448 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2449 memory_level->StrobeEnable = 1; 2450 2451 if (pi->mem_gddr5) { 2452 memory_level->StrobeRatio = 2453 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2454 if (pi->mclk_edc_enable_threshold && 2455 (memory_clock > pi->mclk_edc_enable_threshold)) 2456 memory_level->EdcReadEnable = true; 2457 2458 if (pi->mclk_edc_wr_enable_threshold && 2459 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2460 memory_level->EdcWriteEnable = true; 2461 2462 if (memory_level->StrobeEnable) { 2463 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2464 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2465 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2466 else 2467 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2468 } else { 2469 dll_state_on = pi->dll_default_on; 2470 } 2471 } else { 2472 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2473 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2474 } 2475 2476 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2477 if (ret) 2478 return ret; 2479 2480 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2481 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2482 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2483 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2484 2485 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2486 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2487 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2488 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2489 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2490 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2491 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2492 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2493 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2494 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2495 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2496 2497 return 0; 2498 } 2499 2500 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2501 SMU7_Discrete_DpmTable *table) 2502 { 2503 struct ci_power_info *pi = ci_get_pi(rdev); 2504 struct atom_clock_dividers dividers; 2505 SMU7_Discrete_VoltageLevel voltage_level; 2506 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2507 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2508 u32 dll_cntl = pi->clock_registers.dll_cntl; 2509 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2510 int ret; 2511 2512 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2513 2514 if (pi->acpi_vddc) 2515 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2516 else 2517 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2518 2519 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2520 2521 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2522 2523 ret = radeon_atom_get_clock_dividers(rdev, 2524 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2525 table->ACPILevel.SclkFrequency, false, ÷rs); 2526 if (ret) 2527 return ret; 2528 2529 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2530 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2531 table->ACPILevel.DeepSleepDivId = 0; 2532 2533 spll_func_cntl &= ~SPLL_PWRON; 2534 spll_func_cntl |= SPLL_RESET; 2535 2536 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2537 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 2538 2539 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 2540 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 2541 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 2542 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 2543 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 2544 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2545 table->ACPILevel.CcPwrDynRm = 0; 2546 table->ACPILevel.CcPwrDynRm1 = 0; 2547 2548 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 2549 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 2550 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 2551 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 2552 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 2553 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 2554 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 2555 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 2556 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 2557 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 2558 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 2559 2560 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 2561 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 2562 2563 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2564 if (pi->acpi_vddci) 2565 table->MemoryACPILevel.MinVddci = 2566 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 2567 else 2568 table->MemoryACPILevel.MinVddci = 2569 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 2570 } 2571 2572 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 2573 table->MemoryACPILevel.MinMvdd = 0; 2574 else 2575 table->MemoryACPILevel.MinMvdd = 2576 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 2577 2578 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 2579 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2580 2581 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 2582 2583 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 2584 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 2585 table->MemoryACPILevel.MpllAdFuncCntl = 2586 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 2587 table->MemoryACPILevel.MpllDqFuncCntl = 2588 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 2589 table->MemoryACPILevel.MpllFuncCntl = 2590 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 2591 table->MemoryACPILevel.MpllFuncCntl_1 = 2592 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 2593 table->MemoryACPILevel.MpllFuncCntl_2 = 2594 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 2595 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 2596 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 2597 2598 table->MemoryACPILevel.EnabledForThrottle = 0; 2599 table->MemoryACPILevel.EnabledForActivity = 0; 2600 table->MemoryACPILevel.UpH = 0; 2601 table->MemoryACPILevel.DownH = 100; 2602 table->MemoryACPILevel.VoltageDownH = 0; 2603 table->MemoryACPILevel.ActivityLevel = 2604 cpu_to_be16((u16)pi->mclk_activity_target); 2605 2606 table->MemoryACPILevel.StutterEnable = false; 2607 table->MemoryACPILevel.StrobeEnable = false; 2608 table->MemoryACPILevel.EdcReadEnable = false; 2609 table->MemoryACPILevel.EdcWriteEnable = false; 2610 table->MemoryACPILevel.RttEnable = false; 2611 2612 return 0; 2613 } 2614 2615 2616 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 2617 { 2618 struct ci_power_info *pi = ci_get_pi(rdev); 2619 struct ci_ulv_parm *ulv = &pi->ulv; 2620 2621 if (ulv->supported) { 2622 if (enable) 2623 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 2624 0 : -EINVAL; 2625 else 2626 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 2627 0 : -EINVAL; 2628 } 2629 2630 return 0; 2631 } 2632 2633 static int ci_populate_ulv_level(struct radeon_device *rdev, 2634 SMU7_Discrete_Ulv *state) 2635 { 2636 struct ci_power_info *pi = ci_get_pi(rdev); 2637 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 2638 2639 state->CcPwrDynRm = 0; 2640 state->CcPwrDynRm1 = 0; 2641 2642 if (ulv_voltage == 0) { 2643 pi->ulv.supported = false; 2644 return 0; 2645 } 2646 2647 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2648 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2649 state->VddcOffset = 0; 2650 else 2651 state->VddcOffset = 2652 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 2653 } else { 2654 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2655 state->VddcOffsetVid = 0; 2656 else 2657 state->VddcOffsetVid = (u8) 2658 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 2659 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2660 } 2661 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 2662 2663 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 2664 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 2665 state->VddcOffset = cpu_to_be16(state->VddcOffset); 2666 2667 return 0; 2668 } 2669 2670 static int ci_calculate_sclk_params(struct radeon_device *rdev, 2671 u32 engine_clock, 2672 SMU7_Discrete_GraphicsLevel *sclk) 2673 { 2674 struct ci_power_info *pi = ci_get_pi(rdev); 2675 struct atom_clock_dividers dividers; 2676 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 2677 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 2678 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 2679 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2680 u32 reference_clock = rdev->clock.spll.reference_freq; 2681 u32 reference_divider; 2682 u32 fbdiv; 2683 int ret; 2684 2685 ret = radeon_atom_get_clock_dividers(rdev, 2686 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2687 engine_clock, false, ÷rs); 2688 if (ret) 2689 return ret; 2690 2691 reference_divider = 1 + dividers.ref_div; 2692 fbdiv = dividers.fb_div & 0x3FFFFFF; 2693 2694 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 2695 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 2696 spll_func_cntl_3 |= SPLL_DITHEN; 2697 2698 if (pi->caps_sclk_ss_support) { 2699 struct radeon_atom_ss ss; 2700 u32 vco_freq = engine_clock * dividers.post_div; 2701 2702 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2703 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 2704 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 2705 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 2706 2707 cg_spll_spread_spectrum &= ~CLK_S_MASK; 2708 cg_spll_spread_spectrum |= CLK_S(clk_s); 2709 cg_spll_spread_spectrum |= SSEN; 2710 2711 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 2712 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 2713 } 2714 } 2715 2716 sclk->SclkFrequency = engine_clock; 2717 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 2718 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 2719 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 2720 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 2721 sclk->SclkDid = (u8)dividers.post_divider; 2722 2723 return 0; 2724 } 2725 2726 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 2727 u32 engine_clock, 2728 u16 sclk_activity_level_t, 2729 SMU7_Discrete_GraphicsLevel *graphic_level) 2730 { 2731 struct ci_power_info *pi = ci_get_pi(rdev); 2732 int ret; 2733 2734 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 2735 if (ret) 2736 return ret; 2737 2738 ret = ci_get_dependency_volt_by_clk(rdev, 2739 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2740 engine_clock, &graphic_level->MinVddc); 2741 if (ret) 2742 return ret; 2743 2744 graphic_level->SclkFrequency = engine_clock; 2745 2746 graphic_level->Flags = 0; 2747 graphic_level->MinVddcPhases = 1; 2748 2749 if (pi->vddc_phase_shed_control) 2750 ci_populate_phase_value_based_on_sclk(rdev, 2751 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2752 engine_clock, 2753 &graphic_level->MinVddcPhases); 2754 2755 graphic_level->ActivityLevel = sclk_activity_level_t; 2756 2757 graphic_level->CcPwrDynRm = 0; 2758 graphic_level->CcPwrDynRm1 = 0; 2759 graphic_level->EnabledForActivity = 1; 2760 graphic_level->EnabledForThrottle = 1; 2761 graphic_level->UpH = 0; 2762 graphic_level->DownH = 0; 2763 graphic_level->VoltageDownH = 0; 2764 graphic_level->PowerThrottle = 0; 2765 2766 if (pi->caps_sclk_ds) 2767 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 2768 engine_clock, 2769 CISLAND_MINIMUM_ENGINE_CLOCK); 2770 2771 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2772 2773 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 2774 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 2775 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 2776 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 2777 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 2778 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 2779 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 2780 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 2781 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 2782 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 2783 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 2784 2785 return 0; 2786 } 2787 2788 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 2789 { 2790 struct ci_power_info *pi = ci_get_pi(rdev); 2791 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2792 u32 level_array_address = pi->dpm_table_start + 2793 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 2794 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 2795 SMU7_MAX_LEVELS_GRAPHICS; 2796 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 2797 u32 i, ret; 2798 2799 memset(levels, 0, level_array_size); 2800 2801 for (i = 0; i < dpm_table->sclk_table.count; i++) { 2802 ret = ci_populate_single_graphic_level(rdev, 2803 dpm_table->sclk_table.dpm_levels[i].value, 2804 (u16)pi->activity_target[i], 2805 &pi->smc_state_table.GraphicsLevel[i]); 2806 if (ret) 2807 return ret; 2808 if (i == (dpm_table->sclk_table.count - 1)) 2809 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 2810 PPSMC_DISPLAY_WATERMARK_HIGH; 2811 } 2812 2813 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 2814 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 2815 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 2816 2817 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2818 (u8 *)levels, level_array_size, 2819 pi->sram_end); 2820 if (ret) 2821 return ret; 2822 2823 return 0; 2824 } 2825 2826 static int ci_populate_ulv_state(struct radeon_device *rdev, 2827 SMU7_Discrete_Ulv *ulv_level) 2828 { 2829 return ci_populate_ulv_level(rdev, ulv_level); 2830 } 2831 2832 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 2833 { 2834 struct ci_power_info *pi = ci_get_pi(rdev); 2835 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2836 u32 level_array_address = pi->dpm_table_start + 2837 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 2838 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 2839 SMU7_MAX_LEVELS_MEMORY; 2840 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 2841 u32 i, ret; 2842 2843 memset(levels, 0, level_array_size); 2844 2845 for (i = 0; i < dpm_table->mclk_table.count; i++) { 2846 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 2847 return -EINVAL; 2848 ret = ci_populate_single_memory_level(rdev, 2849 dpm_table->mclk_table.dpm_levels[i].value, 2850 &pi->smc_state_table.MemoryLevel[i]); 2851 if (ret) 2852 return ret; 2853 } 2854 2855 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 2856 2857 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 2858 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 2859 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 2860 2861 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 2862 PPSMC_DISPLAY_WATERMARK_HIGH; 2863 2864 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2865 (u8 *)levels, level_array_size, 2866 pi->sram_end); 2867 if (ret) 2868 return ret; 2869 2870 return 0; 2871 } 2872 2873 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 2874 struct ci_single_dpm_table* dpm_table, 2875 u32 count) 2876 { 2877 u32 i; 2878 2879 dpm_table->count = count; 2880 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 2881 dpm_table->dpm_levels[i].enabled = false; 2882 } 2883 2884 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, 2885 u32 index, u32 pcie_gen, u32 pcie_lanes) 2886 { 2887 dpm_table->dpm_levels[index].value = pcie_gen; 2888 dpm_table->dpm_levels[index].param1 = pcie_lanes; 2889 dpm_table->dpm_levels[index].enabled = true; 2890 } 2891 2892 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 2893 { 2894 struct ci_power_info *pi = ci_get_pi(rdev); 2895 2896 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 2897 return -EINVAL; 2898 2899 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 2900 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 2901 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 2902 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 2903 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 2904 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 2905 } 2906 2907 ci_reset_single_dpm_table(rdev, 2908 &pi->dpm_table.pcie_speed_table, 2909 SMU7_MAX_LEVELS_LINK); 2910 2911 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 2912 pi->pcie_gen_powersaving.min, 2913 pi->pcie_lane_powersaving.min); 2914 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 2915 pi->pcie_gen_performance.min, 2916 pi->pcie_lane_performance.min); 2917 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 2918 pi->pcie_gen_powersaving.min, 2919 pi->pcie_lane_powersaving.max); 2920 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 2921 pi->pcie_gen_performance.min, 2922 pi->pcie_lane_performance.max); 2923 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 2924 pi->pcie_gen_powersaving.max, 2925 pi->pcie_lane_powersaving.max); 2926 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 2927 pi->pcie_gen_performance.max, 2928 pi->pcie_lane_performance.max); 2929 2930 pi->dpm_table.pcie_speed_table.count = 6; 2931 2932 return 0; 2933 } 2934 2935 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 2936 { 2937 struct ci_power_info *pi = ci_get_pi(rdev); 2938 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 2939 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2940 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 2941 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 2942 struct radeon_cac_leakage_table *std_voltage_table = 2943 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2944 u32 i; 2945 2946 if (allowed_sclk_vddc_table == NULL) 2947 return -EINVAL; 2948 if (allowed_sclk_vddc_table->count < 1) 2949 return -EINVAL; 2950 if (allowed_mclk_table == NULL) 2951 return -EINVAL; 2952 if (allowed_mclk_table->count < 1) 2953 return -EINVAL; 2954 2955 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 2956 2957 ci_reset_single_dpm_table(rdev, 2958 &pi->dpm_table.sclk_table, 2959 SMU7_MAX_LEVELS_GRAPHICS); 2960 ci_reset_single_dpm_table(rdev, 2961 &pi->dpm_table.mclk_table, 2962 SMU7_MAX_LEVELS_MEMORY); 2963 ci_reset_single_dpm_table(rdev, 2964 &pi->dpm_table.vddc_table, 2965 SMU7_MAX_LEVELS_VDDC); 2966 ci_reset_single_dpm_table(rdev, 2967 &pi->dpm_table.vddci_table, 2968 SMU7_MAX_LEVELS_VDDCI); 2969 ci_reset_single_dpm_table(rdev, 2970 &pi->dpm_table.mvdd_table, 2971 SMU7_MAX_LEVELS_MVDD); 2972 2973 pi->dpm_table.sclk_table.count = 0; 2974 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2975 if ((i == 0) || 2976 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 2977 allowed_sclk_vddc_table->entries[i].clk)) { 2978 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 2979 allowed_sclk_vddc_table->entries[i].clk; 2980 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true; 2981 pi->dpm_table.sclk_table.count++; 2982 } 2983 } 2984 2985 pi->dpm_table.mclk_table.count = 0; 2986 for (i = 0; i < allowed_mclk_table->count; i++) { 2987 if ((i==0) || 2988 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 2989 allowed_mclk_table->entries[i].clk)) { 2990 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 2991 allowed_mclk_table->entries[i].clk; 2992 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true; 2993 pi->dpm_table.mclk_table.count++; 2994 } 2995 } 2996 2997 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2998 pi->dpm_table.vddc_table.dpm_levels[i].value = 2999 allowed_sclk_vddc_table->entries[i].v; 3000 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 3001 std_voltage_table->entries[i].leakage; 3002 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 3003 } 3004 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 3005 3006 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 3007 if (allowed_mclk_table) { 3008 for (i = 0; i < allowed_mclk_table->count; i++) { 3009 pi->dpm_table.vddci_table.dpm_levels[i].value = 3010 allowed_mclk_table->entries[i].v; 3011 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 3012 } 3013 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 3014 } 3015 3016 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 3017 if (allowed_mclk_table) { 3018 for (i = 0; i < allowed_mclk_table->count; i++) { 3019 pi->dpm_table.mvdd_table.dpm_levels[i].value = 3020 allowed_mclk_table->entries[i].v; 3021 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 3022 } 3023 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 3024 } 3025 3026 ci_setup_default_pcie_tables(rdev); 3027 3028 return 0; 3029 } 3030 3031 static int ci_find_boot_level(struct ci_single_dpm_table *table, 3032 u32 value, u32 *boot_level) 3033 { 3034 u32 i; 3035 int ret = -EINVAL; 3036 3037 for(i = 0; i < table->count; i++) { 3038 if (value == table->dpm_levels[i].value) { 3039 *boot_level = i; 3040 ret = 0; 3041 } 3042 } 3043 3044 return ret; 3045 } 3046 3047 static int ci_init_smc_table(struct radeon_device *rdev) 3048 { 3049 struct ci_power_info *pi = ci_get_pi(rdev); 3050 struct ci_ulv_parm *ulv = &pi->ulv; 3051 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3052 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3053 int ret; 3054 3055 ret = ci_setup_default_dpm_tables(rdev); 3056 if (ret) 3057 return ret; 3058 3059 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3060 ci_populate_smc_voltage_tables(rdev, table); 3061 3062 ci_init_fps_limits(rdev); 3063 3064 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3065 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3066 3067 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3068 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3069 3070 if (pi->mem_gddr5) 3071 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3072 3073 if (ulv->supported) { 3074 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3075 if (ret) 3076 return ret; 3077 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3078 } 3079 3080 ret = ci_populate_all_graphic_levels(rdev); 3081 if (ret) 3082 return ret; 3083 3084 ret = ci_populate_all_memory_levels(rdev); 3085 if (ret) 3086 return ret; 3087 3088 ci_populate_smc_link_level(rdev, table); 3089 3090 ret = ci_populate_smc_acpi_level(rdev, table); 3091 if (ret) 3092 return ret; 3093 3094 ret = ci_populate_smc_vce_level(rdev, table); 3095 if (ret) 3096 return ret; 3097 3098 ret = ci_populate_smc_acp_level(rdev, table); 3099 if (ret) 3100 return ret; 3101 3102 ret = ci_populate_smc_samu_level(rdev, table); 3103 if (ret) 3104 return ret; 3105 3106 ret = ci_do_program_memory_timing_parameters(rdev); 3107 if (ret) 3108 return ret; 3109 3110 ret = ci_populate_smc_uvd_level(rdev, table); 3111 if (ret) 3112 return ret; 3113 3114 table->UvdBootLevel = 0; 3115 table->VceBootLevel = 0; 3116 table->AcpBootLevel = 0; 3117 table->SamuBootLevel = 0; 3118 table->GraphicsBootLevel = 0; 3119 table->MemoryBootLevel = 0; 3120 3121 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3122 pi->vbios_boot_state.sclk_bootup_value, 3123 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3124 3125 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3126 pi->vbios_boot_state.mclk_bootup_value, 3127 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3128 3129 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3130 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3131 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3132 3133 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3134 3135 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3136 if (ret) 3137 return ret; 3138 3139 table->UVDInterval = 1; 3140 table->VCEInterval = 1; 3141 table->ACPInterval = 1; 3142 table->SAMUInterval = 1; 3143 table->GraphicsVoltageChangeEnable = 1; 3144 table->GraphicsThermThrottleEnable = 1; 3145 table->GraphicsInterval = 1; 3146 table->VoltageInterval = 1; 3147 table->ThermalInterval = 1; 3148 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3149 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3150 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3151 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3152 table->MemoryVoltageChangeEnable = 1; 3153 table->MemoryInterval = 1; 3154 table->VoltageResponseTime = 0; 3155 table->VddcVddciDelta = 4000; 3156 table->PhaseResponseTime = 0; 3157 table->MemoryThermThrottleEnable = 1; 3158 table->PCIeBootLinkLevel = 0; 3159 table->PCIeGenInterval = 1; 3160 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3161 table->SVI2Enable = 1; 3162 else 3163 table->SVI2Enable = 0; 3164 3165 table->ThermGpio = 17; 3166 table->SclkStepSize = 0x4000; 3167 3168 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3169 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3170 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3171 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3172 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3173 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3174 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3175 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3176 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3177 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3178 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3179 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3180 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3181 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3182 3183 ret = ci_copy_bytes_to_smc(rdev, 3184 pi->dpm_table_start + 3185 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3186 (u8 *)&table->SystemFlags, 3187 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3188 pi->sram_end); 3189 if (ret) 3190 return ret; 3191 3192 return 0; 3193 } 3194 3195 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3196 struct ci_single_dpm_table *dpm_table, 3197 u32 low_limit, u32 high_limit) 3198 { 3199 u32 i; 3200 3201 for (i = 0; i < dpm_table->count; i++) { 3202 if ((dpm_table->dpm_levels[i].value < low_limit) || 3203 (dpm_table->dpm_levels[i].value > high_limit)) 3204 dpm_table->dpm_levels[i].enabled = false; 3205 else 3206 dpm_table->dpm_levels[i].enabled = true; 3207 } 3208 } 3209 3210 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3211 u32 speed_low, u32 lanes_low, 3212 u32 speed_high, u32 lanes_high) 3213 { 3214 struct ci_power_info *pi = ci_get_pi(rdev); 3215 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3216 u32 i, j; 3217 3218 for (i = 0; i < pcie_table->count; i++) { 3219 if ((pcie_table->dpm_levels[i].value < speed_low) || 3220 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3221 (pcie_table->dpm_levels[i].value > speed_high) || 3222 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3223 pcie_table->dpm_levels[i].enabled = false; 3224 else 3225 pcie_table->dpm_levels[i].enabled = true; 3226 } 3227 3228 for (i = 0; i < pcie_table->count; i++) { 3229 if (pcie_table->dpm_levels[i].enabled) { 3230 for (j = i + 1; j < pcie_table->count; j++) { 3231 if (pcie_table->dpm_levels[j].enabled) { 3232 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3233 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3234 pcie_table->dpm_levels[j].enabled = false; 3235 } 3236 } 3237 } 3238 } 3239 } 3240 3241 static int ci_trim_dpm_states(struct radeon_device *rdev, 3242 struct radeon_ps *radeon_state) 3243 { 3244 struct ci_ps *state = ci_get_ps(radeon_state); 3245 struct ci_power_info *pi = ci_get_pi(rdev); 3246 u32 high_limit_count; 3247 3248 if (state->performance_level_count < 1) 3249 return -EINVAL; 3250 3251 if (state->performance_level_count == 1) 3252 high_limit_count = 0; 3253 else 3254 high_limit_count = 1; 3255 3256 ci_trim_single_dpm_states(rdev, 3257 &pi->dpm_table.sclk_table, 3258 state->performance_levels[0].sclk, 3259 state->performance_levels[high_limit_count].sclk); 3260 3261 ci_trim_single_dpm_states(rdev, 3262 &pi->dpm_table.mclk_table, 3263 state->performance_levels[0].mclk, 3264 state->performance_levels[high_limit_count].mclk); 3265 3266 ci_trim_pcie_dpm_states(rdev, 3267 state->performance_levels[0].pcie_gen, 3268 state->performance_levels[0].pcie_lane, 3269 state->performance_levels[high_limit_count].pcie_gen, 3270 state->performance_levels[high_limit_count].pcie_lane); 3271 3272 return 0; 3273 } 3274 3275 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3276 { 3277 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3278 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3279 struct radeon_clock_voltage_dependency_table *vddc_table = 3280 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3281 u32 requested_voltage = 0; 3282 u32 i; 3283 3284 if (disp_voltage_table == NULL) 3285 return -EINVAL; 3286 if (!disp_voltage_table->count) 3287 return -EINVAL; 3288 3289 for (i = 0; i < disp_voltage_table->count; i++) { 3290 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3291 requested_voltage = disp_voltage_table->entries[i].v; 3292 } 3293 3294 for (i = 0; i < vddc_table->count; i++) { 3295 if (requested_voltage <= vddc_table->entries[i].v) { 3296 requested_voltage = vddc_table->entries[i].v; 3297 return (ci_send_msg_to_smc_with_parameter(rdev, 3298 PPSMC_MSG_VddC_Request, 3299 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3300 0 : -EINVAL; 3301 } 3302 } 3303 3304 return -EINVAL; 3305 } 3306 3307 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3308 { 3309 struct ci_power_info *pi = ci_get_pi(rdev); 3310 PPSMC_Result result; 3311 3312 if (!pi->sclk_dpm_key_disabled) { 3313 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3314 result = ci_send_msg_to_smc_with_parameter(rdev, 3315 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3316 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3317 if (result != PPSMC_Result_OK) 3318 return -EINVAL; 3319 } 3320 } 3321 3322 if (!pi->mclk_dpm_key_disabled) { 3323 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3324 result = ci_send_msg_to_smc_with_parameter(rdev, 3325 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3326 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3327 if (result != PPSMC_Result_OK) 3328 return -EINVAL; 3329 } 3330 } 3331 3332 if (!pi->pcie_dpm_key_disabled) { 3333 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3334 result = ci_send_msg_to_smc_with_parameter(rdev, 3335 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3336 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3337 if (result != PPSMC_Result_OK) 3338 return -EINVAL; 3339 } 3340 } 3341 3342 ci_apply_disp_minimum_voltage_request(rdev); 3343 3344 return 0; 3345 } 3346 3347 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3348 struct radeon_ps *radeon_state) 3349 { 3350 struct ci_power_info *pi = ci_get_pi(rdev); 3351 struct ci_ps *state = ci_get_ps(radeon_state); 3352 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3353 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3354 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3355 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3356 u32 i; 3357 3358 pi->need_update_smu7_dpm_table = 0; 3359 3360 for (i = 0; i < sclk_table->count; i++) { 3361 if (sclk == sclk_table->dpm_levels[i].value) 3362 break; 3363 } 3364 3365 if (i >= sclk_table->count) { 3366 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3367 } else { 3368 /* XXX check display min clock requirements */ 3369 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK) 3370 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3371 } 3372 3373 for (i = 0; i < mclk_table->count; i++) { 3374 if (mclk == mclk_table->dpm_levels[i].value) 3375 break; 3376 } 3377 3378 if (i >= mclk_table->count) 3379 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3380 3381 if (rdev->pm.dpm.current_active_crtc_count != 3382 rdev->pm.dpm.new_active_crtc_count) 3383 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3384 } 3385 3386 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3387 struct radeon_ps *radeon_state) 3388 { 3389 struct ci_power_info *pi = ci_get_pi(rdev); 3390 struct ci_ps *state = ci_get_ps(radeon_state); 3391 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3392 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3393 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3394 int ret; 3395 3396 if (!pi->need_update_smu7_dpm_table) 3397 return 0; 3398 3399 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3400 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3401 3402 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3403 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3404 3405 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3406 ret = ci_populate_all_graphic_levels(rdev); 3407 if (ret) 3408 return ret; 3409 } 3410 3411 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3412 ret = ci_populate_all_memory_levels(rdev); 3413 if (ret) 3414 return ret; 3415 } 3416 3417 return 0; 3418 } 3419 3420 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3421 { 3422 struct ci_power_info *pi = ci_get_pi(rdev); 3423 const struct radeon_clock_and_voltage_limits *max_limits; 3424 int i; 3425 3426 if (rdev->pm.dpm.ac_power) 3427 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3428 else 3429 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3430 3431 if (enable) { 3432 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3433 3434 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3435 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3436 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3437 3438 if (!pi->caps_uvd_dpm) 3439 break; 3440 } 3441 } 3442 3443 ci_send_msg_to_smc_with_parameter(rdev, 3444 PPSMC_MSG_UVDDPM_SetEnabledMask, 3445 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3446 3447 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3448 pi->uvd_enabled = true; 3449 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3450 ci_send_msg_to_smc_with_parameter(rdev, 3451 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3452 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3453 } 3454 } else { 3455 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3456 pi->uvd_enabled = false; 3457 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3458 ci_send_msg_to_smc_with_parameter(rdev, 3459 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3460 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3461 } 3462 } 3463 3464 return (ci_send_msg_to_smc(rdev, enable ? 3465 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3466 0 : -EINVAL; 3467 } 3468 3469 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3470 { 3471 struct ci_power_info *pi = ci_get_pi(rdev); 3472 const struct radeon_clock_and_voltage_limits *max_limits; 3473 int i; 3474 3475 if (rdev->pm.dpm.ac_power) 3476 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3477 else 3478 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3479 3480 if (enable) { 3481 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3482 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3483 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3484 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3485 3486 if (!pi->caps_vce_dpm) 3487 break; 3488 } 3489 } 3490 3491 ci_send_msg_to_smc_with_parameter(rdev, 3492 PPSMC_MSG_VCEDPM_SetEnabledMask, 3493 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3494 } 3495 3496 return (ci_send_msg_to_smc(rdev, enable ? 3497 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 3498 0 : -EINVAL; 3499 } 3500 3501 #if 0 3502 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 3503 { 3504 struct ci_power_info *pi = ci_get_pi(rdev); 3505 const struct radeon_clock_and_voltage_limits *max_limits; 3506 int i; 3507 3508 if (rdev->pm.dpm.ac_power) 3509 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3510 else 3511 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3512 3513 if (enable) { 3514 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 3515 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3516 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3517 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 3518 3519 if (!pi->caps_samu_dpm) 3520 break; 3521 } 3522 } 3523 3524 ci_send_msg_to_smc_with_parameter(rdev, 3525 PPSMC_MSG_SAMUDPM_SetEnabledMask, 3526 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 3527 } 3528 return (ci_send_msg_to_smc(rdev, enable ? 3529 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 3530 0 : -EINVAL; 3531 } 3532 3533 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 3534 { 3535 struct ci_power_info *pi = ci_get_pi(rdev); 3536 const struct radeon_clock_and_voltage_limits *max_limits; 3537 int i; 3538 3539 if (rdev->pm.dpm.ac_power) 3540 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3541 else 3542 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3543 3544 if (enable) { 3545 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 3546 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3547 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3548 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 3549 3550 if (!pi->caps_acp_dpm) 3551 break; 3552 } 3553 } 3554 3555 ci_send_msg_to_smc_with_parameter(rdev, 3556 PPSMC_MSG_ACPDPM_SetEnabledMask, 3557 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 3558 } 3559 3560 return (ci_send_msg_to_smc(rdev, enable ? 3561 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 3562 0 : -EINVAL; 3563 } 3564 #endif 3565 3566 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 3567 { 3568 struct ci_power_info *pi = ci_get_pi(rdev); 3569 u32 tmp; 3570 3571 if (!gate) { 3572 if (pi->caps_uvd_dpm || 3573 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 3574 pi->smc_state_table.UvdBootLevel = 0; 3575 else 3576 pi->smc_state_table.UvdBootLevel = 3577 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 3578 3579 tmp = RREG32_SMC(DPM_TABLE_475); 3580 tmp &= ~UvdBootLevel_MASK; 3581 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 3582 WREG32_SMC(DPM_TABLE_475, tmp); 3583 } 3584 3585 return ci_enable_uvd_dpm(rdev, !gate); 3586 } 3587 3588 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 3589 { 3590 u8 i; 3591 u32 min_evclk = 30000; /* ??? */ 3592 struct radeon_vce_clock_voltage_dependency_table *table = 3593 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3594 3595 for (i = 0; i < table->count; i++) { 3596 if (table->entries[i].evclk >= min_evclk) 3597 return i; 3598 } 3599 3600 return table->count - 1; 3601 } 3602 3603 static int ci_update_vce_dpm(struct radeon_device *rdev, 3604 struct radeon_ps *radeon_new_state, 3605 struct radeon_ps *radeon_current_state) 3606 { 3607 struct ci_power_info *pi = ci_get_pi(rdev); 3608 int ret = 0; 3609 u32 tmp; 3610 3611 if (radeon_current_state->evclk != radeon_new_state->evclk) { 3612 if (radeon_new_state->evclk) { 3613 /* turn the clocks on when encoding */ 3614 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 3615 3616 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 3617 tmp = RREG32_SMC(DPM_TABLE_475); 3618 tmp &= ~VceBootLevel_MASK; 3619 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 3620 WREG32_SMC(DPM_TABLE_475, tmp); 3621 3622 ret = ci_enable_vce_dpm(rdev, true); 3623 } else { 3624 /* turn the clocks off when not encoding */ 3625 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 3626 3627 ret = ci_enable_vce_dpm(rdev, false); 3628 } 3629 } 3630 return ret; 3631 } 3632 3633 #if 0 3634 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 3635 { 3636 return ci_enable_samu_dpm(rdev, gate); 3637 } 3638 3639 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 3640 { 3641 struct ci_power_info *pi = ci_get_pi(rdev); 3642 u32 tmp; 3643 3644 if (!gate) { 3645 pi->smc_state_table.AcpBootLevel = 0; 3646 3647 tmp = RREG32_SMC(DPM_TABLE_475); 3648 tmp &= ~AcpBootLevel_MASK; 3649 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 3650 WREG32_SMC(DPM_TABLE_475, tmp); 3651 } 3652 3653 return ci_enable_acp_dpm(rdev, !gate); 3654 } 3655 #endif 3656 3657 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 3658 struct radeon_ps *radeon_state) 3659 { 3660 struct ci_power_info *pi = ci_get_pi(rdev); 3661 int ret; 3662 3663 ret = ci_trim_dpm_states(rdev, radeon_state); 3664 if (ret) 3665 return ret; 3666 3667 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3668 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 3669 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3670 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 3671 pi->last_mclk_dpm_enable_mask = 3672 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3673 if (pi->uvd_enabled) { 3674 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 3675 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3676 } 3677 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 3678 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 3679 3680 return 0; 3681 } 3682 3683 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 3684 u32 level_mask) 3685 { 3686 u32 level = 0; 3687 3688 while ((level_mask & (1 << level)) == 0) 3689 level++; 3690 3691 return level; 3692 } 3693 3694 3695 int ci_dpm_force_performance_level(struct radeon_device *rdev, 3696 enum radeon_dpm_forced_level level) 3697 { 3698 struct ci_power_info *pi = ci_get_pi(rdev); 3699 PPSMC_Result smc_result; 3700 u32 tmp, levels, i; 3701 int ret; 3702 3703 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3704 if ((!pi->sclk_dpm_key_disabled) && 3705 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3706 levels = 0; 3707 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 3708 while (tmp >>= 1) 3709 levels++; 3710 if (levels) { 3711 ret = ci_dpm_force_state_sclk(rdev, levels); 3712 if (ret) 3713 return ret; 3714 for (i = 0; i < rdev->usec_timeout; i++) { 3715 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3716 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3717 if (tmp == levels) 3718 break; 3719 udelay(1); 3720 } 3721 } 3722 } 3723 if ((!pi->mclk_dpm_key_disabled) && 3724 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3725 levels = 0; 3726 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3727 while (tmp >>= 1) 3728 levels++; 3729 if (levels) { 3730 ret = ci_dpm_force_state_mclk(rdev, levels); 3731 if (ret) 3732 return ret; 3733 for (i = 0; i < rdev->usec_timeout; i++) { 3734 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3735 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3736 if (tmp == levels) 3737 break; 3738 udelay(1); 3739 } 3740 } 3741 } 3742 if ((!pi->pcie_dpm_key_disabled) && 3743 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3744 levels = 0; 3745 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 3746 while (tmp >>= 1) 3747 levels++; 3748 if (levels) { 3749 ret = ci_dpm_force_state_pcie(rdev, level); 3750 if (ret) 3751 return ret; 3752 for (i = 0; i < rdev->usec_timeout; i++) { 3753 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3754 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3755 if (tmp == levels) 3756 break; 3757 udelay(1); 3758 } 3759 } 3760 } 3761 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3762 if ((!pi->sclk_dpm_key_disabled) && 3763 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3764 levels = ci_get_lowest_enabled_level(rdev, 3765 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3766 ret = ci_dpm_force_state_sclk(rdev, levels); 3767 if (ret) 3768 return ret; 3769 for (i = 0; i < rdev->usec_timeout; i++) { 3770 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3771 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3772 if (tmp == levels) 3773 break; 3774 udelay(1); 3775 } 3776 } 3777 if ((!pi->mclk_dpm_key_disabled) && 3778 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3779 levels = ci_get_lowest_enabled_level(rdev, 3780 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3781 ret = ci_dpm_force_state_mclk(rdev, levels); 3782 if (ret) 3783 return ret; 3784 for (i = 0; i < rdev->usec_timeout; i++) { 3785 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3786 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3787 if (tmp == levels) 3788 break; 3789 udelay(1); 3790 } 3791 } 3792 if ((!pi->pcie_dpm_key_disabled) && 3793 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3794 levels = ci_get_lowest_enabled_level(rdev, 3795 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3796 ret = ci_dpm_force_state_pcie(rdev, levels); 3797 if (ret) 3798 return ret; 3799 for (i = 0; i < rdev->usec_timeout; i++) { 3800 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3801 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3802 if (tmp == levels) 3803 break; 3804 udelay(1); 3805 } 3806 } 3807 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3808 if (!pi->sclk_dpm_key_disabled) { 3809 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel); 3810 if (smc_result != PPSMC_Result_OK) 3811 return -EINVAL; 3812 } 3813 if (!pi->mclk_dpm_key_disabled) { 3814 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel); 3815 if (smc_result != PPSMC_Result_OK) 3816 return -EINVAL; 3817 } 3818 if (!pi->pcie_dpm_key_disabled) { 3819 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel); 3820 if (smc_result != PPSMC_Result_OK) 3821 return -EINVAL; 3822 } 3823 } 3824 3825 rdev->pm.dpm.forced_level = level; 3826 3827 return 0; 3828 } 3829 3830 static int ci_set_mc_special_registers(struct radeon_device *rdev, 3831 struct ci_mc_reg_table *table) 3832 { 3833 struct ci_power_info *pi = ci_get_pi(rdev); 3834 u8 i, j, k; 3835 u32 temp_reg; 3836 3837 for (i = 0, j = table->last; i < table->last; i++) { 3838 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3839 return -EINVAL; 3840 switch(table->mc_reg_address[i].s1 << 2) { 3841 case MC_SEQ_MISC1: 3842 temp_reg = RREG32(MC_PMG_CMD_EMRS); 3843 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 3844 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3845 for (k = 0; k < table->num_entries; k++) { 3846 table->mc_reg_table_entry[k].mc_data[j] = 3847 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 3848 } 3849 j++; 3850 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3851 return -EINVAL; 3852 3853 temp_reg = RREG32(MC_PMG_CMD_MRS); 3854 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 3855 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3856 for (k = 0; k < table->num_entries; k++) { 3857 table->mc_reg_table_entry[k].mc_data[j] = 3858 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3859 if (!pi->mem_gddr5) 3860 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 3861 } 3862 j++; 3863 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3864 return -EINVAL; 3865 3866 if (!pi->mem_gddr5) { 3867 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 3868 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 3869 for (k = 0; k < table->num_entries; k++) { 3870 table->mc_reg_table_entry[k].mc_data[j] = 3871 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 3872 } 3873 j++; 3874 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3875 return -EINVAL; 3876 } 3877 break; 3878 case MC_SEQ_RESERVE_M: 3879 temp_reg = RREG32(MC_PMG_CMD_MRS1); 3880 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 3881 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3882 for (k = 0; k < table->num_entries; k++) { 3883 table->mc_reg_table_entry[k].mc_data[j] = 3884 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3885 } 3886 j++; 3887 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3888 return -EINVAL; 3889 break; 3890 default: 3891 break; 3892 } 3893 3894 } 3895 3896 table->last = j; 3897 3898 return 0; 3899 } 3900 3901 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 3902 { 3903 bool result = true; 3904 3905 switch(in_reg) { 3906 case MC_SEQ_RAS_TIMING >> 2: 3907 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 3908 break; 3909 case MC_SEQ_DLL_STBY >> 2: 3910 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 3911 break; 3912 case MC_SEQ_G5PDX_CMD0 >> 2: 3913 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 3914 break; 3915 case MC_SEQ_G5PDX_CMD1 >> 2: 3916 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 3917 break; 3918 case MC_SEQ_G5PDX_CTRL >> 2: 3919 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 3920 break; 3921 case MC_SEQ_CAS_TIMING >> 2: 3922 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 3923 break; 3924 case MC_SEQ_MISC_TIMING >> 2: 3925 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 3926 break; 3927 case MC_SEQ_MISC_TIMING2 >> 2: 3928 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 3929 break; 3930 case MC_SEQ_PMG_DVS_CMD >> 2: 3931 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 3932 break; 3933 case MC_SEQ_PMG_DVS_CTL >> 2: 3934 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 3935 break; 3936 case MC_SEQ_RD_CTL_D0 >> 2: 3937 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 3938 break; 3939 case MC_SEQ_RD_CTL_D1 >> 2: 3940 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 3941 break; 3942 case MC_SEQ_WR_CTL_D0 >> 2: 3943 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 3944 break; 3945 case MC_SEQ_WR_CTL_D1 >> 2: 3946 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 3947 break; 3948 case MC_PMG_CMD_EMRS >> 2: 3949 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3950 break; 3951 case MC_PMG_CMD_MRS >> 2: 3952 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3953 break; 3954 case MC_PMG_CMD_MRS1 >> 2: 3955 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3956 break; 3957 case MC_SEQ_PMG_TIMING >> 2: 3958 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 3959 break; 3960 case MC_PMG_CMD_MRS2 >> 2: 3961 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 3962 break; 3963 case MC_SEQ_WR_CTL_2 >> 2: 3964 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 3965 break; 3966 default: 3967 result = false; 3968 break; 3969 } 3970 3971 return result; 3972 } 3973 3974 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 3975 { 3976 u8 i, j; 3977 3978 for (i = 0; i < table->last; i++) { 3979 for (j = 1; j < table->num_entries; j++) { 3980 if (table->mc_reg_table_entry[j-1].mc_data[i] != 3981 table->mc_reg_table_entry[j].mc_data[i]) { 3982 table->valid_flag |= 1 << i; 3983 break; 3984 } 3985 } 3986 } 3987 } 3988 3989 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 3990 { 3991 u32 i; 3992 u16 address; 3993 3994 for (i = 0; i < table->last; i++) { 3995 table->mc_reg_address[i].s0 = 3996 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 3997 address : table->mc_reg_address[i].s1; 3998 } 3999 } 4000 4001 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 4002 struct ci_mc_reg_table *ci_table) 4003 { 4004 u8 i, j; 4005 4006 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4007 return -EINVAL; 4008 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 4009 return -EINVAL; 4010 4011 for (i = 0; i < table->last; i++) 4012 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 4013 4014 ci_table->last = table->last; 4015 4016 for (i = 0; i < table->num_entries; i++) { 4017 ci_table->mc_reg_table_entry[i].mclk_max = 4018 table->mc_reg_table_entry[i].mclk_max; 4019 for (j = 0; j < table->last; j++) 4020 ci_table->mc_reg_table_entry[i].mc_data[j] = 4021 table->mc_reg_table_entry[i].mc_data[j]; 4022 } 4023 ci_table->num_entries = table->num_entries; 4024 4025 return 0; 4026 } 4027 4028 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 4029 { 4030 struct ci_power_info *pi = ci_get_pi(rdev); 4031 struct atom_mc_reg_table *table; 4032 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 4033 u8 module_index = rv770_get_memory_module_index(rdev); 4034 int ret; 4035 4036 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 4037 if (!table) 4038 return -ENOMEM; 4039 4040 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 4041 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 4042 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4043 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4044 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4045 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4046 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4047 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4048 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4049 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4050 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4051 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4052 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4053 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4054 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4055 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4056 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4057 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4058 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4059 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4060 4061 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4062 if (ret) 4063 goto init_mc_done; 4064 4065 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4066 if (ret) 4067 goto init_mc_done; 4068 4069 ci_set_s0_mc_reg_index(ci_table); 4070 4071 ret = ci_set_mc_special_registers(rdev, ci_table); 4072 if (ret) 4073 goto init_mc_done; 4074 4075 ci_set_valid_flag(ci_table); 4076 4077 init_mc_done: 4078 kfree(table); 4079 4080 return ret; 4081 } 4082 4083 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4084 SMU7_Discrete_MCRegisters *mc_reg_table) 4085 { 4086 struct ci_power_info *pi = ci_get_pi(rdev); 4087 u32 i, j; 4088 4089 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4090 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4091 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4092 return -EINVAL; 4093 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4094 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4095 i++; 4096 } 4097 } 4098 4099 mc_reg_table->last = (u8)i; 4100 4101 return 0; 4102 } 4103 4104 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4105 SMU7_Discrete_MCRegisterSet *data, 4106 u32 num_entries, u32 valid_flag) 4107 { 4108 u32 i, j; 4109 4110 for (i = 0, j = 0; j < num_entries; j++) { 4111 if (valid_flag & (1 << j)) { 4112 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4113 i++; 4114 } 4115 } 4116 } 4117 4118 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4119 const u32 memory_clock, 4120 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4121 { 4122 struct ci_power_info *pi = ci_get_pi(rdev); 4123 u32 i = 0; 4124 4125 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { 4126 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4127 break; 4128 } 4129 4130 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4131 --i; 4132 4133 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4134 mc_reg_table_data, pi->mc_reg_table.last, 4135 pi->mc_reg_table.valid_flag); 4136 } 4137 4138 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4139 SMU7_Discrete_MCRegisters *mc_reg_table) 4140 { 4141 struct ci_power_info *pi = ci_get_pi(rdev); 4142 u32 i; 4143 4144 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4145 ci_convert_mc_reg_table_entry_to_smc(rdev, 4146 pi->dpm_table.mclk_table.dpm_levels[i].value, 4147 &mc_reg_table->data[i]); 4148 } 4149 4150 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4151 { 4152 struct ci_power_info *pi = ci_get_pi(rdev); 4153 int ret; 4154 4155 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4156 4157 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4158 if (ret) 4159 return ret; 4160 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4161 4162 return ci_copy_bytes_to_smc(rdev, 4163 pi->mc_reg_table_start, 4164 (u8 *)&pi->smc_mc_reg_table, 4165 sizeof(SMU7_Discrete_MCRegisters), 4166 pi->sram_end); 4167 } 4168 4169 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4170 { 4171 struct ci_power_info *pi = ci_get_pi(rdev); 4172 4173 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4174 return 0; 4175 4176 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4177 4178 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4179 4180 return ci_copy_bytes_to_smc(rdev, 4181 pi->mc_reg_table_start + 4182 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4183 (u8 *)&pi->smc_mc_reg_table.data[0], 4184 sizeof(SMU7_Discrete_MCRegisterSet) * 4185 pi->dpm_table.mclk_table.count, 4186 pi->sram_end); 4187 } 4188 4189 static void ci_enable_voltage_control(struct radeon_device *rdev) 4190 { 4191 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4192 4193 tmp |= VOLT_PWRMGT_EN; 4194 WREG32_SMC(GENERAL_PWRMGT, tmp); 4195 } 4196 4197 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4198 struct radeon_ps *radeon_state) 4199 { 4200 struct ci_ps *state = ci_get_ps(radeon_state); 4201 int i; 4202 u16 pcie_speed, max_speed = 0; 4203 4204 for (i = 0; i < state->performance_level_count; i++) { 4205 pcie_speed = state->performance_levels[i].pcie_gen; 4206 if (max_speed < pcie_speed) 4207 max_speed = pcie_speed; 4208 } 4209 4210 return max_speed; 4211 } 4212 4213 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4214 { 4215 u32 speed_cntl = 0; 4216 4217 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4218 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4219 4220 return (u16)speed_cntl; 4221 } 4222 4223 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4224 { 4225 u32 link_width = 0; 4226 4227 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4228 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4229 4230 switch (link_width) { 4231 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4232 return 1; 4233 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4234 return 2; 4235 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4236 return 4; 4237 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4238 return 8; 4239 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4240 /* not actually supported */ 4241 return 12; 4242 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4243 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4244 default: 4245 return 16; 4246 } 4247 } 4248 4249 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4250 struct radeon_ps *radeon_new_state, 4251 struct radeon_ps *radeon_current_state) 4252 { 4253 struct ci_power_info *pi = ci_get_pi(rdev); 4254 enum radeon_pcie_gen target_link_speed = 4255 ci_get_maximum_link_speed(rdev, radeon_new_state); 4256 enum radeon_pcie_gen current_link_speed; 4257 4258 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4259 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4260 else 4261 current_link_speed = pi->force_pcie_gen; 4262 4263 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4264 pi->pspp_notify_required = false; 4265 if (target_link_speed > current_link_speed) { 4266 switch (target_link_speed) { 4267 #ifdef CONFIG_ACPI 4268 case RADEON_PCIE_GEN3: 4269 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4270 break; 4271 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4272 if (current_link_speed == RADEON_PCIE_GEN2) 4273 break; 4274 case RADEON_PCIE_GEN2: 4275 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4276 break; 4277 #endif 4278 default: 4279 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4280 break; 4281 } 4282 } else { 4283 if (target_link_speed < current_link_speed) 4284 pi->pspp_notify_required = true; 4285 } 4286 } 4287 4288 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4289 struct radeon_ps *radeon_new_state, 4290 struct radeon_ps *radeon_current_state) 4291 { 4292 struct ci_power_info *pi = ci_get_pi(rdev); 4293 enum radeon_pcie_gen target_link_speed = 4294 ci_get_maximum_link_speed(rdev, radeon_new_state); 4295 u8 request; 4296 4297 if (pi->pspp_notify_required) { 4298 if (target_link_speed == RADEON_PCIE_GEN3) 4299 request = PCIE_PERF_REQ_PECI_GEN3; 4300 else if (target_link_speed == RADEON_PCIE_GEN2) 4301 request = PCIE_PERF_REQ_PECI_GEN2; 4302 else 4303 request = PCIE_PERF_REQ_PECI_GEN1; 4304 4305 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4306 (ci_get_current_pcie_speed(rdev) > 0)) 4307 return; 4308 4309 #ifdef CONFIG_ACPI 4310 radeon_acpi_pcie_performance_request(rdev, request, false); 4311 #endif 4312 } 4313 } 4314 4315 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4316 { 4317 struct ci_power_info *pi = ci_get_pi(rdev); 4318 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4319 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4320 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4321 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4322 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4323 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4324 4325 if (allowed_sclk_vddc_table == NULL) 4326 return -EINVAL; 4327 if (allowed_sclk_vddc_table->count < 1) 4328 return -EINVAL; 4329 if (allowed_mclk_vddc_table == NULL) 4330 return -EINVAL; 4331 if (allowed_mclk_vddc_table->count < 1) 4332 return -EINVAL; 4333 if (allowed_mclk_vddci_table == NULL) 4334 return -EINVAL; 4335 if (allowed_mclk_vddci_table->count < 1) 4336 return -EINVAL; 4337 4338 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4339 pi->max_vddc_in_pp_table = 4340 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4341 4342 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4343 pi->max_vddci_in_pp_table = 4344 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4345 4346 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4347 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4348 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4349 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4350 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4351 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4352 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4353 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4354 4355 return 0; 4356 } 4357 4358 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4359 { 4360 struct ci_power_info *pi = ci_get_pi(rdev); 4361 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4362 u32 leakage_index; 4363 4364 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4365 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4366 *vddc = leakage_table->actual_voltage[leakage_index]; 4367 break; 4368 } 4369 } 4370 } 4371 4372 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4373 { 4374 struct ci_power_info *pi = ci_get_pi(rdev); 4375 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4376 u32 leakage_index; 4377 4378 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4379 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4380 *vddci = leakage_table->actual_voltage[leakage_index]; 4381 break; 4382 } 4383 } 4384 } 4385 4386 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4387 struct radeon_clock_voltage_dependency_table *table) 4388 { 4389 u32 i; 4390 4391 if (table) { 4392 for (i = 0; i < table->count; i++) 4393 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4394 } 4395 } 4396 4397 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4398 struct radeon_clock_voltage_dependency_table *table) 4399 { 4400 u32 i; 4401 4402 if (table) { 4403 for (i = 0; i < table->count; i++) 4404 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4405 } 4406 } 4407 4408 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4409 struct radeon_vce_clock_voltage_dependency_table *table) 4410 { 4411 u32 i; 4412 4413 if (table) { 4414 for (i = 0; i < table->count; i++) 4415 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4416 } 4417 } 4418 4419 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4420 struct radeon_uvd_clock_voltage_dependency_table *table) 4421 { 4422 u32 i; 4423 4424 if (table) { 4425 for (i = 0; i < table->count; i++) 4426 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4427 } 4428 } 4429 4430 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 4431 struct radeon_phase_shedding_limits_table *table) 4432 { 4433 u32 i; 4434 4435 if (table) { 4436 for (i = 0; i < table->count; i++) 4437 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 4438 } 4439 } 4440 4441 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 4442 struct radeon_clock_and_voltage_limits *table) 4443 { 4444 if (table) { 4445 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 4446 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 4447 } 4448 } 4449 4450 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 4451 struct radeon_cac_leakage_table *table) 4452 { 4453 u32 i; 4454 4455 if (table) { 4456 for (i = 0; i < table->count; i++) 4457 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 4458 } 4459 } 4460 4461 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 4462 { 4463 4464 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4465 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 4466 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4467 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 4468 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4469 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 4470 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 4471 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 4472 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4473 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 4474 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4475 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 4476 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4477 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 4478 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4479 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 4480 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 4481 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 4482 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4483 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 4484 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4485 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 4486 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 4487 &rdev->pm.dpm.dyn_state.cac_leakage_table); 4488 4489 } 4490 4491 static void ci_get_memory_type(struct radeon_device *rdev) 4492 { 4493 struct ci_power_info *pi = ci_get_pi(rdev); 4494 u32 tmp; 4495 4496 tmp = RREG32(MC_SEQ_MISC0); 4497 4498 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 4499 MC_SEQ_MISC0_GDDR5_VALUE) 4500 pi->mem_gddr5 = true; 4501 else 4502 pi->mem_gddr5 = false; 4503 4504 } 4505 4506 static void ci_update_current_ps(struct radeon_device *rdev, 4507 struct radeon_ps *rps) 4508 { 4509 struct ci_ps *new_ps = ci_get_ps(rps); 4510 struct ci_power_info *pi = ci_get_pi(rdev); 4511 4512 pi->current_rps = *rps; 4513 pi->current_ps = *new_ps; 4514 pi->current_rps.ps_priv = &pi->current_ps; 4515 } 4516 4517 static void ci_update_requested_ps(struct radeon_device *rdev, 4518 struct radeon_ps *rps) 4519 { 4520 struct ci_ps *new_ps = ci_get_ps(rps); 4521 struct ci_power_info *pi = ci_get_pi(rdev); 4522 4523 pi->requested_rps = *rps; 4524 pi->requested_ps = *new_ps; 4525 pi->requested_rps.ps_priv = &pi->requested_ps; 4526 } 4527 4528 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 4529 { 4530 struct ci_power_info *pi = ci_get_pi(rdev); 4531 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 4532 struct radeon_ps *new_ps = &requested_ps; 4533 4534 ci_update_requested_ps(rdev, new_ps); 4535 4536 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 4537 4538 return 0; 4539 } 4540 4541 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 4542 { 4543 struct ci_power_info *pi = ci_get_pi(rdev); 4544 struct radeon_ps *new_ps = &pi->requested_rps; 4545 4546 ci_update_current_ps(rdev, new_ps); 4547 } 4548 4549 4550 void ci_dpm_setup_asic(struct radeon_device *rdev) 4551 { 4552 int r; 4553 4554 r = ci_mc_load_microcode(rdev); 4555 if (r) 4556 DRM_ERROR("Failed to load MC firmware!\n"); 4557 ci_read_clock_registers(rdev); 4558 ci_get_memory_type(rdev); 4559 ci_enable_acpi_power_management(rdev); 4560 ci_init_sclk_t(rdev); 4561 } 4562 4563 int ci_dpm_enable(struct radeon_device *rdev) 4564 { 4565 struct ci_power_info *pi = ci_get_pi(rdev); 4566 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4567 int ret; 4568 4569 if (ci_is_smc_running(rdev)) 4570 return -EINVAL; 4571 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 4572 ci_enable_voltage_control(rdev); 4573 ret = ci_construct_voltage_tables(rdev); 4574 if (ret) { 4575 DRM_ERROR("ci_construct_voltage_tables failed\n"); 4576 return ret; 4577 } 4578 } 4579 if (pi->caps_dynamic_ac_timing) { 4580 ret = ci_initialize_mc_reg_table(rdev); 4581 if (ret) 4582 pi->caps_dynamic_ac_timing = false; 4583 } 4584 if (pi->dynamic_ss) 4585 ci_enable_spread_spectrum(rdev, true); 4586 if (pi->thermal_protection) 4587 ci_enable_thermal_protection(rdev, true); 4588 ci_program_sstp(rdev); 4589 ci_enable_display_gap(rdev); 4590 ci_program_vc(rdev); 4591 ret = ci_upload_firmware(rdev); 4592 if (ret) { 4593 DRM_ERROR("ci_upload_firmware failed\n"); 4594 return ret; 4595 } 4596 ret = ci_process_firmware_header(rdev); 4597 if (ret) { 4598 DRM_ERROR("ci_process_firmware_header failed\n"); 4599 return ret; 4600 } 4601 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 4602 if (ret) { 4603 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 4604 return ret; 4605 } 4606 ret = ci_init_smc_table(rdev); 4607 if (ret) { 4608 DRM_ERROR("ci_init_smc_table failed\n"); 4609 return ret; 4610 } 4611 ret = ci_init_arb_table_index(rdev); 4612 if (ret) { 4613 DRM_ERROR("ci_init_arb_table_index failed\n"); 4614 return ret; 4615 } 4616 if (pi->caps_dynamic_ac_timing) { 4617 ret = ci_populate_initial_mc_reg_table(rdev); 4618 if (ret) { 4619 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 4620 return ret; 4621 } 4622 } 4623 ret = ci_populate_pm_base(rdev); 4624 if (ret) { 4625 DRM_ERROR("ci_populate_pm_base failed\n"); 4626 return ret; 4627 } 4628 ci_dpm_start_smc(rdev); 4629 ci_enable_vr_hot_gpio_interrupt(rdev); 4630 ret = ci_notify_smc_display_change(rdev, false); 4631 if (ret) { 4632 DRM_ERROR("ci_notify_smc_display_change failed\n"); 4633 return ret; 4634 } 4635 ci_enable_sclk_control(rdev, true); 4636 ret = ci_enable_ulv(rdev, true); 4637 if (ret) { 4638 DRM_ERROR("ci_enable_ulv failed\n"); 4639 return ret; 4640 } 4641 ret = ci_enable_ds_master_switch(rdev, true); 4642 if (ret) { 4643 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 4644 return ret; 4645 } 4646 ret = ci_start_dpm(rdev); 4647 if (ret) { 4648 DRM_ERROR("ci_start_dpm failed\n"); 4649 return ret; 4650 } 4651 ret = ci_enable_didt(rdev, true); 4652 if (ret) { 4653 DRM_ERROR("ci_enable_didt failed\n"); 4654 return ret; 4655 } 4656 ret = ci_enable_smc_cac(rdev, true); 4657 if (ret) { 4658 DRM_ERROR("ci_enable_smc_cac failed\n"); 4659 return ret; 4660 } 4661 ret = ci_enable_power_containment(rdev, true); 4662 if (ret) { 4663 DRM_ERROR("ci_enable_power_containment failed\n"); 4664 return ret; 4665 } 4666 4667 ret = ci_power_control_set_level(rdev); 4668 if (ret) { 4669 DRM_ERROR("ci_power_control_set_level failed\n"); 4670 return ret; 4671 } 4672 4673 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 4674 4675 ci_update_current_ps(rdev, boot_ps); 4676 4677 return 0; 4678 } 4679 4680 int ci_dpm_late_enable(struct radeon_device *rdev) 4681 { 4682 int ret; 4683 4684 if (rdev->irq.installed && 4685 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 4686 #if 0 4687 PPSMC_Result result; 4688 #endif 4689 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 4690 if (ret) { 4691 DRM_ERROR("ci_set_thermal_temperature_range failed\n"); 4692 return ret; 4693 } 4694 rdev->irq.dpm_thermal = true; 4695 radeon_irq_set(rdev); 4696 #if 0 4697 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 4698 4699 if (result != PPSMC_Result_OK) 4700 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 4701 #endif 4702 } 4703 4704 ci_dpm_powergate_uvd(rdev, true); 4705 4706 return 0; 4707 } 4708 4709 void ci_dpm_disable(struct radeon_device *rdev) 4710 { 4711 struct ci_power_info *pi = ci_get_pi(rdev); 4712 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4713 4714 ci_dpm_powergate_uvd(rdev, false); 4715 4716 if (!ci_is_smc_running(rdev)) 4717 return; 4718 4719 if (pi->thermal_protection) 4720 ci_enable_thermal_protection(rdev, false); 4721 ci_enable_power_containment(rdev, false); 4722 ci_enable_smc_cac(rdev, false); 4723 ci_enable_didt(rdev, false); 4724 ci_enable_spread_spectrum(rdev, false); 4725 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 4726 ci_stop_dpm(rdev); 4727 ci_enable_ds_master_switch(rdev, true); 4728 ci_enable_ulv(rdev, false); 4729 ci_clear_vc(rdev); 4730 ci_reset_to_default(rdev); 4731 ci_dpm_stop_smc(rdev); 4732 ci_force_switch_to_arb_f0(rdev); 4733 4734 ci_update_current_ps(rdev, boot_ps); 4735 } 4736 4737 int ci_dpm_set_power_state(struct radeon_device *rdev) 4738 { 4739 struct ci_power_info *pi = ci_get_pi(rdev); 4740 struct radeon_ps *new_ps = &pi->requested_rps; 4741 struct radeon_ps *old_ps = &pi->current_rps; 4742 int ret; 4743 4744 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 4745 if (pi->pcie_performance_request) 4746 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 4747 ret = ci_freeze_sclk_mclk_dpm(rdev); 4748 if (ret) { 4749 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 4750 return ret; 4751 } 4752 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 4753 if (ret) { 4754 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 4755 return ret; 4756 } 4757 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 4758 if (ret) { 4759 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 4760 return ret; 4761 } 4762 4763 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 4764 if (ret) { 4765 DRM_ERROR("ci_update_vce_dpm failed\n"); 4766 return ret; 4767 } 4768 4769 ret = ci_update_sclk_t(rdev); 4770 if (ret) { 4771 DRM_ERROR("ci_update_sclk_t failed\n"); 4772 return ret; 4773 } 4774 if (pi->caps_dynamic_ac_timing) { 4775 ret = ci_update_and_upload_mc_reg_table(rdev); 4776 if (ret) { 4777 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 4778 return ret; 4779 } 4780 } 4781 ret = ci_program_memory_timing_parameters(rdev); 4782 if (ret) { 4783 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 4784 return ret; 4785 } 4786 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 4787 if (ret) { 4788 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 4789 return ret; 4790 } 4791 ret = ci_upload_dpm_level_enable_mask(rdev); 4792 if (ret) { 4793 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 4794 return ret; 4795 } 4796 if (pi->pcie_performance_request) 4797 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 4798 4799 return 0; 4800 } 4801 4802 #if 0 4803 void ci_dpm_reset_asic(struct radeon_device *rdev) 4804 { 4805 ci_set_boot_state(rdev); 4806 } 4807 #endif 4808 4809 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 4810 { 4811 ci_program_display_gap(rdev); 4812 } 4813 4814 union power_info { 4815 struct _ATOM_POWERPLAY_INFO info; 4816 struct _ATOM_POWERPLAY_INFO_V2 info_2; 4817 struct _ATOM_POWERPLAY_INFO_V3 info_3; 4818 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 4819 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 4820 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 4821 }; 4822 4823 union pplib_clock_info { 4824 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 4825 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 4826 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 4827 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 4828 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 4829 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 4830 }; 4831 4832 union pplib_power_state { 4833 struct _ATOM_PPLIB_STATE v1; 4834 struct _ATOM_PPLIB_STATE_V2 v2; 4835 }; 4836 4837 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 4838 struct radeon_ps *rps, 4839 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 4840 u8 table_rev) 4841 { 4842 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 4843 rps->class = le16_to_cpu(non_clock_info->usClassification); 4844 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 4845 4846 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 4847 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 4848 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 4849 } else { 4850 rps->vclk = 0; 4851 rps->dclk = 0; 4852 } 4853 4854 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 4855 rdev->pm.dpm.boot_ps = rps; 4856 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 4857 rdev->pm.dpm.uvd_ps = rps; 4858 } 4859 4860 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 4861 struct radeon_ps *rps, int index, 4862 union pplib_clock_info *clock_info) 4863 { 4864 struct ci_power_info *pi = ci_get_pi(rdev); 4865 struct ci_ps *ps = ci_get_ps(rps); 4866 struct ci_pl *pl = &ps->performance_levels[index]; 4867 4868 ps->performance_level_count = index + 1; 4869 4870 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 4871 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 4872 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 4873 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 4874 4875 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 4876 pi->sys_pcie_mask, 4877 pi->vbios_boot_state.pcie_gen_bootup_value, 4878 clock_info->ci.ucPCIEGen); 4879 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 4880 pi->vbios_boot_state.pcie_lane_bootup_value, 4881 le16_to_cpu(clock_info->ci.usPCIELane)); 4882 4883 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 4884 pi->acpi_pcie_gen = pl->pcie_gen; 4885 } 4886 4887 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 4888 pi->ulv.supported = true; 4889 pi->ulv.pl = *pl; 4890 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 4891 } 4892 4893 /* patch up boot state */ 4894 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 4895 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 4896 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 4897 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 4898 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 4899 } 4900 4901 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 4902 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 4903 pi->use_pcie_powersaving_levels = true; 4904 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 4905 pi->pcie_gen_powersaving.max = pl->pcie_gen; 4906 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 4907 pi->pcie_gen_powersaving.min = pl->pcie_gen; 4908 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 4909 pi->pcie_lane_powersaving.max = pl->pcie_lane; 4910 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 4911 pi->pcie_lane_powersaving.min = pl->pcie_lane; 4912 break; 4913 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 4914 pi->use_pcie_performance_levels = true; 4915 if (pi->pcie_gen_performance.max < pl->pcie_gen) 4916 pi->pcie_gen_performance.max = pl->pcie_gen; 4917 if (pi->pcie_gen_performance.min > pl->pcie_gen) 4918 pi->pcie_gen_performance.min = pl->pcie_gen; 4919 if (pi->pcie_lane_performance.max < pl->pcie_lane) 4920 pi->pcie_lane_performance.max = pl->pcie_lane; 4921 if (pi->pcie_lane_performance.min > pl->pcie_lane) 4922 pi->pcie_lane_performance.min = pl->pcie_lane; 4923 break; 4924 default: 4925 break; 4926 } 4927 } 4928 4929 static int ci_parse_power_table(struct radeon_device *rdev) 4930 { 4931 struct radeon_mode_info *mode_info = &rdev->mode_info; 4932 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 4933 union pplib_power_state *power_state; 4934 int i, j, k, non_clock_array_index, clock_array_index; 4935 union pplib_clock_info *clock_info; 4936 struct _StateArray *state_array; 4937 struct _ClockInfoArray *clock_info_array; 4938 struct _NonClockInfoArray *non_clock_info_array; 4939 union power_info *power_info; 4940 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 4941 u16 data_offset; 4942 u8 frev, crev; 4943 u8 *power_state_offset; 4944 struct ci_ps *ps; 4945 4946 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 4947 &frev, &crev, &data_offset)) 4948 return -EINVAL; 4949 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 4950 4951 state_array = (struct _StateArray *) 4952 (mode_info->atom_context->bios + data_offset + 4953 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 4954 clock_info_array = (struct _ClockInfoArray *) 4955 (mode_info->atom_context->bios + data_offset + 4956 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 4957 non_clock_info_array = (struct _NonClockInfoArray *) 4958 (mode_info->atom_context->bios + data_offset + 4959 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 4960 4961 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 4962 state_array->ucNumEntries, GFP_KERNEL); 4963 if (!rdev->pm.dpm.ps) 4964 return -ENOMEM; 4965 power_state_offset = (u8 *)state_array->states; 4966 for (i = 0; i < state_array->ucNumEntries; i++) { 4967 u8 *idx; 4968 power_state = (union pplib_power_state *)power_state_offset; 4969 non_clock_array_index = power_state->v2.nonClockInfoIndex; 4970 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 4971 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 4972 if (!rdev->pm.power_state[i].clock_info) 4973 return -EINVAL; 4974 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); 4975 if (ps == NULL) { 4976 kfree(rdev->pm.dpm.ps); 4977 return -ENOMEM; 4978 } 4979 rdev->pm.dpm.ps[i].ps_priv = ps; 4980 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 4981 non_clock_info, 4982 non_clock_info_array->ucEntrySize); 4983 k = 0; 4984 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 4985 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 4986 clock_array_index = idx[j]; 4987 if (clock_array_index >= clock_info_array->ucNumEntries) 4988 continue; 4989 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 4990 break; 4991 clock_info = (union pplib_clock_info *) 4992 ((u8 *)&clock_info_array->clockInfo[0] + 4993 (clock_array_index * clock_info_array->ucEntrySize)); 4994 ci_parse_pplib_clock_info(rdev, 4995 &rdev->pm.dpm.ps[i], k, 4996 clock_info); 4997 k++; 4998 } 4999 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 5000 } 5001 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 5002 5003 /* fill in the vce power states */ 5004 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 5005 u32 sclk, mclk; 5006 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 5007 clock_info = (union pplib_clock_info *) 5008 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 5009 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5010 sclk |= clock_info->ci.ucEngineClockHigh << 16; 5011 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5012 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5013 rdev->pm.dpm.vce_states[i].sclk = sclk; 5014 rdev->pm.dpm.vce_states[i].mclk = mclk; 5015 } 5016 5017 return 0; 5018 } 5019 5020 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 5021 struct ci_vbios_boot_state *boot_state) 5022 { 5023 struct radeon_mode_info *mode_info = &rdev->mode_info; 5024 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5025 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 5026 u8 frev, crev; 5027 u16 data_offset; 5028 5029 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 5030 &frev, &crev, &data_offset)) { 5031 firmware_info = 5032 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 5033 data_offset); 5034 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 5035 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 5036 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5037 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5038 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5039 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5040 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5041 5042 return 0; 5043 } 5044 return -EINVAL; 5045 } 5046 5047 void ci_dpm_fini(struct radeon_device *rdev) 5048 { 5049 int i; 5050 5051 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5052 kfree(rdev->pm.dpm.ps[i].ps_priv); 5053 } 5054 kfree(rdev->pm.dpm.ps); 5055 kfree(rdev->pm.dpm.priv); 5056 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5057 r600_free_extended_power_table(rdev); 5058 } 5059 5060 int ci_dpm_init(struct radeon_device *rdev) 5061 { 5062 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5063 u16 data_offset, size; 5064 u8 frev, crev; 5065 struct ci_power_info *pi; 5066 int ret; 5067 u32 mask; 5068 5069 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5070 if (pi == NULL) 5071 return -ENOMEM; 5072 rdev->pm.dpm.priv = pi; 5073 5074 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 5075 if (ret) 5076 pi->sys_pcie_mask = 0; 5077 else 5078 pi->sys_pcie_mask = mask; 5079 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5080 5081 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5082 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5083 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5084 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5085 5086 pi->pcie_lane_performance.max = 0; 5087 pi->pcie_lane_performance.min = 16; 5088 pi->pcie_lane_powersaving.max = 0; 5089 pi->pcie_lane_powersaving.min = 16; 5090 5091 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5092 if (ret) { 5093 ci_dpm_fini(rdev); 5094 return ret; 5095 } 5096 5097 ret = r600_get_platform_caps(rdev); 5098 if (ret) { 5099 ci_dpm_fini(rdev); 5100 return ret; 5101 } 5102 5103 ret = r600_parse_extended_power_table(rdev); 5104 if (ret) { 5105 ci_dpm_fini(rdev); 5106 return ret; 5107 } 5108 5109 ret = ci_parse_power_table(rdev); 5110 if (ret) { 5111 ci_dpm_fini(rdev); 5112 return ret; 5113 } 5114 5115 pi->dll_default_on = false; 5116 pi->sram_end = SMC_RAM_END; 5117 5118 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5119 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5120 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5121 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5122 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5123 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5124 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5125 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5126 5127 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5128 5129 pi->sclk_dpm_key_disabled = 0; 5130 pi->mclk_dpm_key_disabled = 0; 5131 pi->pcie_dpm_key_disabled = 0; 5132 5133 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ 5134 if ((rdev->pdev->device == 0x6658) && 5135 (rdev->mc_fw->datasize == (BONAIRE_MC_UCODE_SIZE * 4))) { 5136 pi->mclk_dpm_key_disabled = 1; 5137 } 5138 5139 pi->caps_sclk_ds = true; 5140 5141 pi->mclk_strobe_mode_threshold = 40000; 5142 pi->mclk_stutter_mode_threshold = 40000; 5143 pi->mclk_edc_enable_threshold = 40000; 5144 pi->mclk_edc_wr_enable_threshold = 40000; 5145 5146 ci_initialize_powertune_defaults(rdev); 5147 5148 pi->caps_fps = false; 5149 5150 pi->caps_sclk_throttle_low_notification = false; 5151 5152 pi->caps_uvd_dpm = true; 5153 pi->caps_vce_dpm = true; 5154 5155 ci_get_leakage_voltages(rdev); 5156 ci_patch_dependency_tables_with_leakage(rdev); 5157 ci_set_private_data_variables_based_on_pptable(rdev); 5158 5159 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5160 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 5161 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5162 ci_dpm_fini(rdev); 5163 return -ENOMEM; 5164 } 5165 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5166 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5167 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5168 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5169 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5170 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5171 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5172 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5173 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5174 5175 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5176 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5177 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5178 5179 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5180 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5181 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5182 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5183 5184 if (rdev->family == CHIP_HAWAII) { 5185 pi->thermal_temp_setting.temperature_low = 94500; 5186 pi->thermal_temp_setting.temperature_high = 95000; 5187 pi->thermal_temp_setting.temperature_shutdown = 104000; 5188 } else { 5189 pi->thermal_temp_setting.temperature_low = 99500; 5190 pi->thermal_temp_setting.temperature_high = 100000; 5191 pi->thermal_temp_setting.temperature_shutdown = 104000; 5192 } 5193 5194 pi->uvd_enabled = false; 5195 5196 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5197 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5198 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5199 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5200 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5201 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5202 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5203 5204 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5205 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5206 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5207 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5208 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5209 else 5210 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5211 } 5212 5213 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5214 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5215 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5216 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5217 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5218 else 5219 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5220 } 5221 5222 pi->vddc_phase_shed_control = true; 5223 5224 #if defined(CONFIG_ACPI) 5225 pi->pcie_performance_request = 5226 radeon_acpi_is_pcie_performance_request_supported(rdev); 5227 #else 5228 pi->pcie_performance_request = false; 5229 #endif 5230 5231 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5232 &frev, &crev, &data_offset)) { 5233 pi->caps_sclk_ss_support = true; 5234 pi->caps_mclk_ss_support = true; 5235 pi->dynamic_ss = true; 5236 } else { 5237 pi->caps_sclk_ss_support = false; 5238 pi->caps_mclk_ss_support = false; 5239 pi->dynamic_ss = true; 5240 } 5241 5242 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5243 pi->thermal_protection = true; 5244 else 5245 pi->thermal_protection = false; 5246 5247 pi->caps_dynamic_ac_timing = true; 5248 5249 pi->uvd_power_gated = false; 5250 5251 /* make sure dc limits are valid */ 5252 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5253 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5254 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5255 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5256 5257 return 0; 5258 } 5259 5260 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5261 struct seq_file *m) 5262 { 5263 struct ci_power_info *pi = ci_get_pi(rdev); 5264 struct radeon_ps *rps = &pi->current_rps; 5265 u32 sclk = ci_get_average_sclk_freq(rdev); 5266 u32 mclk = ci_get_average_mclk_freq(rdev); 5267 5268 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 5269 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 5270 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5271 sclk, mclk); 5272 } 5273 5274 void ci_dpm_print_power_state(struct radeon_device *rdev, 5275 struct radeon_ps *rps) 5276 { 5277 struct ci_ps *ps = ci_get_ps(rps); 5278 struct ci_pl *pl; 5279 int i; 5280 5281 r600_dpm_print_class_info(rps->class, rps->class2); 5282 r600_dpm_print_cap_info(rps->caps); 5283 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5284 for (i = 0; i < ps->performance_level_count; i++) { 5285 pl = &ps->performance_levels[i]; 5286 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5287 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5288 } 5289 r600_dpm_print_ps_status(rdev, rps); 5290 } 5291 5292 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5293 { 5294 struct ci_power_info *pi = ci_get_pi(rdev); 5295 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5296 5297 if (low) 5298 return requested_state->performance_levels[0].sclk; 5299 else 5300 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5301 } 5302 5303 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5304 { 5305 struct ci_power_info *pi = ci_get_pi(rdev); 5306 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5307 5308 if (low) 5309 return requested_state->performance_levels[0].mclk; 5310 else 5311 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5312 } 5313