1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "radeon.h" 28 #include "cikd.h" 29 #include "ppsmc.h" 30 #include "ci_dpm.h" 31 #include "radeon_ucode.h" 32 33 static int ci_set_smc_sram_address(struct radeon_device *rdev, 34 u32 smc_address, u32 limit) 35 { 36 if (smc_address & 3) 37 return -EINVAL; 38 if ((smc_address + 3) > limit) 39 return -EINVAL; 40 41 WREG32(SMC_IND_INDEX_0, smc_address); 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 43 44 return 0; 45 } 46 47 int ci_copy_bytes_to_smc(struct radeon_device *rdev, 48 u32 smc_start_address, 49 const u8 *src, u32 byte_count, u32 limit) 50 { 51 u32 data, original_data; 52 u32 addr; 53 u32 extra_shift; 54 int ret; 55 56 if (smc_start_address & 3) 57 return -EINVAL; 58 if ((smc_start_address + byte_count) > limit) 59 return -EINVAL; 60 61 addr = smc_start_address; 62 63 while (byte_count >= 4) { 64 /* SMC address space is BE */ 65 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 66 67 ret = ci_set_smc_sram_address(rdev, addr, limit); 68 if (ret) 69 return ret; 70 71 WREG32(SMC_IND_DATA_0, data); 72 73 src += 4; 74 byte_count -= 4; 75 addr += 4; 76 } 77 78 /* RMW for the final bytes */ 79 if (byte_count > 0) { 80 data = 0; 81 82 ret = ci_set_smc_sram_address(rdev, addr, limit); 83 if (ret) 84 return ret; 85 86 original_data = RREG32(SMC_IND_DATA_0); 87 88 extra_shift = 8 * (4 - byte_count); 89 90 while (byte_count > 0) { 91 data = (data << 8) + *src++; 92 byte_count--; 93 } 94 95 data <<= extra_shift; 96 97 data |= (original_data & ~((~0UL) << extra_shift)); 98 99 ret = ci_set_smc_sram_address(rdev, addr, limit); 100 if (ret) 101 return ret; 102 103 WREG32(SMC_IND_DATA_0, data); 104 } 105 return 0; 106 } 107 108 void ci_start_smc(struct radeon_device *rdev) 109 { 110 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 111 112 tmp &= ~RST_REG; 113 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 114 } 115 116 void ci_reset_smc(struct radeon_device *rdev) 117 { 118 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 119 120 tmp |= RST_REG; 121 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 122 } 123 124 int ci_program_jump_on_start(struct radeon_device *rdev) 125 { 126 static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 }; 127 128 return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1); 129 } 130 131 void ci_stop_smc_clock(struct radeon_device *rdev) 132 { 133 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 134 135 tmp |= CK_DISABLE; 136 137 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 138 } 139 140 void ci_start_smc_clock(struct radeon_device *rdev) 141 { 142 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 143 144 tmp &= ~CK_DISABLE; 145 146 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 147 } 148 149 bool ci_is_smc_running(struct radeon_device *rdev) 150 { 151 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 152 u32 pc_c = RREG32_SMC(SMC_PC_C); 153 154 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c)) 155 return true; 156 157 return false; 158 } 159 160 PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 161 { 162 u32 tmp; 163 int i; 164 165 if (!ci_is_smc_running(rdev)) 166 return PPSMC_Result_Failed; 167 168 WREG32(SMC_MESSAGE_0, msg); 169 170 for (i = 0; i < rdev->usec_timeout; i++) { 171 tmp = RREG32(SMC_RESP_0); 172 if (tmp != 0) 173 break; 174 udelay(1); 175 } 176 tmp = RREG32(SMC_RESP_0); 177 178 return (PPSMC_Result)tmp; 179 } 180 181 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) 182 { 183 u32 tmp; 184 int i; 185 186 if (!ci_is_smc_running(rdev)) 187 return PPSMC_Result_OK; 188 189 for (i = 0; i < rdev->usec_timeout; i++) { 190 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 191 if ((tmp & CKEN) == 0) 192 break; 193 udelay(1); 194 } 195 196 return PPSMC_Result_OK; 197 } 198 199 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) 200 { 201 u32 ucode_start_address; 202 u32 ucode_size; 203 const u8 *src; 204 u32 data; 205 206 if (!rdev->smc_fw) 207 return -EINVAL; 208 209 switch (rdev->family) { 210 case CHIP_BONAIRE: 211 ucode_start_address = BONAIRE_SMC_UCODE_START; 212 ucode_size = BONAIRE_SMC_UCODE_SIZE; 213 break; 214 default: 215 DRM_ERROR("unknown asic in smc ucode loader\n"); 216 BUG(); 217 } 218 219 if (ucode_size & 3) 220 return -EINVAL; 221 222 src = (const u8 *)rdev->smc_fw->data; 223 WREG32(SMC_IND_INDEX_0, ucode_start_address); 224 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); 225 while (ucode_size >= 4) { 226 /* SMC address space is BE */ 227 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 228 229 WREG32(SMC_IND_DATA_0, data); 230 231 src += 4; 232 ucode_size -= 4; 233 } 234 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 235 236 return 0; 237 } 238 239 int ci_read_smc_sram_dword(struct radeon_device *rdev, 240 u32 smc_address, u32 *value, u32 limit) 241 { 242 int ret; 243 244 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 245 if (ret) 246 return ret; 247 248 *value = RREG32(SMC_IND_DATA_0); 249 return 0; 250 } 251 252 int ci_write_smc_sram_dword(struct radeon_device *rdev, 253 u32 smc_address, u32 value, u32 limit) 254 { 255 int ret; 256 257 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 258 if (ret) 259 return ret; 260 261 WREG32(SMC_IND_DATA_0, value); 262 return 0; 263 } 264