1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "radeon.h" 28 #include "cikd.h" 29 #include "ppsmc.h" 30 #include "radeon_ucode.h" 31 #include "ci_dpm.h" 32 33 static int ci_set_smc_sram_address(struct radeon_device *rdev, 34 u32 smc_address, u32 limit) 35 { 36 if (smc_address & 3) 37 return -EINVAL; 38 if ((smc_address + 3) > limit) 39 return -EINVAL; 40 41 WREG32(SMC_IND_INDEX_0, smc_address); 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 43 44 return 0; 45 } 46 47 int ci_copy_bytes_to_smc(struct radeon_device *rdev, 48 u32 smc_start_address, 49 const u8 *src, u32 byte_count, u32 limit) 50 { 51 u32 data, original_data; 52 u32 addr; 53 u32 extra_shift; 54 int ret = 0; 55 56 if (smc_start_address & 3) 57 return -EINVAL; 58 if ((smc_start_address + byte_count) > limit) 59 return -EINVAL; 60 61 addr = smc_start_address; 62 63 spin_lock(&rdev->smc_idx_lock); 64 while (byte_count >= 4) { 65 /* SMC address space is BE */ 66 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 67 68 ret = ci_set_smc_sram_address(rdev, addr, limit); 69 if (ret) 70 goto done; 71 72 WREG32(SMC_IND_DATA_0, data); 73 74 src += 4; 75 byte_count -= 4; 76 addr += 4; 77 } 78 79 /* RMW for the final bytes */ 80 if (byte_count > 0) { 81 data = 0; 82 83 ret = ci_set_smc_sram_address(rdev, addr, limit); 84 if (ret) 85 goto done; 86 87 original_data = RREG32(SMC_IND_DATA_0); 88 89 extra_shift = 8 * (4 - byte_count); 90 91 while (byte_count > 0) { 92 data = (data << 8) + *src++; 93 byte_count--; 94 } 95 96 data <<= extra_shift; 97 98 data |= (original_data & ~((~0UL) << extra_shift)); 99 100 ret = ci_set_smc_sram_address(rdev, addr, limit); 101 if (ret) 102 goto done; 103 104 WREG32(SMC_IND_DATA_0, data); 105 } 106 107 done: 108 spin_unlock(&rdev->smc_idx_lock); 109 110 return ret; 111 } 112 113 void ci_start_smc(struct radeon_device *rdev) 114 { 115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 116 117 tmp &= ~RST_REG; 118 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 119 } 120 121 void ci_reset_smc(struct radeon_device *rdev) 122 { 123 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 124 125 tmp |= RST_REG; 126 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 127 } 128 129 int ci_program_jump_on_start(struct radeon_device *rdev) 130 { 131 static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 }; 132 133 return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1); 134 } 135 136 void ci_stop_smc_clock(struct radeon_device *rdev) 137 { 138 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 139 140 tmp |= CK_DISABLE; 141 142 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 143 } 144 145 void ci_start_smc_clock(struct radeon_device *rdev) 146 { 147 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 148 149 tmp &= ~CK_DISABLE; 150 151 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 152 } 153 154 bool ci_is_smc_running(struct radeon_device *rdev) 155 { 156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 157 u32 pc_c = RREG32_SMC(SMC_PC_C); 158 159 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c)) 160 return true; 161 162 return false; 163 } 164 165 PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 166 { 167 u32 tmp; 168 int i; 169 170 if (!ci_is_smc_running(rdev)) 171 return PPSMC_Result_Failed; 172 173 WREG32(SMC_MESSAGE_0, msg); 174 175 for (i = 0; i < rdev->usec_timeout; i++) { 176 tmp = RREG32(SMC_RESP_0); 177 if (tmp != 0) 178 break; 179 udelay(1); 180 } 181 tmp = RREG32(SMC_RESP_0); 182 183 return (PPSMC_Result)tmp; 184 } 185 186 #if 0 187 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) 188 { 189 u32 tmp; 190 int i; 191 192 if (!ci_is_smc_running(rdev)) 193 return PPSMC_Result_OK; 194 195 for (i = 0; i < rdev->usec_timeout; i++) { 196 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 197 if ((tmp & CKEN) == 0) 198 break; 199 udelay(1); 200 } 201 202 return PPSMC_Result_OK; 203 } 204 #endif 205 206 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) 207 { 208 u32 ucode_start_address; 209 u32 ucode_size; 210 const u8 *src; 211 u32 data; 212 213 if (!rdev->smc_fw) 214 return -EINVAL; 215 216 if (rdev->new_fw) { 217 const struct smc_firmware_header_v1_0 *hdr = 218 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data; 219 220 radeon_ucode_print_smc_hdr(&hdr->header); 221 222 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 223 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 224 src = (const u8 *) 225 ((const char *)rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 226 } else { 227 switch (rdev->family) { 228 case CHIP_BONAIRE: 229 ucode_start_address = BONAIRE_SMC_UCODE_START; 230 ucode_size = BONAIRE_SMC_UCODE_SIZE; 231 break; 232 case CHIP_HAWAII: 233 ucode_start_address = HAWAII_SMC_UCODE_START; 234 ucode_size = HAWAII_SMC_UCODE_SIZE; 235 break; 236 default: 237 DRM_ERROR("unknown asic in smc ucode loader\n"); 238 BUG(); 239 } 240 241 src = (const u8 *)rdev->smc_fw->data; 242 } 243 244 if (ucode_size & 3) 245 return -EINVAL; 246 247 spin_lock(&rdev->smc_idx_lock); 248 WREG32(SMC_IND_INDEX_0, ucode_start_address); 249 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); 250 while (ucode_size >= 4) { 251 /* SMC address space is BE */ 252 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 253 254 WREG32(SMC_IND_DATA_0, data); 255 256 src += 4; 257 ucode_size -= 4; 258 } 259 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 260 spin_unlock(&rdev->smc_idx_lock); 261 262 return 0; 263 } 264 265 int ci_read_smc_sram_dword(struct radeon_device *rdev, 266 u32 smc_address, u32 *value, u32 limit) 267 { 268 int ret; 269 270 spin_lock(&rdev->smc_idx_lock); 271 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 272 if (ret == 0) 273 *value = RREG32(SMC_IND_DATA_0); 274 spin_unlock(&rdev->smc_idx_lock); 275 276 return ret; 277 } 278 279 int ci_write_smc_sram_dword(struct radeon_device *rdev, 280 u32 smc_address, u32 value, u32 limit) 281 { 282 int ret; 283 284 spin_lock(&rdev->smc_idx_lock); 285 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 286 if (ret == 0) 287 WREG32(SMC_IND_DATA_0, value); 288 spin_unlock(&rdev->smc_idx_lock); 289 290 return ret; 291 } 292