14cd92098Szrj /* 24cd92098Szrj * Copyright 2013 Advanced Micro Devices, Inc. 34cd92098Szrj * 44cd92098Szrj * Permission is hereby granted, free of charge, to any person obtaining a 54cd92098Szrj * copy of this software and associated documentation files (the "Software"), 64cd92098Szrj * to deal in the Software without restriction, including without limitation 74cd92098Szrj * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84cd92098Szrj * and/or sell copies of the Software, and to permit persons to whom the 94cd92098Szrj * Software is furnished to do so, subject to the following conditions: 104cd92098Szrj * 114cd92098Szrj * The above copyright notice and this permission notice shall be included in 124cd92098Szrj * all copies or substantial portions of the Software. 134cd92098Szrj * 144cd92098Szrj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154cd92098Szrj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164cd92098Szrj * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174cd92098Szrj * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184cd92098Szrj * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194cd92098Szrj * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204cd92098Szrj * OTHER DEALINGS IN THE SOFTWARE. 214cd92098Szrj * 224cd92098Szrj * Authors: Alex Deucher 234cd92098Szrj */ 244cd92098Szrj #include <linux/firmware.h> 254cd92098Szrj #include <drm/drmP.h> 264cd92098Szrj #include "radeon.h" 27cb754608SImre Vadász #include "radeon_ucode.h" 284cd92098Szrj #include "radeon_asic.h" 29c6f73aabSFrançois Tigeot #include "radeon_trace.h" 304cd92098Szrj #include "cikd.h" 314cd92098Szrj 324cd92098Szrj /* sdma */ 334cd92098Szrj #define CIK_SDMA_UCODE_SIZE 1050 344cd92098Szrj #define CIK_SDMA_UCODE_VERSION 64 354cd92098Szrj 364cd92098Szrj /* 374cd92098Szrj * sDMA - System DMA 384cd92098Szrj * Starting with CIK, the GPU has new asynchronous 394cd92098Szrj * DMA engines. These engines are used for compute 404cd92098Szrj * and gfx. There are two DMA engines (SDMA0, SDMA1) 414cd92098Szrj * and each one supports 1 ring buffer used for gfx 424cd92098Szrj * and 2 queues used for compute. 434cd92098Szrj * 444cd92098Szrj * The programming model is very similar to the CP 454cd92098Szrj * (ring buffer, IBs, etc.), but sDMA has it's own 464cd92098Szrj * packet format that is different from the PM4 format 474cd92098Szrj * used by the CP. sDMA supports copying data, writing 484cd92098Szrj * embedded data, solid fills, and a number of other 494cd92098Szrj * things. It also has support for tiling/detiling of 504cd92098Szrj * buffers. 514cd92098Szrj */ 524cd92098Szrj 534cd92098Szrj /** 54c6f73aabSFrançois Tigeot * cik_sdma_get_rptr - get the current read pointer 55c6f73aabSFrançois Tigeot * 56c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 57c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 58c6f73aabSFrançois Tigeot * 59c6f73aabSFrançois Tigeot * Get the current rptr from the hardware (CIK+). 60c6f73aabSFrançois Tigeot */ 61c6f73aabSFrançois Tigeot uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, 62c6f73aabSFrançois Tigeot struct radeon_ring *ring) 63c6f73aabSFrançois Tigeot { 64c6f73aabSFrançois Tigeot u32 rptr, reg; 65c6f73aabSFrançois Tigeot 66c6f73aabSFrançois Tigeot if (rdev->wb.enabled) { 67c6f73aabSFrançois Tigeot rptr = rdev->wb.wb[ring->rptr_offs/4]; 68c6f73aabSFrançois Tigeot } else { 69c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 70c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; 71c6f73aabSFrançois Tigeot else 72c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; 73c6f73aabSFrançois Tigeot 74c6f73aabSFrançois Tigeot rptr = RREG32(reg); 75c6f73aabSFrançois Tigeot } 76c6f73aabSFrançois Tigeot 77c6f73aabSFrançois Tigeot return (rptr & 0x3fffc) >> 2; 78c6f73aabSFrançois Tigeot } 79c6f73aabSFrançois Tigeot 80c6f73aabSFrançois Tigeot /** 81c6f73aabSFrançois Tigeot * cik_sdma_get_wptr - get the current write pointer 82c6f73aabSFrançois Tigeot * 83c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 84c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 85c6f73aabSFrançois Tigeot * 86c6f73aabSFrançois Tigeot * Get the current wptr from the hardware (CIK+). 87c6f73aabSFrançois Tigeot */ 88c6f73aabSFrançois Tigeot uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, 89c6f73aabSFrançois Tigeot struct radeon_ring *ring) 90c6f73aabSFrançois Tigeot { 91c6f73aabSFrançois Tigeot u32 reg; 92c6f73aabSFrançois Tigeot 93c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 94c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 95c6f73aabSFrançois Tigeot else 96c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 97c6f73aabSFrançois Tigeot 98c6f73aabSFrançois Tigeot return (RREG32(reg) & 0x3fffc) >> 2; 99c6f73aabSFrançois Tigeot } 100c6f73aabSFrançois Tigeot 101c6f73aabSFrançois Tigeot /** 102c6f73aabSFrançois Tigeot * cik_sdma_set_wptr - commit the write pointer 103c6f73aabSFrançois Tigeot * 104c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 105c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 106c6f73aabSFrançois Tigeot * 107c6f73aabSFrançois Tigeot * Write the wptr back to the hardware (CIK+). 108c6f73aabSFrançois Tigeot */ 109c6f73aabSFrançois Tigeot void cik_sdma_set_wptr(struct radeon_device *rdev, 110c6f73aabSFrançois Tigeot struct radeon_ring *ring) 111c6f73aabSFrançois Tigeot { 112c6f73aabSFrançois Tigeot u32 reg; 113c6f73aabSFrançois Tigeot 114c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 115c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 116c6f73aabSFrançois Tigeot else 117c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 118c6f73aabSFrançois Tigeot 119c6f73aabSFrançois Tigeot WREG32(reg, (ring->wptr << 2) & 0x3fffc); 120c6f73aabSFrançois Tigeot (void)RREG32(reg); 121c6f73aabSFrançois Tigeot } 122c6f73aabSFrançois Tigeot 123c6f73aabSFrançois Tigeot /** 1244cd92098Szrj * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 1254cd92098Szrj * 1264cd92098Szrj * @rdev: radeon_device pointer 1274cd92098Szrj * @ib: IB object to schedule 1284cd92098Szrj * 1294cd92098Szrj * Schedule an IB in the DMA ring (CIK). 1304cd92098Szrj */ 1314cd92098Szrj void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 1324cd92098Szrj struct radeon_ib *ib) 1334cd92098Szrj { 1344cd92098Szrj struct radeon_ring *ring = &rdev->ring[ib->ring]; 1357dcf36dcSFrançois Tigeot u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; 1364cd92098Szrj 1374cd92098Szrj if (rdev->wb.enabled) { 1384cd92098Szrj u32 next_rptr = ring->wptr + 5; 1394cd92098Szrj while ((next_rptr & 7) != 4) 1404cd92098Szrj next_rptr++; 1414cd92098Szrj next_rptr += 4; 1424cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 1434cd92098Szrj radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 144c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 1454cd92098Szrj radeon_ring_write(ring, 1); /* number of DWs to follow */ 1464cd92098Szrj radeon_ring_write(ring, next_rptr); 1474cd92098Szrj } 1484cd92098Szrj 1494cd92098Szrj /* IB packet must end on a 8 DW boundary */ 1504cd92098Szrj while ((ring->wptr & 7) != 4) 1514cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 1524cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 1534cd92098Szrj radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 154c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1554cd92098Szrj radeon_ring_write(ring, ib->length_dw); 1564cd92098Szrj 1574cd92098Szrj } 1584cd92098Szrj 1594cd92098Szrj /** 160c6f73aabSFrançois Tigeot * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 161c6f73aabSFrançois Tigeot * 162c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 163c6f73aabSFrançois Tigeot * @ridx: radeon ring index 164c6f73aabSFrançois Tigeot * 165c6f73aabSFrançois Tigeot * Emit an hdp flush packet on the requested DMA ring. 166c6f73aabSFrançois Tigeot */ 167c6f73aabSFrançois Tigeot static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, 168c6f73aabSFrançois Tigeot int ridx) 169c6f73aabSFrançois Tigeot { 170c6f73aabSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[ridx]; 171c6f73aabSFrançois Tigeot u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 172c6f73aabSFrançois Tigeot SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 173c6f73aabSFrançois Tigeot u32 ref_and_mask; 174c6f73aabSFrançois Tigeot 175c6f73aabSFrançois Tigeot if (ridx == R600_RING_TYPE_DMA_INDEX) 176c6f73aabSFrançois Tigeot ref_and_mask = SDMA0; 177c6f73aabSFrançois Tigeot else 178c6f73aabSFrançois Tigeot ref_and_mask = SDMA1; 179c6f73aabSFrançois Tigeot 180c6f73aabSFrançois Tigeot radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 181c6f73aabSFrançois Tigeot radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 182c6f73aabSFrançois Tigeot radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 183c6f73aabSFrançois Tigeot radeon_ring_write(ring, ref_and_mask); /* reference */ 184c6f73aabSFrançois Tigeot radeon_ring_write(ring, ref_and_mask); /* mask */ 185c6f73aabSFrançois Tigeot radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 186c6f73aabSFrançois Tigeot } 187c6f73aabSFrançois Tigeot 188c6f73aabSFrançois Tigeot /** 1894cd92098Szrj * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 1904cd92098Szrj * 1914cd92098Szrj * @rdev: radeon_device pointer 1924cd92098Szrj * @fence: radeon fence object 1934cd92098Szrj * 1944cd92098Szrj * Add a DMA fence packet to the ring to write 1954cd92098Szrj * the fence seq number and DMA trap packet to generate 1964cd92098Szrj * an interrupt if needed (CIK). 1974cd92098Szrj */ 1984cd92098Szrj void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 1994cd92098Szrj struct radeon_fence *fence) 2004cd92098Szrj { 2014cd92098Szrj struct radeon_ring *ring = &rdev->ring[fence->ring]; 2024cd92098Szrj u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2034cd92098Szrj 2044cd92098Szrj /* write the fence */ 2054cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 206c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(addr)); 207c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(addr)); 2084cd92098Szrj radeon_ring_write(ring, fence->seq); 2094cd92098Szrj /* generate an interrupt */ 2104cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 2114cd92098Szrj /* flush HDP */ 212c6f73aabSFrançois Tigeot cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); 2134cd92098Szrj } 2144cd92098Szrj 2154cd92098Szrj /** 2164cd92098Szrj * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring 2174cd92098Szrj * 2184cd92098Szrj * @rdev: radeon_device pointer 2194cd92098Szrj * @ring: radeon_ring structure holding ring information 2204cd92098Szrj * @semaphore: radeon semaphore object 2214cd92098Szrj * @emit_wait: wait or signal semaphore 2224cd92098Szrj * 2234cd92098Szrj * Add a DMA semaphore packet to the ring wait on or signal 2244cd92098Szrj * other rings (CIK). 2254cd92098Szrj */ 226c6f73aabSFrançois Tigeot bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 2274cd92098Szrj struct radeon_ring *ring, 2284cd92098Szrj struct radeon_semaphore *semaphore, 2294cd92098Szrj bool emit_wait) 2304cd92098Szrj { 2314cd92098Szrj u64 addr = semaphore->gpu_addr; 2324cd92098Szrj u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; 2334cd92098Szrj 2344cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 2354cd92098Szrj radeon_ring_write(ring, addr & 0xfffffff8); 236c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(addr)); 237c6f73aabSFrançois Tigeot 238c6f73aabSFrançois Tigeot return true; 2394cd92098Szrj } 2404cd92098Szrj 2414cd92098Szrj /** 2424cd92098Szrj * cik_sdma_gfx_stop - stop the gfx async dma engines 2434cd92098Szrj * 2444cd92098Szrj * @rdev: radeon_device pointer 2454cd92098Szrj * 2464cd92098Szrj * Stop the gfx async dma ring buffers (CIK). 2474cd92098Szrj */ 2484cd92098Szrj static void cik_sdma_gfx_stop(struct radeon_device *rdev) 2494cd92098Szrj { 2504cd92098Szrj u32 rb_cntl, reg_offset; 2514cd92098Szrj int i; 2524cd92098Szrj 253c6f73aabSFrançois Tigeot if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 254c6f73aabSFrançois Tigeot (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 2554cd92098Szrj radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2564cd92098Szrj 2574cd92098Szrj for (i = 0; i < 2; i++) { 2584cd92098Szrj if (i == 0) 2594cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 2604cd92098Szrj else 2614cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 2624cd92098Szrj rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); 2634cd92098Szrj rb_cntl &= ~SDMA_RB_ENABLE; 2644cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 2654cd92098Szrj WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); 2664cd92098Szrj } 267c6f73aabSFrançois Tigeot rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 268c6f73aabSFrançois Tigeot rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; 269*c59a5c48SFrançois Tigeot 270*c59a5c48SFrançois Tigeot /* FIXME use something else than big hammer but after few days can not 271*c59a5c48SFrançois Tigeot * seem to find good combination so reset SDMA blocks as it seems we 272*c59a5c48SFrançois Tigeot * do not shut them down properly. This fix hibernation and does not 273*c59a5c48SFrançois Tigeot * affect suspend to ram. 274*c59a5c48SFrançois Tigeot */ 275*c59a5c48SFrançois Tigeot WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); 276*c59a5c48SFrançois Tigeot (void)RREG32(SRBM_SOFT_RESET); 277*c59a5c48SFrançois Tigeot udelay(50); 278*c59a5c48SFrançois Tigeot WREG32(SRBM_SOFT_RESET, 0); 279*c59a5c48SFrançois Tigeot (void)RREG32(SRBM_SOFT_RESET); 2804cd92098Szrj } 2814cd92098Szrj 2824cd92098Szrj /** 2834cd92098Szrj * cik_sdma_rlc_stop - stop the compute async dma engines 2844cd92098Szrj * 2854cd92098Szrj * @rdev: radeon_device pointer 2864cd92098Szrj * 2874cd92098Szrj * Stop the compute async dma queues (CIK). 2884cd92098Szrj */ 2894cd92098Szrj static void cik_sdma_rlc_stop(struct radeon_device *rdev) 2904cd92098Szrj { 2914cd92098Szrj /* XXX todo */ 2924cd92098Szrj } 2934cd92098Szrj 2944cd92098Szrj /** 295*c59a5c48SFrançois Tigeot * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption 296*c59a5c48SFrançois Tigeot * 297*c59a5c48SFrançois Tigeot * @rdev: radeon_device pointer 298*c59a5c48SFrançois Tigeot * @enable: enable/disable preemption. 299*c59a5c48SFrançois Tigeot * 300*c59a5c48SFrançois Tigeot * Halt or unhalt the async dma engines (CIK). 301*c59a5c48SFrançois Tigeot */ 302*c59a5c48SFrançois Tigeot static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable) 303*c59a5c48SFrançois Tigeot { 304*c59a5c48SFrançois Tigeot uint32_t reg_offset, value; 305*c59a5c48SFrançois Tigeot int i; 306*c59a5c48SFrançois Tigeot 307*c59a5c48SFrançois Tigeot for (i = 0; i < 2; i++) { 308*c59a5c48SFrançois Tigeot if (i == 0) 309*c59a5c48SFrançois Tigeot reg_offset = SDMA0_REGISTER_OFFSET; 310*c59a5c48SFrançois Tigeot else 311*c59a5c48SFrançois Tigeot reg_offset = SDMA1_REGISTER_OFFSET; 312*c59a5c48SFrançois Tigeot value = RREG32(SDMA0_CNTL + reg_offset); 313*c59a5c48SFrançois Tigeot if (enable) 314*c59a5c48SFrançois Tigeot value |= AUTO_CTXSW_ENABLE; 315*c59a5c48SFrançois Tigeot else 316*c59a5c48SFrançois Tigeot value &= ~AUTO_CTXSW_ENABLE; 317*c59a5c48SFrançois Tigeot WREG32(SDMA0_CNTL + reg_offset, value); 318*c59a5c48SFrançois Tigeot } 319*c59a5c48SFrançois Tigeot } 320*c59a5c48SFrançois Tigeot 321*c59a5c48SFrançois Tigeot /** 3224cd92098Szrj * cik_sdma_enable - stop the async dma engines 3234cd92098Szrj * 3244cd92098Szrj * @rdev: radeon_device pointer 3254cd92098Szrj * @enable: enable/disable the DMA MEs. 3264cd92098Szrj * 3274cd92098Szrj * Halt or unhalt the async dma engines (CIK). 3284cd92098Szrj */ 3294cd92098Szrj void cik_sdma_enable(struct radeon_device *rdev, bool enable) 3304cd92098Szrj { 3314cd92098Szrj u32 me_cntl, reg_offset; 3324cd92098Szrj int i; 3334cd92098Szrj 334c6f73aabSFrançois Tigeot if (enable == false) { 335c6f73aabSFrançois Tigeot cik_sdma_gfx_stop(rdev); 336c6f73aabSFrançois Tigeot cik_sdma_rlc_stop(rdev); 337c6f73aabSFrançois Tigeot } 338c6f73aabSFrançois Tigeot 3394cd92098Szrj for (i = 0; i < 2; i++) { 3404cd92098Szrj if (i == 0) 3414cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 3424cd92098Szrj else 3434cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 3444cd92098Szrj me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); 3454cd92098Szrj if (enable) 3464cd92098Szrj me_cntl &= ~SDMA_HALT; 3474cd92098Szrj else 3484cd92098Szrj me_cntl |= SDMA_HALT; 3494cd92098Szrj WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); 3504cd92098Szrj } 351*c59a5c48SFrançois Tigeot 352*c59a5c48SFrançois Tigeot cik_sdma_ctx_switch_enable(rdev, enable); 3534cd92098Szrj } 3544cd92098Szrj 3554cd92098Szrj /** 3564cd92098Szrj * cik_sdma_gfx_resume - setup and start the async dma engines 3574cd92098Szrj * 3584cd92098Szrj * @rdev: radeon_device pointer 3594cd92098Szrj * 3604cd92098Szrj * Set up the gfx DMA ring buffers and enable them (CIK). 3614cd92098Szrj * Returns 0 for success, error for failure. 3624cd92098Szrj */ 3634cd92098Szrj static int cik_sdma_gfx_resume(struct radeon_device *rdev) 3644cd92098Szrj { 3654cd92098Szrj struct radeon_ring *ring; 3664cd92098Szrj u32 rb_cntl, ib_cntl; 3674cd92098Szrj u32 rb_bufsz; 3684cd92098Szrj u32 reg_offset, wb_offset; 3694cd92098Szrj int i, r; 3704cd92098Szrj 3714cd92098Szrj for (i = 0; i < 2; i++) { 3724cd92098Szrj if (i == 0) { 3734cd92098Szrj ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3744cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 3754cd92098Szrj wb_offset = R600_WB_DMA_RPTR_OFFSET; 3764cd92098Szrj } else { 3774cd92098Szrj ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 3784cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 3794cd92098Szrj wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; 3804cd92098Szrj } 3814cd92098Szrj 3824cd92098Szrj WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 3834cd92098Szrj WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 3844cd92098Szrj 3854cd92098Szrj /* Set ring buffer size in dwords */ 3864cd92098Szrj rb_bufsz = order_base_2(ring->ring_size / 4); 3874cd92098Szrj rb_cntl = rb_bufsz << 1; 3884cd92098Szrj #ifdef __BIG_ENDIAN 3894cd92098Szrj rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 3904cd92098Szrj #endif 3914cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 3924cd92098Szrj 3934cd92098Szrj /* Initialize the ring buffer's read and write pointers */ 3944cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); 3954cd92098Szrj WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); 3964cd92098Szrj 3974cd92098Szrj /* set the wb address whether it's enabled or not */ 3984cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, 3994cd92098Szrj upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 4004cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, 4014cd92098Szrj ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 4024cd92098Szrj 4034cd92098Szrj if (rdev->wb.enabled) 4044cd92098Szrj rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; 4054cd92098Szrj 4064cd92098Szrj WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 4074cd92098Szrj WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 4084cd92098Szrj 4094cd92098Szrj ring->wptr = 0; 4104cd92098Szrj WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); 4114cd92098Szrj 4124cd92098Szrj /* enable DMA RB */ 4134cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); 4144cd92098Szrj 4154cd92098Szrj ib_cntl = SDMA_IB_ENABLE; 4164cd92098Szrj #ifdef __BIG_ENDIAN 4174cd92098Szrj ib_cntl |= SDMA_IB_SWAP_ENABLE; 4184cd92098Szrj #endif 4194cd92098Szrj /* enable DMA IBs */ 4204cd92098Szrj WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); 4214cd92098Szrj 4224cd92098Szrj ring->ready = true; 4234cd92098Szrj 4244cd92098Szrj r = radeon_ring_test(rdev, ring->idx, ring); 4254cd92098Szrj if (r) { 4264cd92098Szrj ring->ready = false; 4274cd92098Szrj return r; 4284cd92098Szrj } 4294cd92098Szrj } 4304cd92098Szrj 431c6f73aabSFrançois Tigeot if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 432c6f73aabSFrançois Tigeot (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 4334cd92098Szrj radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 4344cd92098Szrj 4354cd92098Szrj return 0; 4364cd92098Szrj } 4374cd92098Szrj 4384cd92098Szrj /** 4394cd92098Szrj * cik_sdma_rlc_resume - setup and start the async dma engines 4404cd92098Szrj * 4414cd92098Szrj * @rdev: radeon_device pointer 4424cd92098Szrj * 4434cd92098Szrj * Set up the compute DMA queues and enable them (CIK). 4444cd92098Szrj * Returns 0 for success, error for failure. 4454cd92098Szrj */ 4464cd92098Szrj static int cik_sdma_rlc_resume(struct radeon_device *rdev) 4474cd92098Szrj { 4484cd92098Szrj /* XXX todo */ 4494cd92098Szrj return 0; 4504cd92098Szrj } 4514cd92098Szrj 4524cd92098Szrj /** 4534cd92098Szrj * cik_sdma_load_microcode - load the sDMA ME ucode 4544cd92098Szrj * 4554cd92098Szrj * @rdev: radeon_device pointer 4564cd92098Szrj * 4574cd92098Szrj * Loads the sDMA0/1 ucode. 4584cd92098Szrj * Returns 0 for success, -EINVAL if the ucode is not available. 4594cd92098Szrj */ 4604cd92098Szrj static int cik_sdma_load_microcode(struct radeon_device *rdev) 4614cd92098Szrj { 4624cd92098Szrj int i; 4634cd92098Szrj 4644cd92098Szrj if (!rdev->sdma_fw) 4654cd92098Szrj return -EINVAL; 4664cd92098Szrj 4674cd92098Szrj /* halt the MEs */ 4684cd92098Szrj cik_sdma_enable(rdev, false); 4694cd92098Szrj 470cb754608SImre Vadász if (rdev->new_fw) { 471cb754608SImre Vadász const struct sdma_firmware_header_v1_0 *hdr = 472cb754608SImre Vadász (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; 473cb754608SImre Vadász const __le32 *fw_data; 474cb754608SImre Vadász u32 fw_size; 475cb754608SImre Vadász 476cb754608SImre Vadász radeon_ucode_print_sdma_hdr(&hdr->header); 477cb754608SImre Vadász 478cb754608SImre Vadász /* sdma0 */ 479cb754608SImre Vadász fw_data = (const __le32 *) 480*c59a5c48SFrançois Tigeot (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 481cb754608SImre Vadász fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 482cb754608SImre Vadász WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 483cb754608SImre Vadász for (i = 0; i < fw_size; i++) 484cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 485cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 486cb754608SImre Vadász 487cb754608SImre Vadász /* sdma1 */ 488cb754608SImre Vadász fw_data = (const __le32 *) 489*c59a5c48SFrançois Tigeot (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 490cb754608SImre Vadász fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 491cb754608SImre Vadász WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 492cb754608SImre Vadász for (i = 0; i < fw_size; i++) 493cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 494cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 495cb754608SImre Vadász } else { 496cb754608SImre Vadász const __be32 *fw_data; 497cb754608SImre Vadász 4984cd92098Szrj /* sdma0 */ 4994cd92098Szrj fw_data = (const __be32 *)rdev->sdma_fw->data; 5004cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 5014cd92098Szrj for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 5024cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 5034cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 5044cd92098Szrj 5054cd92098Szrj /* sdma1 */ 5064cd92098Szrj fw_data = (const __be32 *)rdev->sdma_fw->data; 5074cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 5084cd92098Szrj for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 5094cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 5104cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 511cb754608SImre Vadász } 5124cd92098Szrj 5134cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 5144cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 5154cd92098Szrj return 0; 5164cd92098Szrj } 5174cd92098Szrj 5184cd92098Szrj /** 5194cd92098Szrj * cik_sdma_resume - setup and start the async dma engines 5204cd92098Szrj * 5214cd92098Szrj * @rdev: radeon_device pointer 5224cd92098Szrj * 5234cd92098Szrj * Set up the DMA engines and enable them (CIK). 5244cd92098Szrj * Returns 0 for success, error for failure. 5254cd92098Szrj */ 5264cd92098Szrj int cik_sdma_resume(struct radeon_device *rdev) 5274cd92098Szrj { 5284cd92098Szrj int r; 5294cd92098Szrj 5304cd92098Szrj r = cik_sdma_load_microcode(rdev); 5314cd92098Szrj if (r) 5324cd92098Szrj return r; 5334cd92098Szrj 5344cd92098Szrj /* unhalt the MEs */ 5354cd92098Szrj cik_sdma_enable(rdev, true); 5364cd92098Szrj 5374cd92098Szrj /* start the gfx rings and rlc compute queues */ 5384cd92098Szrj r = cik_sdma_gfx_resume(rdev); 5394cd92098Szrj if (r) 5404cd92098Szrj return r; 5414cd92098Szrj r = cik_sdma_rlc_resume(rdev); 5424cd92098Szrj if (r) 5434cd92098Szrj return r; 5444cd92098Szrj 5454cd92098Szrj return 0; 5464cd92098Szrj } 5474cd92098Szrj 5484cd92098Szrj /** 5494cd92098Szrj * cik_sdma_fini - tear down the async dma engines 5504cd92098Szrj * 5514cd92098Szrj * @rdev: radeon_device pointer 5524cd92098Szrj * 5534cd92098Szrj * Stop the async dma engines and free the rings (CIK). 5544cd92098Szrj */ 5554cd92098Szrj void cik_sdma_fini(struct radeon_device *rdev) 5564cd92098Szrj { 5574cd92098Szrj /* halt the MEs */ 5584cd92098Szrj cik_sdma_enable(rdev, false); 5594cd92098Szrj radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 5604cd92098Szrj radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 5614cd92098Szrj /* XXX - compute dma queue tear down */ 5624cd92098Szrj } 5634cd92098Szrj 5644cd92098Szrj /** 5654cd92098Szrj * cik_copy_dma - copy pages using the DMA engine 5664cd92098Szrj * 5674cd92098Szrj * @rdev: radeon_device pointer 5684cd92098Szrj * @src_offset: src GPU address 5694cd92098Szrj * @dst_offset: dst GPU address 5704cd92098Szrj * @num_gpu_pages: number of GPU pages to xfer 5711cfef1a5SFrançois Tigeot * @resv: reservation object to sync to 5724cd92098Szrj * 5734cd92098Szrj * Copy GPU paging using the DMA engine (CIK). 5744cd92098Szrj * Used by the radeon ttm implementation to move pages if 5754cd92098Szrj * registered as the asic copy callback. 5764cd92098Szrj */ 5771cfef1a5SFrançois Tigeot struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 5784cd92098Szrj uint64_t src_offset, uint64_t dst_offset, 5794cd92098Szrj unsigned num_gpu_pages, 5801cfef1a5SFrançois Tigeot struct reservation_object *resv) 5814cd92098Szrj { 5821cfef1a5SFrançois Tigeot struct radeon_fence *fence; 5837dcf36dcSFrançois Tigeot struct radeon_sync sync; 5844cd92098Szrj int ring_index = rdev->asic->copy.dma_ring_index; 5854cd92098Szrj struct radeon_ring *ring = &rdev->ring[ring_index]; 5864cd92098Szrj u32 size_in_bytes, cur_size_in_bytes; 5874cd92098Szrj int i, num_loops; 5884cd92098Szrj int r = 0; 5894cd92098Szrj 5907dcf36dcSFrançois Tigeot radeon_sync_create(&sync); 5914cd92098Szrj 5924cd92098Szrj size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 5934cd92098Szrj num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 5944cd92098Szrj r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); 5954cd92098Szrj if (r) { 5964cd92098Szrj DRM_ERROR("radeon: moving bo (%d).\n", r); 5977dcf36dcSFrançois Tigeot radeon_sync_free(rdev, &sync, NULL); 5981cfef1a5SFrançois Tigeot return ERR_PTR(r); 5994cd92098Szrj } 6004cd92098Szrj 6017dcf36dcSFrançois Tigeot radeon_sync_resv(rdev, &sync, resv, false); 6027dcf36dcSFrançois Tigeot radeon_sync_rings(rdev, &sync, ring->idx); 6034cd92098Szrj 6044cd92098Szrj for (i = 0; i < num_loops; i++) { 6054cd92098Szrj cur_size_in_bytes = size_in_bytes; 6064cd92098Szrj if (cur_size_in_bytes > 0x1fffff) 6074cd92098Szrj cur_size_in_bytes = 0x1fffff; 6084cd92098Szrj size_in_bytes -= cur_size_in_bytes; 6094cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 6104cd92098Szrj radeon_ring_write(ring, cur_size_in_bytes); 6114cd92098Szrj radeon_ring_write(ring, 0); /* src/dst endian swap */ 612c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(src_offset)); 613c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(src_offset)); 614c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(dst_offset)); 615c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(dst_offset)); 6164cd92098Szrj src_offset += cur_size_in_bytes; 6174cd92098Szrj dst_offset += cur_size_in_bytes; 6184cd92098Szrj } 6194cd92098Szrj 6201cfef1a5SFrançois Tigeot r = radeon_fence_emit(rdev, &fence, ring->idx); 6214cd92098Szrj if (r) { 6224cd92098Szrj radeon_ring_unlock_undo(rdev, ring); 6237dcf36dcSFrançois Tigeot radeon_sync_free(rdev, &sync, NULL); 6241cfef1a5SFrançois Tigeot return ERR_PTR(r); 6254cd92098Szrj } 6264cd92098Szrj 627c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false); 6287dcf36dcSFrançois Tigeot radeon_sync_free(rdev, &sync, fence); 6294cd92098Szrj 6301cfef1a5SFrançois Tigeot return fence; 6314cd92098Szrj } 6324cd92098Szrj 6334cd92098Szrj /** 6344cd92098Szrj * cik_sdma_ring_test - simple async dma engine test 6354cd92098Szrj * 6364cd92098Szrj * @rdev: radeon_device pointer 6374cd92098Szrj * @ring: radeon_ring structure holding ring information 6384cd92098Szrj * 6394cd92098Szrj * Test the DMA engine by writing using it to write an 6404cd92098Szrj * value to memory. (CIK). 6414cd92098Szrj * Returns 0 for success, error for failure. 6424cd92098Szrj */ 6434cd92098Szrj int cik_sdma_ring_test(struct radeon_device *rdev, 6444cd92098Szrj struct radeon_ring *ring) 6454cd92098Szrj { 6464cd92098Szrj unsigned i; 6474cd92098Szrj int r; 648591d5043SFrançois Tigeot unsigned index; 6494cd92098Szrj u32 tmp; 650591d5043SFrançois Tigeot u64 gpu_addr; 6514cd92098Szrj 652591d5043SFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 653591d5043SFrançois Tigeot index = R600_WB_DMA_RING_TEST_OFFSET; 654591d5043SFrançois Tigeot else 655591d5043SFrançois Tigeot index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 656591d5043SFrançois Tigeot 657591d5043SFrançois Tigeot gpu_addr = rdev->wb.gpu_addr + index; 6584cd92098Szrj 6594cd92098Szrj tmp = 0xCAFEDEAD; 660591d5043SFrançois Tigeot rdev->wb.wb[index/4] = cpu_to_le32(tmp); 6614cd92098Szrj 662c6f73aabSFrançois Tigeot r = radeon_ring_lock(rdev, ring, 5); 6634cd92098Szrj if (r) { 6644cd92098Szrj DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 6654cd92098Szrj return r; 6664cd92098Szrj } 6674cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 668591d5043SFrançois Tigeot radeon_ring_write(ring, lower_32_bits(gpu_addr)); 669591d5043SFrançois Tigeot radeon_ring_write(ring, upper_32_bits(gpu_addr)); 6704cd92098Szrj radeon_ring_write(ring, 1); /* number of DWs to follow */ 6714cd92098Szrj radeon_ring_write(ring, 0xDEADBEEF); 672c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false); 6734cd92098Szrj 6744cd92098Szrj for (i = 0; i < rdev->usec_timeout; i++) { 675591d5043SFrançois Tigeot tmp = le32_to_cpu(rdev->wb.wb[index/4]); 6764cd92098Szrj if (tmp == 0xDEADBEEF) 6774cd92098Szrj break; 6784cd92098Szrj DRM_UDELAY(1); 6794cd92098Szrj } 6804cd92098Szrj 6814cd92098Szrj if (i < rdev->usec_timeout) { 6824cd92098Szrj DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 6834cd92098Szrj } else { 6844cd92098Szrj DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 6854cd92098Szrj ring->idx, tmp); 6864cd92098Szrj r = -EINVAL; 6874cd92098Szrj } 6884cd92098Szrj return r; 6894cd92098Szrj } 6904cd92098Szrj 6914cd92098Szrj /** 6924cd92098Szrj * cik_sdma_ib_test - test an IB on the DMA engine 6934cd92098Szrj * 6944cd92098Szrj * @rdev: radeon_device pointer 6954cd92098Szrj * @ring: radeon_ring structure holding ring information 6964cd92098Szrj * 6974cd92098Szrj * Test a simple IB in the DMA ring (CIK). 6984cd92098Szrj * Returns 0 on success, error on failure. 6994cd92098Szrj */ 7004cd92098Szrj int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 7014cd92098Szrj { 7024cd92098Szrj struct radeon_ib ib; 7034cd92098Szrj unsigned i; 704591d5043SFrançois Tigeot unsigned index; 7054cd92098Szrj int r; 7064cd92098Szrj u32 tmp = 0; 707591d5043SFrançois Tigeot u64 gpu_addr; 7084cd92098Szrj 709591d5043SFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 710591d5043SFrançois Tigeot index = R600_WB_DMA_RING_TEST_OFFSET; 711591d5043SFrançois Tigeot else 712591d5043SFrançois Tigeot index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 713591d5043SFrançois Tigeot 714591d5043SFrançois Tigeot gpu_addr = rdev->wb.gpu_addr + index; 7154cd92098Szrj 7164cd92098Szrj tmp = 0xCAFEDEAD; 717591d5043SFrançois Tigeot rdev->wb.wb[index/4] = cpu_to_le32(tmp); 7184cd92098Szrj 7194cd92098Szrj r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 7204cd92098Szrj if (r) { 7214cd92098Szrj DRM_ERROR("radeon: failed to get ib (%d).\n", r); 7224cd92098Szrj return r; 7234cd92098Szrj } 7244cd92098Szrj 7254cd92098Szrj ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 726591d5043SFrançois Tigeot ib.ptr[1] = lower_32_bits(gpu_addr); 727591d5043SFrançois Tigeot ib.ptr[2] = upper_32_bits(gpu_addr); 7284cd92098Szrj ib.ptr[3] = 1; 7294cd92098Szrj ib.ptr[4] = 0xDEADBEEF; 7304cd92098Szrj ib.length_dw = 5; 7314cd92098Szrj 732c6f73aabSFrançois Tigeot r = radeon_ib_schedule(rdev, &ib, NULL, false); 7334cd92098Szrj if (r) { 7344cd92098Szrj radeon_ib_free(rdev, &ib); 7354cd92098Szrj DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 7364cd92098Szrj return r; 7374cd92098Szrj } 738ee479021SImre Vadász r = radeon_fence_wait(ib.fence, false); 739ee479021SImre Vadász if (r) { 7404cd92098Szrj DRM_ERROR("radeon: fence wait failed (%d).\n", r); 7414cd92098Szrj return r; 7424cd92098Szrj } 7434cd92098Szrj for (i = 0; i < rdev->usec_timeout; i++) { 744591d5043SFrançois Tigeot tmp = le32_to_cpu(rdev->wb.wb[index/4]); 7454cd92098Szrj if (tmp == 0xDEADBEEF) 7464cd92098Szrj break; 7474cd92098Szrj DRM_UDELAY(1); 7484cd92098Szrj } 7494cd92098Szrj if (i < rdev->usec_timeout) { 7504cd92098Szrj DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 7514cd92098Szrj } else { 7524cd92098Szrj DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 7534cd92098Szrj r = -EINVAL; 7544cd92098Szrj } 7554cd92098Szrj radeon_ib_free(rdev, &ib); 7564cd92098Szrj return r; 7574cd92098Szrj } 7584cd92098Szrj 7594cd92098Szrj /** 7604cd92098Szrj * cik_sdma_is_lockup - Check if the DMA engine is locked up 7614cd92098Szrj * 7624cd92098Szrj * @rdev: radeon_device pointer 7634cd92098Szrj * @ring: radeon_ring structure holding ring information 7644cd92098Szrj * 7654cd92098Szrj * Check if the async DMA engine is locked up (CIK). 7664cd92098Szrj * Returns true if the engine appears to be locked up, false if not. 7674cd92098Szrj */ 7684cd92098Szrj bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 7694cd92098Szrj { 7704cd92098Szrj u32 reset_mask = cik_gpu_check_soft_reset(rdev); 7714cd92098Szrj u32 mask; 7724cd92098Szrj 7734cd92098Szrj if (ring->idx == R600_RING_TYPE_DMA_INDEX) 7744cd92098Szrj mask = RADEON_RESET_DMA; 7754cd92098Szrj else 7764cd92098Szrj mask = RADEON_RESET_DMA1; 7774cd92098Szrj 7784cd92098Szrj if (!(reset_mask & mask)) { 779c6f73aabSFrançois Tigeot radeon_ring_lockup_update(rdev, ring); 7804cd92098Szrj return false; 7814cd92098Szrj } 7824cd92098Szrj return radeon_ring_test_lockup(rdev, ring); 7834cd92098Szrj } 7844cd92098Szrj 7854cd92098Szrj /** 786c6f73aabSFrançois Tigeot * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 787c6f73aabSFrançois Tigeot * 788c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 789c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with commands 790c6f73aabSFrançois Tigeot * @pe: addr of the page entry 791c6f73aabSFrançois Tigeot * @src: src addr to copy from 792c6f73aabSFrançois Tigeot * @count: number of page entries to update 793c6f73aabSFrançois Tigeot * 794c6f73aabSFrançois Tigeot * Update PTEs by copying them from the GART using sDMA (CIK). 795c6f73aabSFrançois Tigeot */ 796c6f73aabSFrançois Tigeot void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 797c6f73aabSFrançois Tigeot struct radeon_ib *ib, 798c6f73aabSFrançois Tigeot uint64_t pe, uint64_t src, 799c6f73aabSFrançois Tigeot unsigned count) 800c6f73aabSFrançois Tigeot { 801c6f73aabSFrançois Tigeot while (count) { 802c6f73aabSFrançois Tigeot unsigned bytes = count * 8; 803c6f73aabSFrançois Tigeot if (bytes > 0x1FFFF8) 804c6f73aabSFrançois Tigeot bytes = 0x1FFFF8; 805c6f73aabSFrançois Tigeot 806c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 807c6f73aabSFrançois Tigeot SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 808c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = bytes; 809c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 810c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = lower_32_bits(src); 811c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(src); 812c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = lower_32_bits(pe); 813c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(pe); 814c6f73aabSFrançois Tigeot 815c6f73aabSFrançois Tigeot pe += bytes; 816c6f73aabSFrançois Tigeot src += bytes; 817c6f73aabSFrançois Tigeot count -= bytes / 8; 818c6f73aabSFrançois Tigeot } 819c6f73aabSFrançois Tigeot } 820c6f73aabSFrançois Tigeot 821c6f73aabSFrançois Tigeot /** 822c6f73aabSFrançois Tigeot * cik_sdma_vm_write_pages - update PTEs by writing them manually 823c6f73aabSFrançois Tigeot * 824c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 825c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with commands 826c6f73aabSFrançois Tigeot * @pe: addr of the page entry 827c6f73aabSFrançois Tigeot * @addr: dst addr to write into pe 828c6f73aabSFrançois Tigeot * @count: number of page entries to update 829c6f73aabSFrançois Tigeot * @incr: increase next addr by incr bytes 830c6f73aabSFrançois Tigeot * @flags: access flags 831c6f73aabSFrançois Tigeot * 832c6f73aabSFrançois Tigeot * Update PTEs by writing them manually using sDMA (CIK). 833c6f73aabSFrançois Tigeot */ 834c6f73aabSFrançois Tigeot void cik_sdma_vm_write_pages(struct radeon_device *rdev, 835c6f73aabSFrançois Tigeot struct radeon_ib *ib, 836c6f73aabSFrançois Tigeot uint64_t pe, 837c6f73aabSFrançois Tigeot uint64_t addr, unsigned count, 838c6f73aabSFrançois Tigeot uint32_t incr, uint32_t flags) 839c6f73aabSFrançois Tigeot { 840c6f73aabSFrançois Tigeot uint64_t value; 841c6f73aabSFrançois Tigeot unsigned ndw; 842c6f73aabSFrançois Tigeot 843c6f73aabSFrançois Tigeot while (count) { 844c6f73aabSFrançois Tigeot ndw = count * 2; 845c6f73aabSFrançois Tigeot if (ndw > 0xFFFFE) 846c6f73aabSFrançois Tigeot ndw = 0xFFFFE; 847c6f73aabSFrançois Tigeot 848c6f73aabSFrançois Tigeot /* for non-physically contiguous pages (system) */ 849c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 850c6f73aabSFrançois Tigeot SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 851c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = pe; 852c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(pe); 853c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = ndw; 854c6f73aabSFrançois Tigeot for (; ndw > 0; ndw -= 2, --count, pe += 8) { 855c6f73aabSFrançois Tigeot if (flags & R600_PTE_SYSTEM) { 856c6f73aabSFrançois Tigeot value = radeon_vm_map_gart(rdev, addr); 857c6f73aabSFrançois Tigeot } else if (flags & R600_PTE_VALID) { 858c6f73aabSFrançois Tigeot value = addr; 859c6f73aabSFrançois Tigeot } else { 860c6f73aabSFrançois Tigeot value = 0; 861c6f73aabSFrançois Tigeot } 862c6f73aabSFrançois Tigeot addr += incr; 863c6f73aabSFrançois Tigeot value |= flags; 864c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = value; 865c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(value); 866c6f73aabSFrançois Tigeot } 867c6f73aabSFrançois Tigeot } 868c6f73aabSFrançois Tigeot } 869c6f73aabSFrançois Tigeot 870c6f73aabSFrançois Tigeot /** 871c6f73aabSFrançois Tigeot * cik_sdma_vm_set_pages - update the page tables using sDMA 8724cd92098Szrj * 8734cd92098Szrj * @rdev: radeon_device pointer 8744cd92098Szrj * @ib: indirect buffer to fill with commands 8754cd92098Szrj * @pe: addr of the page entry 8764cd92098Szrj * @addr: dst addr to write into pe 8774cd92098Szrj * @count: number of page entries to update 8784cd92098Szrj * @incr: increase next addr by incr bytes 8794cd92098Szrj * @flags: access flags 8804cd92098Szrj * 8814cd92098Szrj * Update the page tables using sDMA (CIK). 8824cd92098Szrj */ 883c6f73aabSFrançois Tigeot void cik_sdma_vm_set_pages(struct radeon_device *rdev, 8844cd92098Szrj struct radeon_ib *ib, 8854cd92098Szrj uint64_t pe, 8864cd92098Szrj uint64_t addr, unsigned count, 8874cd92098Szrj uint32_t incr, uint32_t flags) 8884cd92098Szrj { 8894cd92098Szrj uint64_t value; 8904cd92098Szrj unsigned ndw; 8914cd92098Szrj 8924cd92098Szrj while (count) { 8934cd92098Szrj ndw = count; 8944cd92098Szrj if (ndw > 0x7FFFF) 8954cd92098Szrj ndw = 0x7FFFF; 8964cd92098Szrj 897c6f73aabSFrançois Tigeot if (flags & R600_PTE_VALID) 8984cd92098Szrj value = addr; 8994cd92098Szrj else 9004cd92098Szrj value = 0; 901c6f73aabSFrançois Tigeot 9024cd92098Szrj /* for physically contiguous pages (vram) */ 9034cd92098Szrj ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 9044cd92098Szrj ib->ptr[ib->length_dw++] = pe; /* dst addr */ 9054cd92098Szrj ib->ptr[ib->length_dw++] = upper_32_bits(pe); 906c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = flags; /* mask */ 9074cd92098Szrj ib->ptr[ib->length_dw++] = 0; 9084cd92098Szrj ib->ptr[ib->length_dw++] = value; /* value */ 9094cd92098Szrj ib->ptr[ib->length_dw++] = upper_32_bits(value); 9104cd92098Szrj ib->ptr[ib->length_dw++] = incr; /* increment size */ 9114cd92098Szrj ib->ptr[ib->length_dw++] = 0; 9124cd92098Szrj ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 913c6f73aabSFrançois Tigeot 9144cd92098Szrj pe += ndw * 8; 9154cd92098Szrj addr += ndw * incr; 9164cd92098Szrj count -= ndw; 9174cd92098Szrj } 9184cd92098Szrj } 919c6f73aabSFrançois Tigeot 920c6f73aabSFrançois Tigeot /** 921c6f73aabSFrançois Tigeot * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 922c6f73aabSFrançois Tigeot * 923c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with padding 924c6f73aabSFrançois Tigeot * 925c6f73aabSFrançois Tigeot */ 926c6f73aabSFrançois Tigeot void cik_sdma_vm_pad_ib(struct radeon_ib *ib) 927c6f73aabSFrançois Tigeot { 9284cd92098Szrj while (ib->length_dw & 0x7) 9294cd92098Szrj ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 9304cd92098Szrj } 9314cd92098Szrj 9324cd92098Szrj /** 9334cd92098Szrj * cik_dma_vm_flush - cik vm flush using sDMA 9344cd92098Szrj * 9354cd92098Szrj * @rdev: radeon_device pointer 9364cd92098Szrj * 9374cd92098Szrj * Update the page table base and flush the VM TLB 9384cd92098Szrj * using sDMA (CIK). 9394cd92098Szrj */ 9407dcf36dcSFrançois Tigeot void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 9417dcf36dcSFrançois Tigeot unsigned vm_id, uint64_t pd_addr) 9424cd92098Szrj { 9437dcf36dcSFrançois Tigeot u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 9447dcf36dcSFrançois Tigeot SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 9454cd92098Szrj 9464cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9477dcf36dcSFrançois Tigeot if (vm_id < 8) { 9487dcf36dcSFrançois Tigeot radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); 9494cd92098Szrj } else { 9507dcf36dcSFrançois Tigeot radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); 9514cd92098Szrj } 9527dcf36dcSFrançois Tigeot radeon_ring_write(ring, pd_addr >> 12); 9534cd92098Szrj 9544cd92098Szrj /* update SH_MEM_* regs */ 9554cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9564cd92098Szrj radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9577dcf36dcSFrançois Tigeot radeon_ring_write(ring, VMID(vm_id)); 9584cd92098Szrj 9594cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9604cd92098Szrj radeon_ring_write(ring, SH_MEM_BASES >> 2); 9614cd92098Szrj radeon_ring_write(ring, 0); 9624cd92098Szrj 9634cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9644cd92098Szrj radeon_ring_write(ring, SH_MEM_CONFIG >> 2); 9654cd92098Szrj radeon_ring_write(ring, 0); 9664cd92098Szrj 9674cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9684cd92098Szrj radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); 9694cd92098Szrj radeon_ring_write(ring, 1); 9704cd92098Szrj 9714cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9724cd92098Szrj radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); 9734cd92098Szrj radeon_ring_write(ring, 0); 9744cd92098Szrj 9754cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9764cd92098Szrj radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9774cd92098Szrj radeon_ring_write(ring, VMID(0)); 9784cd92098Szrj 9794cd92098Szrj /* flush HDP */ 9807dcf36dcSFrançois Tigeot cik_sdma_hdp_flush_ring_emit(rdev, ring->idx); 9814cd92098Szrj 9824cd92098Szrj /* flush TLB */ 9834cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9844cd92098Szrj radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 9857dcf36dcSFrançois Tigeot radeon_ring_write(ring, 1 << vm_id); 9867dcf36dcSFrançois Tigeot 9877dcf36dcSFrançois Tigeot radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 9887dcf36dcSFrançois Tigeot radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 9897dcf36dcSFrançois Tigeot radeon_ring_write(ring, 0); 9907dcf36dcSFrançois Tigeot radeon_ring_write(ring, 0); /* reference */ 9917dcf36dcSFrançois Tigeot radeon_ring_write(ring, 0); /* mask */ 9927dcf36dcSFrançois Tigeot radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 9934cd92098Szrj } 994*c59a5c48SFrançois Tigeot 995