14cd92098Szrj /* 24cd92098Szrj * Copyright 2013 Advanced Micro Devices, Inc. 34cd92098Szrj * 44cd92098Szrj * Permission is hereby granted, free of charge, to any person obtaining a 54cd92098Szrj * copy of this software and associated documentation files (the "Software"), 64cd92098Szrj * to deal in the Software without restriction, including without limitation 74cd92098Szrj * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84cd92098Szrj * and/or sell copies of the Software, and to permit persons to whom the 94cd92098Szrj * Software is furnished to do so, subject to the following conditions: 104cd92098Szrj * 114cd92098Szrj * The above copyright notice and this permission notice shall be included in 124cd92098Szrj * all copies or substantial portions of the Software. 134cd92098Szrj * 144cd92098Szrj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154cd92098Szrj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164cd92098Szrj * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174cd92098Szrj * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184cd92098Szrj * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194cd92098Szrj * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204cd92098Szrj * OTHER DEALINGS IN THE SOFTWARE. 214cd92098Szrj * 224cd92098Szrj * Authors: Alex Deucher 234cd92098Szrj */ 244cd92098Szrj #include <linux/firmware.h> 254cd92098Szrj #include <drm/drmP.h> 264cd92098Szrj #include "radeon.h" 27*cb754608SImre Vadász #include "radeon_ucode.h" 284cd92098Szrj #include "radeon_asic.h" 29c6f73aabSFrançois Tigeot #ifdef TRACE_TODO 30c6f73aabSFrançois Tigeot #include "radeon_trace.h" 31c6f73aabSFrançois Tigeot #endif 324cd92098Szrj #include "cikd.h" 334cd92098Szrj 344cd92098Szrj /* sdma */ 354cd92098Szrj #define CIK_SDMA_UCODE_SIZE 1050 364cd92098Szrj #define CIK_SDMA_UCODE_VERSION 64 374cd92098Szrj 384cd92098Szrj /* 394cd92098Szrj * sDMA - System DMA 404cd92098Szrj * Starting with CIK, the GPU has new asynchronous 414cd92098Szrj * DMA engines. These engines are used for compute 424cd92098Szrj * and gfx. There are two DMA engines (SDMA0, SDMA1) 434cd92098Szrj * and each one supports 1 ring buffer used for gfx 444cd92098Szrj * and 2 queues used for compute. 454cd92098Szrj * 464cd92098Szrj * The programming model is very similar to the CP 474cd92098Szrj * (ring buffer, IBs, etc.), but sDMA has it's own 484cd92098Szrj * packet format that is different from the PM4 format 494cd92098Szrj * used by the CP. sDMA supports copying data, writing 504cd92098Szrj * embedded data, solid fills, and a number of other 514cd92098Szrj * things. It also has support for tiling/detiling of 524cd92098Szrj * buffers. 534cd92098Szrj */ 544cd92098Szrj 554cd92098Szrj /** 56c6f73aabSFrançois Tigeot * cik_sdma_get_rptr - get the current read pointer 57c6f73aabSFrançois Tigeot * 58c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 59c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 60c6f73aabSFrançois Tigeot * 61c6f73aabSFrançois Tigeot * Get the current rptr from the hardware (CIK+). 62c6f73aabSFrançois Tigeot */ 63c6f73aabSFrançois Tigeot uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, 64c6f73aabSFrançois Tigeot struct radeon_ring *ring) 65c6f73aabSFrançois Tigeot { 66c6f73aabSFrançois Tigeot u32 rptr, reg; 67c6f73aabSFrançois Tigeot 68c6f73aabSFrançois Tigeot if (rdev->wb.enabled) { 69c6f73aabSFrançois Tigeot rptr = rdev->wb.wb[ring->rptr_offs/4]; 70c6f73aabSFrançois Tigeot } else { 71c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 72c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; 73c6f73aabSFrançois Tigeot else 74c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; 75c6f73aabSFrançois Tigeot 76c6f73aabSFrançois Tigeot rptr = RREG32(reg); 77c6f73aabSFrançois Tigeot } 78c6f73aabSFrançois Tigeot 79c6f73aabSFrançois Tigeot return (rptr & 0x3fffc) >> 2; 80c6f73aabSFrançois Tigeot } 81c6f73aabSFrançois Tigeot 82c6f73aabSFrançois Tigeot /** 83c6f73aabSFrançois Tigeot * cik_sdma_get_wptr - get the current write pointer 84c6f73aabSFrançois Tigeot * 85c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 86c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 87c6f73aabSFrançois Tigeot * 88c6f73aabSFrançois Tigeot * Get the current wptr from the hardware (CIK+). 89c6f73aabSFrançois Tigeot */ 90c6f73aabSFrançois Tigeot uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, 91c6f73aabSFrançois Tigeot struct radeon_ring *ring) 92c6f73aabSFrançois Tigeot { 93c6f73aabSFrançois Tigeot u32 reg; 94c6f73aabSFrançois Tigeot 95c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 96c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 97c6f73aabSFrançois Tigeot else 98c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 99c6f73aabSFrançois Tigeot 100c6f73aabSFrançois Tigeot return (RREG32(reg) & 0x3fffc) >> 2; 101c6f73aabSFrançois Tigeot } 102c6f73aabSFrançois Tigeot 103c6f73aabSFrançois Tigeot /** 104c6f73aabSFrançois Tigeot * cik_sdma_set_wptr - commit the write pointer 105c6f73aabSFrançois Tigeot * 106c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 107c6f73aabSFrançois Tigeot * @ring: radeon ring pointer 108c6f73aabSFrançois Tigeot * 109c6f73aabSFrançois Tigeot * Write the wptr back to the hardware (CIK+). 110c6f73aabSFrançois Tigeot */ 111c6f73aabSFrançois Tigeot void cik_sdma_set_wptr(struct radeon_device *rdev, 112c6f73aabSFrançois Tigeot struct radeon_ring *ring) 113c6f73aabSFrançois Tigeot { 114c6f73aabSFrançois Tigeot u32 reg; 115c6f73aabSFrançois Tigeot 116c6f73aabSFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 117c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 118c6f73aabSFrançois Tigeot else 119c6f73aabSFrançois Tigeot reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 120c6f73aabSFrançois Tigeot 121c6f73aabSFrançois Tigeot WREG32(reg, (ring->wptr << 2) & 0x3fffc); 122c6f73aabSFrançois Tigeot (void)RREG32(reg); 123c6f73aabSFrançois Tigeot } 124c6f73aabSFrançois Tigeot 125c6f73aabSFrançois Tigeot /** 1264cd92098Szrj * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 1274cd92098Szrj * 1284cd92098Szrj * @rdev: radeon_device pointer 1294cd92098Szrj * @ib: IB object to schedule 1304cd92098Szrj * 1314cd92098Szrj * Schedule an IB in the DMA ring (CIK). 1324cd92098Szrj */ 1334cd92098Szrj void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 1344cd92098Szrj struct radeon_ib *ib) 1354cd92098Szrj { 1364cd92098Szrj struct radeon_ring *ring = &rdev->ring[ib->ring]; 1374cd92098Szrj u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; 1384cd92098Szrj 1394cd92098Szrj if (rdev->wb.enabled) { 1404cd92098Szrj u32 next_rptr = ring->wptr + 5; 1414cd92098Szrj while ((next_rptr & 7) != 4) 1424cd92098Szrj next_rptr++; 1434cd92098Szrj next_rptr += 4; 1444cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 1454cd92098Szrj radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 146c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 1474cd92098Szrj radeon_ring_write(ring, 1); /* number of DWs to follow */ 1484cd92098Szrj radeon_ring_write(ring, next_rptr); 1494cd92098Szrj } 1504cd92098Szrj 1514cd92098Szrj /* IB packet must end on a 8 DW boundary */ 1524cd92098Szrj while ((ring->wptr & 7) != 4) 1534cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 1544cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 1554cd92098Szrj radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 156c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1574cd92098Szrj radeon_ring_write(ring, ib->length_dw); 1584cd92098Szrj 1594cd92098Szrj } 1604cd92098Szrj 1614cd92098Szrj /** 162c6f73aabSFrançois Tigeot * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 163c6f73aabSFrançois Tigeot * 164c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 165c6f73aabSFrançois Tigeot * @ridx: radeon ring index 166c6f73aabSFrançois Tigeot * 167c6f73aabSFrançois Tigeot * Emit an hdp flush packet on the requested DMA ring. 168c6f73aabSFrançois Tigeot */ 169c6f73aabSFrançois Tigeot static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, 170c6f73aabSFrançois Tigeot int ridx) 171c6f73aabSFrançois Tigeot { 172c6f73aabSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[ridx]; 173c6f73aabSFrançois Tigeot u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 174c6f73aabSFrançois Tigeot SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 175c6f73aabSFrançois Tigeot u32 ref_and_mask; 176c6f73aabSFrançois Tigeot 177c6f73aabSFrançois Tigeot if (ridx == R600_RING_TYPE_DMA_INDEX) 178c6f73aabSFrançois Tigeot ref_and_mask = SDMA0; 179c6f73aabSFrançois Tigeot else 180c6f73aabSFrançois Tigeot ref_and_mask = SDMA1; 181c6f73aabSFrançois Tigeot 182c6f73aabSFrançois Tigeot radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 183c6f73aabSFrançois Tigeot radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 184c6f73aabSFrançois Tigeot radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 185c6f73aabSFrançois Tigeot radeon_ring_write(ring, ref_and_mask); /* reference */ 186c6f73aabSFrançois Tigeot radeon_ring_write(ring, ref_and_mask); /* mask */ 187c6f73aabSFrançois Tigeot radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 188c6f73aabSFrançois Tigeot } 189c6f73aabSFrançois Tigeot 190c6f73aabSFrançois Tigeot /** 1914cd92098Szrj * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 1924cd92098Szrj * 1934cd92098Szrj * @rdev: radeon_device pointer 1944cd92098Szrj * @fence: radeon fence object 1954cd92098Szrj * 1964cd92098Szrj * Add a DMA fence packet to the ring to write 1974cd92098Szrj * the fence seq number and DMA trap packet to generate 1984cd92098Szrj * an interrupt if needed (CIK). 1994cd92098Szrj */ 2004cd92098Szrj void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 2014cd92098Szrj struct radeon_fence *fence) 2024cd92098Szrj { 2034cd92098Szrj struct radeon_ring *ring = &rdev->ring[fence->ring]; 2044cd92098Szrj u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2054cd92098Szrj 2064cd92098Szrj /* write the fence */ 2074cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 208c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(addr)); 209c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(addr)); 2104cd92098Szrj radeon_ring_write(ring, fence->seq); 2114cd92098Szrj /* generate an interrupt */ 2124cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 2134cd92098Szrj /* flush HDP */ 214c6f73aabSFrançois Tigeot cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); 2154cd92098Szrj } 2164cd92098Szrj 2174cd92098Szrj /** 2184cd92098Szrj * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring 2194cd92098Szrj * 2204cd92098Szrj * @rdev: radeon_device pointer 2214cd92098Szrj * @ring: radeon_ring structure holding ring information 2224cd92098Szrj * @semaphore: radeon semaphore object 2234cd92098Szrj * @emit_wait: wait or signal semaphore 2244cd92098Szrj * 2254cd92098Szrj * Add a DMA semaphore packet to the ring wait on or signal 2264cd92098Szrj * other rings (CIK). 2274cd92098Szrj */ 228c6f73aabSFrançois Tigeot bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 2294cd92098Szrj struct radeon_ring *ring, 2304cd92098Szrj struct radeon_semaphore *semaphore, 2314cd92098Szrj bool emit_wait) 2324cd92098Szrj { 2334cd92098Szrj u64 addr = semaphore->gpu_addr; 2344cd92098Szrj u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; 2354cd92098Szrj 2364cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 2374cd92098Szrj radeon_ring_write(ring, addr & 0xfffffff8); 238c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(addr)); 239c6f73aabSFrançois Tigeot 240c6f73aabSFrançois Tigeot return true; 2414cd92098Szrj } 2424cd92098Szrj 2434cd92098Szrj /** 2444cd92098Szrj * cik_sdma_gfx_stop - stop the gfx async dma engines 2454cd92098Szrj * 2464cd92098Szrj * @rdev: radeon_device pointer 2474cd92098Szrj * 2484cd92098Szrj * Stop the gfx async dma ring buffers (CIK). 2494cd92098Szrj */ 2504cd92098Szrj static void cik_sdma_gfx_stop(struct radeon_device *rdev) 2514cd92098Szrj { 2524cd92098Szrj u32 rb_cntl, reg_offset; 2534cd92098Szrj int i; 2544cd92098Szrj 255c6f73aabSFrançois Tigeot if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 256c6f73aabSFrançois Tigeot (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 2574cd92098Szrj radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2584cd92098Szrj 2594cd92098Szrj for (i = 0; i < 2; i++) { 2604cd92098Szrj if (i == 0) 2614cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 2624cd92098Szrj else 2634cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 2644cd92098Szrj rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); 2654cd92098Szrj rb_cntl &= ~SDMA_RB_ENABLE; 2664cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 2674cd92098Szrj WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); 2684cd92098Szrj } 269c6f73aabSFrançois Tigeot rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 270c6f73aabSFrançois Tigeot rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; 2714cd92098Szrj } 2724cd92098Szrj 2734cd92098Szrj /** 2744cd92098Szrj * cik_sdma_rlc_stop - stop the compute async dma engines 2754cd92098Szrj * 2764cd92098Szrj * @rdev: radeon_device pointer 2774cd92098Szrj * 2784cd92098Szrj * Stop the compute async dma queues (CIK). 2794cd92098Szrj */ 2804cd92098Szrj static void cik_sdma_rlc_stop(struct radeon_device *rdev) 2814cd92098Szrj { 2824cd92098Szrj /* XXX todo */ 2834cd92098Szrj } 2844cd92098Szrj 2854cd92098Szrj /** 2864cd92098Szrj * cik_sdma_enable - stop the async dma engines 2874cd92098Szrj * 2884cd92098Szrj * @rdev: radeon_device pointer 2894cd92098Szrj * @enable: enable/disable the DMA MEs. 2904cd92098Szrj * 2914cd92098Szrj * Halt or unhalt the async dma engines (CIK). 2924cd92098Szrj */ 2934cd92098Szrj void cik_sdma_enable(struct radeon_device *rdev, bool enable) 2944cd92098Szrj { 2954cd92098Szrj u32 me_cntl, reg_offset; 2964cd92098Szrj int i; 2974cd92098Szrj 298c6f73aabSFrançois Tigeot if (enable == false) { 299c6f73aabSFrançois Tigeot cik_sdma_gfx_stop(rdev); 300c6f73aabSFrançois Tigeot cik_sdma_rlc_stop(rdev); 301c6f73aabSFrançois Tigeot } 302c6f73aabSFrançois Tigeot 3034cd92098Szrj for (i = 0; i < 2; i++) { 3044cd92098Szrj if (i == 0) 3054cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 3064cd92098Szrj else 3074cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 3084cd92098Szrj me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); 3094cd92098Szrj if (enable) 3104cd92098Szrj me_cntl &= ~SDMA_HALT; 3114cd92098Szrj else 3124cd92098Szrj me_cntl |= SDMA_HALT; 3134cd92098Szrj WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); 3144cd92098Szrj } 3154cd92098Szrj } 3164cd92098Szrj 3174cd92098Szrj /** 3184cd92098Szrj * cik_sdma_gfx_resume - setup and start the async dma engines 3194cd92098Szrj * 3204cd92098Szrj * @rdev: radeon_device pointer 3214cd92098Szrj * 3224cd92098Szrj * Set up the gfx DMA ring buffers and enable them (CIK). 3234cd92098Szrj * Returns 0 for success, error for failure. 3244cd92098Szrj */ 3254cd92098Szrj static int cik_sdma_gfx_resume(struct radeon_device *rdev) 3264cd92098Szrj { 3274cd92098Szrj struct radeon_ring *ring; 3284cd92098Szrj u32 rb_cntl, ib_cntl; 3294cd92098Szrj u32 rb_bufsz; 3304cd92098Szrj u32 reg_offset, wb_offset; 3314cd92098Szrj int i, r; 3324cd92098Szrj 3334cd92098Szrj for (i = 0; i < 2; i++) { 3344cd92098Szrj if (i == 0) { 3354cd92098Szrj ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3364cd92098Szrj reg_offset = SDMA0_REGISTER_OFFSET; 3374cd92098Szrj wb_offset = R600_WB_DMA_RPTR_OFFSET; 3384cd92098Szrj } else { 3394cd92098Szrj ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 3404cd92098Szrj reg_offset = SDMA1_REGISTER_OFFSET; 3414cd92098Szrj wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; 3424cd92098Szrj } 3434cd92098Szrj 3444cd92098Szrj WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 3454cd92098Szrj WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 3464cd92098Szrj 3474cd92098Szrj /* Set ring buffer size in dwords */ 3484cd92098Szrj rb_bufsz = order_base_2(ring->ring_size / 4); 3494cd92098Szrj rb_cntl = rb_bufsz << 1; 3504cd92098Szrj #ifdef __BIG_ENDIAN 3514cd92098Szrj rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 3524cd92098Szrj #endif 3534cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 3544cd92098Szrj 3554cd92098Szrj /* Initialize the ring buffer's read and write pointers */ 3564cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); 3574cd92098Szrj WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); 3584cd92098Szrj 3594cd92098Szrj /* set the wb address whether it's enabled or not */ 3604cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, 3614cd92098Szrj upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 3624cd92098Szrj WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, 3634cd92098Szrj ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 3644cd92098Szrj 3654cd92098Szrj if (rdev->wb.enabled) 3664cd92098Szrj rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; 3674cd92098Szrj 3684cd92098Szrj WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 3694cd92098Szrj WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 3704cd92098Szrj 3714cd92098Szrj ring->wptr = 0; 3724cd92098Szrj WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); 3734cd92098Szrj 3744cd92098Szrj /* enable DMA RB */ 3754cd92098Szrj WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); 3764cd92098Szrj 3774cd92098Szrj ib_cntl = SDMA_IB_ENABLE; 3784cd92098Szrj #ifdef __BIG_ENDIAN 3794cd92098Szrj ib_cntl |= SDMA_IB_SWAP_ENABLE; 3804cd92098Szrj #endif 3814cd92098Szrj /* enable DMA IBs */ 3824cd92098Szrj WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); 3834cd92098Szrj 3844cd92098Szrj ring->ready = true; 3854cd92098Szrj 3864cd92098Szrj r = radeon_ring_test(rdev, ring->idx, ring); 3874cd92098Szrj if (r) { 3884cd92098Szrj ring->ready = false; 3894cd92098Szrj return r; 3904cd92098Szrj } 3914cd92098Szrj } 3924cd92098Szrj 393c6f73aabSFrançois Tigeot if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 394c6f73aabSFrançois Tigeot (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 3954cd92098Szrj radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 3964cd92098Szrj 3974cd92098Szrj return 0; 3984cd92098Szrj } 3994cd92098Szrj 4004cd92098Szrj /** 4014cd92098Szrj * cik_sdma_rlc_resume - setup and start the async dma engines 4024cd92098Szrj * 4034cd92098Szrj * @rdev: radeon_device pointer 4044cd92098Szrj * 4054cd92098Szrj * Set up the compute DMA queues and enable them (CIK). 4064cd92098Szrj * Returns 0 for success, error for failure. 4074cd92098Szrj */ 4084cd92098Szrj static int cik_sdma_rlc_resume(struct radeon_device *rdev) 4094cd92098Szrj { 4104cd92098Szrj /* XXX todo */ 4114cd92098Szrj return 0; 4124cd92098Szrj } 4134cd92098Szrj 4144cd92098Szrj /** 4154cd92098Szrj * cik_sdma_load_microcode - load the sDMA ME ucode 4164cd92098Szrj * 4174cd92098Szrj * @rdev: radeon_device pointer 4184cd92098Szrj * 4194cd92098Szrj * Loads the sDMA0/1 ucode. 4204cd92098Szrj * Returns 0 for success, -EINVAL if the ucode is not available. 4214cd92098Szrj */ 4224cd92098Szrj static int cik_sdma_load_microcode(struct radeon_device *rdev) 4234cd92098Szrj { 4244cd92098Szrj int i; 4254cd92098Szrj 4264cd92098Szrj if (!rdev->sdma_fw) 4274cd92098Szrj return -EINVAL; 4284cd92098Szrj 4294cd92098Szrj /* halt the MEs */ 4304cd92098Szrj cik_sdma_enable(rdev, false); 4314cd92098Szrj 432*cb754608SImre Vadász if (rdev->new_fw) { 433*cb754608SImre Vadász const struct sdma_firmware_header_v1_0 *hdr = 434*cb754608SImre Vadász (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; 435*cb754608SImre Vadász const __le32 *fw_data; 436*cb754608SImre Vadász u32 fw_size; 437*cb754608SImre Vadász 438*cb754608SImre Vadász radeon_ucode_print_sdma_hdr(&hdr->header); 439*cb754608SImre Vadász 440*cb754608SImre Vadász /* sdma0 */ 441*cb754608SImre Vadász fw_data = (const __le32 *) 442*cb754608SImre Vadász ((const char *)rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 443*cb754608SImre Vadász fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 444*cb754608SImre Vadász WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 445*cb754608SImre Vadász for (i = 0; i < fw_size; i++) 446*cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 447*cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 448*cb754608SImre Vadász 449*cb754608SImre Vadász /* sdma1 */ 450*cb754608SImre Vadász fw_data = (const __le32 *) 451*cb754608SImre Vadász ((const char *)rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 452*cb754608SImre Vadász fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 453*cb754608SImre Vadász WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 454*cb754608SImre Vadász for (i = 0; i < fw_size; i++) 455*cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 456*cb754608SImre Vadász WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 457*cb754608SImre Vadász } else { 458*cb754608SImre Vadász const __be32 *fw_data; 459*cb754608SImre Vadász 4604cd92098Szrj /* sdma0 */ 4614cd92098Szrj fw_data = (const __be32 *)rdev->sdma_fw->data; 4624cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 4634cd92098Szrj for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 4644cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 4654cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 4664cd92098Szrj 4674cd92098Szrj /* sdma1 */ 4684cd92098Szrj fw_data = (const __be32 *)rdev->sdma_fw->data; 4694cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 4704cd92098Szrj for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 4714cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 4724cd92098Szrj WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 473*cb754608SImre Vadász } 4744cd92098Szrj 4754cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 4764cd92098Szrj WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 4774cd92098Szrj return 0; 4784cd92098Szrj } 4794cd92098Szrj 4804cd92098Szrj /** 4814cd92098Szrj * cik_sdma_resume - setup and start the async dma engines 4824cd92098Szrj * 4834cd92098Szrj * @rdev: radeon_device pointer 4844cd92098Szrj * 4854cd92098Szrj * Set up the DMA engines and enable them (CIK). 4864cd92098Szrj * Returns 0 for success, error for failure. 4874cd92098Szrj */ 4884cd92098Szrj int cik_sdma_resume(struct radeon_device *rdev) 4894cd92098Szrj { 4904cd92098Szrj int r; 4914cd92098Szrj 4924cd92098Szrj r = cik_sdma_load_microcode(rdev); 4934cd92098Szrj if (r) 4944cd92098Szrj return r; 4954cd92098Szrj 4964cd92098Szrj /* unhalt the MEs */ 4974cd92098Szrj cik_sdma_enable(rdev, true); 4984cd92098Szrj 4994cd92098Szrj /* start the gfx rings and rlc compute queues */ 5004cd92098Szrj r = cik_sdma_gfx_resume(rdev); 5014cd92098Szrj if (r) 5024cd92098Szrj return r; 5034cd92098Szrj r = cik_sdma_rlc_resume(rdev); 5044cd92098Szrj if (r) 5054cd92098Szrj return r; 5064cd92098Szrj 5074cd92098Szrj return 0; 5084cd92098Szrj } 5094cd92098Szrj 5104cd92098Szrj /** 5114cd92098Szrj * cik_sdma_fini - tear down the async dma engines 5124cd92098Szrj * 5134cd92098Szrj * @rdev: radeon_device pointer 5144cd92098Szrj * 5154cd92098Szrj * Stop the async dma engines and free the rings (CIK). 5164cd92098Szrj */ 5174cd92098Szrj void cik_sdma_fini(struct radeon_device *rdev) 5184cd92098Szrj { 5194cd92098Szrj /* halt the MEs */ 5204cd92098Szrj cik_sdma_enable(rdev, false); 5214cd92098Szrj radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 5224cd92098Szrj radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 5234cd92098Szrj /* XXX - compute dma queue tear down */ 5244cd92098Szrj } 5254cd92098Szrj 5264cd92098Szrj /** 5274cd92098Szrj * cik_copy_dma - copy pages using the DMA engine 5284cd92098Szrj * 5294cd92098Szrj * @rdev: radeon_device pointer 5304cd92098Szrj * @src_offset: src GPU address 5314cd92098Szrj * @dst_offset: dst GPU address 5324cd92098Szrj * @num_gpu_pages: number of GPU pages to xfer 5334cd92098Szrj * @fence: radeon fence object 5344cd92098Szrj * 5354cd92098Szrj * Copy GPU paging using the DMA engine (CIK). 5364cd92098Szrj * Used by the radeon ttm implementation to move pages if 5374cd92098Szrj * registered as the asic copy callback. 5384cd92098Szrj */ 5394cd92098Szrj int cik_copy_dma(struct radeon_device *rdev, 5404cd92098Szrj uint64_t src_offset, uint64_t dst_offset, 5414cd92098Szrj unsigned num_gpu_pages, 5424cd92098Szrj struct radeon_fence **fence) 5434cd92098Szrj { 5444cd92098Szrj struct radeon_semaphore *sem = NULL; 5454cd92098Szrj int ring_index = rdev->asic->copy.dma_ring_index; 5464cd92098Szrj struct radeon_ring *ring = &rdev->ring[ring_index]; 5474cd92098Szrj u32 size_in_bytes, cur_size_in_bytes; 5484cd92098Szrj int i, num_loops; 5494cd92098Szrj int r = 0; 5504cd92098Szrj 5514cd92098Szrj r = radeon_semaphore_create(rdev, &sem); 5524cd92098Szrj if (r) { 5534cd92098Szrj DRM_ERROR("radeon: moving bo (%d).\n", r); 5544cd92098Szrj return r; 5554cd92098Szrj } 5564cd92098Szrj 5574cd92098Szrj size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 5584cd92098Szrj num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 5594cd92098Szrj r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); 5604cd92098Szrj if (r) { 5614cd92098Szrj DRM_ERROR("radeon: moving bo (%d).\n", r); 5624cd92098Szrj radeon_semaphore_free(rdev, &sem, NULL); 5634cd92098Szrj return r; 5644cd92098Szrj } 5654cd92098Szrj 566c6f73aabSFrançois Tigeot radeon_semaphore_sync_to(sem, *fence); 567c6f73aabSFrançois Tigeot radeon_semaphore_sync_rings(rdev, sem, ring->idx); 5684cd92098Szrj 5694cd92098Szrj for (i = 0; i < num_loops; i++) { 5704cd92098Szrj cur_size_in_bytes = size_in_bytes; 5714cd92098Szrj if (cur_size_in_bytes > 0x1fffff) 5724cd92098Szrj cur_size_in_bytes = 0x1fffff; 5734cd92098Szrj size_in_bytes -= cur_size_in_bytes; 5744cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 5754cd92098Szrj radeon_ring_write(ring, cur_size_in_bytes); 5764cd92098Szrj radeon_ring_write(ring, 0); /* src/dst endian swap */ 577c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(src_offset)); 578c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(src_offset)); 579c6f73aabSFrançois Tigeot radeon_ring_write(ring, lower_32_bits(dst_offset)); 580c6f73aabSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(dst_offset)); 5814cd92098Szrj src_offset += cur_size_in_bytes; 5824cd92098Szrj dst_offset += cur_size_in_bytes; 5834cd92098Szrj } 5844cd92098Szrj 5854cd92098Szrj r = radeon_fence_emit(rdev, fence, ring->idx); 5864cd92098Szrj if (r) { 5874cd92098Szrj radeon_ring_unlock_undo(rdev, ring); 588c6f73aabSFrançois Tigeot radeon_semaphore_free(rdev, &sem, NULL); 5894cd92098Szrj return r; 5904cd92098Szrj } 5914cd92098Szrj 592c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false); 5934cd92098Szrj radeon_semaphore_free(rdev, &sem, *fence); 5944cd92098Szrj 5954cd92098Szrj return r; 5964cd92098Szrj } 5974cd92098Szrj 5984cd92098Szrj /** 5994cd92098Szrj * cik_sdma_ring_test - simple async dma engine test 6004cd92098Szrj * 6014cd92098Szrj * @rdev: radeon_device pointer 6024cd92098Szrj * @ring: radeon_ring structure holding ring information 6034cd92098Szrj * 6044cd92098Szrj * Test the DMA engine by writing using it to write an 6054cd92098Szrj * value to memory. (CIK). 6064cd92098Szrj * Returns 0 for success, error for failure. 6074cd92098Szrj */ 6084cd92098Szrj int cik_sdma_ring_test(struct radeon_device *rdev, 6094cd92098Szrj struct radeon_ring *ring) 6104cd92098Szrj { 6114cd92098Szrj unsigned i; 6124cd92098Szrj int r; 613591d5043SFrançois Tigeot unsigned index; 6144cd92098Szrj u32 tmp; 615591d5043SFrançois Tigeot u64 gpu_addr; 6164cd92098Szrj 617591d5043SFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 618591d5043SFrançois Tigeot index = R600_WB_DMA_RING_TEST_OFFSET; 619591d5043SFrançois Tigeot else 620591d5043SFrançois Tigeot index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 621591d5043SFrançois Tigeot 622591d5043SFrançois Tigeot gpu_addr = rdev->wb.gpu_addr + index; 6234cd92098Szrj 6244cd92098Szrj tmp = 0xCAFEDEAD; 625591d5043SFrançois Tigeot rdev->wb.wb[index/4] = cpu_to_le32(tmp); 6264cd92098Szrj 627c6f73aabSFrançois Tigeot r = radeon_ring_lock(rdev, ring, 5); 6284cd92098Szrj if (r) { 6294cd92098Szrj DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 6304cd92098Szrj return r; 6314cd92098Szrj } 6324cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 633591d5043SFrançois Tigeot radeon_ring_write(ring, lower_32_bits(gpu_addr)); 634591d5043SFrançois Tigeot radeon_ring_write(ring, upper_32_bits(gpu_addr)); 6354cd92098Szrj radeon_ring_write(ring, 1); /* number of DWs to follow */ 6364cd92098Szrj radeon_ring_write(ring, 0xDEADBEEF); 637c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false); 6384cd92098Szrj 6394cd92098Szrj for (i = 0; i < rdev->usec_timeout; i++) { 640591d5043SFrançois Tigeot tmp = le32_to_cpu(rdev->wb.wb[index/4]); 6414cd92098Szrj if (tmp == 0xDEADBEEF) 6424cd92098Szrj break; 6434cd92098Szrj DRM_UDELAY(1); 6444cd92098Szrj } 6454cd92098Szrj 6464cd92098Szrj if (i < rdev->usec_timeout) { 6474cd92098Szrj DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 6484cd92098Szrj } else { 6494cd92098Szrj DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 6504cd92098Szrj ring->idx, tmp); 6514cd92098Szrj r = -EINVAL; 6524cd92098Szrj } 6534cd92098Szrj return r; 6544cd92098Szrj } 6554cd92098Szrj 6564cd92098Szrj /** 6574cd92098Szrj * cik_sdma_ib_test - test an IB on the DMA engine 6584cd92098Szrj * 6594cd92098Szrj * @rdev: radeon_device pointer 6604cd92098Szrj * @ring: radeon_ring structure holding ring information 6614cd92098Szrj * 6624cd92098Szrj * Test a simple IB in the DMA ring (CIK). 6634cd92098Szrj * Returns 0 on success, error on failure. 6644cd92098Szrj */ 6654cd92098Szrj int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 6664cd92098Szrj { 6674cd92098Szrj struct radeon_ib ib; 6684cd92098Szrj unsigned i; 669591d5043SFrançois Tigeot unsigned index; 6704cd92098Szrj int r; 6714cd92098Szrj u32 tmp = 0; 672591d5043SFrançois Tigeot u64 gpu_addr; 6734cd92098Szrj 674591d5043SFrançois Tigeot if (ring->idx == R600_RING_TYPE_DMA_INDEX) 675591d5043SFrançois Tigeot index = R600_WB_DMA_RING_TEST_OFFSET; 676591d5043SFrançois Tigeot else 677591d5043SFrançois Tigeot index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 678591d5043SFrançois Tigeot 679591d5043SFrançois Tigeot gpu_addr = rdev->wb.gpu_addr + index; 6804cd92098Szrj 6814cd92098Szrj tmp = 0xCAFEDEAD; 682591d5043SFrançois Tigeot rdev->wb.wb[index/4] = cpu_to_le32(tmp); 6834cd92098Szrj 6844cd92098Szrj r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 6854cd92098Szrj if (r) { 6864cd92098Szrj DRM_ERROR("radeon: failed to get ib (%d).\n", r); 6874cd92098Szrj return r; 6884cd92098Szrj } 6894cd92098Szrj 6904cd92098Szrj ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 691591d5043SFrançois Tigeot ib.ptr[1] = lower_32_bits(gpu_addr); 692591d5043SFrançois Tigeot ib.ptr[2] = upper_32_bits(gpu_addr); 6934cd92098Szrj ib.ptr[3] = 1; 6944cd92098Szrj ib.ptr[4] = 0xDEADBEEF; 6954cd92098Szrj ib.length_dw = 5; 6964cd92098Szrj 697c6f73aabSFrançois Tigeot r = radeon_ib_schedule(rdev, &ib, NULL, false); 6984cd92098Szrj if (r) { 6994cd92098Szrj radeon_ib_free(rdev, &ib); 7004cd92098Szrj DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 7014cd92098Szrj return r; 7024cd92098Szrj } 7034cd92098Szrj r = radeon_fence_wait(ib.fence, false); 7044cd92098Szrj if (r) { 7054cd92098Szrj DRM_ERROR("radeon: fence wait failed (%d).\n", r); 7064cd92098Szrj return r; 7074cd92098Szrj } 7084cd92098Szrj for (i = 0; i < rdev->usec_timeout; i++) { 709591d5043SFrançois Tigeot tmp = le32_to_cpu(rdev->wb.wb[index/4]); 7104cd92098Szrj if (tmp == 0xDEADBEEF) 7114cd92098Szrj break; 7124cd92098Szrj DRM_UDELAY(1); 7134cd92098Szrj } 7144cd92098Szrj if (i < rdev->usec_timeout) { 7154cd92098Szrj DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 7164cd92098Szrj } else { 7174cd92098Szrj DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 7184cd92098Szrj r = -EINVAL; 7194cd92098Szrj } 7204cd92098Szrj radeon_ib_free(rdev, &ib); 7214cd92098Szrj return r; 7224cd92098Szrj } 7234cd92098Szrj 7244cd92098Szrj /** 7254cd92098Szrj * cik_sdma_is_lockup - Check if the DMA engine is locked up 7264cd92098Szrj * 7274cd92098Szrj * @rdev: radeon_device pointer 7284cd92098Szrj * @ring: radeon_ring structure holding ring information 7294cd92098Szrj * 7304cd92098Szrj * Check if the async DMA engine is locked up (CIK). 7314cd92098Szrj * Returns true if the engine appears to be locked up, false if not. 7324cd92098Szrj */ 7334cd92098Szrj bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 7344cd92098Szrj { 7354cd92098Szrj u32 reset_mask = cik_gpu_check_soft_reset(rdev); 7364cd92098Szrj u32 mask; 7374cd92098Szrj 7384cd92098Szrj if (ring->idx == R600_RING_TYPE_DMA_INDEX) 7394cd92098Szrj mask = RADEON_RESET_DMA; 7404cd92098Szrj else 7414cd92098Szrj mask = RADEON_RESET_DMA1; 7424cd92098Szrj 7434cd92098Szrj if (!(reset_mask & mask)) { 744c6f73aabSFrançois Tigeot radeon_ring_lockup_update(rdev, ring); 7454cd92098Szrj return false; 7464cd92098Szrj } 7474cd92098Szrj return radeon_ring_test_lockup(rdev, ring); 7484cd92098Szrj } 7494cd92098Szrj 7504cd92098Szrj /** 751c6f73aabSFrançois Tigeot * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 752c6f73aabSFrançois Tigeot * 753c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 754c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with commands 755c6f73aabSFrançois Tigeot * @pe: addr of the page entry 756c6f73aabSFrançois Tigeot * @src: src addr to copy from 757c6f73aabSFrançois Tigeot * @count: number of page entries to update 758c6f73aabSFrançois Tigeot * 759c6f73aabSFrançois Tigeot * Update PTEs by copying them from the GART using sDMA (CIK). 760c6f73aabSFrançois Tigeot */ 761c6f73aabSFrançois Tigeot void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 762c6f73aabSFrançois Tigeot struct radeon_ib *ib, 763c6f73aabSFrançois Tigeot uint64_t pe, uint64_t src, 764c6f73aabSFrançois Tigeot unsigned count) 765c6f73aabSFrançois Tigeot { 766c6f73aabSFrançois Tigeot while (count) { 767c6f73aabSFrançois Tigeot unsigned bytes = count * 8; 768c6f73aabSFrançois Tigeot if (bytes > 0x1FFFF8) 769c6f73aabSFrançois Tigeot bytes = 0x1FFFF8; 770c6f73aabSFrançois Tigeot 771c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 772c6f73aabSFrançois Tigeot SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 773c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = bytes; 774c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 775c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = lower_32_bits(src); 776c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(src); 777c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = lower_32_bits(pe); 778c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(pe); 779c6f73aabSFrançois Tigeot 780c6f73aabSFrançois Tigeot pe += bytes; 781c6f73aabSFrançois Tigeot src += bytes; 782c6f73aabSFrançois Tigeot count -= bytes / 8; 783c6f73aabSFrançois Tigeot } 784c6f73aabSFrançois Tigeot } 785c6f73aabSFrançois Tigeot 786c6f73aabSFrançois Tigeot /** 787c6f73aabSFrançois Tigeot * cik_sdma_vm_write_pages - update PTEs by writing them manually 788c6f73aabSFrançois Tigeot * 789c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 790c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with commands 791c6f73aabSFrançois Tigeot * @pe: addr of the page entry 792c6f73aabSFrançois Tigeot * @addr: dst addr to write into pe 793c6f73aabSFrançois Tigeot * @count: number of page entries to update 794c6f73aabSFrançois Tigeot * @incr: increase next addr by incr bytes 795c6f73aabSFrançois Tigeot * @flags: access flags 796c6f73aabSFrançois Tigeot * 797c6f73aabSFrançois Tigeot * Update PTEs by writing them manually using sDMA (CIK). 798c6f73aabSFrançois Tigeot */ 799c6f73aabSFrançois Tigeot void cik_sdma_vm_write_pages(struct radeon_device *rdev, 800c6f73aabSFrançois Tigeot struct radeon_ib *ib, 801c6f73aabSFrançois Tigeot uint64_t pe, 802c6f73aabSFrançois Tigeot uint64_t addr, unsigned count, 803c6f73aabSFrançois Tigeot uint32_t incr, uint32_t flags) 804c6f73aabSFrançois Tigeot { 805c6f73aabSFrançois Tigeot uint64_t value; 806c6f73aabSFrançois Tigeot unsigned ndw; 807c6f73aabSFrançois Tigeot 808c6f73aabSFrançois Tigeot while (count) { 809c6f73aabSFrançois Tigeot ndw = count * 2; 810c6f73aabSFrançois Tigeot if (ndw > 0xFFFFE) 811c6f73aabSFrançois Tigeot ndw = 0xFFFFE; 812c6f73aabSFrançois Tigeot 813c6f73aabSFrançois Tigeot /* for non-physically contiguous pages (system) */ 814c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 815c6f73aabSFrançois Tigeot SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 816c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = pe; 817c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(pe); 818c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = ndw; 819c6f73aabSFrançois Tigeot for (; ndw > 0; ndw -= 2, --count, pe += 8) { 820c6f73aabSFrançois Tigeot if (flags & R600_PTE_SYSTEM) { 821c6f73aabSFrançois Tigeot value = radeon_vm_map_gart(rdev, addr); 822c6f73aabSFrançois Tigeot value &= 0xFFFFFFFFFFFFF000ULL; 823c6f73aabSFrançois Tigeot } else if (flags & R600_PTE_VALID) { 824c6f73aabSFrançois Tigeot value = addr; 825c6f73aabSFrançois Tigeot } else { 826c6f73aabSFrançois Tigeot value = 0; 827c6f73aabSFrançois Tigeot } 828c6f73aabSFrançois Tigeot addr += incr; 829c6f73aabSFrançois Tigeot value |= flags; 830c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = value; 831c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = upper_32_bits(value); 832c6f73aabSFrançois Tigeot } 833c6f73aabSFrançois Tigeot } 834c6f73aabSFrançois Tigeot } 835c6f73aabSFrançois Tigeot 836c6f73aabSFrançois Tigeot /** 837c6f73aabSFrançois Tigeot * cik_sdma_vm_set_pages - update the page tables using sDMA 8384cd92098Szrj * 8394cd92098Szrj * @rdev: radeon_device pointer 8404cd92098Szrj * @ib: indirect buffer to fill with commands 8414cd92098Szrj * @pe: addr of the page entry 8424cd92098Szrj * @addr: dst addr to write into pe 8434cd92098Szrj * @count: number of page entries to update 8444cd92098Szrj * @incr: increase next addr by incr bytes 8454cd92098Szrj * @flags: access flags 8464cd92098Szrj * 8474cd92098Szrj * Update the page tables using sDMA (CIK). 8484cd92098Szrj */ 849c6f73aabSFrançois Tigeot void cik_sdma_vm_set_pages(struct radeon_device *rdev, 8504cd92098Szrj struct radeon_ib *ib, 8514cd92098Szrj uint64_t pe, 8524cd92098Szrj uint64_t addr, unsigned count, 8534cd92098Szrj uint32_t incr, uint32_t flags) 8544cd92098Szrj { 8554cd92098Szrj uint64_t value; 8564cd92098Szrj unsigned ndw; 8574cd92098Szrj 8584cd92098Szrj while (count) { 8594cd92098Szrj ndw = count; 8604cd92098Szrj if (ndw > 0x7FFFF) 8614cd92098Szrj ndw = 0x7FFFF; 8624cd92098Szrj 863c6f73aabSFrançois Tigeot if (flags & R600_PTE_VALID) 8644cd92098Szrj value = addr; 8654cd92098Szrj else 8664cd92098Szrj value = 0; 867c6f73aabSFrançois Tigeot 8684cd92098Szrj /* for physically contiguous pages (vram) */ 8694cd92098Szrj ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 8704cd92098Szrj ib->ptr[ib->length_dw++] = pe; /* dst addr */ 8714cd92098Szrj ib->ptr[ib->length_dw++] = upper_32_bits(pe); 872c6f73aabSFrançois Tigeot ib->ptr[ib->length_dw++] = flags; /* mask */ 8734cd92098Szrj ib->ptr[ib->length_dw++] = 0; 8744cd92098Szrj ib->ptr[ib->length_dw++] = value; /* value */ 8754cd92098Szrj ib->ptr[ib->length_dw++] = upper_32_bits(value); 8764cd92098Szrj ib->ptr[ib->length_dw++] = incr; /* increment size */ 8774cd92098Szrj ib->ptr[ib->length_dw++] = 0; 8784cd92098Szrj ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 879c6f73aabSFrançois Tigeot 8804cd92098Szrj pe += ndw * 8; 8814cd92098Szrj addr += ndw * incr; 8824cd92098Szrj count -= ndw; 8834cd92098Szrj } 8844cd92098Szrj } 885c6f73aabSFrançois Tigeot 886c6f73aabSFrançois Tigeot /** 887c6f73aabSFrançois Tigeot * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 888c6f73aabSFrançois Tigeot * 889c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with padding 890c6f73aabSFrançois Tigeot * 891c6f73aabSFrançois Tigeot */ 892c6f73aabSFrançois Tigeot void cik_sdma_vm_pad_ib(struct radeon_ib *ib) 893c6f73aabSFrançois Tigeot { 8944cd92098Szrj while (ib->length_dw & 0x7) 8954cd92098Szrj ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 8964cd92098Szrj } 8974cd92098Szrj 8984cd92098Szrj /** 8994cd92098Szrj * cik_dma_vm_flush - cik vm flush using sDMA 9004cd92098Szrj * 9014cd92098Szrj * @rdev: radeon_device pointer 9024cd92098Szrj * 9034cd92098Szrj * Update the page table base and flush the VM TLB 9044cd92098Szrj * using sDMA (CIK). 9054cd92098Szrj */ 9064cd92098Szrj void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 9074cd92098Szrj { 9084cd92098Szrj struct radeon_ring *ring = &rdev->ring[ridx]; 9094cd92098Szrj 9104cd92098Szrj if (vm == NULL) 9114cd92098Szrj return; 9124cd92098Szrj 9134cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9144cd92098Szrj if (vm->id < 8) { 9154cd92098Szrj radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 9164cd92098Szrj } else { 9174cd92098Szrj radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 9184cd92098Szrj } 9194cd92098Szrj radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 9204cd92098Szrj 9214cd92098Szrj /* update SH_MEM_* regs */ 9224cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9234cd92098Szrj radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9244cd92098Szrj radeon_ring_write(ring, VMID(vm->id)); 9254cd92098Szrj 9264cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9274cd92098Szrj radeon_ring_write(ring, SH_MEM_BASES >> 2); 9284cd92098Szrj radeon_ring_write(ring, 0); 9294cd92098Szrj 9304cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9314cd92098Szrj radeon_ring_write(ring, SH_MEM_CONFIG >> 2); 9324cd92098Szrj radeon_ring_write(ring, 0); 9334cd92098Szrj 9344cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9354cd92098Szrj radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); 9364cd92098Szrj radeon_ring_write(ring, 1); 9374cd92098Szrj 9384cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9394cd92098Szrj radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); 9404cd92098Szrj radeon_ring_write(ring, 0); 9414cd92098Szrj 9424cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9434cd92098Szrj radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9444cd92098Szrj radeon_ring_write(ring, VMID(0)); 9454cd92098Szrj 9464cd92098Szrj /* flush HDP */ 947c6f73aabSFrançois Tigeot cik_sdma_hdp_flush_ring_emit(rdev, ridx); 9484cd92098Szrj 9494cd92098Szrj /* flush TLB */ 9504cd92098Szrj radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9514cd92098Szrj radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 9524cd92098Szrj radeon_ring_write(ring, 1 << vm->id); 9534cd92098Szrj } 954