1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_ucode.h" 28 #include "radeon_asic.h" 29 #ifdef TRACE_TODO 30 #include "radeon_trace.h" 31 #endif 32 #include "cikd.h" 33 34 /* sdma */ 35 #define CIK_SDMA_UCODE_SIZE 1050 36 #define CIK_SDMA_UCODE_VERSION 64 37 38 /* 39 * sDMA - System DMA 40 * Starting with CIK, the GPU has new asynchronous 41 * DMA engines. These engines are used for compute 42 * and gfx. There are two DMA engines (SDMA0, SDMA1) 43 * and each one supports 1 ring buffer used for gfx 44 * and 2 queues used for compute. 45 * 46 * The programming model is very similar to the CP 47 * (ring buffer, IBs, etc.), but sDMA has it's own 48 * packet format that is different from the PM4 format 49 * used by the CP. sDMA supports copying data, writing 50 * embedded data, solid fills, and a number of other 51 * things. It also has support for tiling/detiling of 52 * buffers. 53 */ 54 55 /** 56 * cik_sdma_get_rptr - get the current read pointer 57 * 58 * @rdev: radeon_device pointer 59 * @ring: radeon ring pointer 60 * 61 * Get the current rptr from the hardware (CIK+). 62 */ 63 uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, 64 struct radeon_ring *ring) 65 { 66 u32 rptr, reg; 67 68 if (rdev->wb.enabled) { 69 rptr = rdev->wb.wb[ring->rptr_offs/4]; 70 } else { 71 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 72 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; 73 else 74 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; 75 76 rptr = RREG32(reg); 77 } 78 79 return (rptr & 0x3fffc) >> 2; 80 } 81 82 /** 83 * cik_sdma_get_wptr - get the current write pointer 84 * 85 * @rdev: radeon_device pointer 86 * @ring: radeon ring pointer 87 * 88 * Get the current wptr from the hardware (CIK+). 89 */ 90 uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, 91 struct radeon_ring *ring) 92 { 93 u32 reg; 94 95 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 96 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 97 else 98 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 99 100 return (RREG32(reg) & 0x3fffc) >> 2; 101 } 102 103 /** 104 * cik_sdma_set_wptr - commit the write pointer 105 * 106 * @rdev: radeon_device pointer 107 * @ring: radeon ring pointer 108 * 109 * Write the wptr back to the hardware (CIK+). 110 */ 111 void cik_sdma_set_wptr(struct radeon_device *rdev, 112 struct radeon_ring *ring) 113 { 114 u32 reg; 115 116 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 117 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 118 else 119 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 120 121 WREG32(reg, (ring->wptr << 2) & 0x3fffc); 122 (void)RREG32(reg); 123 } 124 125 /** 126 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 127 * 128 * @rdev: radeon_device pointer 129 * @ib: IB object to schedule 130 * 131 * Schedule an IB in the DMA ring (CIK). 132 */ 133 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 134 struct radeon_ib *ib) 135 { 136 struct radeon_ring *ring = &rdev->ring[ib->ring]; 137 u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; 138 139 if (rdev->wb.enabled) { 140 u32 next_rptr = ring->wptr + 5; 141 while ((next_rptr & 7) != 4) 142 next_rptr++; 143 next_rptr += 4; 144 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 147 radeon_ring_write(ring, 1); /* number of DWs to follow */ 148 radeon_ring_write(ring, next_rptr); 149 } 150 151 /* IB packet must end on a 8 DW boundary */ 152 while ((ring->wptr & 7) != 4) 153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 154 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 157 radeon_ring_write(ring, ib->length_dw); 158 159 } 160 161 /** 162 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 163 * 164 * @rdev: radeon_device pointer 165 * @ridx: radeon ring index 166 * 167 * Emit an hdp flush packet on the requested DMA ring. 168 */ 169 static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, 170 int ridx) 171 { 172 struct radeon_ring *ring = &rdev->ring[ridx]; 173 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 174 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 175 u32 ref_and_mask; 176 177 if (ridx == R600_RING_TYPE_DMA_INDEX) 178 ref_and_mask = SDMA0; 179 else 180 ref_and_mask = SDMA1; 181 182 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 183 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 184 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 185 radeon_ring_write(ring, ref_and_mask); /* reference */ 186 radeon_ring_write(ring, ref_and_mask); /* mask */ 187 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 188 } 189 190 /** 191 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 192 * 193 * @rdev: radeon_device pointer 194 * @fence: radeon fence object 195 * 196 * Add a DMA fence packet to the ring to write 197 * the fence seq number and DMA trap packet to generate 198 * an interrupt if needed (CIK). 199 */ 200 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 201 struct radeon_fence *fence) 202 { 203 struct radeon_ring *ring = &rdev->ring[fence->ring]; 204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 205 206 /* write the fence */ 207 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 208 radeon_ring_write(ring, lower_32_bits(addr)); 209 radeon_ring_write(ring, upper_32_bits(addr)); 210 radeon_ring_write(ring, fence->seq); 211 /* generate an interrupt */ 212 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 213 /* flush HDP */ 214 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); 215 } 216 217 /** 218 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring 219 * 220 * @rdev: radeon_device pointer 221 * @ring: radeon_ring structure holding ring information 222 * @semaphore: radeon semaphore object 223 * @emit_wait: wait or signal semaphore 224 * 225 * Add a DMA semaphore packet to the ring wait on or signal 226 * other rings (CIK). 227 */ 228 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 229 struct radeon_ring *ring, 230 struct radeon_semaphore *semaphore, 231 bool emit_wait) 232 { 233 u64 addr = semaphore->gpu_addr; 234 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; 235 236 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 237 radeon_ring_write(ring, addr & 0xfffffff8); 238 radeon_ring_write(ring, upper_32_bits(addr)); 239 240 return true; 241 } 242 243 /** 244 * cik_sdma_gfx_stop - stop the gfx async dma engines 245 * 246 * @rdev: radeon_device pointer 247 * 248 * Stop the gfx async dma ring buffers (CIK). 249 */ 250 static void cik_sdma_gfx_stop(struct radeon_device *rdev) 251 { 252 u32 rb_cntl, reg_offset; 253 int i; 254 255 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 256 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 257 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 258 259 for (i = 0; i < 2; i++) { 260 if (i == 0) 261 reg_offset = SDMA0_REGISTER_OFFSET; 262 else 263 reg_offset = SDMA1_REGISTER_OFFSET; 264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); 265 rb_cntl &= ~SDMA_RB_ENABLE; 266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 267 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); 268 } 269 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 270 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; 271 } 272 273 /** 274 * cik_sdma_rlc_stop - stop the compute async dma engines 275 * 276 * @rdev: radeon_device pointer 277 * 278 * Stop the compute async dma queues (CIK). 279 */ 280 static void cik_sdma_rlc_stop(struct radeon_device *rdev) 281 { 282 /* XXX todo */ 283 } 284 285 /** 286 * cik_sdma_enable - stop the async dma engines 287 * 288 * @rdev: radeon_device pointer 289 * @enable: enable/disable the DMA MEs. 290 * 291 * Halt or unhalt the async dma engines (CIK). 292 */ 293 void cik_sdma_enable(struct radeon_device *rdev, bool enable) 294 { 295 u32 me_cntl, reg_offset; 296 int i; 297 298 if (enable == false) { 299 cik_sdma_gfx_stop(rdev); 300 cik_sdma_rlc_stop(rdev); 301 } 302 303 for (i = 0; i < 2; i++) { 304 if (i == 0) 305 reg_offset = SDMA0_REGISTER_OFFSET; 306 else 307 reg_offset = SDMA1_REGISTER_OFFSET; 308 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); 309 if (enable) 310 me_cntl &= ~SDMA_HALT; 311 else 312 me_cntl |= SDMA_HALT; 313 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); 314 } 315 } 316 317 /** 318 * cik_sdma_gfx_resume - setup and start the async dma engines 319 * 320 * @rdev: radeon_device pointer 321 * 322 * Set up the gfx DMA ring buffers and enable them (CIK). 323 * Returns 0 for success, error for failure. 324 */ 325 static int cik_sdma_gfx_resume(struct radeon_device *rdev) 326 { 327 struct radeon_ring *ring; 328 u32 rb_cntl, ib_cntl; 329 u32 rb_bufsz; 330 u32 reg_offset, wb_offset; 331 int i, r; 332 333 for (i = 0; i < 2; i++) { 334 if (i == 0) { 335 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 336 reg_offset = SDMA0_REGISTER_OFFSET; 337 wb_offset = R600_WB_DMA_RPTR_OFFSET; 338 } else { 339 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 340 reg_offset = SDMA1_REGISTER_OFFSET; 341 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; 342 } 343 344 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 345 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 346 347 /* Set ring buffer size in dwords */ 348 rb_bufsz = order_base_2(ring->ring_size / 4); 349 rb_cntl = rb_bufsz << 1; 350 #ifdef __BIG_ENDIAN 351 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 352 #endif 353 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 354 355 /* Initialize the ring buffer's read and write pointers */ 356 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); 357 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); 358 359 /* set the wb address whether it's enabled or not */ 360 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, 361 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 362 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, 363 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 364 365 if (rdev->wb.enabled) 366 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; 367 368 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 369 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 370 371 ring->wptr = 0; 372 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); 373 374 /* enable DMA RB */ 375 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); 376 377 ib_cntl = SDMA_IB_ENABLE; 378 #ifdef __BIG_ENDIAN 379 ib_cntl |= SDMA_IB_SWAP_ENABLE; 380 #endif 381 /* enable DMA IBs */ 382 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); 383 384 ring->ready = true; 385 386 r = radeon_ring_test(rdev, ring->idx, ring); 387 if (r) { 388 ring->ready = false; 389 return r; 390 } 391 } 392 393 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 394 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 395 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 396 397 return 0; 398 } 399 400 /** 401 * cik_sdma_rlc_resume - setup and start the async dma engines 402 * 403 * @rdev: radeon_device pointer 404 * 405 * Set up the compute DMA queues and enable them (CIK). 406 * Returns 0 for success, error for failure. 407 */ 408 static int cik_sdma_rlc_resume(struct radeon_device *rdev) 409 { 410 /* XXX todo */ 411 return 0; 412 } 413 414 /** 415 * cik_sdma_load_microcode - load the sDMA ME ucode 416 * 417 * @rdev: radeon_device pointer 418 * 419 * Loads the sDMA0/1 ucode. 420 * Returns 0 for success, -EINVAL if the ucode is not available. 421 */ 422 static int cik_sdma_load_microcode(struct radeon_device *rdev) 423 { 424 int i; 425 426 if (!rdev->sdma_fw) 427 return -EINVAL; 428 429 /* halt the MEs */ 430 cik_sdma_enable(rdev, false); 431 432 if (rdev->new_fw) { 433 const struct sdma_firmware_header_v1_0 *hdr = 434 (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; 435 const __le32 *fw_data; 436 u32 fw_size; 437 438 radeon_ucode_print_sdma_hdr(&hdr->header); 439 440 /* sdma0 */ 441 fw_data = (const __le32 *) 442 ((const char *)rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 443 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 444 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 445 for (i = 0; i < fw_size; i++) 446 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 447 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 448 449 /* sdma1 */ 450 fw_data = (const __le32 *) 451 ((const char *)rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 452 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 453 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 454 for (i = 0; i < fw_size; i++) 455 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 456 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 457 } else { 458 const __be32 *fw_data; 459 460 /* sdma0 */ 461 fw_data = (const __be32 *)rdev->sdma_fw->data; 462 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 463 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 464 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 465 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 466 467 /* sdma1 */ 468 fw_data = (const __be32 *)rdev->sdma_fw->data; 469 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 470 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 471 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 472 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 473 } 474 475 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 476 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 477 return 0; 478 } 479 480 /** 481 * cik_sdma_resume - setup and start the async dma engines 482 * 483 * @rdev: radeon_device pointer 484 * 485 * Set up the DMA engines and enable them (CIK). 486 * Returns 0 for success, error for failure. 487 */ 488 int cik_sdma_resume(struct radeon_device *rdev) 489 { 490 int r; 491 492 r = cik_sdma_load_microcode(rdev); 493 if (r) 494 return r; 495 496 /* unhalt the MEs */ 497 cik_sdma_enable(rdev, true); 498 499 /* start the gfx rings and rlc compute queues */ 500 r = cik_sdma_gfx_resume(rdev); 501 if (r) 502 return r; 503 r = cik_sdma_rlc_resume(rdev); 504 if (r) 505 return r; 506 507 return 0; 508 } 509 510 /** 511 * cik_sdma_fini - tear down the async dma engines 512 * 513 * @rdev: radeon_device pointer 514 * 515 * Stop the async dma engines and free the rings (CIK). 516 */ 517 void cik_sdma_fini(struct radeon_device *rdev) 518 { 519 /* halt the MEs */ 520 cik_sdma_enable(rdev, false); 521 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 522 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 523 /* XXX - compute dma queue tear down */ 524 } 525 526 /** 527 * cik_copy_dma - copy pages using the DMA engine 528 * 529 * @rdev: radeon_device pointer 530 * @src_offset: src GPU address 531 * @dst_offset: dst GPU address 532 * @num_gpu_pages: number of GPU pages to xfer 533 * @fence: radeon fence object 534 * 535 * Copy GPU paging using the DMA engine (CIK). 536 * Used by the radeon ttm implementation to move pages if 537 * registered as the asic copy callback. 538 */ 539 int cik_copy_dma(struct radeon_device *rdev, 540 uint64_t src_offset, uint64_t dst_offset, 541 unsigned num_gpu_pages, 542 struct radeon_fence **fence) 543 { 544 struct radeon_semaphore *sem = NULL; 545 int ring_index = rdev->asic->copy.dma_ring_index; 546 struct radeon_ring *ring = &rdev->ring[ring_index]; 547 u32 size_in_bytes, cur_size_in_bytes; 548 int i, num_loops; 549 int r = 0; 550 551 r = radeon_semaphore_create(rdev, &sem); 552 if (r) { 553 DRM_ERROR("radeon: moving bo (%d).\n", r); 554 return r; 555 } 556 557 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 558 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 559 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); 560 if (r) { 561 DRM_ERROR("radeon: moving bo (%d).\n", r); 562 radeon_semaphore_free(rdev, &sem, NULL); 563 return r; 564 } 565 566 radeon_semaphore_sync_to(sem, *fence); 567 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 568 569 for (i = 0; i < num_loops; i++) { 570 cur_size_in_bytes = size_in_bytes; 571 if (cur_size_in_bytes > 0x1fffff) 572 cur_size_in_bytes = 0x1fffff; 573 size_in_bytes -= cur_size_in_bytes; 574 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 575 radeon_ring_write(ring, cur_size_in_bytes); 576 radeon_ring_write(ring, 0); /* src/dst endian swap */ 577 radeon_ring_write(ring, lower_32_bits(src_offset)); 578 radeon_ring_write(ring, upper_32_bits(src_offset)); 579 radeon_ring_write(ring, lower_32_bits(dst_offset)); 580 radeon_ring_write(ring, upper_32_bits(dst_offset)); 581 src_offset += cur_size_in_bytes; 582 dst_offset += cur_size_in_bytes; 583 } 584 585 r = radeon_fence_emit(rdev, fence, ring->idx); 586 if (r) { 587 radeon_ring_unlock_undo(rdev, ring); 588 radeon_semaphore_free(rdev, &sem, NULL); 589 return r; 590 } 591 592 radeon_ring_unlock_commit(rdev, ring, false); 593 radeon_semaphore_free(rdev, &sem, *fence); 594 595 return r; 596 } 597 598 /** 599 * cik_sdma_ring_test - simple async dma engine test 600 * 601 * @rdev: radeon_device pointer 602 * @ring: radeon_ring structure holding ring information 603 * 604 * Test the DMA engine by writing using it to write an 605 * value to memory. (CIK). 606 * Returns 0 for success, error for failure. 607 */ 608 int cik_sdma_ring_test(struct radeon_device *rdev, 609 struct radeon_ring *ring) 610 { 611 unsigned i; 612 int r; 613 unsigned index; 614 u32 tmp; 615 u64 gpu_addr; 616 617 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 618 index = R600_WB_DMA_RING_TEST_OFFSET; 619 else 620 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 621 622 gpu_addr = rdev->wb.gpu_addr + index; 623 624 tmp = 0xCAFEDEAD; 625 rdev->wb.wb[index/4] = cpu_to_le32(tmp); 626 627 r = radeon_ring_lock(rdev, ring, 5); 628 if (r) { 629 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 630 return r; 631 } 632 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 633 radeon_ring_write(ring, lower_32_bits(gpu_addr)); 634 radeon_ring_write(ring, upper_32_bits(gpu_addr)); 635 radeon_ring_write(ring, 1); /* number of DWs to follow */ 636 radeon_ring_write(ring, 0xDEADBEEF); 637 radeon_ring_unlock_commit(rdev, ring, false); 638 639 for (i = 0; i < rdev->usec_timeout; i++) { 640 tmp = le32_to_cpu(rdev->wb.wb[index/4]); 641 if (tmp == 0xDEADBEEF) 642 break; 643 DRM_UDELAY(1); 644 } 645 646 if (i < rdev->usec_timeout) { 647 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 648 } else { 649 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 650 ring->idx, tmp); 651 r = -EINVAL; 652 } 653 return r; 654 } 655 656 /** 657 * cik_sdma_ib_test - test an IB on the DMA engine 658 * 659 * @rdev: radeon_device pointer 660 * @ring: radeon_ring structure holding ring information 661 * 662 * Test a simple IB in the DMA ring (CIK). 663 * Returns 0 on success, error on failure. 664 */ 665 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 666 { 667 struct radeon_ib ib; 668 unsigned i; 669 unsigned index; 670 int r; 671 u32 tmp = 0; 672 u64 gpu_addr; 673 674 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 675 index = R600_WB_DMA_RING_TEST_OFFSET; 676 else 677 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 678 679 gpu_addr = rdev->wb.gpu_addr + index; 680 681 tmp = 0xCAFEDEAD; 682 rdev->wb.wb[index/4] = cpu_to_le32(tmp); 683 684 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 685 if (r) { 686 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 687 return r; 688 } 689 690 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 691 ib.ptr[1] = lower_32_bits(gpu_addr); 692 ib.ptr[2] = upper_32_bits(gpu_addr); 693 ib.ptr[3] = 1; 694 ib.ptr[4] = 0xDEADBEEF; 695 ib.length_dw = 5; 696 697 r = radeon_ib_schedule(rdev, &ib, NULL, false); 698 if (r) { 699 radeon_ib_free(rdev, &ib); 700 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 701 return r; 702 } 703 r = radeon_fence_wait(ib.fence, false); 704 if (r) { 705 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 706 return r; 707 } 708 for (i = 0; i < rdev->usec_timeout; i++) { 709 tmp = le32_to_cpu(rdev->wb.wb[index/4]); 710 if (tmp == 0xDEADBEEF) 711 break; 712 DRM_UDELAY(1); 713 } 714 if (i < rdev->usec_timeout) { 715 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 716 } else { 717 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 718 r = -EINVAL; 719 } 720 radeon_ib_free(rdev, &ib); 721 return r; 722 } 723 724 /** 725 * cik_sdma_is_lockup - Check if the DMA engine is locked up 726 * 727 * @rdev: radeon_device pointer 728 * @ring: radeon_ring structure holding ring information 729 * 730 * Check if the async DMA engine is locked up (CIK). 731 * Returns true if the engine appears to be locked up, false if not. 732 */ 733 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 734 { 735 u32 reset_mask = cik_gpu_check_soft_reset(rdev); 736 u32 mask; 737 738 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 739 mask = RADEON_RESET_DMA; 740 else 741 mask = RADEON_RESET_DMA1; 742 743 if (!(reset_mask & mask)) { 744 radeon_ring_lockup_update(rdev, ring); 745 return false; 746 } 747 return radeon_ring_test_lockup(rdev, ring); 748 } 749 750 /** 751 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 752 * 753 * @rdev: radeon_device pointer 754 * @ib: indirect buffer to fill with commands 755 * @pe: addr of the page entry 756 * @src: src addr to copy from 757 * @count: number of page entries to update 758 * 759 * Update PTEs by copying them from the GART using sDMA (CIK). 760 */ 761 void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 762 struct radeon_ib *ib, 763 uint64_t pe, uint64_t src, 764 unsigned count) 765 { 766 while (count) { 767 unsigned bytes = count * 8; 768 if (bytes > 0x1FFFF8) 769 bytes = 0x1FFFF8; 770 771 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 772 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 773 ib->ptr[ib->length_dw++] = bytes; 774 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 775 ib->ptr[ib->length_dw++] = lower_32_bits(src); 776 ib->ptr[ib->length_dw++] = upper_32_bits(src); 777 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 778 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 779 780 pe += bytes; 781 src += bytes; 782 count -= bytes / 8; 783 } 784 } 785 786 /** 787 * cik_sdma_vm_write_pages - update PTEs by writing them manually 788 * 789 * @rdev: radeon_device pointer 790 * @ib: indirect buffer to fill with commands 791 * @pe: addr of the page entry 792 * @addr: dst addr to write into pe 793 * @count: number of page entries to update 794 * @incr: increase next addr by incr bytes 795 * @flags: access flags 796 * 797 * Update PTEs by writing them manually using sDMA (CIK). 798 */ 799 void cik_sdma_vm_write_pages(struct radeon_device *rdev, 800 struct radeon_ib *ib, 801 uint64_t pe, 802 uint64_t addr, unsigned count, 803 uint32_t incr, uint32_t flags) 804 { 805 uint64_t value; 806 unsigned ndw; 807 808 while (count) { 809 ndw = count * 2; 810 if (ndw > 0xFFFFE) 811 ndw = 0xFFFFE; 812 813 /* for non-physically contiguous pages (system) */ 814 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 815 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 816 ib->ptr[ib->length_dw++] = pe; 817 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 818 ib->ptr[ib->length_dw++] = ndw; 819 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 820 if (flags & R600_PTE_SYSTEM) { 821 value = radeon_vm_map_gart(rdev, addr); 822 value &= 0xFFFFFFFFFFFFF000ULL; 823 } else if (flags & R600_PTE_VALID) { 824 value = addr; 825 } else { 826 value = 0; 827 } 828 addr += incr; 829 value |= flags; 830 ib->ptr[ib->length_dw++] = value; 831 ib->ptr[ib->length_dw++] = upper_32_bits(value); 832 } 833 } 834 } 835 836 /** 837 * cik_sdma_vm_set_pages - update the page tables using sDMA 838 * 839 * @rdev: radeon_device pointer 840 * @ib: indirect buffer to fill with commands 841 * @pe: addr of the page entry 842 * @addr: dst addr to write into pe 843 * @count: number of page entries to update 844 * @incr: increase next addr by incr bytes 845 * @flags: access flags 846 * 847 * Update the page tables using sDMA (CIK). 848 */ 849 void cik_sdma_vm_set_pages(struct radeon_device *rdev, 850 struct radeon_ib *ib, 851 uint64_t pe, 852 uint64_t addr, unsigned count, 853 uint32_t incr, uint32_t flags) 854 { 855 uint64_t value; 856 unsigned ndw; 857 858 while (count) { 859 ndw = count; 860 if (ndw > 0x7FFFF) 861 ndw = 0x7FFFF; 862 863 if (flags & R600_PTE_VALID) 864 value = addr; 865 else 866 value = 0; 867 868 /* for physically contiguous pages (vram) */ 869 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 870 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 871 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 872 ib->ptr[ib->length_dw++] = flags; /* mask */ 873 ib->ptr[ib->length_dw++] = 0; 874 ib->ptr[ib->length_dw++] = value; /* value */ 875 ib->ptr[ib->length_dw++] = upper_32_bits(value); 876 ib->ptr[ib->length_dw++] = incr; /* increment size */ 877 ib->ptr[ib->length_dw++] = 0; 878 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 879 880 pe += ndw * 8; 881 addr += ndw * incr; 882 count -= ndw; 883 } 884 } 885 886 /** 887 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 888 * 889 * @ib: indirect buffer to fill with padding 890 * 891 */ 892 void cik_sdma_vm_pad_ib(struct radeon_ib *ib) 893 { 894 while (ib->length_dw & 0x7) 895 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 896 } 897 898 /** 899 * cik_dma_vm_flush - cik vm flush using sDMA 900 * 901 * @rdev: radeon_device pointer 902 * 903 * Update the page table base and flush the VM TLB 904 * using sDMA (CIK). 905 */ 906 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 907 { 908 struct radeon_ring *ring = &rdev->ring[ridx]; 909 910 if (vm == NULL) 911 return; 912 913 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 914 if (vm->id < 8) { 915 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 916 } else { 917 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 918 } 919 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 920 921 /* update SH_MEM_* regs */ 922 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 923 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 924 radeon_ring_write(ring, VMID(vm->id)); 925 926 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 927 radeon_ring_write(ring, SH_MEM_BASES >> 2); 928 radeon_ring_write(ring, 0); 929 930 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 931 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); 932 radeon_ring_write(ring, 0); 933 934 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 935 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); 936 radeon_ring_write(ring, 1); 937 938 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 939 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); 940 radeon_ring_write(ring, 0); 941 942 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 943 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 944 radeon_ring_write(ring, VMID(0)); 945 946 /* flush HDP */ 947 cik_sdma_hdp_flush_ring_emit(rdev, ridx); 948 949 /* flush TLB */ 950 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 951 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 952 radeon_ring_write(ring, 1 << vm->id); 953 } 954