157e252bfSMichael Neumann /* 257e252bfSMichael Neumann * Copyright 2012 Advanced Micro Devices, Inc. 357e252bfSMichael Neumann * 457e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 557e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 657e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 757e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 857e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 957e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 1057e252bfSMichael Neumann * 1157e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 1257e252bfSMichael Neumann * all copies or substantial portions of the Software. 1357e252bfSMichael Neumann * 1457e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1557e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1657e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1757e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1857e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1957e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2057e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 2157e252bfSMichael Neumann * 2257e252bfSMichael Neumann * Authors: Alex Deucher 2357e252bfSMichael Neumann */ 2457e252bfSMichael Neumann #ifndef CIK_H 2557e252bfSMichael Neumann #define CIK_H 2657e252bfSMichael Neumann 2757e252bfSMichael Neumann #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 2857e252bfSMichael Neumann 2957e252bfSMichael Neumann #define CIK_RB_BITMAP_WIDTH_PER_SH 2 3057e252bfSMichael Neumann 31*4cd92098Szrj /* DIDT IND registers */ 32*4cd92098Szrj #define DIDT_SQ_CTRL0 0x0 33*4cd92098Szrj # define DIDT_CTRL_EN (1 << 0) 34*4cd92098Szrj #define DIDT_DB_CTRL0 0x20 35*4cd92098Szrj #define DIDT_TD_CTRL0 0x40 36*4cd92098Szrj #define DIDT_TCP_CTRL0 0x60 3757e252bfSMichael Neumann 38*4cd92098Szrj /* SMC IND registers */ 39*4cd92098Szrj #define DPM_TABLE_475 0x3F768 40*4cd92098Szrj # define SamuBootLevel(x) ((x) << 0) 41*4cd92098Szrj # define SamuBootLevel_MASK 0x000000ff 42*4cd92098Szrj # define SamuBootLevel_SHIFT 0 43*4cd92098Szrj # define AcpBootLevel(x) ((x) << 8) 44*4cd92098Szrj # define AcpBootLevel_MASK 0x0000ff00 45*4cd92098Szrj # define AcpBootLevel_SHIFT 8 46*4cd92098Szrj # define VceBootLevel(x) ((x) << 16) 47*4cd92098Szrj # define VceBootLevel_MASK 0x00ff0000 48*4cd92098Szrj # define VceBootLevel_SHIFT 16 49*4cd92098Szrj # define UvdBootLevel(x) ((x) << 24) 50*4cd92098Szrj # define UvdBootLevel_MASK 0xff000000 51*4cd92098Szrj # define UvdBootLevel_SHIFT 24 52*4cd92098Szrj 53*4cd92098Szrj #define FIRMWARE_FLAGS 0x3F800 54*4cd92098Szrj # define INTERRUPTS_ENABLED (1 << 0) 55*4cd92098Szrj 56*4cd92098Szrj #define NB_DPM_CONFIG_1 0x3F9E8 57*4cd92098Szrj # define Dpm0PgNbPsLo(x) ((x) << 0) 58*4cd92098Szrj # define Dpm0PgNbPsLo_MASK 0x000000ff 59*4cd92098Szrj # define Dpm0PgNbPsLo_SHIFT 0 60*4cd92098Szrj # define Dpm0PgNbPsHi(x) ((x) << 8) 61*4cd92098Szrj # define Dpm0PgNbPsHi_MASK 0x0000ff00 62*4cd92098Szrj # define Dpm0PgNbPsHi_SHIFT 8 63*4cd92098Szrj # define DpmXNbPsLo(x) ((x) << 16) 64*4cd92098Szrj # define DpmXNbPsLo_MASK 0x00ff0000 65*4cd92098Szrj # define DpmXNbPsLo_SHIFT 16 66*4cd92098Szrj # define DpmXNbPsHi(x) ((x) << 24) 67*4cd92098Szrj # define DpmXNbPsHi_MASK 0xff000000 68*4cd92098Szrj # define DpmXNbPsHi_SHIFT 24 69*4cd92098Szrj 70*4cd92098Szrj #define SMC_SYSCON_RESET_CNTL 0x80000000 71*4cd92098Szrj # define RST_REG (1 << 0) 72*4cd92098Szrj #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 73*4cd92098Szrj # define CK_DISABLE (1 << 0) 74*4cd92098Szrj # define CKEN (1 << 24) 75*4cd92098Szrj 76*4cd92098Szrj #define SMC_SYSCON_MISC_CNTL 0x80000010 77*4cd92098Szrj 78*4cd92098Szrj #define SMC_SYSCON_MSG_ARG_0 0x80000068 79*4cd92098Szrj 80*4cd92098Szrj #define SMC_PC_C 0x80000370 81*4cd92098Szrj 82*4cd92098Szrj #define SMC_SCRATCH9 0x80000424 83*4cd92098Szrj 84*4cd92098Szrj #define RCU_UC_EVENTS 0xC0000004 85*4cd92098Szrj # define BOOT_SEQ_DONE (1 << 7) 86*4cd92098Szrj 87*4cd92098Szrj #define GENERAL_PWRMGT 0xC0200000 88*4cd92098Szrj # define GLOBAL_PWRMGT_EN (1 << 0) 89*4cd92098Szrj # define STATIC_PM_EN (1 << 1) 90*4cd92098Szrj # define THERMAL_PROTECTION_DIS (1 << 2) 91*4cd92098Szrj # define THERMAL_PROTECTION_TYPE (1 << 3) 92*4cd92098Szrj # define SW_SMIO_INDEX(x) ((x) << 6) 93*4cd92098Szrj # define SW_SMIO_INDEX_MASK (1 << 6) 94*4cd92098Szrj # define SW_SMIO_INDEX_SHIFT 6 95*4cd92098Szrj # define VOLT_PWRMGT_EN (1 << 10) 96*4cd92098Szrj # define GPU_COUNTER_CLK (1 << 15) 97*4cd92098Szrj # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 98*4cd92098Szrj 99*4cd92098Szrj #define CNB_PWRMGT_CNTL 0xC0200004 100*4cd92098Szrj # define GNB_SLOW_MODE(x) ((x) << 0) 101*4cd92098Szrj # define GNB_SLOW_MODE_MASK (3 << 0) 102*4cd92098Szrj # define GNB_SLOW_MODE_SHIFT 0 103*4cd92098Szrj # define GNB_SLOW (1 << 2) 104*4cd92098Szrj # define FORCE_NB_PS1 (1 << 3) 105*4cd92098Szrj # define DPM_ENABLED (1 << 4) 106*4cd92098Szrj 107*4cd92098Szrj #define SCLK_PWRMGT_CNTL 0xC0200008 108*4cd92098Szrj # define SCLK_PWRMGT_OFF (1 << 0) 109*4cd92098Szrj # define RESET_BUSY_CNT (1 << 4) 110*4cd92098Szrj # define RESET_SCLK_CNT (1 << 5) 111*4cd92098Szrj # define DYNAMIC_PM_EN (1 << 21) 112*4cd92098Szrj 113*4cd92098Szrj #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 114*4cd92098Szrj # define CURRENT_STATE_MASK (0xf << 4) 115*4cd92098Szrj # define CURRENT_STATE_SHIFT 4 116*4cd92098Szrj # define CURR_MCLK_INDEX_MASK (0xf << 8) 117*4cd92098Szrj # define CURR_MCLK_INDEX_SHIFT 8 118*4cd92098Szrj # define CURR_SCLK_INDEX_MASK (0x1f << 16) 119*4cd92098Szrj # define CURR_SCLK_INDEX_SHIFT 16 120*4cd92098Szrj 121*4cd92098Szrj #define CG_SSP 0xC0200044 122*4cd92098Szrj # define SST(x) ((x) << 0) 123*4cd92098Szrj # define SST_MASK (0xffff << 0) 124*4cd92098Szrj # define SSTU(x) ((x) << 16) 125*4cd92098Szrj # define SSTU_MASK (0xf << 16) 126*4cd92098Szrj 127*4cd92098Szrj #define CG_DISPLAY_GAP_CNTL 0xC0200060 128*4cd92098Szrj # define DISP_GAP(x) ((x) << 0) 129*4cd92098Szrj # define DISP_GAP_MASK (3 << 0) 130*4cd92098Szrj # define VBI_TIMER_COUNT(x) ((x) << 4) 131*4cd92098Szrj # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 132*4cd92098Szrj # define VBI_TIMER_UNIT(x) ((x) << 20) 133*4cd92098Szrj # define VBI_TIMER_UNIT_MASK (7 << 20) 134*4cd92098Szrj # define DISP_GAP_MCHG(x) ((x) << 24) 135*4cd92098Szrj # define DISP_GAP_MCHG_MASK (3 << 24) 136*4cd92098Szrj 137*4cd92098Szrj #define SMU_VOLTAGE_STATUS 0xC0200094 138*4cd92098Szrj # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 139*4cd92098Szrj # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 140*4cd92098Szrj 141*4cd92098Szrj #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 142*4cd92098Szrj # define CURR_PCIE_INDEX_MASK (0xf << 24) 143*4cd92098Szrj # define CURR_PCIE_INDEX_SHIFT 24 144*4cd92098Szrj 145*4cd92098Szrj #define CG_ULV_PARAMETER 0xC0200158 146*4cd92098Szrj 147*4cd92098Szrj #define CG_FTV_0 0xC02001A8 148*4cd92098Szrj #define CG_FTV_1 0xC02001AC 149*4cd92098Szrj #define CG_FTV_2 0xC02001B0 150*4cd92098Szrj #define CG_FTV_3 0xC02001B4 151*4cd92098Szrj #define CG_FTV_4 0xC02001B8 152*4cd92098Szrj #define CG_FTV_5 0xC02001BC 153*4cd92098Szrj #define CG_FTV_6 0xC02001C0 154*4cd92098Szrj #define CG_FTV_7 0xC02001C4 155*4cd92098Szrj 156*4cd92098Szrj #define CG_DISPLAY_GAP_CNTL2 0xC0200230 157*4cd92098Szrj 158*4cd92098Szrj #define LCAC_SX0_OVR_SEL 0xC0400D04 159*4cd92098Szrj #define LCAC_SX0_OVR_VAL 0xC0400D08 160*4cd92098Szrj 161*4cd92098Szrj #define LCAC_MC0_CNTL 0xC0400D30 162*4cd92098Szrj #define LCAC_MC0_OVR_SEL 0xC0400D34 163*4cd92098Szrj #define LCAC_MC0_OVR_VAL 0xC0400D38 164*4cd92098Szrj #define LCAC_MC1_CNTL 0xC0400D3C 165*4cd92098Szrj #define LCAC_MC1_OVR_SEL 0xC0400D40 166*4cd92098Szrj #define LCAC_MC1_OVR_VAL 0xC0400D44 167*4cd92098Szrj 168*4cd92098Szrj #define LCAC_MC2_OVR_SEL 0xC0400D4C 169*4cd92098Szrj #define LCAC_MC2_OVR_VAL 0xC0400D50 170*4cd92098Szrj 171*4cd92098Szrj #define LCAC_MC3_OVR_SEL 0xC0400D58 172*4cd92098Szrj #define LCAC_MC3_OVR_VAL 0xC0400D5C 173*4cd92098Szrj 174*4cd92098Szrj #define LCAC_CPL_CNTL 0xC0400D80 175*4cd92098Szrj #define LCAC_CPL_OVR_SEL 0xC0400D84 176*4cd92098Szrj #define LCAC_CPL_OVR_VAL 0xC0400D88 177*4cd92098Szrj 178*4cd92098Szrj /* dGPU */ 179*4cd92098Szrj #define CG_THERMAL_CTRL 0xC0300004 180*4cd92098Szrj #define DPM_EVENT_SRC(x) ((x) << 0) 181*4cd92098Szrj #define DPM_EVENT_SRC_MASK (7 << 0) 182*4cd92098Szrj #define DIG_THERM_DPM(x) ((x) << 14) 183*4cd92098Szrj #define DIG_THERM_DPM_MASK 0x003FC000 184*4cd92098Szrj #define DIG_THERM_DPM_SHIFT 14 185*4cd92098Szrj 186*4cd92098Szrj #define CG_THERMAL_INT 0xC030000C 187*4cd92098Szrj #define CI_DIG_THERM_INTH(x) ((x) << 8) 188*4cd92098Szrj #define CI_DIG_THERM_INTH_MASK 0x0000FF00 189*4cd92098Szrj #define CI_DIG_THERM_INTH_SHIFT 8 190*4cd92098Szrj #define CI_DIG_THERM_INTL(x) ((x) << 16) 191*4cd92098Szrj #define CI_DIG_THERM_INTL_MASK 0x00FF0000 192*4cd92098Szrj #define CI_DIG_THERM_INTL_SHIFT 16 193*4cd92098Szrj #define THERM_INT_MASK_HIGH (1 << 24) 194*4cd92098Szrj #define THERM_INT_MASK_LOW (1 << 25) 195*4cd92098Szrj 196*4cd92098Szrj #define CG_MULT_THERMAL_STATUS 0xC0300014 197*4cd92098Szrj #define ASIC_MAX_TEMP(x) ((x) << 0) 198*4cd92098Szrj #define ASIC_MAX_TEMP_MASK 0x000001ff 199*4cd92098Szrj #define ASIC_MAX_TEMP_SHIFT 0 200*4cd92098Szrj #define CTF_TEMP(x) ((x) << 9) 201*4cd92098Szrj #define CTF_TEMP_MASK 0x0003fe00 202*4cd92098Szrj #define CTF_TEMP_SHIFT 9 203*4cd92098Szrj 204*4cd92098Szrj #define CG_SPLL_FUNC_CNTL 0xC0500140 205*4cd92098Szrj #define SPLL_RESET (1 << 0) 206*4cd92098Szrj #define SPLL_PWRON (1 << 1) 207*4cd92098Szrj #define SPLL_BYPASS_EN (1 << 3) 208*4cd92098Szrj #define SPLL_REF_DIV(x) ((x) << 5) 209*4cd92098Szrj #define SPLL_REF_DIV_MASK (0x3f << 5) 210*4cd92098Szrj #define SPLL_PDIV_A(x) ((x) << 20) 211*4cd92098Szrj #define SPLL_PDIV_A_MASK (0x7f << 20) 212*4cd92098Szrj #define SPLL_PDIV_A_SHIFT 20 213*4cd92098Szrj #define CG_SPLL_FUNC_CNTL_2 0xC0500144 214*4cd92098Szrj #define SCLK_MUX_SEL(x) ((x) << 0) 215*4cd92098Szrj #define SCLK_MUX_SEL_MASK (0x1ff << 0) 216*4cd92098Szrj #define CG_SPLL_FUNC_CNTL_3 0xC0500148 217*4cd92098Szrj #define SPLL_FB_DIV(x) ((x) << 0) 218*4cd92098Szrj #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 219*4cd92098Szrj #define SPLL_FB_DIV_SHIFT 0 220*4cd92098Szrj #define SPLL_DITHEN (1 << 28) 221*4cd92098Szrj #define CG_SPLL_FUNC_CNTL_4 0xC050014C 222*4cd92098Szrj 223*4cd92098Szrj #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 224*4cd92098Szrj #define SSEN (1 << 0) 225*4cd92098Szrj #define CLK_S(x) ((x) << 4) 226*4cd92098Szrj #define CLK_S_MASK (0xfff << 4) 227*4cd92098Szrj #define CLK_S_SHIFT 4 228*4cd92098Szrj #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 229*4cd92098Szrj #define CLK_V(x) ((x) << 0) 230*4cd92098Szrj #define CLK_V_MASK (0x3ffffff << 0) 231*4cd92098Szrj #define CLK_V_SHIFT 0 232*4cd92098Szrj 233*4cd92098Szrj #define MPLL_BYPASSCLK_SEL 0xC050019C 234*4cd92098Szrj # define MPLL_CLKOUT_SEL(x) ((x) << 8) 235*4cd92098Szrj # define MPLL_CLKOUT_SEL_MASK 0xFF00 23657e252bfSMichael Neumann #define CG_CLKPIN_CNTL 0xC05001A0 23757e252bfSMichael Neumann # define XTALIN_DIVIDE (1 << 1) 238*4cd92098Szrj # define BCLK_AS_XCLK (1 << 2) 239*4cd92098Szrj #define CG_CLKPIN_CNTL_2 0xC05001A4 240*4cd92098Szrj # define FORCE_BIF_REFCLK_EN (1 << 3) 241*4cd92098Szrj # define MUX_TCLK_TO_XCLK (1 << 8) 242*4cd92098Szrj #define THM_CLK_CNTL 0xC05001A8 243*4cd92098Szrj # define CMON_CLK_SEL(x) ((x) << 0) 244*4cd92098Szrj # define CMON_CLK_SEL_MASK 0xFF 245*4cd92098Szrj # define TMON_CLK_SEL(x) ((x) << 8) 246*4cd92098Szrj # define TMON_CLK_SEL_MASK 0xFF00 247*4cd92098Szrj #define MISC_CLK_CTRL 0xC05001AC 248*4cd92098Szrj # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 249*4cd92098Szrj # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 250*4cd92098Szrj # define ZCLK_SEL(x) ((x) << 8) 251*4cd92098Szrj # define ZCLK_SEL_MASK 0xFF00 25257e252bfSMichael Neumann 253*4cd92098Szrj /* KV/KB */ 254*4cd92098Szrj #define CG_THERMAL_INT_CTRL 0xC2100028 255*4cd92098Szrj #define DIG_THERM_INTH(x) ((x) << 0) 256*4cd92098Szrj #define DIG_THERM_INTH_MASK 0x000000FF 257*4cd92098Szrj #define DIG_THERM_INTH_SHIFT 0 258*4cd92098Szrj #define DIG_THERM_INTL(x) ((x) << 8) 259*4cd92098Szrj #define DIG_THERM_INTL_MASK 0x0000FF00 260*4cd92098Szrj #define DIG_THERM_INTL_SHIFT 8 261*4cd92098Szrj #define THERM_INTH_MASK (1 << 24) 262*4cd92098Szrj #define THERM_INTL_MASK (1 << 25) 263*4cd92098Szrj 264*4cd92098Szrj /* PCIE registers idx/data 0x38/0x3c */ 265*4cd92098Szrj #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 266*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 267*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 268*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 269*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 270*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 271*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 272*4cd92098Szrj # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 273*4cd92098Szrj # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 274*4cd92098Szrj # define PLL_RAMP_UP_TIME_0_SHIFT 24 275*4cd92098Szrj #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 276*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 277*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 278*4cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 279*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 280*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 281*4cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 282*4cd92098Szrj # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 283*4cd92098Szrj # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 284*4cd92098Szrj # define PLL_RAMP_UP_TIME_1_SHIFT 24 285*4cd92098Szrj 286*4cd92098Szrj #define PCIE_CNTL2 0x1001001c /* PCIE */ 287*4cd92098Szrj # define SLV_MEM_LS_EN (1 << 16) 288*4cd92098Szrj # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 289*4cd92098Szrj # define MST_MEM_LS_EN (1 << 18) 290*4cd92098Szrj # define REPLAY_MEM_LS_EN (1 << 19) 291*4cd92098Szrj 292*4cd92098Szrj #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 293*4cd92098Szrj # define LC_REVERSE_RCVR (1 << 0) 294*4cd92098Szrj # define LC_REVERSE_XMIT (1 << 1) 295*4cd92098Szrj # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 296*4cd92098Szrj # define LC_OPERATING_LINK_WIDTH_SHIFT 2 297*4cd92098Szrj # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 298*4cd92098Szrj # define LC_DETECTED_LINK_WIDTH_SHIFT 5 299*4cd92098Szrj 300*4cd92098Szrj #define PCIE_P_CNTL 0x1400040 /* PCIE */ 301*4cd92098Szrj # define P_IGNORE_EDB_ERR (1 << 6) 302*4cd92098Szrj 303*4cd92098Szrj #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 304*4cd92098Szrj #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 305*4cd92098Szrj 306*4cd92098Szrj #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 307*4cd92098Szrj # define LC_L0S_INACTIVITY(x) ((x) << 8) 308*4cd92098Szrj # define LC_L0S_INACTIVITY_MASK (0xf << 8) 309*4cd92098Szrj # define LC_L0S_INACTIVITY_SHIFT 8 310*4cd92098Szrj # define LC_L1_INACTIVITY(x) ((x) << 12) 311*4cd92098Szrj # define LC_L1_INACTIVITY_MASK (0xf << 12) 312*4cd92098Szrj # define LC_L1_INACTIVITY_SHIFT 12 313*4cd92098Szrj # define LC_PMI_TO_L1_DIS (1 << 16) 314*4cd92098Szrj # define LC_ASPM_TO_L1_DIS (1 << 24) 315*4cd92098Szrj 316*4cd92098Szrj #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 317*4cd92098Szrj # define LC_LINK_WIDTH_SHIFT 0 318*4cd92098Szrj # define LC_LINK_WIDTH_MASK 0x7 319*4cd92098Szrj # define LC_LINK_WIDTH_X0 0 320*4cd92098Szrj # define LC_LINK_WIDTH_X1 1 321*4cd92098Szrj # define LC_LINK_WIDTH_X2 2 322*4cd92098Szrj # define LC_LINK_WIDTH_X4 3 323*4cd92098Szrj # define LC_LINK_WIDTH_X8 4 324*4cd92098Szrj # define LC_LINK_WIDTH_X16 6 325*4cd92098Szrj # define LC_LINK_WIDTH_RD_SHIFT 4 326*4cd92098Szrj # define LC_LINK_WIDTH_RD_MASK 0x70 327*4cd92098Szrj # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 328*4cd92098Szrj # define LC_RECONFIG_NOW (1 << 8) 329*4cd92098Szrj # define LC_RENEGOTIATION_SUPPORT (1 << 9) 330*4cd92098Szrj # define LC_RENEGOTIATE_EN (1 << 10) 331*4cd92098Szrj # define LC_SHORT_RECONFIG_EN (1 << 11) 332*4cd92098Szrj # define LC_UPCONFIGURE_SUPPORT (1 << 12) 333*4cd92098Szrj # define LC_UPCONFIGURE_DIS (1 << 13) 334*4cd92098Szrj # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 335*4cd92098Szrj # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 336*4cd92098Szrj # define LC_DYN_LANES_PWR_STATE_SHIFT 21 337*4cd92098Szrj #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 338*4cd92098Szrj # define LC_XMIT_N_FTS(x) ((x) << 0) 339*4cd92098Szrj # define LC_XMIT_N_FTS_MASK (0xff << 0) 340*4cd92098Szrj # define LC_XMIT_N_FTS_SHIFT 0 341*4cd92098Szrj # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 342*4cd92098Szrj # define LC_N_FTS_MASK (0xff << 24) 343*4cd92098Szrj #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 344*4cd92098Szrj # define LC_GEN2_EN_STRAP (1 << 0) 345*4cd92098Szrj # define LC_GEN3_EN_STRAP (1 << 1) 346*4cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 347*4cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 348*4cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 349*4cd92098Szrj # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 350*4cd92098Szrj # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 351*4cd92098Szrj # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 352*4cd92098Szrj # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 353*4cd92098Szrj # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 354*4cd92098Szrj # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 355*4cd92098Szrj # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 356*4cd92098Szrj # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 357*4cd92098Szrj # define LC_CURRENT_DATA_RATE_SHIFT 13 358*4cd92098Szrj # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 359*4cd92098Szrj # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 360*4cd92098Szrj # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 361*4cd92098Szrj # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 362*4cd92098Szrj # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 363*4cd92098Szrj 364*4cd92098Szrj #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 365*4cd92098Szrj # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 366*4cd92098Szrj # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 367*4cd92098Szrj 368*4cd92098Szrj #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 369*4cd92098Szrj # define LC_GO_TO_RECOVERY (1 << 30) 370*4cd92098Szrj #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 371*4cd92098Szrj # define LC_REDO_EQ (1 << 5) 372*4cd92098Szrj # define LC_SET_QUIESCE (1 << 13) 373*4cd92098Szrj 374*4cd92098Szrj /* direct registers */ 37557e252bfSMichael Neumann #define PCIE_INDEX 0x38 37657e252bfSMichael Neumann #define PCIE_DATA 0x3C 37757e252bfSMichael Neumann 378*4cd92098Szrj #define SMC_IND_INDEX_0 0x200 379*4cd92098Szrj #define SMC_IND_DATA_0 0x204 380*4cd92098Szrj 381*4cd92098Szrj #define SMC_IND_ACCESS_CNTL 0x240 382*4cd92098Szrj #define AUTO_INCREMENT_IND_0 (1 << 0) 383*4cd92098Szrj 384*4cd92098Szrj #define SMC_MESSAGE_0 0x250 385*4cd92098Szrj #define SMC_MSG_MASK 0xffff 386*4cd92098Szrj #define SMC_RESP_0 0x254 387*4cd92098Szrj #define SMC_RESP_MASK 0xffff 388*4cd92098Szrj 389*4cd92098Szrj #define SMC_MSG_ARG_0 0x290 390*4cd92098Szrj 39157e252bfSMichael Neumann #define VGA_HDP_CONTROL 0x328 39257e252bfSMichael Neumann #define VGA_MEMORY_DISABLE (1 << 4) 39357e252bfSMichael Neumann 39457e252bfSMichael Neumann #define DMIF_ADDR_CALC 0xC00 39557e252bfSMichael Neumann 396*4cd92098Szrj #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 397*4cd92098Szrj # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 398*4cd92098Szrj # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 399*4cd92098Szrj 40057e252bfSMichael Neumann #define SRBM_GFX_CNTL 0xE44 40157e252bfSMichael Neumann #define PIPEID(x) ((x) << 0) 40257e252bfSMichael Neumann #define MEID(x) ((x) << 2) 40357e252bfSMichael Neumann #define VMID(x) ((x) << 4) 40457e252bfSMichael Neumann #define QUEUEID(x) ((x) << 8) 40557e252bfSMichael Neumann 40657e252bfSMichael Neumann #define SRBM_STATUS2 0xE4C 40757e252bfSMichael Neumann #define SDMA_BUSY (1 << 5) 40857e252bfSMichael Neumann #define SDMA1_BUSY (1 << 6) 40957e252bfSMichael Neumann #define SRBM_STATUS 0xE50 41057e252bfSMichael Neumann #define UVD_RQ_PENDING (1 << 1) 41157e252bfSMichael Neumann #define GRBM_RQ_PENDING (1 << 5) 41257e252bfSMichael Neumann #define VMC_BUSY (1 << 8) 41357e252bfSMichael Neumann #define MCB_BUSY (1 << 9) 41457e252bfSMichael Neumann #define MCB_NON_DISPLAY_BUSY (1 << 10) 41557e252bfSMichael Neumann #define MCC_BUSY (1 << 11) 41657e252bfSMichael Neumann #define MCD_BUSY (1 << 12) 41757e252bfSMichael Neumann #define SEM_BUSY (1 << 14) 41857e252bfSMichael Neumann #define IH_BUSY (1 << 17) 41957e252bfSMichael Neumann #define UVD_BUSY (1 << 19) 42057e252bfSMichael Neumann 42157e252bfSMichael Neumann #define SRBM_SOFT_RESET 0xE60 42257e252bfSMichael Neumann #define SOFT_RESET_BIF (1 << 1) 42357e252bfSMichael Neumann #define SOFT_RESET_R0PLL (1 << 4) 42457e252bfSMichael Neumann #define SOFT_RESET_DC (1 << 5) 42557e252bfSMichael Neumann #define SOFT_RESET_SDMA1 (1 << 6) 42657e252bfSMichael Neumann #define SOFT_RESET_GRBM (1 << 8) 42757e252bfSMichael Neumann #define SOFT_RESET_HDP (1 << 9) 42857e252bfSMichael Neumann #define SOFT_RESET_IH (1 << 10) 42957e252bfSMichael Neumann #define SOFT_RESET_MC (1 << 11) 43057e252bfSMichael Neumann #define SOFT_RESET_ROM (1 << 14) 43157e252bfSMichael Neumann #define SOFT_RESET_SEM (1 << 15) 43257e252bfSMichael Neumann #define SOFT_RESET_VMC (1 << 17) 43357e252bfSMichael Neumann #define SOFT_RESET_SDMA (1 << 20) 43457e252bfSMichael Neumann #define SOFT_RESET_TST (1 << 21) 43557e252bfSMichael Neumann #define SOFT_RESET_REGBB (1 << 22) 43657e252bfSMichael Neumann #define SOFT_RESET_ORB (1 << 23) 43757e252bfSMichael Neumann #define SOFT_RESET_VCE (1 << 24) 43857e252bfSMichael Neumann 43957e252bfSMichael Neumann #define VM_L2_CNTL 0x1400 44057e252bfSMichael Neumann #define ENABLE_L2_CACHE (1 << 0) 44157e252bfSMichael Neumann #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 44257e252bfSMichael Neumann #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 44357e252bfSMichael Neumann #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 44457e252bfSMichael Neumann #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 44557e252bfSMichael Neumann #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 44657e252bfSMichael Neumann #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 44757e252bfSMichael Neumann #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 44857e252bfSMichael Neumann #define VM_L2_CNTL2 0x1404 44957e252bfSMichael Neumann #define INVALIDATE_ALL_L1_TLBS (1 << 0) 45057e252bfSMichael Neumann #define INVALIDATE_L2_CACHE (1 << 1) 45157e252bfSMichael Neumann #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 45257e252bfSMichael Neumann #define INVALIDATE_PTE_AND_PDE_CACHES 0 45357e252bfSMichael Neumann #define INVALIDATE_ONLY_PTE_CACHES 1 45457e252bfSMichael Neumann #define INVALIDATE_ONLY_PDE_CACHES 2 45557e252bfSMichael Neumann #define VM_L2_CNTL3 0x1408 45657e252bfSMichael Neumann #define BANK_SELECT(x) ((x) << 0) 45757e252bfSMichael Neumann #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 45857e252bfSMichael Neumann #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 45957e252bfSMichael Neumann #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 46057e252bfSMichael Neumann #define VM_L2_STATUS 0x140C 46157e252bfSMichael Neumann #define L2_BUSY (1 << 0) 46257e252bfSMichael Neumann #define VM_CONTEXT0_CNTL 0x1410 46357e252bfSMichael Neumann #define ENABLE_CONTEXT (1 << 0) 46457e252bfSMichael Neumann #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 46557e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 46657e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 46757e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 46857e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 46957e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 47057e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 47157e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 47257e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 47357e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 47457e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 47557e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 47657e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 47757e252bfSMichael Neumann #define VM_CONTEXT1_CNTL 0x1414 47857e252bfSMichael Neumann #define VM_CONTEXT0_CNTL2 0x1430 47957e252bfSMichael Neumann #define VM_CONTEXT1_CNTL2 0x1434 48057e252bfSMichael Neumann #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 48157e252bfSMichael Neumann #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 48257e252bfSMichael Neumann #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 48357e252bfSMichael Neumann #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 48457e252bfSMichael Neumann #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 48557e252bfSMichael Neumann #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 48657e252bfSMichael Neumann #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 48757e252bfSMichael Neumann #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 48857e252bfSMichael Neumann 48957e252bfSMichael Neumann #define VM_INVALIDATE_REQUEST 0x1478 49057e252bfSMichael Neumann #define VM_INVALIDATE_RESPONSE 0x147c 49157e252bfSMichael Neumann 49257e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 49357e252bfSMichael Neumann #define PROTECTIONS_MASK (0xf << 0) 49457e252bfSMichael Neumann #define PROTECTIONS_SHIFT 0 49557e252bfSMichael Neumann /* bit 0: range 49657e252bfSMichael Neumann * bit 1: pde0 49757e252bfSMichael Neumann * bit 2: valid 49857e252bfSMichael Neumann * bit 3: read 49957e252bfSMichael Neumann * bit 4: write 50057e252bfSMichael Neumann */ 50157e252bfSMichael Neumann #define MEMORY_CLIENT_ID_MASK (0xff << 12) 50257e252bfSMichael Neumann #define MEMORY_CLIENT_ID_SHIFT 12 50357e252bfSMichael Neumann #define MEMORY_CLIENT_RW_MASK (1 << 24) 50457e252bfSMichael Neumann #define MEMORY_CLIENT_RW_SHIFT 24 50557e252bfSMichael Neumann #define FAULT_VMID_MASK (0xf << 25) 50657e252bfSMichael Neumann #define FAULT_VMID_SHIFT 25 50757e252bfSMichael Neumann 50857e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 50957e252bfSMichael Neumann 51057e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 51157e252bfSMichael Neumann 51257e252bfSMichael Neumann #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 51357e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 51457e252bfSMichael Neumann 51557e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 51657e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 51757e252bfSMichael Neumann #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 51857e252bfSMichael Neumann #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 51957e252bfSMichael Neumann #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 52057e252bfSMichael Neumann #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 52157e252bfSMichael Neumann #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 52257e252bfSMichael Neumann #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 52357e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 52457e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 52557e252bfSMichael Neumann 52657e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 52757e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 52857e252bfSMichael Neumann 529*4cd92098Szrj #define VM_L2_CG 0x15c0 530*4cd92098Szrj #define MC_CG_ENABLE (1 << 18) 531*4cd92098Szrj #define MC_LS_ENABLE (1 << 19) 532*4cd92098Szrj 53357e252bfSMichael Neumann #define MC_SHARED_CHMAP 0x2004 53457e252bfSMichael Neumann #define NOOFCHAN_SHIFT 12 53557e252bfSMichael Neumann #define NOOFCHAN_MASK 0x0000f000 53657e252bfSMichael Neumann #define MC_SHARED_CHREMAP 0x2008 53757e252bfSMichael Neumann 53857e252bfSMichael Neumann #define CHUB_CONTROL 0x1864 53957e252bfSMichael Neumann #define BYPASS_VM (1 << 0) 54057e252bfSMichael Neumann 54157e252bfSMichael Neumann #define MC_VM_FB_LOCATION 0x2024 54257e252bfSMichael Neumann #define MC_VM_AGP_TOP 0x2028 54357e252bfSMichael Neumann #define MC_VM_AGP_BOT 0x202C 54457e252bfSMichael Neumann #define MC_VM_AGP_BASE 0x2030 54557e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 54657e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 54757e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 54857e252bfSMichael Neumann 54957e252bfSMichael Neumann #define MC_VM_MX_L1_TLB_CNTL 0x2064 55057e252bfSMichael Neumann #define ENABLE_L1_TLB (1 << 0) 55157e252bfSMichael Neumann #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 55257e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 55357e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 55457e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 55557e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 55657e252bfSMichael Neumann #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 55757e252bfSMichael Neumann #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 55857e252bfSMichael Neumann #define MC_VM_FB_OFFSET 0x2068 55957e252bfSMichael Neumann 56057e252bfSMichael Neumann #define MC_SHARED_BLACKOUT_CNTL 0x20ac 56157e252bfSMichael Neumann 562*4cd92098Szrj #define MC_HUB_MISC_HUB_CG 0x20b8 563*4cd92098Szrj #define MC_HUB_MISC_VM_CG 0x20bc 564*4cd92098Szrj 565*4cd92098Szrj #define MC_HUB_MISC_SIP_CG 0x20c0 566*4cd92098Szrj 567*4cd92098Szrj #define MC_XPB_CLK_GAT 0x2478 568*4cd92098Szrj 569*4cd92098Szrj #define MC_CITF_MISC_RD_CG 0x2648 570*4cd92098Szrj #define MC_CITF_MISC_WR_CG 0x264c 571*4cd92098Szrj #define MC_CITF_MISC_VM_CG 0x2650 572*4cd92098Szrj 57357e252bfSMichael Neumann #define MC_ARB_RAMCFG 0x2760 57457e252bfSMichael Neumann #define NOOFBANK_SHIFT 0 57557e252bfSMichael Neumann #define NOOFBANK_MASK 0x00000003 57657e252bfSMichael Neumann #define NOOFRANK_SHIFT 2 57757e252bfSMichael Neumann #define NOOFRANK_MASK 0x00000004 57857e252bfSMichael Neumann #define NOOFROWS_SHIFT 3 57957e252bfSMichael Neumann #define NOOFROWS_MASK 0x00000038 58057e252bfSMichael Neumann #define NOOFCOLS_SHIFT 6 58157e252bfSMichael Neumann #define NOOFCOLS_MASK 0x000000C0 58257e252bfSMichael Neumann #define CHANSIZE_SHIFT 8 58357e252bfSMichael Neumann #define CHANSIZE_MASK 0x00000100 58457e252bfSMichael Neumann #define NOOFGROUPS_SHIFT 12 58557e252bfSMichael Neumann #define NOOFGROUPS_MASK 0x00001000 58657e252bfSMichael Neumann 587*4cd92098Szrj #define MC_ARB_DRAM_TIMING 0x2774 588*4cd92098Szrj #define MC_ARB_DRAM_TIMING2 0x2778 589*4cd92098Szrj 590*4cd92098Szrj #define MC_ARB_BURST_TIME 0x2808 591*4cd92098Szrj #define STATE0(x) ((x) << 0) 592*4cd92098Szrj #define STATE0_MASK (0x1f << 0) 593*4cd92098Szrj #define STATE0_SHIFT 0 594*4cd92098Szrj #define STATE1(x) ((x) << 5) 595*4cd92098Szrj #define STATE1_MASK (0x1f << 5) 596*4cd92098Szrj #define STATE1_SHIFT 5 597*4cd92098Szrj #define STATE2(x) ((x) << 10) 598*4cd92098Szrj #define STATE2_MASK (0x1f << 10) 599*4cd92098Szrj #define STATE2_SHIFT 10 600*4cd92098Szrj #define STATE3(x) ((x) << 15) 601*4cd92098Szrj #define STATE3_MASK (0x1f << 15) 602*4cd92098Szrj #define STATE3_SHIFT 15 603*4cd92098Szrj 604*4cd92098Szrj #define MC_SEQ_RAS_TIMING 0x28a0 605*4cd92098Szrj #define MC_SEQ_CAS_TIMING 0x28a4 606*4cd92098Szrj #define MC_SEQ_MISC_TIMING 0x28a8 607*4cd92098Szrj #define MC_SEQ_MISC_TIMING2 0x28ac 608*4cd92098Szrj #define MC_SEQ_PMG_TIMING 0x28b0 609*4cd92098Szrj #define MC_SEQ_RD_CTL_D0 0x28b4 610*4cd92098Szrj #define MC_SEQ_RD_CTL_D1 0x28b8 611*4cd92098Szrj #define MC_SEQ_WR_CTL_D0 0x28bc 612*4cd92098Szrj #define MC_SEQ_WR_CTL_D1 0x28c0 613*4cd92098Szrj 61457e252bfSMichael Neumann #define MC_SEQ_SUP_CNTL 0x28c8 61557e252bfSMichael Neumann #define RUN_MASK (1 << 0) 61657e252bfSMichael Neumann #define MC_SEQ_SUP_PGM 0x28cc 617*4cd92098Szrj #define MC_PMG_AUTO_CMD 0x28d0 61857e252bfSMichael Neumann 61957e252bfSMichael Neumann #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 62057e252bfSMichael Neumann #define TRAIN_DONE_D0 (1 << 30) 62157e252bfSMichael Neumann #define TRAIN_DONE_D1 (1 << 31) 62257e252bfSMichael Neumann 62357e252bfSMichael Neumann #define MC_IO_PAD_CNTL_D0 0x29d0 62457e252bfSMichael Neumann #define MEM_FALL_OUT_CMD (1 << 8) 62557e252bfSMichael Neumann 626*4cd92098Szrj #define MC_SEQ_MISC0 0x2a00 627*4cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 628*4cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 629*4cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_VALUE 3 630*4cd92098Szrj #define MC_SEQ_MISC0_REV_ID_SHIFT 12 631*4cd92098Szrj #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 632*4cd92098Szrj #define MC_SEQ_MISC0_REV_ID_VALUE 1 633*4cd92098Szrj #define MC_SEQ_MISC0_GDDR5_SHIFT 28 634*4cd92098Szrj #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 635*4cd92098Szrj #define MC_SEQ_MISC0_GDDR5_VALUE 5 636*4cd92098Szrj #define MC_SEQ_MISC1 0x2a04 637*4cd92098Szrj #define MC_SEQ_RESERVE_M 0x2a08 638*4cd92098Szrj #define MC_PMG_CMD_EMRS 0x2a0c 639*4cd92098Szrj 64057e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 64157e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_DATA 0x2a48 64257e252bfSMichael Neumann 643*4cd92098Szrj #define MC_SEQ_MISC5 0x2a54 644*4cd92098Szrj #define MC_SEQ_MISC6 0x2a58 645*4cd92098Szrj 646*4cd92098Szrj #define MC_SEQ_MISC7 0x2a64 647*4cd92098Szrj 648*4cd92098Szrj #define MC_SEQ_RAS_TIMING_LP 0x2a6c 649*4cd92098Szrj #define MC_SEQ_CAS_TIMING_LP 0x2a70 650*4cd92098Szrj #define MC_SEQ_MISC_TIMING_LP 0x2a74 651*4cd92098Szrj #define MC_SEQ_MISC_TIMING2_LP 0x2a78 652*4cd92098Szrj #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 653*4cd92098Szrj #define MC_SEQ_WR_CTL_D1_LP 0x2a80 654*4cd92098Szrj #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 655*4cd92098Szrj #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 656*4cd92098Szrj 657*4cd92098Szrj #define MC_PMG_CMD_MRS 0x2aac 658*4cd92098Szrj 659*4cd92098Szrj #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 660*4cd92098Szrj #define MC_SEQ_RD_CTL_D1_LP 0x2b20 661*4cd92098Szrj 662*4cd92098Szrj #define MC_PMG_CMD_MRS1 0x2b44 663*4cd92098Szrj #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 664*4cd92098Szrj #define MC_SEQ_PMG_TIMING_LP 0x2b4c 665*4cd92098Szrj 666*4cd92098Szrj #define MC_SEQ_WR_CTL_2 0x2b54 667*4cd92098Szrj #define MC_SEQ_WR_CTL_2_LP 0x2b58 668*4cd92098Szrj #define MC_PMG_CMD_MRS2 0x2b5c 669*4cd92098Szrj #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 670*4cd92098Szrj 671*4cd92098Szrj #define MCLK_PWRMGT_CNTL 0x2ba0 672*4cd92098Szrj # define DLL_SPEED(x) ((x) << 0) 673*4cd92098Szrj # define DLL_SPEED_MASK (0x1f << 0) 674*4cd92098Szrj # define DLL_READY (1 << 6) 675*4cd92098Szrj # define MC_INT_CNTL (1 << 7) 676*4cd92098Szrj # define MRDCK0_PDNB (1 << 8) 677*4cd92098Szrj # define MRDCK1_PDNB (1 << 9) 678*4cd92098Szrj # define MRDCK0_RESET (1 << 16) 679*4cd92098Szrj # define MRDCK1_RESET (1 << 17) 680*4cd92098Szrj # define DLL_READY_READ (1 << 24) 681*4cd92098Szrj #define DLL_CNTL 0x2ba4 682*4cd92098Szrj # define MRDCK0_BYPASS (1 << 24) 683*4cd92098Szrj # define MRDCK1_BYPASS (1 << 25) 684*4cd92098Szrj 685*4cd92098Szrj #define MPLL_FUNC_CNTL 0x2bb4 686*4cd92098Szrj #define BWCTRL(x) ((x) << 20) 687*4cd92098Szrj #define BWCTRL_MASK (0xff << 20) 688*4cd92098Szrj #define MPLL_FUNC_CNTL_1 0x2bb8 689*4cd92098Szrj #define VCO_MODE(x) ((x) << 0) 690*4cd92098Szrj #define VCO_MODE_MASK (3 << 0) 691*4cd92098Szrj #define CLKFRAC(x) ((x) << 4) 692*4cd92098Szrj #define CLKFRAC_MASK (0xfff << 4) 693*4cd92098Szrj #define CLKF(x) ((x) << 16) 694*4cd92098Szrj #define CLKF_MASK (0xfff << 16) 695*4cd92098Szrj #define MPLL_FUNC_CNTL_2 0x2bbc 696*4cd92098Szrj #define MPLL_AD_FUNC_CNTL 0x2bc0 697*4cd92098Szrj #define YCLK_POST_DIV(x) ((x) << 0) 698*4cd92098Szrj #define YCLK_POST_DIV_MASK (7 << 0) 699*4cd92098Szrj #define MPLL_DQ_FUNC_CNTL 0x2bc4 700*4cd92098Szrj #define YCLK_SEL(x) ((x) << 4) 701*4cd92098Szrj #define YCLK_SEL_MASK (1 << 4) 702*4cd92098Szrj 703*4cd92098Szrj #define MPLL_SS1 0x2bcc 704*4cd92098Szrj #define CLKV(x) ((x) << 0) 705*4cd92098Szrj #define CLKV_MASK (0x3ffffff << 0) 706*4cd92098Szrj #define MPLL_SS2 0x2bd0 707*4cd92098Szrj #define CLKS(x) ((x) << 0) 708*4cd92098Szrj #define CLKS_MASK (0xfff << 0) 709*4cd92098Szrj 71057e252bfSMichael Neumann #define HDP_HOST_PATH_CNTL 0x2C00 711*4cd92098Szrj #define CLOCK_GATING_DIS (1 << 23) 71257e252bfSMichael Neumann #define HDP_NONSURFACE_BASE 0x2C04 71357e252bfSMichael Neumann #define HDP_NONSURFACE_INFO 0x2C08 71457e252bfSMichael Neumann #define HDP_NONSURFACE_SIZE 0x2C0C 71557e252bfSMichael Neumann 71657e252bfSMichael Neumann #define HDP_ADDR_CONFIG 0x2F48 71757e252bfSMichael Neumann #define HDP_MISC_CNTL 0x2F4C 71857e252bfSMichael Neumann #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 719*4cd92098Szrj #define HDP_MEM_POWER_LS 0x2F50 720*4cd92098Szrj #define HDP_LS_ENABLE (1 << 0) 721*4cd92098Szrj 722*4cd92098Szrj #define ATC_MISC_CG 0x3350 723*4cd92098Szrj 724*4cd92098Szrj #define MC_SEQ_CNTL_3 0x3600 725*4cd92098Szrj # define CAC_EN (1 << 31) 726*4cd92098Szrj #define MC_SEQ_G5PDX_CTRL 0x3604 727*4cd92098Szrj #define MC_SEQ_G5PDX_CTRL_LP 0x3608 728*4cd92098Szrj #define MC_SEQ_G5PDX_CMD0 0x360c 729*4cd92098Szrj #define MC_SEQ_G5PDX_CMD0_LP 0x3610 730*4cd92098Szrj #define MC_SEQ_G5PDX_CMD1 0x3614 731*4cd92098Szrj #define MC_SEQ_G5PDX_CMD1_LP 0x3618 732*4cd92098Szrj 733*4cd92098Szrj #define MC_SEQ_PMG_DVS_CTL 0x3628 734*4cd92098Szrj #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 735*4cd92098Szrj #define MC_SEQ_PMG_DVS_CMD 0x3630 736*4cd92098Szrj #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 737*4cd92098Szrj #define MC_SEQ_DLL_STBY 0x3638 738*4cd92098Szrj #define MC_SEQ_DLL_STBY_LP 0x363c 73957e252bfSMichael Neumann 74057e252bfSMichael Neumann #define IH_RB_CNTL 0x3e00 74157e252bfSMichael Neumann # define IH_RB_ENABLE (1 << 0) 74257e252bfSMichael Neumann # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 74357e252bfSMichael Neumann # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 74457e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 74557e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 74657e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 74757e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 74857e252bfSMichael Neumann #define IH_RB_BASE 0x3e04 74957e252bfSMichael Neumann #define IH_RB_RPTR 0x3e08 75057e252bfSMichael Neumann #define IH_RB_WPTR 0x3e0c 75157e252bfSMichael Neumann # define RB_OVERFLOW (1 << 0) 75257e252bfSMichael Neumann # define WPTR_OFFSET_MASK 0x3fffc 75357e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_HI 0x3e10 75457e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_LO 0x3e14 75557e252bfSMichael Neumann #define IH_CNTL 0x3e18 75657e252bfSMichael Neumann # define ENABLE_INTR (1 << 0) 75757e252bfSMichael Neumann # define IH_MC_SWAP(x) ((x) << 1) 75857e252bfSMichael Neumann # define IH_MC_SWAP_NONE 0 75957e252bfSMichael Neumann # define IH_MC_SWAP_16BIT 1 76057e252bfSMichael Neumann # define IH_MC_SWAP_32BIT 2 76157e252bfSMichael Neumann # define IH_MC_SWAP_64BIT 3 76257e252bfSMichael Neumann # define RPTR_REARM (1 << 4) 76357e252bfSMichael Neumann # define MC_WRREQ_CREDIT(x) ((x) << 15) 76457e252bfSMichael Neumann # define MC_WR_CLEAN_CNT(x) ((x) << 20) 76557e252bfSMichael Neumann # define MC_VMID(x) ((x) << 25) 76657e252bfSMichael Neumann 767*4cd92098Szrj #define BIF_LNCNT_RESET 0x5220 768*4cd92098Szrj # define RESET_LNCNT_EN (1 << 0) 769*4cd92098Szrj 77057e252bfSMichael Neumann #define CONFIG_MEMSIZE 0x5428 77157e252bfSMichael Neumann 77257e252bfSMichael Neumann #define INTERRUPT_CNTL 0x5468 77357e252bfSMichael Neumann # define IH_DUMMY_RD_OVERRIDE (1 << 0) 77457e252bfSMichael Neumann # define IH_DUMMY_RD_EN (1 << 1) 77557e252bfSMichael Neumann # define IH_REQ_NONSNOOP_EN (1 << 3) 77657e252bfSMichael Neumann # define GEN_IH_INT_EN (1 << 8) 77757e252bfSMichael Neumann #define INTERRUPT_CNTL2 0x546c 77857e252bfSMichael Neumann 77957e252bfSMichael Neumann #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 78057e252bfSMichael Neumann 78157e252bfSMichael Neumann #define BIF_FB_EN 0x5490 78257e252bfSMichael Neumann #define FB_READ_EN (1 << 0) 78357e252bfSMichael Neumann #define FB_WRITE_EN (1 << 1) 78457e252bfSMichael Neumann 78557e252bfSMichael Neumann #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 78657e252bfSMichael Neumann 78757e252bfSMichael Neumann #define GPU_HDP_FLUSH_REQ 0x54DC 78857e252bfSMichael Neumann #define GPU_HDP_FLUSH_DONE 0x54E0 78957e252bfSMichael Neumann #define CP0 (1 << 0) 79057e252bfSMichael Neumann #define CP1 (1 << 1) 79157e252bfSMichael Neumann #define CP2 (1 << 2) 79257e252bfSMichael Neumann #define CP3 (1 << 3) 79357e252bfSMichael Neumann #define CP4 (1 << 4) 79457e252bfSMichael Neumann #define CP5 (1 << 5) 79557e252bfSMichael Neumann #define CP6 (1 << 6) 79657e252bfSMichael Neumann #define CP7 (1 << 7) 79757e252bfSMichael Neumann #define CP8 (1 << 8) 79857e252bfSMichael Neumann #define CP9 (1 << 9) 79957e252bfSMichael Neumann #define SDMA0 (1 << 10) 80057e252bfSMichael Neumann #define SDMA1 (1 << 11) 80157e252bfSMichael Neumann 80257e252bfSMichael Neumann /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 80357e252bfSMichael Neumann #define LB_MEMORY_CTRL 0x6b04 80457e252bfSMichael Neumann #define LB_MEMORY_SIZE(x) ((x) << 0) 80557e252bfSMichael Neumann #define LB_MEMORY_CONFIG(x) ((x) << 20) 80657e252bfSMichael Neumann 80757e252bfSMichael Neumann #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 80857e252bfSMichael Neumann # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 80957e252bfSMichael Neumann #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 81057e252bfSMichael Neumann # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 81157e252bfSMichael Neumann # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 81257e252bfSMichael Neumann 81357e252bfSMichael Neumann /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 81457e252bfSMichael Neumann #define LB_VLINE_STATUS 0x6b24 81557e252bfSMichael Neumann # define VLINE_OCCURRED (1 << 0) 81657e252bfSMichael Neumann # define VLINE_ACK (1 << 4) 81757e252bfSMichael Neumann # define VLINE_STAT (1 << 12) 81857e252bfSMichael Neumann # define VLINE_INTERRUPT (1 << 16) 81957e252bfSMichael Neumann # define VLINE_INTERRUPT_TYPE (1 << 17) 82057e252bfSMichael Neumann /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 82157e252bfSMichael Neumann #define LB_VBLANK_STATUS 0x6b2c 82257e252bfSMichael Neumann # define VBLANK_OCCURRED (1 << 0) 82357e252bfSMichael Neumann # define VBLANK_ACK (1 << 4) 82457e252bfSMichael Neumann # define VBLANK_STAT (1 << 12) 82557e252bfSMichael Neumann # define VBLANK_INTERRUPT (1 << 16) 82657e252bfSMichael Neumann # define VBLANK_INTERRUPT_TYPE (1 << 17) 82757e252bfSMichael Neumann 82857e252bfSMichael Neumann /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 82957e252bfSMichael Neumann #define LB_INTERRUPT_MASK 0x6b20 83057e252bfSMichael Neumann # define VBLANK_INTERRUPT_MASK (1 << 0) 83157e252bfSMichael Neumann # define VLINE_INTERRUPT_MASK (1 << 4) 83257e252bfSMichael Neumann # define VLINE2_INTERRUPT_MASK (1 << 8) 83357e252bfSMichael Neumann 83457e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS 0x60f4 83557e252bfSMichael Neumann # define LB_D1_VLINE_INTERRUPT (1 << 2) 83657e252bfSMichael Neumann # define LB_D1_VBLANK_INTERRUPT (1 << 3) 83757e252bfSMichael Neumann # define DC_HPD1_INTERRUPT (1 << 17) 83857e252bfSMichael Neumann # define DC_HPD1_RX_INTERRUPT (1 << 18) 83957e252bfSMichael Neumann # define DACA_AUTODETECT_INTERRUPT (1 << 22) 84057e252bfSMichael Neumann # define DACB_AUTODETECT_INTERRUPT (1 << 23) 84157e252bfSMichael Neumann # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 84257e252bfSMichael Neumann # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 84357e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 84457e252bfSMichael Neumann # define LB_D2_VLINE_INTERRUPT (1 << 2) 84557e252bfSMichael Neumann # define LB_D2_VBLANK_INTERRUPT (1 << 3) 84657e252bfSMichael Neumann # define DC_HPD2_INTERRUPT (1 << 17) 84757e252bfSMichael Neumann # define DC_HPD2_RX_INTERRUPT (1 << 18) 84857e252bfSMichael Neumann # define DISP_TIMER_INTERRUPT (1 << 24) 84957e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 85057e252bfSMichael Neumann # define LB_D3_VLINE_INTERRUPT (1 << 2) 85157e252bfSMichael Neumann # define LB_D3_VBLANK_INTERRUPT (1 << 3) 85257e252bfSMichael Neumann # define DC_HPD3_INTERRUPT (1 << 17) 85357e252bfSMichael Neumann # define DC_HPD3_RX_INTERRUPT (1 << 18) 85457e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 85557e252bfSMichael Neumann # define LB_D4_VLINE_INTERRUPT (1 << 2) 85657e252bfSMichael Neumann # define LB_D4_VBLANK_INTERRUPT (1 << 3) 85757e252bfSMichael Neumann # define DC_HPD4_INTERRUPT (1 << 17) 85857e252bfSMichael Neumann # define DC_HPD4_RX_INTERRUPT (1 << 18) 85957e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 86057e252bfSMichael Neumann # define LB_D5_VLINE_INTERRUPT (1 << 2) 86157e252bfSMichael Neumann # define LB_D5_VBLANK_INTERRUPT (1 << 3) 86257e252bfSMichael Neumann # define DC_HPD5_INTERRUPT (1 << 17) 86357e252bfSMichael Neumann # define DC_HPD5_RX_INTERRUPT (1 << 18) 86457e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 86557e252bfSMichael Neumann # define LB_D6_VLINE_INTERRUPT (1 << 2) 86657e252bfSMichael Neumann # define LB_D6_VBLANK_INTERRUPT (1 << 3) 86757e252bfSMichael Neumann # define DC_HPD6_INTERRUPT (1 << 17) 86857e252bfSMichael Neumann # define DC_HPD6_RX_INTERRUPT (1 << 18) 86957e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 87057e252bfSMichael Neumann 87157e252bfSMichael Neumann #define DAC_AUTODETECT_INT_CONTROL 0x67c8 87257e252bfSMichael Neumann 87357e252bfSMichael Neumann #define DC_HPD1_INT_STATUS 0x601c 87457e252bfSMichael Neumann #define DC_HPD2_INT_STATUS 0x6028 87557e252bfSMichael Neumann #define DC_HPD3_INT_STATUS 0x6034 87657e252bfSMichael Neumann #define DC_HPD4_INT_STATUS 0x6040 87757e252bfSMichael Neumann #define DC_HPD5_INT_STATUS 0x604c 87857e252bfSMichael Neumann #define DC_HPD6_INT_STATUS 0x6058 87957e252bfSMichael Neumann # define DC_HPDx_INT_STATUS (1 << 0) 88057e252bfSMichael Neumann # define DC_HPDx_SENSE (1 << 1) 88157e252bfSMichael Neumann # define DC_HPDx_SENSE_DELAYED (1 << 4) 88257e252bfSMichael Neumann # define DC_HPDx_RX_INT_STATUS (1 << 8) 88357e252bfSMichael Neumann 88457e252bfSMichael Neumann #define DC_HPD1_INT_CONTROL 0x6020 88557e252bfSMichael Neumann #define DC_HPD2_INT_CONTROL 0x602c 88657e252bfSMichael Neumann #define DC_HPD3_INT_CONTROL 0x6038 88757e252bfSMichael Neumann #define DC_HPD4_INT_CONTROL 0x6044 88857e252bfSMichael Neumann #define DC_HPD5_INT_CONTROL 0x6050 88957e252bfSMichael Neumann #define DC_HPD6_INT_CONTROL 0x605c 89057e252bfSMichael Neumann # define DC_HPDx_INT_ACK (1 << 0) 89157e252bfSMichael Neumann # define DC_HPDx_INT_POLARITY (1 << 8) 89257e252bfSMichael Neumann # define DC_HPDx_INT_EN (1 << 16) 89357e252bfSMichael Neumann # define DC_HPDx_RX_INT_ACK (1 << 20) 89457e252bfSMichael Neumann # define DC_HPDx_RX_INT_EN (1 << 24) 89557e252bfSMichael Neumann 89657e252bfSMichael Neumann #define DC_HPD1_CONTROL 0x6024 89757e252bfSMichael Neumann #define DC_HPD2_CONTROL 0x6030 89857e252bfSMichael Neumann #define DC_HPD3_CONTROL 0x603c 89957e252bfSMichael Neumann #define DC_HPD4_CONTROL 0x6048 90057e252bfSMichael Neumann #define DC_HPD5_CONTROL 0x6054 90157e252bfSMichael Neumann #define DC_HPD6_CONTROL 0x6060 90257e252bfSMichael Neumann # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 90357e252bfSMichael Neumann # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 90457e252bfSMichael Neumann # define DC_HPDx_EN (1 << 28) 90557e252bfSMichael Neumann 906*4cd92098Szrj #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 907*4cd92098Szrj # define STUTTER_ENABLE (1 << 0) 908*4cd92098Szrj 90957e252bfSMichael Neumann #define GRBM_CNTL 0x8000 91057e252bfSMichael Neumann #define GRBM_READ_TIMEOUT(x) ((x) << 0) 91157e252bfSMichael Neumann 91257e252bfSMichael Neumann #define GRBM_STATUS2 0x8008 91357e252bfSMichael Neumann #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 91457e252bfSMichael Neumann #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 91557e252bfSMichael Neumann #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 91657e252bfSMichael Neumann #define ME1PIPE0_RQ_PENDING (1 << 6) 91757e252bfSMichael Neumann #define ME1PIPE1_RQ_PENDING (1 << 7) 91857e252bfSMichael Neumann #define ME1PIPE2_RQ_PENDING (1 << 8) 91957e252bfSMichael Neumann #define ME1PIPE3_RQ_PENDING (1 << 9) 92057e252bfSMichael Neumann #define ME2PIPE0_RQ_PENDING (1 << 10) 92157e252bfSMichael Neumann #define ME2PIPE1_RQ_PENDING (1 << 11) 92257e252bfSMichael Neumann #define ME2PIPE2_RQ_PENDING (1 << 12) 92357e252bfSMichael Neumann #define ME2PIPE3_RQ_PENDING (1 << 13) 92457e252bfSMichael Neumann #define RLC_RQ_PENDING (1 << 14) 92557e252bfSMichael Neumann #define RLC_BUSY (1 << 24) 92657e252bfSMichael Neumann #define TC_BUSY (1 << 25) 92757e252bfSMichael Neumann #define CPF_BUSY (1 << 28) 92857e252bfSMichael Neumann #define CPC_BUSY (1 << 29) 92957e252bfSMichael Neumann #define CPG_BUSY (1 << 30) 93057e252bfSMichael Neumann 93157e252bfSMichael Neumann #define GRBM_STATUS 0x8010 93257e252bfSMichael Neumann #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 93357e252bfSMichael Neumann #define SRBM_RQ_PENDING (1 << 5) 93457e252bfSMichael Neumann #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 93557e252bfSMichael Neumann #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 93657e252bfSMichael Neumann #define GDS_DMA_RQ_PENDING (1 << 9) 93757e252bfSMichael Neumann #define DB_CLEAN (1 << 12) 93857e252bfSMichael Neumann #define CB_CLEAN (1 << 13) 93957e252bfSMichael Neumann #define TA_BUSY (1 << 14) 94057e252bfSMichael Neumann #define GDS_BUSY (1 << 15) 94157e252bfSMichael Neumann #define WD_BUSY_NO_DMA (1 << 16) 94257e252bfSMichael Neumann #define VGT_BUSY (1 << 17) 94357e252bfSMichael Neumann #define IA_BUSY_NO_DMA (1 << 18) 94457e252bfSMichael Neumann #define IA_BUSY (1 << 19) 94557e252bfSMichael Neumann #define SX_BUSY (1 << 20) 94657e252bfSMichael Neumann #define WD_BUSY (1 << 21) 94757e252bfSMichael Neumann #define SPI_BUSY (1 << 22) 94857e252bfSMichael Neumann #define BCI_BUSY (1 << 23) 94957e252bfSMichael Neumann #define SC_BUSY (1 << 24) 95057e252bfSMichael Neumann #define PA_BUSY (1 << 25) 95157e252bfSMichael Neumann #define DB_BUSY (1 << 26) 95257e252bfSMichael Neumann #define CP_COHERENCY_BUSY (1 << 28) 95357e252bfSMichael Neumann #define CP_BUSY (1 << 29) 95457e252bfSMichael Neumann #define CB_BUSY (1 << 30) 95557e252bfSMichael Neumann #define GUI_ACTIVE (1 << 31) 95657e252bfSMichael Neumann #define GRBM_STATUS_SE0 0x8014 95757e252bfSMichael Neumann #define GRBM_STATUS_SE1 0x8018 95857e252bfSMichael Neumann #define GRBM_STATUS_SE2 0x8038 95957e252bfSMichael Neumann #define GRBM_STATUS_SE3 0x803C 96057e252bfSMichael Neumann #define SE_DB_CLEAN (1 << 1) 96157e252bfSMichael Neumann #define SE_CB_CLEAN (1 << 2) 96257e252bfSMichael Neumann #define SE_BCI_BUSY (1 << 22) 96357e252bfSMichael Neumann #define SE_VGT_BUSY (1 << 23) 96457e252bfSMichael Neumann #define SE_PA_BUSY (1 << 24) 96557e252bfSMichael Neumann #define SE_TA_BUSY (1 << 25) 96657e252bfSMichael Neumann #define SE_SX_BUSY (1 << 26) 96757e252bfSMichael Neumann #define SE_SPI_BUSY (1 << 27) 96857e252bfSMichael Neumann #define SE_SC_BUSY (1 << 29) 96957e252bfSMichael Neumann #define SE_DB_BUSY (1 << 30) 97057e252bfSMichael Neumann #define SE_CB_BUSY (1 << 31) 97157e252bfSMichael Neumann 97257e252bfSMichael Neumann #define GRBM_SOFT_RESET 0x8020 97357e252bfSMichael Neumann #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 97457e252bfSMichael Neumann #define SOFT_RESET_RLC (1 << 2) /* RLC */ 97557e252bfSMichael Neumann #define SOFT_RESET_GFX (1 << 16) /* GFX */ 97657e252bfSMichael Neumann #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 97757e252bfSMichael Neumann #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 97857e252bfSMichael Neumann #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 97957e252bfSMichael Neumann 98057e252bfSMichael Neumann #define GRBM_INT_CNTL 0x8060 98157e252bfSMichael Neumann # define RDERR_INT_ENABLE (1 << 0) 98257e252bfSMichael Neumann # define GUI_IDLE_INT_ENABLE (1 << 19) 98357e252bfSMichael Neumann 98457e252bfSMichael Neumann #define CP_CPC_STATUS 0x8210 98557e252bfSMichael Neumann #define CP_CPC_BUSY_STAT 0x8214 98657e252bfSMichael Neumann #define CP_CPC_STALLED_STAT1 0x8218 98757e252bfSMichael Neumann #define CP_CPF_STATUS 0x821c 98857e252bfSMichael Neumann #define CP_CPF_BUSY_STAT 0x8220 98957e252bfSMichael Neumann #define CP_CPF_STALLED_STAT1 0x8224 99057e252bfSMichael Neumann 99157e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 99257e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 99357e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 99457e252bfSMichael Neumann 99557e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 99657e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 99757e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 99857e252bfSMichael Neumann 99957e252bfSMichael Neumann #define CP_STALLED_STAT3 0x8670 100057e252bfSMichael Neumann #define CP_STALLED_STAT1 0x8674 100157e252bfSMichael Neumann #define CP_STALLED_STAT2 0x8678 100257e252bfSMichael Neumann 100357e252bfSMichael Neumann #define CP_STAT 0x8680 100457e252bfSMichael Neumann 100557e252bfSMichael Neumann #define CP_ME_CNTL 0x86D8 100657e252bfSMichael Neumann #define CP_CE_HALT (1 << 24) 100757e252bfSMichael Neumann #define CP_PFP_HALT (1 << 26) 100857e252bfSMichael Neumann #define CP_ME_HALT (1 << 28) 100957e252bfSMichael Neumann 101057e252bfSMichael Neumann #define CP_RB0_RPTR 0x8700 101157e252bfSMichael Neumann #define CP_RB_WPTR_DELAY 0x8704 1012*4cd92098Szrj #define CP_RB_WPTR_POLL_CNTL 0x8708 1013*4cd92098Szrj #define IDLE_POLL_COUNT(x) ((x) << 16) 1014*4cd92098Szrj #define IDLE_POLL_COUNT_MASK (0xffff << 16) 101557e252bfSMichael Neumann 101657e252bfSMichael Neumann #define CP_MEQ_THRESHOLDS 0x8764 101757e252bfSMichael Neumann #define MEQ1_START(x) ((x) << 0) 101857e252bfSMichael Neumann #define MEQ2_START(x) ((x) << 8) 101957e252bfSMichael Neumann 102057e252bfSMichael Neumann #define VGT_VTX_VECT_EJECT_REG 0x88B0 102157e252bfSMichael Neumann 102257e252bfSMichael Neumann #define VGT_CACHE_INVALIDATION 0x88C4 102357e252bfSMichael Neumann #define CACHE_INVALIDATION(x) ((x) << 0) 102457e252bfSMichael Neumann #define VC_ONLY 0 102557e252bfSMichael Neumann #define TC_ONLY 1 102657e252bfSMichael Neumann #define VC_AND_TC 2 102757e252bfSMichael Neumann #define AUTO_INVLD_EN(x) ((x) << 6) 102857e252bfSMichael Neumann #define NO_AUTO 0 102957e252bfSMichael Neumann #define ES_AUTO 1 103057e252bfSMichael Neumann #define GS_AUTO 2 103157e252bfSMichael Neumann #define ES_AND_GS_AUTO 3 103257e252bfSMichael Neumann 103357e252bfSMichael Neumann #define VGT_GS_VERTEX_REUSE 0x88D4 103457e252bfSMichael Neumann 103557e252bfSMichael Neumann #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 103657e252bfSMichael Neumann #define INACTIVE_CUS_MASK 0xFFFF0000 103757e252bfSMichael Neumann #define INACTIVE_CUS_SHIFT 16 103857e252bfSMichael Neumann #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 103957e252bfSMichael Neumann 104057e252bfSMichael Neumann #define PA_CL_ENHANCE 0x8A14 104157e252bfSMichael Neumann #define CLIP_VTX_REORDER_ENA (1 << 0) 104257e252bfSMichael Neumann #define NUM_CLIP_SEQ(x) ((x) << 1) 104357e252bfSMichael Neumann 104457e252bfSMichael Neumann #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 104557e252bfSMichael Neumann #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 104657e252bfSMichael Neumann #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 104757e252bfSMichael Neumann 104857e252bfSMichael Neumann #define PA_SC_FIFO_SIZE 0x8BCC 104957e252bfSMichael Neumann #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 105057e252bfSMichael Neumann #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 105157e252bfSMichael Neumann #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 105257e252bfSMichael Neumann #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 105357e252bfSMichael Neumann 105457e252bfSMichael Neumann #define PA_SC_ENHANCE 0x8BF0 105557e252bfSMichael Neumann #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 105657e252bfSMichael Neumann #define DISABLE_PA_SC_GUIDANCE (1 << 13) 105757e252bfSMichael Neumann 105857e252bfSMichael Neumann #define SQ_CONFIG 0x8C00 105957e252bfSMichael Neumann 106057e252bfSMichael Neumann #define SH_MEM_BASES 0x8C28 106157e252bfSMichael Neumann /* if PTR32, these are the bases for scratch and lds */ 106257e252bfSMichael Neumann #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 106357e252bfSMichael Neumann #define SHARED_BASE(x) ((x) << 16) /* LDS */ 106457e252bfSMichael Neumann #define SH_MEM_APE1_BASE 0x8C2C 106557e252bfSMichael Neumann /* if PTR32, this is the base location of GPUVM */ 106657e252bfSMichael Neumann #define SH_MEM_APE1_LIMIT 0x8C30 106757e252bfSMichael Neumann /* if PTR32, this is the upper limit of GPUVM */ 106857e252bfSMichael Neumann #define SH_MEM_CONFIG 0x8C34 106957e252bfSMichael Neumann #define PTR32 (1 << 0) 107057e252bfSMichael Neumann #define ALIGNMENT_MODE(x) ((x) << 2) 107157e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD 0 107257e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 107357e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_STRICT 2 107457e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 107557e252bfSMichael Neumann #define DEFAULT_MTYPE(x) ((x) << 4) 107657e252bfSMichael Neumann #define APE1_MTYPE(x) ((x) << 7) 107757e252bfSMichael Neumann 107857e252bfSMichael Neumann #define SX_DEBUG_1 0x9060 107957e252bfSMichael Neumann 108057e252bfSMichael Neumann #define SPI_CONFIG_CNTL 0x9100 108157e252bfSMichael Neumann 108257e252bfSMichael Neumann #define SPI_CONFIG_CNTL_1 0x913C 108357e252bfSMichael Neumann #define VTX_DONE_DELAY(x) ((x) << 0) 108457e252bfSMichael Neumann #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 108557e252bfSMichael Neumann 108657e252bfSMichael Neumann #define TA_CNTL_AUX 0x9508 108757e252bfSMichael Neumann 108857e252bfSMichael Neumann #define DB_DEBUG 0x9830 108957e252bfSMichael Neumann #define DB_DEBUG2 0x9834 109057e252bfSMichael Neumann #define DB_DEBUG3 0x9838 109157e252bfSMichael Neumann 109257e252bfSMichael Neumann #define CC_RB_BACKEND_DISABLE 0x98F4 109357e252bfSMichael Neumann #define BACKEND_DISABLE(x) ((x) << 16) 109457e252bfSMichael Neumann #define GB_ADDR_CONFIG 0x98F8 109557e252bfSMichael Neumann #define NUM_PIPES(x) ((x) << 0) 109657e252bfSMichael Neumann #define NUM_PIPES_MASK 0x00000007 109757e252bfSMichael Neumann #define NUM_PIPES_SHIFT 0 109857e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 109957e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 110057e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_SHIFT 4 110157e252bfSMichael Neumann #define NUM_SHADER_ENGINES(x) ((x) << 12) 110257e252bfSMichael Neumann #define NUM_SHADER_ENGINES_MASK 0x00003000 110357e252bfSMichael Neumann #define NUM_SHADER_ENGINES_SHIFT 12 110457e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 110557e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 110657e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 110757e252bfSMichael Neumann #define ROW_SIZE(x) ((x) << 28) 110857e252bfSMichael Neumann #define ROW_SIZE_MASK 0x30000000 110957e252bfSMichael Neumann #define ROW_SIZE_SHIFT 28 111057e252bfSMichael Neumann 111157e252bfSMichael Neumann #define GB_TILE_MODE0 0x9910 111257e252bfSMichael Neumann # define ARRAY_MODE(x) ((x) << 2) 111357e252bfSMichael Neumann # define ARRAY_LINEAR_GENERAL 0 111457e252bfSMichael Neumann # define ARRAY_LINEAR_ALIGNED 1 111557e252bfSMichael Neumann # define ARRAY_1D_TILED_THIN1 2 111657e252bfSMichael Neumann # define ARRAY_2D_TILED_THIN1 4 111757e252bfSMichael Neumann # define ARRAY_PRT_TILED_THIN1 5 111857e252bfSMichael Neumann # define ARRAY_PRT_2D_TILED_THIN1 6 111957e252bfSMichael Neumann # define PIPE_CONFIG(x) ((x) << 6) 112057e252bfSMichael Neumann # define ADDR_SURF_P2 0 112157e252bfSMichael Neumann # define ADDR_SURF_P4_8x16 4 112257e252bfSMichael Neumann # define ADDR_SURF_P4_16x16 5 112357e252bfSMichael Neumann # define ADDR_SURF_P4_16x32 6 112457e252bfSMichael Neumann # define ADDR_SURF_P4_32x32 7 112557e252bfSMichael Neumann # define ADDR_SURF_P8_16x16_8x16 8 112657e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_8x16 9 112757e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_8x16 10 112857e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_16x16 11 112957e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x16 12 113057e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x32 13 113157e252bfSMichael Neumann # define ADDR_SURF_P8_32x64_32x32 14 113257e252bfSMichael Neumann # define TILE_SPLIT(x) ((x) << 11) 113357e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_64B 0 113457e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_128B 1 113557e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_256B 2 113657e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_512B 3 113757e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_1KB 4 113857e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_2KB 5 113957e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_4KB 6 114057e252bfSMichael Neumann # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 114157e252bfSMichael Neumann # define ADDR_SURF_DISPLAY_MICRO_TILING 0 114257e252bfSMichael Neumann # define ADDR_SURF_THIN_MICRO_TILING 1 114357e252bfSMichael Neumann # define ADDR_SURF_DEPTH_MICRO_TILING 2 114457e252bfSMichael Neumann # define ADDR_SURF_ROTATED_MICRO_TILING 3 114557e252bfSMichael Neumann # define SAMPLE_SPLIT(x) ((x) << 25) 114657e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_1 0 114757e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_2 1 114857e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_4 2 114957e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_8 3 115057e252bfSMichael Neumann 115157e252bfSMichael Neumann #define GB_MACROTILE_MODE0 0x9990 115257e252bfSMichael Neumann # define BANK_WIDTH(x) ((x) << 0) 115357e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_1 0 115457e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_2 1 115557e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_4 2 115657e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_8 3 115757e252bfSMichael Neumann # define BANK_HEIGHT(x) ((x) << 2) 115857e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_1 0 115957e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_2 1 116057e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_4 2 116157e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_8 3 116257e252bfSMichael Neumann # define MACRO_TILE_ASPECT(x) ((x) << 4) 116357e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_1 0 116457e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_2 1 116557e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_4 2 116657e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_8 3 116757e252bfSMichael Neumann # define NUM_BANKS(x) ((x) << 6) 116857e252bfSMichael Neumann # define ADDR_SURF_2_BANK 0 116957e252bfSMichael Neumann # define ADDR_SURF_4_BANK 1 117057e252bfSMichael Neumann # define ADDR_SURF_8_BANK 2 117157e252bfSMichael Neumann # define ADDR_SURF_16_BANK 3 117257e252bfSMichael Neumann 117357e252bfSMichael Neumann #define CB_HW_CONTROL 0x9A10 117457e252bfSMichael Neumann 117557e252bfSMichael Neumann #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 117657e252bfSMichael Neumann #define BACKEND_DISABLE_MASK 0x00FF0000 117757e252bfSMichael Neumann #define BACKEND_DISABLE_SHIFT 16 117857e252bfSMichael Neumann 117957e252bfSMichael Neumann #define TCP_CHAN_STEER_LO 0xac0c 118057e252bfSMichael Neumann #define TCP_CHAN_STEER_HI 0xac10 118157e252bfSMichael Neumann 118257e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY0 0xAC68 118357e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 118457e252bfSMichael Neumann #define TC_CFG_L1_STORE_POLICY 0xAC70 118557e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY0 0xAC74 118657e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY1 0xAC78 118757e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY0 0xAC7C 118857e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY1 0xAC80 118957e252bfSMichael Neumann #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 119057e252bfSMichael Neumann #define TC_CFG_L1_VOLATILE 0xAC88 119157e252bfSMichael Neumann #define TC_CFG_L2_VOLATILE 0xAC8C 119257e252bfSMichael Neumann 119357e252bfSMichael Neumann #define CP_RB0_BASE 0xC100 119457e252bfSMichael Neumann #define CP_RB0_CNTL 0xC104 119557e252bfSMichael Neumann #define RB_BUFSZ(x) ((x) << 0) 119657e252bfSMichael Neumann #define RB_BLKSZ(x) ((x) << 8) 119757e252bfSMichael Neumann #define BUF_SWAP_32BIT (2 << 16) 119857e252bfSMichael Neumann #define RB_NO_UPDATE (1 << 27) 119957e252bfSMichael Neumann #define RB_RPTR_WR_ENA (1 << 31) 120057e252bfSMichael Neumann 120157e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR 0xC10C 120257e252bfSMichael Neumann #define RB_RPTR_SWAP_32BIT (2 << 0) 120357e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR_HI 0xC110 120457e252bfSMichael Neumann #define CP_RB0_WPTR 0xC114 120557e252bfSMichael Neumann 120657e252bfSMichael Neumann #define CP_DEVICE_ID 0xC12C 120757e252bfSMichael Neumann #define CP_ENDIAN_SWAP 0xC140 120857e252bfSMichael Neumann #define CP_RB_VMID 0xC144 120957e252bfSMichael Neumann 121057e252bfSMichael Neumann #define CP_PFP_UCODE_ADDR 0xC150 121157e252bfSMichael Neumann #define CP_PFP_UCODE_DATA 0xC154 121257e252bfSMichael Neumann #define CP_ME_RAM_RADDR 0xC158 121357e252bfSMichael Neumann #define CP_ME_RAM_WADDR 0xC15C 121457e252bfSMichael Neumann #define CP_ME_RAM_DATA 0xC160 121557e252bfSMichael Neumann 121657e252bfSMichael Neumann #define CP_CE_UCODE_ADDR 0xC168 121757e252bfSMichael Neumann #define CP_CE_UCODE_DATA 0xC16C 121857e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_ADDR 0xC170 121957e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_DATA 0xC174 122057e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_ADDR 0xC178 122157e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_DATA 0xC17C 122257e252bfSMichael Neumann 122357e252bfSMichael Neumann #define CP_INT_CNTL_RING0 0xC1A8 122457e252bfSMichael Neumann # define CNTX_BUSY_INT_ENABLE (1 << 19) 122557e252bfSMichael Neumann # define CNTX_EMPTY_INT_ENABLE (1 << 20) 122657e252bfSMichael Neumann # define PRIV_INSTR_INT_ENABLE (1 << 22) 122757e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 122857e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 122957e252bfSMichael Neumann # define CP_RINGID2_INT_ENABLE (1 << 29) 123057e252bfSMichael Neumann # define CP_RINGID1_INT_ENABLE (1 << 30) 123157e252bfSMichael Neumann # define CP_RINGID0_INT_ENABLE (1 << 31) 123257e252bfSMichael Neumann 123357e252bfSMichael Neumann #define CP_INT_STATUS_RING0 0xC1B4 123457e252bfSMichael Neumann # define PRIV_INSTR_INT_STAT (1 << 22) 123557e252bfSMichael Neumann # define PRIV_REG_INT_STAT (1 << 23) 123657e252bfSMichael Neumann # define TIME_STAMP_INT_STAT (1 << 26) 123757e252bfSMichael Neumann # define CP_RINGID2_INT_STAT (1 << 29) 123857e252bfSMichael Neumann # define CP_RINGID1_INT_STAT (1 << 30) 123957e252bfSMichael Neumann # define CP_RINGID0_INT_STAT (1 << 31) 124057e252bfSMichael Neumann 1241*4cd92098Szrj #define CP_MEM_SLP_CNTL 0xC1E4 1242*4cd92098Szrj # define CP_MEM_LS_EN (1 << 0) 1243*4cd92098Szrj 124457e252bfSMichael Neumann #define CP_CPF_DEBUG 0xC200 124557e252bfSMichael Neumann 124657e252bfSMichael Neumann #define CP_PQ_WPTR_POLL_CNTL 0xC20C 124757e252bfSMichael Neumann #define WPTR_POLL_EN (1 << 31) 124857e252bfSMichael Neumann 124957e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_CNTL 0xC214 125057e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_CNTL 0xC218 125157e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_CNTL 0xC21C 125257e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_CNTL 0xC220 125357e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_CNTL 0xC224 125457e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_CNTL 0xC228 125557e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_CNTL 0xC22C 125657e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_CNTL 0xC230 125757e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 125857e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 125957e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 126057e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 126157e252bfSMichael Neumann # define GENERIC2_INT_ENABLE (1 << 29) 126257e252bfSMichael Neumann # define GENERIC1_INT_ENABLE (1 << 30) 126357e252bfSMichael Neumann # define GENERIC0_INT_ENABLE (1 << 31) 126457e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_STATUS 0xC214 126557e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_STATUS 0xC218 126657e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_STATUS 0xC21C 126757e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_STATUS 0xC220 126857e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_STATUS 0xC224 126957e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_STATUS 0xC228 127057e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_STATUS 0xC22C 127157e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_STATUS 0xC230 127257e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 127357e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 127457e252bfSMichael Neumann # define PRIV_REG_INT_STATUS (1 << 23) 127557e252bfSMichael Neumann # define TIME_STAMP_INT_STATUS (1 << 26) 127657e252bfSMichael Neumann # define GENERIC2_INT_STATUS (1 << 29) 127757e252bfSMichael Neumann # define GENERIC1_INT_STATUS (1 << 30) 127857e252bfSMichael Neumann # define GENERIC0_INT_STATUS (1 << 31) 127957e252bfSMichael Neumann 128057e252bfSMichael Neumann #define CP_MAX_CONTEXT 0xC2B8 128157e252bfSMichael Neumann 128257e252bfSMichael Neumann #define CP_RB0_BASE_HI 0xC2C4 128357e252bfSMichael Neumann 128457e252bfSMichael Neumann #define RLC_CNTL 0xC300 128557e252bfSMichael Neumann # define RLC_ENABLE (1 << 0) 128657e252bfSMichael Neumann 128757e252bfSMichael Neumann #define RLC_MC_CNTL 0xC30C 128857e252bfSMichael Neumann 1289*4cd92098Szrj #define RLC_MEM_SLP_CNTL 0xC318 1290*4cd92098Szrj # define RLC_MEM_LS_EN (1 << 0) 1291*4cd92098Szrj 129257e252bfSMichael Neumann #define RLC_LB_CNTR_MAX 0xC348 129357e252bfSMichael Neumann 129457e252bfSMichael Neumann #define RLC_LB_CNTL 0xC364 1295*4cd92098Szrj # define LOAD_BALANCE_ENABLE (1 << 0) 129657e252bfSMichael Neumann 129757e252bfSMichael Neumann #define RLC_LB_CNTR_INIT 0xC36C 129857e252bfSMichael Neumann 129957e252bfSMichael Neumann #define RLC_SAVE_AND_RESTORE_BASE 0xC374 1300*4cd92098Szrj #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 1301*4cd92098Szrj #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 1302*4cd92098Szrj #define RLC_PG_DELAY_2 0xC37C 130357e252bfSMichael Neumann 130457e252bfSMichael Neumann #define RLC_GPM_UCODE_ADDR 0xC388 130557e252bfSMichael Neumann #define RLC_GPM_UCODE_DATA 0xC38C 130657e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 130757e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 130857e252bfSMichael Neumann #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 130957e252bfSMichael Neumann #define RLC_UCODE_CNTL 0xC39C 131057e252bfSMichael Neumann 1311*4cd92098Szrj #define RLC_GPM_STAT 0xC400 1312*4cd92098Szrj # define RLC_GPM_BUSY (1 << 0) 1313*4cd92098Szrj # define GFX_POWER_STATUS (1 << 1) 1314*4cd92098Szrj # define GFX_CLOCK_STATUS (1 << 2) 1315*4cd92098Szrj 1316*4cd92098Szrj #define RLC_PG_CNTL 0xC40C 1317*4cd92098Szrj # define GFX_PG_ENABLE (1 << 0) 1318*4cd92098Szrj # define GFX_PG_SRC (1 << 1) 1319*4cd92098Szrj # define DYN_PER_CU_PG_ENABLE (1 << 2) 1320*4cd92098Szrj # define STATIC_PER_CU_PG_ENABLE (1 << 3) 1321*4cd92098Szrj # define DISABLE_GDS_PG (1 << 13) 1322*4cd92098Szrj # define DISABLE_CP_PG (1 << 15) 1323*4cd92098Szrj # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 1324*4cd92098Szrj # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 1325*4cd92098Szrj 1326*4cd92098Szrj #define RLC_CGTT_MGCG_OVERRIDE 0xC420 132757e252bfSMichael Neumann #define RLC_CGCG_CGLS_CTRL 0xC424 1328*4cd92098Szrj # define CGCG_EN (1 << 0) 1329*4cd92098Szrj # define CGLS_EN (1 << 1) 1330*4cd92098Szrj 1331*4cd92098Szrj #define RLC_PG_DELAY 0xC434 133257e252bfSMichael Neumann 133357e252bfSMichael Neumann #define RLC_LB_INIT_CU_MASK 0xC43C 133457e252bfSMichael Neumann 133557e252bfSMichael Neumann #define RLC_LB_PARAMS 0xC444 133657e252bfSMichael Neumann 1337*4cd92098Szrj #define RLC_PG_AO_CU_MASK 0xC44C 1338*4cd92098Szrj 1339*4cd92098Szrj #define RLC_MAX_PG_CU 0xC450 1340*4cd92098Szrj # define MAX_PU_CU(x) ((x) << 0) 1341*4cd92098Szrj # define MAX_PU_CU_MASK (0xff << 0) 1342*4cd92098Szrj #define RLC_AUTO_PG_CTRL 0xC454 1343*4cd92098Szrj # define AUTO_PG_EN (1 << 0) 1344*4cd92098Szrj # define GRBM_REG_SGIT(x) ((x) << 3) 1345*4cd92098Szrj # define GRBM_REG_SGIT_MASK (0xffff << 3) 1346*4cd92098Szrj 1347*4cd92098Szrj #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 1348*4cd92098Szrj #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 1349*4cd92098Szrj #define RLC_SERDES_WR_CTRL 0xC47C 1350*4cd92098Szrj #define BPM_ADDR(x) ((x) << 0) 1351*4cd92098Szrj #define BPM_ADDR_MASK (0xff << 0) 1352*4cd92098Szrj #define CGLS_ENABLE (1 << 16) 1353*4cd92098Szrj #define CGCG_OVERRIDE_0 (1 << 20) 1354*4cd92098Szrj #define MGCG_OVERRIDE_0 (1 << 22) 1355*4cd92098Szrj #define MGCG_OVERRIDE_1 (1 << 23) 1356*4cd92098Szrj 135757e252bfSMichael Neumann #define RLC_SERDES_CU_MASTER_BUSY 0xC484 135857e252bfSMichael Neumann #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 135957e252bfSMichael Neumann # define SE_MASTER_BUSY_MASK 0x0000ffff 136057e252bfSMichael Neumann # define GC_MASTER_BUSY (1 << 16) 136157e252bfSMichael Neumann # define TC0_MASTER_BUSY (1 << 17) 136257e252bfSMichael Neumann # define TC1_MASTER_BUSY (1 << 18) 136357e252bfSMichael Neumann 136457e252bfSMichael Neumann #define RLC_GPM_SCRATCH_ADDR 0xC4B0 136557e252bfSMichael Neumann #define RLC_GPM_SCRATCH_DATA 0xC4B4 136657e252bfSMichael Neumann 1367*4cd92098Szrj #define RLC_GPR_REG2 0xC4E8 1368*4cd92098Szrj #define REQ 0x00000001 1369*4cd92098Szrj #define MESSAGE(x) ((x) << 1) 1370*4cd92098Szrj #define MESSAGE_MASK 0x0000001e 1371*4cd92098Szrj #define MSG_ENTER_RLC_SAFE_MODE 1 1372*4cd92098Szrj #define MSG_EXIT_RLC_SAFE_MODE 0 1373*4cd92098Szrj 137457e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR 0xC904 137557e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 137657e252bfSMichael Neumann #define CP_HPD_EOP_VMID 0xC90C 137757e252bfSMichael Neumann #define CP_HPD_EOP_CONTROL 0xC910 137857e252bfSMichael Neumann #define EOP_SIZE(x) ((x) << 0) 137957e252bfSMichael Neumann #define EOP_SIZE_MASK (0x3f << 0) 138057e252bfSMichael Neumann #define CP_MQD_BASE_ADDR 0xC914 138157e252bfSMichael Neumann #define CP_MQD_BASE_ADDR_HI 0xC918 138257e252bfSMichael Neumann #define CP_HQD_ACTIVE 0xC91C 138357e252bfSMichael Neumann #define CP_HQD_VMID 0xC920 138457e252bfSMichael Neumann 138557e252bfSMichael Neumann #define CP_HQD_PQ_BASE 0xC934 138657e252bfSMichael Neumann #define CP_HQD_PQ_BASE_HI 0xC938 138757e252bfSMichael Neumann #define CP_HQD_PQ_RPTR 0xC93C 138857e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 138957e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 139057e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 139157e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 139257e252bfSMichael Neumann #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 139357e252bfSMichael Neumann #define DOORBELL_OFFSET(x) ((x) << 2) 139457e252bfSMichael Neumann #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 139557e252bfSMichael Neumann #define DOORBELL_SOURCE (1 << 28) 139657e252bfSMichael Neumann #define DOORBELL_SCHD_HIT (1 << 29) 139757e252bfSMichael Neumann #define DOORBELL_EN (1 << 30) 139857e252bfSMichael Neumann #define DOORBELL_HIT (1 << 31) 139957e252bfSMichael Neumann #define CP_HQD_PQ_WPTR 0xC954 140057e252bfSMichael Neumann #define CP_HQD_PQ_CONTROL 0xC958 140157e252bfSMichael Neumann #define QUEUE_SIZE(x) ((x) << 0) 140257e252bfSMichael Neumann #define QUEUE_SIZE_MASK (0x3f << 0) 140357e252bfSMichael Neumann #define RPTR_BLOCK_SIZE(x) ((x) << 8) 140457e252bfSMichael Neumann #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 140557e252bfSMichael Neumann #define PQ_VOLATILE (1 << 26) 140657e252bfSMichael Neumann #define NO_UPDATE_RPTR (1 << 27) 140757e252bfSMichael Neumann #define UNORD_DISPATCH (1 << 28) 140857e252bfSMichael Neumann #define ROQ_PQ_IB_FLIP (1 << 29) 140957e252bfSMichael Neumann #define PRIV_STATE (1 << 30) 141057e252bfSMichael Neumann #define KMD_QUEUE (1 << 31) 141157e252bfSMichael Neumann 141257e252bfSMichael Neumann #define CP_HQD_DEQUEUE_REQUEST 0xC974 141357e252bfSMichael Neumann 141457e252bfSMichael Neumann #define CP_MQD_CONTROL 0xC99C 141557e252bfSMichael Neumann #define MQD_VMID(x) ((x) << 0) 141657e252bfSMichael Neumann #define MQD_VMID_MASK (0xf << 0) 141757e252bfSMichael Neumann 1418*4cd92098Szrj #define DB_RENDER_CONTROL 0x28000 1419*4cd92098Szrj 142057e252bfSMichael Neumann #define PA_SC_RASTER_CONFIG 0x28350 142157e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_0 0 142257e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_1 1 142357e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_2 2 142457e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_3 3 142557e252bfSMichael Neumann 142657e252bfSMichael Neumann #define VGT_EVENT_INITIATOR 0x28a90 142757e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 142857e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 142957e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 143057e252bfSMichael Neumann # define CACHE_FLUSH_TS (4 << 0) 143157e252bfSMichael Neumann # define CACHE_FLUSH (6 << 0) 143257e252bfSMichael Neumann # define CS_PARTIAL_FLUSH (7 << 0) 143357e252bfSMichael Neumann # define VGT_STREAMOUT_RESET (10 << 0) 143457e252bfSMichael Neumann # define END_OF_PIPE_INCR_DE (11 << 0) 143557e252bfSMichael Neumann # define END_OF_PIPE_IB_END (12 << 0) 143657e252bfSMichael Neumann # define RST_PIX_CNT (13 << 0) 143757e252bfSMichael Neumann # define VS_PARTIAL_FLUSH (15 << 0) 143857e252bfSMichael Neumann # define PS_PARTIAL_FLUSH (16 << 0) 143957e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 144057e252bfSMichael Neumann # define ZPASS_DONE (21 << 0) 144157e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 144257e252bfSMichael Neumann # define PERFCOUNTER_START (23 << 0) 144357e252bfSMichael Neumann # define PERFCOUNTER_STOP (24 << 0) 144457e252bfSMichael Neumann # define PIPELINESTAT_START (25 << 0) 144557e252bfSMichael Neumann # define PIPELINESTAT_STOP (26 << 0) 144657e252bfSMichael Neumann # define PERFCOUNTER_SAMPLE (27 << 0) 144757e252bfSMichael Neumann # define SAMPLE_PIPELINESTAT (30 << 0) 144857e252bfSMichael Neumann # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 144957e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS (32 << 0) 145057e252bfSMichael Neumann # define RESET_VTX_CNT (33 << 0) 145157e252bfSMichael Neumann # define VGT_FLUSH (36 << 0) 145257e252bfSMichael Neumann # define BOTTOM_OF_PIPE_TS (40 << 0) 145357e252bfSMichael Neumann # define DB_CACHE_FLUSH_AND_INV (42 << 0) 145457e252bfSMichael Neumann # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 145557e252bfSMichael Neumann # define FLUSH_AND_INV_DB_META (44 << 0) 145657e252bfSMichael Neumann # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 145757e252bfSMichael Neumann # define FLUSH_AND_INV_CB_META (46 << 0) 145857e252bfSMichael Neumann # define CS_DONE (47 << 0) 145957e252bfSMichael Neumann # define PS_DONE (48 << 0) 146057e252bfSMichael Neumann # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 146157e252bfSMichael Neumann # define THREAD_TRACE_START (51 << 0) 146257e252bfSMichael Neumann # define THREAD_TRACE_STOP (52 << 0) 146357e252bfSMichael Neumann # define THREAD_TRACE_FLUSH (54 << 0) 146457e252bfSMichael Neumann # define THREAD_TRACE_FINISH (55 << 0) 146557e252bfSMichael Neumann # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 146657e252bfSMichael Neumann # define PIXEL_PIPE_STAT_DUMP (57 << 0) 146757e252bfSMichael Neumann # define PIXEL_PIPE_STAT_RESET (58 << 0) 146857e252bfSMichael Neumann 146957e252bfSMichael Neumann #define SCRATCH_REG0 0x30100 147057e252bfSMichael Neumann #define SCRATCH_REG1 0x30104 147157e252bfSMichael Neumann #define SCRATCH_REG2 0x30108 147257e252bfSMichael Neumann #define SCRATCH_REG3 0x3010C 147357e252bfSMichael Neumann #define SCRATCH_REG4 0x30110 147457e252bfSMichael Neumann #define SCRATCH_REG5 0x30114 147557e252bfSMichael Neumann #define SCRATCH_REG6 0x30118 147657e252bfSMichael Neumann #define SCRATCH_REG7 0x3011C 147757e252bfSMichael Neumann 147857e252bfSMichael Neumann #define SCRATCH_UMSK 0x30140 147957e252bfSMichael Neumann #define SCRATCH_ADDR 0x30144 148057e252bfSMichael Neumann 148157e252bfSMichael Neumann #define CP_SEM_WAIT_TIMER 0x301BC 148257e252bfSMichael Neumann 148357e252bfSMichael Neumann #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 148457e252bfSMichael Neumann 148557e252bfSMichael Neumann #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 148657e252bfSMichael Neumann 148757e252bfSMichael Neumann #define GRBM_GFX_INDEX 0x30800 148857e252bfSMichael Neumann #define INSTANCE_INDEX(x) ((x) << 0) 148957e252bfSMichael Neumann #define SH_INDEX(x) ((x) << 8) 149057e252bfSMichael Neumann #define SE_INDEX(x) ((x) << 16) 149157e252bfSMichael Neumann #define SH_BROADCAST_WRITES (1 << 29) 149257e252bfSMichael Neumann #define INSTANCE_BROADCAST_WRITES (1 << 30) 149357e252bfSMichael Neumann #define SE_BROADCAST_WRITES (1 << 31) 149457e252bfSMichael Neumann 149557e252bfSMichael Neumann #define VGT_ESGS_RING_SIZE 0x30900 149657e252bfSMichael Neumann #define VGT_GSVS_RING_SIZE 0x30904 149757e252bfSMichael Neumann #define VGT_PRIMITIVE_TYPE 0x30908 149857e252bfSMichael Neumann #define VGT_INDEX_TYPE 0x3090C 149957e252bfSMichael Neumann 150057e252bfSMichael Neumann #define VGT_NUM_INDICES 0x30930 150157e252bfSMichael Neumann #define VGT_NUM_INSTANCES 0x30934 150257e252bfSMichael Neumann #define VGT_TF_RING_SIZE 0x30938 150357e252bfSMichael Neumann #define VGT_HS_OFFCHIP_PARAM 0x3093C 150457e252bfSMichael Neumann #define VGT_TF_MEMORY_BASE 0x30940 150557e252bfSMichael Neumann 150657e252bfSMichael Neumann #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 150757e252bfSMichael Neumann #define PA_SC_LINE_STIPPLE_STATE 0x30a04 150857e252bfSMichael Neumann 150957e252bfSMichael Neumann #define SQC_CACHES 0x30d20 151057e252bfSMichael Neumann 151157e252bfSMichael Neumann #define CP_PERFMON_CNTL 0x36020 151257e252bfSMichael Neumann 1513*4cd92098Szrj #define CGTS_SM_CTRL_REG 0x3c000 1514*4cd92098Szrj #define SM_MODE(x) ((x) << 17) 1515*4cd92098Szrj #define SM_MODE_MASK (0x7 << 17) 1516*4cd92098Szrj #define SM_MODE_ENABLE (1 << 20) 1517*4cd92098Szrj #define CGTS_OVERRIDE (1 << 21) 1518*4cd92098Szrj #define CGTS_LS_OVERRIDE (1 << 22) 1519*4cd92098Szrj #define ON_MONITOR_ADD_EN (1 << 23) 1520*4cd92098Szrj #define ON_MONITOR_ADD(x) ((x) << 24) 1521*4cd92098Szrj #define ON_MONITOR_ADD_MASK (0xff << 24) 1522*4cd92098Szrj 152357e252bfSMichael Neumann #define CGTS_TCC_DISABLE 0x3c00c 152457e252bfSMichael Neumann #define CGTS_USER_TCC_DISABLE 0x3c010 152557e252bfSMichael Neumann #define TCC_DISABLE_MASK 0xFFFF0000 152657e252bfSMichael Neumann #define TCC_DISABLE_SHIFT 16 152757e252bfSMichael Neumann 152857e252bfSMichael Neumann #define CB_CGTT_SCLK_CTRL 0x3c2a0 152957e252bfSMichael Neumann 153057e252bfSMichael Neumann /* 153157e252bfSMichael Neumann * PM4 153257e252bfSMichael Neumann */ 153357e252bfSMichael Neumann #define PACKET_TYPE0 0 153457e252bfSMichael Neumann #define PACKET_TYPE1 1 153557e252bfSMichael Neumann #define PACKET_TYPE2 2 153657e252bfSMichael Neumann #define PACKET_TYPE3 3 153757e252bfSMichael Neumann 153857e252bfSMichael Neumann #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 153957e252bfSMichael Neumann #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 154057e252bfSMichael Neumann #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 154157e252bfSMichael Neumann #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 154257e252bfSMichael Neumann #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 154357e252bfSMichael Neumann (((reg) >> 2) & 0xFFFF) | \ 154457e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 154557e252bfSMichael Neumann #define CP_PACKET2 0x80000000 154657e252bfSMichael Neumann #define PACKET2_PAD_SHIFT 0 154757e252bfSMichael Neumann #define PACKET2_PAD_MASK (0x3fffffff << 0) 154857e252bfSMichael Neumann 154957e252bfSMichael Neumann #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 155057e252bfSMichael Neumann 155157e252bfSMichael Neumann #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 155257e252bfSMichael Neumann (((op) & 0xFF) << 8) | \ 155357e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 155457e252bfSMichael Neumann 155557e252bfSMichael Neumann #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 155657e252bfSMichael Neumann 155757e252bfSMichael Neumann /* Packet 3 types */ 155857e252bfSMichael Neumann #define PACKET3_NOP 0x10 155957e252bfSMichael Neumann #define PACKET3_SET_BASE 0x11 156057e252bfSMichael Neumann #define PACKET3_BASE_INDEX(x) ((x) << 0) 156157e252bfSMichael Neumann #define CE_PARTITION_BASE 3 156257e252bfSMichael Neumann #define PACKET3_CLEAR_STATE 0x12 156357e252bfSMichael Neumann #define PACKET3_INDEX_BUFFER_SIZE 0x13 156457e252bfSMichael Neumann #define PACKET3_DISPATCH_DIRECT 0x15 156557e252bfSMichael Neumann #define PACKET3_DISPATCH_INDIRECT 0x16 156657e252bfSMichael Neumann #define PACKET3_ATOMIC_GDS 0x1D 156757e252bfSMichael Neumann #define PACKET3_ATOMIC_MEM 0x1E 156857e252bfSMichael Neumann #define PACKET3_OCCLUSION_QUERY 0x1F 156957e252bfSMichael Neumann #define PACKET3_SET_PREDICATION 0x20 157057e252bfSMichael Neumann #define PACKET3_REG_RMW 0x21 157157e252bfSMichael Neumann #define PACKET3_COND_EXEC 0x22 157257e252bfSMichael Neumann #define PACKET3_PRED_EXEC 0x23 157357e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT 0x24 157457e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT 0x25 157557e252bfSMichael Neumann #define PACKET3_INDEX_BASE 0x26 157657e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_2 0x27 157757e252bfSMichael Neumann #define PACKET3_CONTEXT_CONTROL 0x28 157857e252bfSMichael Neumann #define PACKET3_INDEX_TYPE 0x2A 157957e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 158057e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_AUTO 0x2D 158157e252bfSMichael Neumann #define PACKET3_NUM_INSTANCES 0x2F 158257e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 158357e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER_CONST 0x33 158457e252bfSMichael Neumann #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 158557e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 158657e252bfSMichael Neumann #define PACKET3_DRAW_PREAMBLE 0x36 158757e252bfSMichael Neumann #define PACKET3_WRITE_DATA 0x37 158857e252bfSMichael Neumann #define WRITE_DATA_DST_SEL(x) ((x) << 8) 158957e252bfSMichael Neumann /* 0 - register 159057e252bfSMichael Neumann * 1 - memory (sync - via GRBM) 159157e252bfSMichael Neumann * 2 - gl2 159257e252bfSMichael Neumann * 3 - gds 159357e252bfSMichael Neumann * 4 - reserved 159457e252bfSMichael Neumann * 5 - memory (async - direct) 159557e252bfSMichael Neumann */ 159657e252bfSMichael Neumann #define WR_ONE_ADDR (1 << 16) 159757e252bfSMichael Neumann #define WR_CONFIRM (1 << 20) 159857e252bfSMichael Neumann #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 159957e252bfSMichael Neumann /* 0 - LRU 160057e252bfSMichael Neumann * 1 - Stream 160157e252bfSMichael Neumann */ 160257e252bfSMichael Neumann #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 160357e252bfSMichael Neumann /* 0 - me 160457e252bfSMichael Neumann * 1 - pfp 160557e252bfSMichael Neumann * 2 - ce 160657e252bfSMichael Neumann */ 160757e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 160857e252bfSMichael Neumann #define PACKET3_MEM_SEMAPHORE 0x39 160957e252bfSMichael Neumann # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 161057e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 161157e252bfSMichael Neumann # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 161257e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 161357e252bfSMichael Neumann # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 161457e252bfSMichael Neumann #define PACKET3_COPY_DW 0x3B 161557e252bfSMichael Neumann #define PACKET3_WAIT_REG_MEM 0x3C 161657e252bfSMichael Neumann #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 161757e252bfSMichael Neumann /* 0 - always 161857e252bfSMichael Neumann * 1 - < 161957e252bfSMichael Neumann * 2 - <= 162057e252bfSMichael Neumann * 3 - == 162157e252bfSMichael Neumann * 4 - != 162257e252bfSMichael Neumann * 5 - >= 162357e252bfSMichael Neumann * 6 - > 162457e252bfSMichael Neumann */ 162557e252bfSMichael Neumann #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 162657e252bfSMichael Neumann /* 0 - reg 162757e252bfSMichael Neumann * 1 - mem 162857e252bfSMichael Neumann */ 162957e252bfSMichael Neumann #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 163057e252bfSMichael Neumann /* 0 - wait_reg_mem 163157e252bfSMichael Neumann * 1 - wr_wait_wr_reg 163257e252bfSMichael Neumann */ 163357e252bfSMichael Neumann #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 163457e252bfSMichael Neumann /* 0 - me 163557e252bfSMichael Neumann * 1 - pfp 163657e252bfSMichael Neumann */ 163757e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER 0x3F 163857e252bfSMichael Neumann #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 163957e252bfSMichael Neumann #define INDIRECT_BUFFER_VALID (1 << 23) 164057e252bfSMichael Neumann #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 164157e252bfSMichael Neumann /* 0 - LRU 164257e252bfSMichael Neumann * 1 - Stream 164357e252bfSMichael Neumann * 2 - Bypass 164457e252bfSMichael Neumann */ 164557e252bfSMichael Neumann #define PACKET3_COPY_DATA 0x40 164657e252bfSMichael Neumann #define PACKET3_PFP_SYNC_ME 0x42 164757e252bfSMichael Neumann #define PACKET3_SURFACE_SYNC 0x43 164857e252bfSMichael Neumann # define PACKET3_DEST_BASE_0_ENA (1 << 0) 164957e252bfSMichael Neumann # define PACKET3_DEST_BASE_1_ENA (1 << 1) 165057e252bfSMichael Neumann # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 165157e252bfSMichael Neumann # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 165257e252bfSMichael Neumann # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 165357e252bfSMichael Neumann # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 165457e252bfSMichael Neumann # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 165557e252bfSMichael Neumann # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 165657e252bfSMichael Neumann # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 165757e252bfSMichael Neumann # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 165857e252bfSMichael Neumann # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 165957e252bfSMichael Neumann # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 166057e252bfSMichael Neumann # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 166157e252bfSMichael Neumann # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 166257e252bfSMichael Neumann # define PACKET3_DEST_BASE_2_ENA (1 << 19) 166357e252bfSMichael Neumann # define PACKET3_DEST_BASE_3_ENA (1 << 21) 166457e252bfSMichael Neumann # define PACKET3_TCL1_ACTION_ENA (1 << 22) 166557e252bfSMichael Neumann # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 166657e252bfSMichael Neumann # define PACKET3_CB_ACTION_ENA (1 << 25) 166757e252bfSMichael Neumann # define PACKET3_DB_ACTION_ENA (1 << 26) 166857e252bfSMichael Neumann # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 166957e252bfSMichael Neumann # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 167057e252bfSMichael Neumann # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 167157e252bfSMichael Neumann #define PACKET3_COND_WRITE 0x45 167257e252bfSMichael Neumann #define PACKET3_EVENT_WRITE 0x46 167357e252bfSMichael Neumann #define EVENT_TYPE(x) ((x) << 0) 167457e252bfSMichael Neumann #define EVENT_INDEX(x) ((x) << 8) 167557e252bfSMichael Neumann /* 0 - any non-TS event 167657e252bfSMichael Neumann * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 167757e252bfSMichael Neumann * 2 - SAMPLE_PIPELINESTAT 167857e252bfSMichael Neumann * 3 - SAMPLE_STREAMOUTSTAT* 167957e252bfSMichael Neumann * 4 - *S_PARTIAL_FLUSH 168057e252bfSMichael Neumann * 5 - EOP events 168157e252bfSMichael Neumann * 6 - EOS events 168257e252bfSMichael Neumann */ 168357e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOP 0x47 168457e252bfSMichael Neumann #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 168557e252bfSMichael Neumann #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 168657e252bfSMichael Neumann #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 168757e252bfSMichael Neumann #define EOP_TCL1_ACTION_EN (1 << 16) 168857e252bfSMichael Neumann #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 168957e252bfSMichael Neumann #define EOP_CACHE_POLICY(x) ((x) << 25) 169057e252bfSMichael Neumann /* 0 - LRU 169157e252bfSMichael Neumann * 1 - Stream 169257e252bfSMichael Neumann * 2 - Bypass 169357e252bfSMichael Neumann */ 169457e252bfSMichael Neumann #define EOP_TCL2_VOLATILE (1 << 27) 169557e252bfSMichael Neumann #define DATA_SEL(x) ((x) << 29) 169657e252bfSMichael Neumann /* 0 - discard 169757e252bfSMichael Neumann * 1 - send low 32bit data 169857e252bfSMichael Neumann * 2 - send 64bit data 169957e252bfSMichael Neumann * 3 - send 64bit GPU counter value 170057e252bfSMichael Neumann * 4 - send 64bit sys counter value 170157e252bfSMichael Neumann */ 170257e252bfSMichael Neumann #define INT_SEL(x) ((x) << 24) 170357e252bfSMichael Neumann /* 0 - none 170457e252bfSMichael Neumann * 1 - interrupt only (DATA_SEL = 0) 170557e252bfSMichael Neumann * 2 - interrupt when data write is confirmed 170657e252bfSMichael Neumann */ 170757e252bfSMichael Neumann #define DST_SEL(x) ((x) << 16) 170857e252bfSMichael Neumann /* 0 - MC 170957e252bfSMichael Neumann * 1 - TC/L2 171057e252bfSMichael Neumann */ 171157e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOS 0x48 171257e252bfSMichael Neumann #define PACKET3_RELEASE_MEM 0x49 171357e252bfSMichael Neumann #define PACKET3_PREAMBLE_CNTL 0x4A 171457e252bfSMichael Neumann # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 171557e252bfSMichael Neumann # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 171657e252bfSMichael Neumann #define PACKET3_DMA_DATA 0x50 171757e252bfSMichael Neumann #define PACKET3_AQUIRE_MEM 0x58 171857e252bfSMichael Neumann #define PACKET3_REWIND 0x59 171957e252bfSMichael Neumann #define PACKET3_LOAD_UCONFIG_REG 0x5E 172057e252bfSMichael Neumann #define PACKET3_LOAD_SH_REG 0x5F 172157e252bfSMichael Neumann #define PACKET3_LOAD_CONFIG_REG 0x60 172257e252bfSMichael Neumann #define PACKET3_LOAD_CONTEXT_REG 0x61 172357e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG 0x68 172457e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_START 0x00008000 172557e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_END 0x0000b000 172657e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG 0x69 172757e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_START 0x00028000 172857e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_END 0x00029000 172957e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 173057e252bfSMichael Neumann #define PACKET3_SET_SH_REG 0x76 173157e252bfSMichael Neumann #define PACKET3_SET_SH_REG_START 0x0000b000 173257e252bfSMichael Neumann #define PACKET3_SET_SH_REG_END 0x0000c000 173357e252bfSMichael Neumann #define PACKET3_SET_SH_REG_OFFSET 0x77 173457e252bfSMichael Neumann #define PACKET3_SET_QUEUE_REG 0x78 173557e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG 0x79 173657e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_START 0x00030000 173757e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_END 0x00031000 173857e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_WRITE 0x7D 173957e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_READ 0x7E 174057e252bfSMichael Neumann #define PACKET3_LOAD_CONST_RAM 0x80 174157e252bfSMichael Neumann #define PACKET3_WRITE_CONST_RAM 0x81 174257e252bfSMichael Neumann #define PACKET3_DUMP_CONST_RAM 0x83 174357e252bfSMichael Neumann #define PACKET3_INCREMENT_CE_COUNTER 0x84 174457e252bfSMichael Neumann #define PACKET3_INCREMENT_DE_COUNTER 0x85 174557e252bfSMichael Neumann #define PACKET3_WAIT_ON_CE_COUNTER 0x86 174657e252bfSMichael Neumann #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 174757e252bfSMichael Neumann #define PACKET3_SWITCH_BUFFER 0x8B 174857e252bfSMichael Neumann 174957e252bfSMichael Neumann /* SDMA - first instance at 0xd000, second at 0xd800 */ 175057e252bfSMichael Neumann #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 175157e252bfSMichael Neumann #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 175257e252bfSMichael Neumann 175357e252bfSMichael Neumann #define SDMA0_UCODE_ADDR 0xD000 175457e252bfSMichael Neumann #define SDMA0_UCODE_DATA 0xD004 1755*4cd92098Szrj #define SDMA0_POWER_CNTL 0xD008 1756*4cd92098Szrj #define SDMA0_CLK_CTRL 0xD00C 175757e252bfSMichael Neumann 175857e252bfSMichael Neumann #define SDMA0_CNTL 0xD010 175957e252bfSMichael Neumann # define TRAP_ENABLE (1 << 0) 176057e252bfSMichael Neumann # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 176157e252bfSMichael Neumann # define SEM_WAIT_INT_ENABLE (1 << 2) 176257e252bfSMichael Neumann # define DATA_SWAP_ENABLE (1 << 3) 176357e252bfSMichael Neumann # define FENCE_SWAP_ENABLE (1 << 4) 176457e252bfSMichael Neumann # define AUTO_CTXSW_ENABLE (1 << 18) 176557e252bfSMichael Neumann # define CTXEMPTY_INT_ENABLE (1 << 28) 176657e252bfSMichael Neumann 176757e252bfSMichael Neumann #define SDMA0_TILING_CONFIG 0xD018 176857e252bfSMichael Neumann 176957e252bfSMichael Neumann #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 177057e252bfSMichael Neumann #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 177157e252bfSMichael Neumann 177257e252bfSMichael Neumann #define SDMA0_STATUS_REG 0xd034 177357e252bfSMichael Neumann # define SDMA_IDLE (1 << 0) 177457e252bfSMichael Neumann 177557e252bfSMichael Neumann #define SDMA0_ME_CNTL 0xD048 177657e252bfSMichael Neumann # define SDMA_HALT (1 << 0) 177757e252bfSMichael Neumann 177857e252bfSMichael Neumann #define SDMA0_GFX_RB_CNTL 0xD200 177957e252bfSMichael Neumann # define SDMA_RB_ENABLE (1 << 0) 178057e252bfSMichael Neumann # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 178157e252bfSMichael Neumann # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 178257e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 178357e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 178457e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 178557e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE 0xD204 178657e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE_HI 0xD208 178757e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR 0xD20C 178857e252bfSMichael Neumann #define SDMA0_GFX_RB_WPTR 0xD210 178957e252bfSMichael Neumann 179057e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 179157e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 179257e252bfSMichael Neumann #define SDMA0_GFX_IB_CNTL 0xD228 179357e252bfSMichael Neumann # define SDMA_IB_ENABLE (1 << 0) 179457e252bfSMichael Neumann # define SDMA_IB_SWAP_ENABLE (1 << 4) 179557e252bfSMichael Neumann # define SDMA_SWITCH_INSIDE_IB (1 << 8) 179657e252bfSMichael Neumann # define SDMA_CMD_VMID(x) ((x) << 16) 179757e252bfSMichael Neumann 179857e252bfSMichael Neumann #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 179957e252bfSMichael Neumann #define SDMA0_GFX_APE1_CNTL 0xD2A0 180057e252bfSMichael Neumann 180157e252bfSMichael Neumann #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 180257e252bfSMichael Neumann (((sub_op) & 0xFF) << 8) | \ 180357e252bfSMichael Neumann (((op) & 0xFF) << 0)) 180457e252bfSMichael Neumann /* sDMA opcodes */ 180557e252bfSMichael Neumann #define SDMA_OPCODE_NOP 0 180657e252bfSMichael Neumann #define SDMA_OPCODE_COPY 1 180757e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR 0 180857e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED 1 180957e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_SOA 3 181057e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 181157e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 181257e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 181357e252bfSMichael Neumann #define SDMA_OPCODE_WRITE 2 181457e252bfSMichael Neumann # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 181557e252bfSMichael Neumann # define SDMA_WRTIE_SUB_OPCODE_TILED 1 181657e252bfSMichael Neumann #define SDMA_OPCODE_INDIRECT_BUFFER 4 181757e252bfSMichael Neumann #define SDMA_OPCODE_FENCE 5 181857e252bfSMichael Neumann #define SDMA_OPCODE_TRAP 6 181957e252bfSMichael Neumann #define SDMA_OPCODE_SEMAPHORE 7 182057e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 182157e252bfSMichael Neumann /* 0 - increment 182257e252bfSMichael Neumann * 1 - write 1 182357e252bfSMichael Neumann */ 182457e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 182557e252bfSMichael Neumann /* 0 - wait 182657e252bfSMichael Neumann * 1 - signal 182757e252bfSMichael Neumann */ 182857e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 182957e252bfSMichael Neumann /* mailbox */ 183057e252bfSMichael Neumann #define SDMA_OPCODE_POLL_REG_MEM 8 183157e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 183257e252bfSMichael Neumann /* 0 - wait_reg_mem 183357e252bfSMichael Neumann * 1 - wr_wait_wr_reg 183457e252bfSMichael Neumann */ 183557e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 183657e252bfSMichael Neumann /* 0 - always 183757e252bfSMichael Neumann * 1 - < 183857e252bfSMichael Neumann * 2 - <= 183957e252bfSMichael Neumann * 3 - == 184057e252bfSMichael Neumann * 4 - != 184157e252bfSMichael Neumann * 5 - >= 184257e252bfSMichael Neumann * 6 - > 184357e252bfSMichael Neumann */ 184457e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 184557e252bfSMichael Neumann /* 0 = register 184657e252bfSMichael Neumann * 1 = memory 184757e252bfSMichael Neumann */ 184857e252bfSMichael Neumann #define SDMA_OPCODE_COND_EXEC 9 184957e252bfSMichael Neumann #define SDMA_OPCODE_CONSTANT_FILL 11 185057e252bfSMichael Neumann # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 185157e252bfSMichael Neumann /* 0 = byte fill 185257e252bfSMichael Neumann * 2 = DW fill 185357e252bfSMichael Neumann */ 185457e252bfSMichael Neumann #define SDMA_OPCODE_GENERATE_PTE_PDE 12 185557e252bfSMichael Neumann #define SDMA_OPCODE_TIMESTAMP 13 185657e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 185757e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 185857e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 185957e252bfSMichael Neumann #define SDMA_OPCODE_SRBM_WRITE 14 186057e252bfSMichael Neumann # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 186157e252bfSMichael Neumann /* byte mask */ 186257e252bfSMichael Neumann 186357e252bfSMichael Neumann /* UVD */ 186457e252bfSMichael Neumann 186557e252bfSMichael Neumann #define UVD_UDEC_ADDR_CONFIG 0xef4c 186657e252bfSMichael Neumann #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 186757e252bfSMichael Neumann #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 186857e252bfSMichael Neumann 186957e252bfSMichael Neumann #define UVD_LMI_EXT40_ADDR 0xf498 187057e252bfSMichael Neumann #define UVD_LMI_ADDR_EXT 0xf594 187157e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET0 0xf608 187257e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE0 0xf60c 187357e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET1 0xf610 187457e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE1 0xf614 187557e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET2 0xf618 187657e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE2 0xf61c 187757e252bfSMichael Neumann 187857e252bfSMichael Neumann #define UVD_RBC_RB_RPTR 0xf690 187957e252bfSMichael Neumann #define UVD_RBC_RB_WPTR 0xf694 188057e252bfSMichael Neumann 1881*4cd92098Szrj #define UVD_CGC_CTRL 0xF4B0 1882*4cd92098Szrj # define DCM (1 << 0) 1883*4cd92098Szrj # define CG_DT(x) ((x) << 2) 1884*4cd92098Szrj # define CG_DT_MASK (0xf << 2) 1885*4cd92098Szrj # define CLK_OD(x) ((x) << 6) 1886*4cd92098Szrj # define CLK_OD_MASK (0x1f << 6) 1887*4cd92098Szrj 188857e252bfSMichael Neumann /* UVD clocks */ 188957e252bfSMichael Neumann 189057e252bfSMichael Neumann #define CG_DCLK_CNTL 0xC050009C 189157e252bfSMichael Neumann # define DCLK_DIVIDER_MASK 0x7f 189257e252bfSMichael Neumann # define DCLK_DIR_CNTL_EN (1 << 8) 189357e252bfSMichael Neumann #define CG_DCLK_STATUS 0xC05000A0 189457e252bfSMichael Neumann # define DCLK_STATUS (1 << 0) 189557e252bfSMichael Neumann #define CG_VCLK_CNTL 0xC05000A4 189657e252bfSMichael Neumann #define CG_VCLK_STATUS 0xC05000A8 189757e252bfSMichael Neumann 1898*4cd92098Szrj /* UVD CTX indirect */ 1899*4cd92098Szrj #define UVD_CGC_MEM_CTRL 0xC0 1900*4cd92098Szrj 190157e252bfSMichael Neumann #endif 1902