1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2012 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann * Authors: Alex Deucher 23*57e252bfSMichael Neumann */ 24*57e252bfSMichael Neumann #ifndef CIK_H 25*57e252bfSMichael Neumann #define CIK_H 26*57e252bfSMichael Neumann 27*57e252bfSMichael Neumann #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28*57e252bfSMichael Neumann 29*57e252bfSMichael Neumann #define CIK_RB_BITMAP_WIDTH_PER_SH 2 30*57e252bfSMichael Neumann 31*57e252bfSMichael Neumann /* SMC IND registers */ 32*57e252bfSMichael Neumann #define GENERAL_PWRMGT 0xC0200000 33*57e252bfSMichael Neumann # define GPU_COUNTER_CLK (1 << 15) 34*57e252bfSMichael Neumann 35*57e252bfSMichael Neumann #define CG_CLKPIN_CNTL 0xC05001A0 36*57e252bfSMichael Neumann # define XTALIN_DIVIDE (1 << 1) 37*57e252bfSMichael Neumann 38*57e252bfSMichael Neumann #define PCIE_INDEX 0x38 39*57e252bfSMichael Neumann #define PCIE_DATA 0x3C 40*57e252bfSMichael Neumann 41*57e252bfSMichael Neumann #define VGA_HDP_CONTROL 0x328 42*57e252bfSMichael Neumann #define VGA_MEMORY_DISABLE (1 << 4) 43*57e252bfSMichael Neumann 44*57e252bfSMichael Neumann #define DMIF_ADDR_CALC 0xC00 45*57e252bfSMichael Neumann 46*57e252bfSMichael Neumann #define SRBM_GFX_CNTL 0xE44 47*57e252bfSMichael Neumann #define PIPEID(x) ((x) << 0) 48*57e252bfSMichael Neumann #define MEID(x) ((x) << 2) 49*57e252bfSMichael Neumann #define VMID(x) ((x) << 4) 50*57e252bfSMichael Neumann #define QUEUEID(x) ((x) << 8) 51*57e252bfSMichael Neumann 52*57e252bfSMichael Neumann #define SRBM_STATUS2 0xE4C 53*57e252bfSMichael Neumann #define SDMA_BUSY (1 << 5) 54*57e252bfSMichael Neumann #define SDMA1_BUSY (1 << 6) 55*57e252bfSMichael Neumann #define SRBM_STATUS 0xE50 56*57e252bfSMichael Neumann #define UVD_RQ_PENDING (1 << 1) 57*57e252bfSMichael Neumann #define GRBM_RQ_PENDING (1 << 5) 58*57e252bfSMichael Neumann #define VMC_BUSY (1 << 8) 59*57e252bfSMichael Neumann #define MCB_BUSY (1 << 9) 60*57e252bfSMichael Neumann #define MCB_NON_DISPLAY_BUSY (1 << 10) 61*57e252bfSMichael Neumann #define MCC_BUSY (1 << 11) 62*57e252bfSMichael Neumann #define MCD_BUSY (1 << 12) 63*57e252bfSMichael Neumann #define SEM_BUSY (1 << 14) 64*57e252bfSMichael Neumann #define IH_BUSY (1 << 17) 65*57e252bfSMichael Neumann #define UVD_BUSY (1 << 19) 66*57e252bfSMichael Neumann 67*57e252bfSMichael Neumann #define SRBM_SOFT_RESET 0xE60 68*57e252bfSMichael Neumann #define SOFT_RESET_BIF (1 << 1) 69*57e252bfSMichael Neumann #define SOFT_RESET_R0PLL (1 << 4) 70*57e252bfSMichael Neumann #define SOFT_RESET_DC (1 << 5) 71*57e252bfSMichael Neumann #define SOFT_RESET_SDMA1 (1 << 6) 72*57e252bfSMichael Neumann #define SOFT_RESET_GRBM (1 << 8) 73*57e252bfSMichael Neumann #define SOFT_RESET_HDP (1 << 9) 74*57e252bfSMichael Neumann #define SOFT_RESET_IH (1 << 10) 75*57e252bfSMichael Neumann #define SOFT_RESET_MC (1 << 11) 76*57e252bfSMichael Neumann #define SOFT_RESET_ROM (1 << 14) 77*57e252bfSMichael Neumann #define SOFT_RESET_SEM (1 << 15) 78*57e252bfSMichael Neumann #define SOFT_RESET_VMC (1 << 17) 79*57e252bfSMichael Neumann #define SOFT_RESET_SDMA (1 << 20) 80*57e252bfSMichael Neumann #define SOFT_RESET_TST (1 << 21) 81*57e252bfSMichael Neumann #define SOFT_RESET_REGBB (1 << 22) 82*57e252bfSMichael Neumann #define SOFT_RESET_ORB (1 << 23) 83*57e252bfSMichael Neumann #define SOFT_RESET_VCE (1 << 24) 84*57e252bfSMichael Neumann 85*57e252bfSMichael Neumann #define VM_L2_CNTL 0x1400 86*57e252bfSMichael Neumann #define ENABLE_L2_CACHE (1 << 0) 87*57e252bfSMichael Neumann #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 88*57e252bfSMichael Neumann #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 89*57e252bfSMichael Neumann #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 90*57e252bfSMichael Neumann #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 91*57e252bfSMichael Neumann #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 92*57e252bfSMichael Neumann #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 93*57e252bfSMichael Neumann #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 94*57e252bfSMichael Neumann #define VM_L2_CNTL2 0x1404 95*57e252bfSMichael Neumann #define INVALIDATE_ALL_L1_TLBS (1 << 0) 96*57e252bfSMichael Neumann #define INVALIDATE_L2_CACHE (1 << 1) 97*57e252bfSMichael Neumann #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 98*57e252bfSMichael Neumann #define INVALIDATE_PTE_AND_PDE_CACHES 0 99*57e252bfSMichael Neumann #define INVALIDATE_ONLY_PTE_CACHES 1 100*57e252bfSMichael Neumann #define INVALIDATE_ONLY_PDE_CACHES 2 101*57e252bfSMichael Neumann #define VM_L2_CNTL3 0x1408 102*57e252bfSMichael Neumann #define BANK_SELECT(x) ((x) << 0) 103*57e252bfSMichael Neumann #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 104*57e252bfSMichael Neumann #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 105*57e252bfSMichael Neumann #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 106*57e252bfSMichael Neumann #define VM_L2_STATUS 0x140C 107*57e252bfSMichael Neumann #define L2_BUSY (1 << 0) 108*57e252bfSMichael Neumann #define VM_CONTEXT0_CNTL 0x1410 109*57e252bfSMichael Neumann #define ENABLE_CONTEXT (1 << 0) 110*57e252bfSMichael Neumann #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 111*57e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 112*57e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 113*57e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 114*57e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 115*57e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 116*57e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 117*57e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 118*57e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 119*57e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 120*57e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 121*57e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 122*57e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 123*57e252bfSMichael Neumann #define VM_CONTEXT1_CNTL 0x1414 124*57e252bfSMichael Neumann #define VM_CONTEXT0_CNTL2 0x1430 125*57e252bfSMichael Neumann #define VM_CONTEXT1_CNTL2 0x1434 126*57e252bfSMichael Neumann #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 127*57e252bfSMichael Neumann #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 128*57e252bfSMichael Neumann #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 129*57e252bfSMichael Neumann #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 130*57e252bfSMichael Neumann #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 131*57e252bfSMichael Neumann #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 132*57e252bfSMichael Neumann #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 133*57e252bfSMichael Neumann #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 134*57e252bfSMichael Neumann 135*57e252bfSMichael Neumann #define VM_INVALIDATE_REQUEST 0x1478 136*57e252bfSMichael Neumann #define VM_INVALIDATE_RESPONSE 0x147c 137*57e252bfSMichael Neumann 138*57e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 139*57e252bfSMichael Neumann #define PROTECTIONS_MASK (0xf << 0) 140*57e252bfSMichael Neumann #define PROTECTIONS_SHIFT 0 141*57e252bfSMichael Neumann /* bit 0: range 142*57e252bfSMichael Neumann * bit 1: pde0 143*57e252bfSMichael Neumann * bit 2: valid 144*57e252bfSMichael Neumann * bit 3: read 145*57e252bfSMichael Neumann * bit 4: write 146*57e252bfSMichael Neumann */ 147*57e252bfSMichael Neumann #define MEMORY_CLIENT_ID_MASK (0xff << 12) 148*57e252bfSMichael Neumann #define MEMORY_CLIENT_ID_SHIFT 12 149*57e252bfSMichael Neumann #define MEMORY_CLIENT_RW_MASK (1 << 24) 150*57e252bfSMichael Neumann #define MEMORY_CLIENT_RW_SHIFT 24 151*57e252bfSMichael Neumann #define FAULT_VMID_MASK (0xf << 25) 152*57e252bfSMichael Neumann #define FAULT_VMID_SHIFT 25 153*57e252bfSMichael Neumann 154*57e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 155*57e252bfSMichael Neumann 156*57e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 157*57e252bfSMichael Neumann 158*57e252bfSMichael Neumann #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 159*57e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 160*57e252bfSMichael Neumann 161*57e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 162*57e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 163*57e252bfSMichael Neumann #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 164*57e252bfSMichael Neumann #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 165*57e252bfSMichael Neumann #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 166*57e252bfSMichael Neumann #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 167*57e252bfSMichael Neumann #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 168*57e252bfSMichael Neumann #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 169*57e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 170*57e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 171*57e252bfSMichael Neumann 172*57e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 173*57e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 174*57e252bfSMichael Neumann 175*57e252bfSMichael Neumann #define MC_SHARED_CHMAP 0x2004 176*57e252bfSMichael Neumann #define NOOFCHAN_SHIFT 12 177*57e252bfSMichael Neumann #define NOOFCHAN_MASK 0x0000f000 178*57e252bfSMichael Neumann #define MC_SHARED_CHREMAP 0x2008 179*57e252bfSMichael Neumann 180*57e252bfSMichael Neumann #define CHUB_CONTROL 0x1864 181*57e252bfSMichael Neumann #define BYPASS_VM (1 << 0) 182*57e252bfSMichael Neumann 183*57e252bfSMichael Neumann #define MC_VM_FB_LOCATION 0x2024 184*57e252bfSMichael Neumann #define MC_VM_AGP_TOP 0x2028 185*57e252bfSMichael Neumann #define MC_VM_AGP_BOT 0x202C 186*57e252bfSMichael Neumann #define MC_VM_AGP_BASE 0x2030 187*57e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 188*57e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 189*57e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 190*57e252bfSMichael Neumann 191*57e252bfSMichael Neumann #define MC_VM_MX_L1_TLB_CNTL 0x2064 192*57e252bfSMichael Neumann #define ENABLE_L1_TLB (1 << 0) 193*57e252bfSMichael Neumann #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 194*57e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 195*57e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 196*57e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 197*57e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 198*57e252bfSMichael Neumann #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 199*57e252bfSMichael Neumann #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 200*57e252bfSMichael Neumann #define MC_VM_FB_OFFSET 0x2068 201*57e252bfSMichael Neumann 202*57e252bfSMichael Neumann #define MC_SHARED_BLACKOUT_CNTL 0x20ac 203*57e252bfSMichael Neumann 204*57e252bfSMichael Neumann #define MC_ARB_RAMCFG 0x2760 205*57e252bfSMichael Neumann #define NOOFBANK_SHIFT 0 206*57e252bfSMichael Neumann #define NOOFBANK_MASK 0x00000003 207*57e252bfSMichael Neumann #define NOOFRANK_SHIFT 2 208*57e252bfSMichael Neumann #define NOOFRANK_MASK 0x00000004 209*57e252bfSMichael Neumann #define NOOFROWS_SHIFT 3 210*57e252bfSMichael Neumann #define NOOFROWS_MASK 0x00000038 211*57e252bfSMichael Neumann #define NOOFCOLS_SHIFT 6 212*57e252bfSMichael Neumann #define NOOFCOLS_MASK 0x000000C0 213*57e252bfSMichael Neumann #define CHANSIZE_SHIFT 8 214*57e252bfSMichael Neumann #define CHANSIZE_MASK 0x00000100 215*57e252bfSMichael Neumann #define NOOFGROUPS_SHIFT 12 216*57e252bfSMichael Neumann #define NOOFGROUPS_MASK 0x00001000 217*57e252bfSMichael Neumann 218*57e252bfSMichael Neumann #define MC_SEQ_SUP_CNTL 0x28c8 219*57e252bfSMichael Neumann #define RUN_MASK (1 << 0) 220*57e252bfSMichael Neumann #define MC_SEQ_SUP_PGM 0x28cc 221*57e252bfSMichael Neumann 222*57e252bfSMichael Neumann #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 223*57e252bfSMichael Neumann #define TRAIN_DONE_D0 (1 << 30) 224*57e252bfSMichael Neumann #define TRAIN_DONE_D1 (1 << 31) 225*57e252bfSMichael Neumann 226*57e252bfSMichael Neumann #define MC_IO_PAD_CNTL_D0 0x29d0 227*57e252bfSMichael Neumann #define MEM_FALL_OUT_CMD (1 << 8) 228*57e252bfSMichael Neumann 229*57e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 230*57e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_DATA 0x2a48 231*57e252bfSMichael Neumann 232*57e252bfSMichael Neumann #define HDP_HOST_PATH_CNTL 0x2C00 233*57e252bfSMichael Neumann #define HDP_NONSURFACE_BASE 0x2C04 234*57e252bfSMichael Neumann #define HDP_NONSURFACE_INFO 0x2C08 235*57e252bfSMichael Neumann #define HDP_NONSURFACE_SIZE 0x2C0C 236*57e252bfSMichael Neumann 237*57e252bfSMichael Neumann #define HDP_ADDR_CONFIG 0x2F48 238*57e252bfSMichael Neumann #define HDP_MISC_CNTL 0x2F4C 239*57e252bfSMichael Neumann #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 240*57e252bfSMichael Neumann 241*57e252bfSMichael Neumann #define IH_RB_CNTL 0x3e00 242*57e252bfSMichael Neumann # define IH_RB_ENABLE (1 << 0) 243*57e252bfSMichael Neumann # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 244*57e252bfSMichael Neumann # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 245*57e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 246*57e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 247*57e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 248*57e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 249*57e252bfSMichael Neumann #define IH_RB_BASE 0x3e04 250*57e252bfSMichael Neumann #define IH_RB_RPTR 0x3e08 251*57e252bfSMichael Neumann #define IH_RB_WPTR 0x3e0c 252*57e252bfSMichael Neumann # define RB_OVERFLOW (1 << 0) 253*57e252bfSMichael Neumann # define WPTR_OFFSET_MASK 0x3fffc 254*57e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_HI 0x3e10 255*57e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_LO 0x3e14 256*57e252bfSMichael Neumann #define IH_CNTL 0x3e18 257*57e252bfSMichael Neumann # define ENABLE_INTR (1 << 0) 258*57e252bfSMichael Neumann # define IH_MC_SWAP(x) ((x) << 1) 259*57e252bfSMichael Neumann # define IH_MC_SWAP_NONE 0 260*57e252bfSMichael Neumann # define IH_MC_SWAP_16BIT 1 261*57e252bfSMichael Neumann # define IH_MC_SWAP_32BIT 2 262*57e252bfSMichael Neumann # define IH_MC_SWAP_64BIT 3 263*57e252bfSMichael Neumann # define RPTR_REARM (1 << 4) 264*57e252bfSMichael Neumann # define MC_WRREQ_CREDIT(x) ((x) << 15) 265*57e252bfSMichael Neumann # define MC_WR_CLEAN_CNT(x) ((x) << 20) 266*57e252bfSMichael Neumann # define MC_VMID(x) ((x) << 25) 267*57e252bfSMichael Neumann 268*57e252bfSMichael Neumann #define CONFIG_MEMSIZE 0x5428 269*57e252bfSMichael Neumann 270*57e252bfSMichael Neumann #define INTERRUPT_CNTL 0x5468 271*57e252bfSMichael Neumann # define IH_DUMMY_RD_OVERRIDE (1 << 0) 272*57e252bfSMichael Neumann # define IH_DUMMY_RD_EN (1 << 1) 273*57e252bfSMichael Neumann # define IH_REQ_NONSNOOP_EN (1 << 3) 274*57e252bfSMichael Neumann # define GEN_IH_INT_EN (1 << 8) 275*57e252bfSMichael Neumann #define INTERRUPT_CNTL2 0x546c 276*57e252bfSMichael Neumann 277*57e252bfSMichael Neumann #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 278*57e252bfSMichael Neumann 279*57e252bfSMichael Neumann #define BIF_FB_EN 0x5490 280*57e252bfSMichael Neumann #define FB_READ_EN (1 << 0) 281*57e252bfSMichael Neumann #define FB_WRITE_EN (1 << 1) 282*57e252bfSMichael Neumann 283*57e252bfSMichael Neumann #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 284*57e252bfSMichael Neumann 285*57e252bfSMichael Neumann #define GPU_HDP_FLUSH_REQ 0x54DC 286*57e252bfSMichael Neumann #define GPU_HDP_FLUSH_DONE 0x54E0 287*57e252bfSMichael Neumann #define CP0 (1 << 0) 288*57e252bfSMichael Neumann #define CP1 (1 << 1) 289*57e252bfSMichael Neumann #define CP2 (1 << 2) 290*57e252bfSMichael Neumann #define CP3 (1 << 3) 291*57e252bfSMichael Neumann #define CP4 (1 << 4) 292*57e252bfSMichael Neumann #define CP5 (1 << 5) 293*57e252bfSMichael Neumann #define CP6 (1 << 6) 294*57e252bfSMichael Neumann #define CP7 (1 << 7) 295*57e252bfSMichael Neumann #define CP8 (1 << 8) 296*57e252bfSMichael Neumann #define CP9 (1 << 9) 297*57e252bfSMichael Neumann #define SDMA0 (1 << 10) 298*57e252bfSMichael Neumann #define SDMA1 (1 << 11) 299*57e252bfSMichael Neumann 300*57e252bfSMichael Neumann /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 301*57e252bfSMichael Neumann #define LB_MEMORY_CTRL 0x6b04 302*57e252bfSMichael Neumann #define LB_MEMORY_SIZE(x) ((x) << 0) 303*57e252bfSMichael Neumann #define LB_MEMORY_CONFIG(x) ((x) << 20) 304*57e252bfSMichael Neumann 305*57e252bfSMichael Neumann #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 306*57e252bfSMichael Neumann # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 307*57e252bfSMichael Neumann #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 308*57e252bfSMichael Neumann # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 309*57e252bfSMichael Neumann # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 310*57e252bfSMichael Neumann 311*57e252bfSMichael Neumann /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 312*57e252bfSMichael Neumann #define LB_VLINE_STATUS 0x6b24 313*57e252bfSMichael Neumann # define VLINE_OCCURRED (1 << 0) 314*57e252bfSMichael Neumann # define VLINE_ACK (1 << 4) 315*57e252bfSMichael Neumann # define VLINE_STAT (1 << 12) 316*57e252bfSMichael Neumann # define VLINE_INTERRUPT (1 << 16) 317*57e252bfSMichael Neumann # define VLINE_INTERRUPT_TYPE (1 << 17) 318*57e252bfSMichael Neumann /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 319*57e252bfSMichael Neumann #define LB_VBLANK_STATUS 0x6b2c 320*57e252bfSMichael Neumann # define VBLANK_OCCURRED (1 << 0) 321*57e252bfSMichael Neumann # define VBLANK_ACK (1 << 4) 322*57e252bfSMichael Neumann # define VBLANK_STAT (1 << 12) 323*57e252bfSMichael Neumann # define VBLANK_INTERRUPT (1 << 16) 324*57e252bfSMichael Neumann # define VBLANK_INTERRUPT_TYPE (1 << 17) 325*57e252bfSMichael Neumann 326*57e252bfSMichael Neumann /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 327*57e252bfSMichael Neumann #define LB_INTERRUPT_MASK 0x6b20 328*57e252bfSMichael Neumann # define VBLANK_INTERRUPT_MASK (1 << 0) 329*57e252bfSMichael Neumann # define VLINE_INTERRUPT_MASK (1 << 4) 330*57e252bfSMichael Neumann # define VLINE2_INTERRUPT_MASK (1 << 8) 331*57e252bfSMichael Neumann 332*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS 0x60f4 333*57e252bfSMichael Neumann # define LB_D1_VLINE_INTERRUPT (1 << 2) 334*57e252bfSMichael Neumann # define LB_D1_VBLANK_INTERRUPT (1 << 3) 335*57e252bfSMichael Neumann # define DC_HPD1_INTERRUPT (1 << 17) 336*57e252bfSMichael Neumann # define DC_HPD1_RX_INTERRUPT (1 << 18) 337*57e252bfSMichael Neumann # define DACA_AUTODETECT_INTERRUPT (1 << 22) 338*57e252bfSMichael Neumann # define DACB_AUTODETECT_INTERRUPT (1 << 23) 339*57e252bfSMichael Neumann # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 340*57e252bfSMichael Neumann # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 341*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 342*57e252bfSMichael Neumann # define LB_D2_VLINE_INTERRUPT (1 << 2) 343*57e252bfSMichael Neumann # define LB_D2_VBLANK_INTERRUPT (1 << 3) 344*57e252bfSMichael Neumann # define DC_HPD2_INTERRUPT (1 << 17) 345*57e252bfSMichael Neumann # define DC_HPD2_RX_INTERRUPT (1 << 18) 346*57e252bfSMichael Neumann # define DISP_TIMER_INTERRUPT (1 << 24) 347*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 348*57e252bfSMichael Neumann # define LB_D3_VLINE_INTERRUPT (1 << 2) 349*57e252bfSMichael Neumann # define LB_D3_VBLANK_INTERRUPT (1 << 3) 350*57e252bfSMichael Neumann # define DC_HPD3_INTERRUPT (1 << 17) 351*57e252bfSMichael Neumann # define DC_HPD3_RX_INTERRUPT (1 << 18) 352*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 353*57e252bfSMichael Neumann # define LB_D4_VLINE_INTERRUPT (1 << 2) 354*57e252bfSMichael Neumann # define LB_D4_VBLANK_INTERRUPT (1 << 3) 355*57e252bfSMichael Neumann # define DC_HPD4_INTERRUPT (1 << 17) 356*57e252bfSMichael Neumann # define DC_HPD4_RX_INTERRUPT (1 << 18) 357*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 358*57e252bfSMichael Neumann # define LB_D5_VLINE_INTERRUPT (1 << 2) 359*57e252bfSMichael Neumann # define LB_D5_VBLANK_INTERRUPT (1 << 3) 360*57e252bfSMichael Neumann # define DC_HPD5_INTERRUPT (1 << 17) 361*57e252bfSMichael Neumann # define DC_HPD5_RX_INTERRUPT (1 << 18) 362*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 363*57e252bfSMichael Neumann # define LB_D6_VLINE_INTERRUPT (1 << 2) 364*57e252bfSMichael Neumann # define LB_D6_VBLANK_INTERRUPT (1 << 3) 365*57e252bfSMichael Neumann # define DC_HPD6_INTERRUPT (1 << 17) 366*57e252bfSMichael Neumann # define DC_HPD6_RX_INTERRUPT (1 << 18) 367*57e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 368*57e252bfSMichael Neumann 369*57e252bfSMichael Neumann #define DAC_AUTODETECT_INT_CONTROL 0x67c8 370*57e252bfSMichael Neumann 371*57e252bfSMichael Neumann #define DC_HPD1_INT_STATUS 0x601c 372*57e252bfSMichael Neumann #define DC_HPD2_INT_STATUS 0x6028 373*57e252bfSMichael Neumann #define DC_HPD3_INT_STATUS 0x6034 374*57e252bfSMichael Neumann #define DC_HPD4_INT_STATUS 0x6040 375*57e252bfSMichael Neumann #define DC_HPD5_INT_STATUS 0x604c 376*57e252bfSMichael Neumann #define DC_HPD6_INT_STATUS 0x6058 377*57e252bfSMichael Neumann # define DC_HPDx_INT_STATUS (1 << 0) 378*57e252bfSMichael Neumann # define DC_HPDx_SENSE (1 << 1) 379*57e252bfSMichael Neumann # define DC_HPDx_SENSE_DELAYED (1 << 4) 380*57e252bfSMichael Neumann # define DC_HPDx_RX_INT_STATUS (1 << 8) 381*57e252bfSMichael Neumann 382*57e252bfSMichael Neumann #define DC_HPD1_INT_CONTROL 0x6020 383*57e252bfSMichael Neumann #define DC_HPD2_INT_CONTROL 0x602c 384*57e252bfSMichael Neumann #define DC_HPD3_INT_CONTROL 0x6038 385*57e252bfSMichael Neumann #define DC_HPD4_INT_CONTROL 0x6044 386*57e252bfSMichael Neumann #define DC_HPD5_INT_CONTROL 0x6050 387*57e252bfSMichael Neumann #define DC_HPD6_INT_CONTROL 0x605c 388*57e252bfSMichael Neumann # define DC_HPDx_INT_ACK (1 << 0) 389*57e252bfSMichael Neumann # define DC_HPDx_INT_POLARITY (1 << 8) 390*57e252bfSMichael Neumann # define DC_HPDx_INT_EN (1 << 16) 391*57e252bfSMichael Neumann # define DC_HPDx_RX_INT_ACK (1 << 20) 392*57e252bfSMichael Neumann # define DC_HPDx_RX_INT_EN (1 << 24) 393*57e252bfSMichael Neumann 394*57e252bfSMichael Neumann #define DC_HPD1_CONTROL 0x6024 395*57e252bfSMichael Neumann #define DC_HPD2_CONTROL 0x6030 396*57e252bfSMichael Neumann #define DC_HPD3_CONTROL 0x603c 397*57e252bfSMichael Neumann #define DC_HPD4_CONTROL 0x6048 398*57e252bfSMichael Neumann #define DC_HPD5_CONTROL 0x6054 399*57e252bfSMichael Neumann #define DC_HPD6_CONTROL 0x6060 400*57e252bfSMichael Neumann # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 401*57e252bfSMichael Neumann # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 402*57e252bfSMichael Neumann # define DC_HPDx_EN (1 << 28) 403*57e252bfSMichael Neumann 404*57e252bfSMichael Neumann #define GRBM_CNTL 0x8000 405*57e252bfSMichael Neumann #define GRBM_READ_TIMEOUT(x) ((x) << 0) 406*57e252bfSMichael Neumann 407*57e252bfSMichael Neumann #define GRBM_STATUS2 0x8008 408*57e252bfSMichael Neumann #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 409*57e252bfSMichael Neumann #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 410*57e252bfSMichael Neumann #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 411*57e252bfSMichael Neumann #define ME1PIPE0_RQ_PENDING (1 << 6) 412*57e252bfSMichael Neumann #define ME1PIPE1_RQ_PENDING (1 << 7) 413*57e252bfSMichael Neumann #define ME1PIPE2_RQ_PENDING (1 << 8) 414*57e252bfSMichael Neumann #define ME1PIPE3_RQ_PENDING (1 << 9) 415*57e252bfSMichael Neumann #define ME2PIPE0_RQ_PENDING (1 << 10) 416*57e252bfSMichael Neumann #define ME2PIPE1_RQ_PENDING (1 << 11) 417*57e252bfSMichael Neumann #define ME2PIPE2_RQ_PENDING (1 << 12) 418*57e252bfSMichael Neumann #define ME2PIPE3_RQ_PENDING (1 << 13) 419*57e252bfSMichael Neumann #define RLC_RQ_PENDING (1 << 14) 420*57e252bfSMichael Neumann #define RLC_BUSY (1 << 24) 421*57e252bfSMichael Neumann #define TC_BUSY (1 << 25) 422*57e252bfSMichael Neumann #define CPF_BUSY (1 << 28) 423*57e252bfSMichael Neumann #define CPC_BUSY (1 << 29) 424*57e252bfSMichael Neumann #define CPG_BUSY (1 << 30) 425*57e252bfSMichael Neumann 426*57e252bfSMichael Neumann #define GRBM_STATUS 0x8010 427*57e252bfSMichael Neumann #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 428*57e252bfSMichael Neumann #define SRBM_RQ_PENDING (1 << 5) 429*57e252bfSMichael Neumann #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 430*57e252bfSMichael Neumann #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 431*57e252bfSMichael Neumann #define GDS_DMA_RQ_PENDING (1 << 9) 432*57e252bfSMichael Neumann #define DB_CLEAN (1 << 12) 433*57e252bfSMichael Neumann #define CB_CLEAN (1 << 13) 434*57e252bfSMichael Neumann #define TA_BUSY (1 << 14) 435*57e252bfSMichael Neumann #define GDS_BUSY (1 << 15) 436*57e252bfSMichael Neumann #define WD_BUSY_NO_DMA (1 << 16) 437*57e252bfSMichael Neumann #define VGT_BUSY (1 << 17) 438*57e252bfSMichael Neumann #define IA_BUSY_NO_DMA (1 << 18) 439*57e252bfSMichael Neumann #define IA_BUSY (1 << 19) 440*57e252bfSMichael Neumann #define SX_BUSY (1 << 20) 441*57e252bfSMichael Neumann #define WD_BUSY (1 << 21) 442*57e252bfSMichael Neumann #define SPI_BUSY (1 << 22) 443*57e252bfSMichael Neumann #define BCI_BUSY (1 << 23) 444*57e252bfSMichael Neumann #define SC_BUSY (1 << 24) 445*57e252bfSMichael Neumann #define PA_BUSY (1 << 25) 446*57e252bfSMichael Neumann #define DB_BUSY (1 << 26) 447*57e252bfSMichael Neumann #define CP_COHERENCY_BUSY (1 << 28) 448*57e252bfSMichael Neumann #define CP_BUSY (1 << 29) 449*57e252bfSMichael Neumann #define CB_BUSY (1 << 30) 450*57e252bfSMichael Neumann #define GUI_ACTIVE (1 << 31) 451*57e252bfSMichael Neumann #define GRBM_STATUS_SE0 0x8014 452*57e252bfSMichael Neumann #define GRBM_STATUS_SE1 0x8018 453*57e252bfSMichael Neumann #define GRBM_STATUS_SE2 0x8038 454*57e252bfSMichael Neumann #define GRBM_STATUS_SE3 0x803C 455*57e252bfSMichael Neumann #define SE_DB_CLEAN (1 << 1) 456*57e252bfSMichael Neumann #define SE_CB_CLEAN (1 << 2) 457*57e252bfSMichael Neumann #define SE_BCI_BUSY (1 << 22) 458*57e252bfSMichael Neumann #define SE_VGT_BUSY (1 << 23) 459*57e252bfSMichael Neumann #define SE_PA_BUSY (1 << 24) 460*57e252bfSMichael Neumann #define SE_TA_BUSY (1 << 25) 461*57e252bfSMichael Neumann #define SE_SX_BUSY (1 << 26) 462*57e252bfSMichael Neumann #define SE_SPI_BUSY (1 << 27) 463*57e252bfSMichael Neumann #define SE_SC_BUSY (1 << 29) 464*57e252bfSMichael Neumann #define SE_DB_BUSY (1 << 30) 465*57e252bfSMichael Neumann #define SE_CB_BUSY (1 << 31) 466*57e252bfSMichael Neumann 467*57e252bfSMichael Neumann #define GRBM_SOFT_RESET 0x8020 468*57e252bfSMichael Neumann #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 469*57e252bfSMichael Neumann #define SOFT_RESET_RLC (1 << 2) /* RLC */ 470*57e252bfSMichael Neumann #define SOFT_RESET_GFX (1 << 16) /* GFX */ 471*57e252bfSMichael Neumann #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 472*57e252bfSMichael Neumann #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 473*57e252bfSMichael Neumann #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 474*57e252bfSMichael Neumann 475*57e252bfSMichael Neumann #define GRBM_INT_CNTL 0x8060 476*57e252bfSMichael Neumann # define RDERR_INT_ENABLE (1 << 0) 477*57e252bfSMichael Neumann # define GUI_IDLE_INT_ENABLE (1 << 19) 478*57e252bfSMichael Neumann 479*57e252bfSMichael Neumann #define CP_CPC_STATUS 0x8210 480*57e252bfSMichael Neumann #define CP_CPC_BUSY_STAT 0x8214 481*57e252bfSMichael Neumann #define CP_CPC_STALLED_STAT1 0x8218 482*57e252bfSMichael Neumann #define CP_CPF_STATUS 0x821c 483*57e252bfSMichael Neumann #define CP_CPF_BUSY_STAT 0x8220 484*57e252bfSMichael Neumann #define CP_CPF_STALLED_STAT1 0x8224 485*57e252bfSMichael Neumann 486*57e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 487*57e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 488*57e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 489*57e252bfSMichael Neumann 490*57e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 491*57e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 492*57e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 493*57e252bfSMichael Neumann 494*57e252bfSMichael Neumann #define CP_STALLED_STAT3 0x8670 495*57e252bfSMichael Neumann #define CP_STALLED_STAT1 0x8674 496*57e252bfSMichael Neumann #define CP_STALLED_STAT2 0x8678 497*57e252bfSMichael Neumann 498*57e252bfSMichael Neumann #define CP_STAT 0x8680 499*57e252bfSMichael Neumann 500*57e252bfSMichael Neumann #define CP_ME_CNTL 0x86D8 501*57e252bfSMichael Neumann #define CP_CE_HALT (1 << 24) 502*57e252bfSMichael Neumann #define CP_PFP_HALT (1 << 26) 503*57e252bfSMichael Neumann #define CP_ME_HALT (1 << 28) 504*57e252bfSMichael Neumann 505*57e252bfSMichael Neumann #define CP_RB0_RPTR 0x8700 506*57e252bfSMichael Neumann #define CP_RB_WPTR_DELAY 0x8704 507*57e252bfSMichael Neumann 508*57e252bfSMichael Neumann #define CP_MEQ_THRESHOLDS 0x8764 509*57e252bfSMichael Neumann #define MEQ1_START(x) ((x) << 0) 510*57e252bfSMichael Neumann #define MEQ2_START(x) ((x) << 8) 511*57e252bfSMichael Neumann 512*57e252bfSMichael Neumann #define VGT_VTX_VECT_EJECT_REG 0x88B0 513*57e252bfSMichael Neumann 514*57e252bfSMichael Neumann #define VGT_CACHE_INVALIDATION 0x88C4 515*57e252bfSMichael Neumann #define CACHE_INVALIDATION(x) ((x) << 0) 516*57e252bfSMichael Neumann #define VC_ONLY 0 517*57e252bfSMichael Neumann #define TC_ONLY 1 518*57e252bfSMichael Neumann #define VC_AND_TC 2 519*57e252bfSMichael Neumann #define AUTO_INVLD_EN(x) ((x) << 6) 520*57e252bfSMichael Neumann #define NO_AUTO 0 521*57e252bfSMichael Neumann #define ES_AUTO 1 522*57e252bfSMichael Neumann #define GS_AUTO 2 523*57e252bfSMichael Neumann #define ES_AND_GS_AUTO 3 524*57e252bfSMichael Neumann 525*57e252bfSMichael Neumann #define VGT_GS_VERTEX_REUSE 0x88D4 526*57e252bfSMichael Neumann 527*57e252bfSMichael Neumann #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 528*57e252bfSMichael Neumann #define INACTIVE_CUS_MASK 0xFFFF0000 529*57e252bfSMichael Neumann #define INACTIVE_CUS_SHIFT 16 530*57e252bfSMichael Neumann #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 531*57e252bfSMichael Neumann 532*57e252bfSMichael Neumann #define PA_CL_ENHANCE 0x8A14 533*57e252bfSMichael Neumann #define CLIP_VTX_REORDER_ENA (1 << 0) 534*57e252bfSMichael Neumann #define NUM_CLIP_SEQ(x) ((x) << 1) 535*57e252bfSMichael Neumann 536*57e252bfSMichael Neumann #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 537*57e252bfSMichael Neumann #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 538*57e252bfSMichael Neumann #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 539*57e252bfSMichael Neumann 540*57e252bfSMichael Neumann #define PA_SC_FIFO_SIZE 0x8BCC 541*57e252bfSMichael Neumann #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 542*57e252bfSMichael Neumann #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 543*57e252bfSMichael Neumann #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 544*57e252bfSMichael Neumann #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 545*57e252bfSMichael Neumann 546*57e252bfSMichael Neumann #define PA_SC_ENHANCE 0x8BF0 547*57e252bfSMichael Neumann #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 548*57e252bfSMichael Neumann #define DISABLE_PA_SC_GUIDANCE (1 << 13) 549*57e252bfSMichael Neumann 550*57e252bfSMichael Neumann #define SQ_CONFIG 0x8C00 551*57e252bfSMichael Neumann 552*57e252bfSMichael Neumann #define SH_MEM_BASES 0x8C28 553*57e252bfSMichael Neumann /* if PTR32, these are the bases for scratch and lds */ 554*57e252bfSMichael Neumann #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 555*57e252bfSMichael Neumann #define SHARED_BASE(x) ((x) << 16) /* LDS */ 556*57e252bfSMichael Neumann #define SH_MEM_APE1_BASE 0x8C2C 557*57e252bfSMichael Neumann /* if PTR32, this is the base location of GPUVM */ 558*57e252bfSMichael Neumann #define SH_MEM_APE1_LIMIT 0x8C30 559*57e252bfSMichael Neumann /* if PTR32, this is the upper limit of GPUVM */ 560*57e252bfSMichael Neumann #define SH_MEM_CONFIG 0x8C34 561*57e252bfSMichael Neumann #define PTR32 (1 << 0) 562*57e252bfSMichael Neumann #define ALIGNMENT_MODE(x) ((x) << 2) 563*57e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD 0 564*57e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 565*57e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_STRICT 2 566*57e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 567*57e252bfSMichael Neumann #define DEFAULT_MTYPE(x) ((x) << 4) 568*57e252bfSMichael Neumann #define APE1_MTYPE(x) ((x) << 7) 569*57e252bfSMichael Neumann 570*57e252bfSMichael Neumann #define SX_DEBUG_1 0x9060 571*57e252bfSMichael Neumann 572*57e252bfSMichael Neumann #define SPI_CONFIG_CNTL 0x9100 573*57e252bfSMichael Neumann 574*57e252bfSMichael Neumann #define SPI_CONFIG_CNTL_1 0x913C 575*57e252bfSMichael Neumann #define VTX_DONE_DELAY(x) ((x) << 0) 576*57e252bfSMichael Neumann #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 577*57e252bfSMichael Neumann 578*57e252bfSMichael Neumann #define TA_CNTL_AUX 0x9508 579*57e252bfSMichael Neumann 580*57e252bfSMichael Neumann #define DB_DEBUG 0x9830 581*57e252bfSMichael Neumann #define DB_DEBUG2 0x9834 582*57e252bfSMichael Neumann #define DB_DEBUG3 0x9838 583*57e252bfSMichael Neumann 584*57e252bfSMichael Neumann #define CC_RB_BACKEND_DISABLE 0x98F4 585*57e252bfSMichael Neumann #define BACKEND_DISABLE(x) ((x) << 16) 586*57e252bfSMichael Neumann #define GB_ADDR_CONFIG 0x98F8 587*57e252bfSMichael Neumann #define NUM_PIPES(x) ((x) << 0) 588*57e252bfSMichael Neumann #define NUM_PIPES_MASK 0x00000007 589*57e252bfSMichael Neumann #define NUM_PIPES_SHIFT 0 590*57e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 591*57e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 592*57e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_SHIFT 4 593*57e252bfSMichael Neumann #define NUM_SHADER_ENGINES(x) ((x) << 12) 594*57e252bfSMichael Neumann #define NUM_SHADER_ENGINES_MASK 0x00003000 595*57e252bfSMichael Neumann #define NUM_SHADER_ENGINES_SHIFT 12 596*57e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 597*57e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 598*57e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 599*57e252bfSMichael Neumann #define ROW_SIZE(x) ((x) << 28) 600*57e252bfSMichael Neumann #define ROW_SIZE_MASK 0x30000000 601*57e252bfSMichael Neumann #define ROW_SIZE_SHIFT 28 602*57e252bfSMichael Neumann 603*57e252bfSMichael Neumann #define GB_TILE_MODE0 0x9910 604*57e252bfSMichael Neumann # define ARRAY_MODE(x) ((x) << 2) 605*57e252bfSMichael Neumann # define ARRAY_LINEAR_GENERAL 0 606*57e252bfSMichael Neumann # define ARRAY_LINEAR_ALIGNED 1 607*57e252bfSMichael Neumann # define ARRAY_1D_TILED_THIN1 2 608*57e252bfSMichael Neumann # define ARRAY_2D_TILED_THIN1 4 609*57e252bfSMichael Neumann # define ARRAY_PRT_TILED_THIN1 5 610*57e252bfSMichael Neumann # define ARRAY_PRT_2D_TILED_THIN1 6 611*57e252bfSMichael Neumann # define PIPE_CONFIG(x) ((x) << 6) 612*57e252bfSMichael Neumann # define ADDR_SURF_P2 0 613*57e252bfSMichael Neumann # define ADDR_SURF_P4_8x16 4 614*57e252bfSMichael Neumann # define ADDR_SURF_P4_16x16 5 615*57e252bfSMichael Neumann # define ADDR_SURF_P4_16x32 6 616*57e252bfSMichael Neumann # define ADDR_SURF_P4_32x32 7 617*57e252bfSMichael Neumann # define ADDR_SURF_P8_16x16_8x16 8 618*57e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_8x16 9 619*57e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_8x16 10 620*57e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_16x16 11 621*57e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x16 12 622*57e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x32 13 623*57e252bfSMichael Neumann # define ADDR_SURF_P8_32x64_32x32 14 624*57e252bfSMichael Neumann # define TILE_SPLIT(x) ((x) << 11) 625*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_64B 0 626*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_128B 1 627*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_256B 2 628*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_512B 3 629*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_1KB 4 630*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_2KB 5 631*57e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_4KB 6 632*57e252bfSMichael Neumann # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 633*57e252bfSMichael Neumann # define ADDR_SURF_DISPLAY_MICRO_TILING 0 634*57e252bfSMichael Neumann # define ADDR_SURF_THIN_MICRO_TILING 1 635*57e252bfSMichael Neumann # define ADDR_SURF_DEPTH_MICRO_TILING 2 636*57e252bfSMichael Neumann # define ADDR_SURF_ROTATED_MICRO_TILING 3 637*57e252bfSMichael Neumann # define SAMPLE_SPLIT(x) ((x) << 25) 638*57e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_1 0 639*57e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_2 1 640*57e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_4 2 641*57e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_8 3 642*57e252bfSMichael Neumann 643*57e252bfSMichael Neumann #define GB_MACROTILE_MODE0 0x9990 644*57e252bfSMichael Neumann # define BANK_WIDTH(x) ((x) << 0) 645*57e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_1 0 646*57e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_2 1 647*57e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_4 2 648*57e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_8 3 649*57e252bfSMichael Neumann # define BANK_HEIGHT(x) ((x) << 2) 650*57e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_1 0 651*57e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_2 1 652*57e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_4 2 653*57e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_8 3 654*57e252bfSMichael Neumann # define MACRO_TILE_ASPECT(x) ((x) << 4) 655*57e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_1 0 656*57e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_2 1 657*57e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_4 2 658*57e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_8 3 659*57e252bfSMichael Neumann # define NUM_BANKS(x) ((x) << 6) 660*57e252bfSMichael Neumann # define ADDR_SURF_2_BANK 0 661*57e252bfSMichael Neumann # define ADDR_SURF_4_BANK 1 662*57e252bfSMichael Neumann # define ADDR_SURF_8_BANK 2 663*57e252bfSMichael Neumann # define ADDR_SURF_16_BANK 3 664*57e252bfSMichael Neumann 665*57e252bfSMichael Neumann #define CB_HW_CONTROL 0x9A10 666*57e252bfSMichael Neumann 667*57e252bfSMichael Neumann #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 668*57e252bfSMichael Neumann #define BACKEND_DISABLE_MASK 0x00FF0000 669*57e252bfSMichael Neumann #define BACKEND_DISABLE_SHIFT 16 670*57e252bfSMichael Neumann 671*57e252bfSMichael Neumann #define TCP_CHAN_STEER_LO 0xac0c 672*57e252bfSMichael Neumann #define TCP_CHAN_STEER_HI 0xac10 673*57e252bfSMichael Neumann 674*57e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY0 0xAC68 675*57e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 676*57e252bfSMichael Neumann #define TC_CFG_L1_STORE_POLICY 0xAC70 677*57e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY0 0xAC74 678*57e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY1 0xAC78 679*57e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY0 0xAC7C 680*57e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY1 0xAC80 681*57e252bfSMichael Neumann #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 682*57e252bfSMichael Neumann #define TC_CFG_L1_VOLATILE 0xAC88 683*57e252bfSMichael Neumann #define TC_CFG_L2_VOLATILE 0xAC8C 684*57e252bfSMichael Neumann 685*57e252bfSMichael Neumann #define CP_RB0_BASE 0xC100 686*57e252bfSMichael Neumann #define CP_RB0_CNTL 0xC104 687*57e252bfSMichael Neumann #define RB_BUFSZ(x) ((x) << 0) 688*57e252bfSMichael Neumann #define RB_BLKSZ(x) ((x) << 8) 689*57e252bfSMichael Neumann #define BUF_SWAP_32BIT (2 << 16) 690*57e252bfSMichael Neumann #define RB_NO_UPDATE (1 << 27) 691*57e252bfSMichael Neumann #define RB_RPTR_WR_ENA (1 << 31) 692*57e252bfSMichael Neumann 693*57e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR 0xC10C 694*57e252bfSMichael Neumann #define RB_RPTR_SWAP_32BIT (2 << 0) 695*57e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR_HI 0xC110 696*57e252bfSMichael Neumann #define CP_RB0_WPTR 0xC114 697*57e252bfSMichael Neumann 698*57e252bfSMichael Neumann #define CP_DEVICE_ID 0xC12C 699*57e252bfSMichael Neumann #define CP_ENDIAN_SWAP 0xC140 700*57e252bfSMichael Neumann #define CP_RB_VMID 0xC144 701*57e252bfSMichael Neumann 702*57e252bfSMichael Neumann #define CP_PFP_UCODE_ADDR 0xC150 703*57e252bfSMichael Neumann #define CP_PFP_UCODE_DATA 0xC154 704*57e252bfSMichael Neumann #define CP_ME_RAM_RADDR 0xC158 705*57e252bfSMichael Neumann #define CP_ME_RAM_WADDR 0xC15C 706*57e252bfSMichael Neumann #define CP_ME_RAM_DATA 0xC160 707*57e252bfSMichael Neumann 708*57e252bfSMichael Neumann #define CP_CE_UCODE_ADDR 0xC168 709*57e252bfSMichael Neumann #define CP_CE_UCODE_DATA 0xC16C 710*57e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_ADDR 0xC170 711*57e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_DATA 0xC174 712*57e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_ADDR 0xC178 713*57e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_DATA 0xC17C 714*57e252bfSMichael Neumann 715*57e252bfSMichael Neumann #define CP_INT_CNTL_RING0 0xC1A8 716*57e252bfSMichael Neumann # define CNTX_BUSY_INT_ENABLE (1 << 19) 717*57e252bfSMichael Neumann # define CNTX_EMPTY_INT_ENABLE (1 << 20) 718*57e252bfSMichael Neumann # define PRIV_INSTR_INT_ENABLE (1 << 22) 719*57e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 720*57e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 721*57e252bfSMichael Neumann # define CP_RINGID2_INT_ENABLE (1 << 29) 722*57e252bfSMichael Neumann # define CP_RINGID1_INT_ENABLE (1 << 30) 723*57e252bfSMichael Neumann # define CP_RINGID0_INT_ENABLE (1 << 31) 724*57e252bfSMichael Neumann 725*57e252bfSMichael Neumann #define CP_INT_STATUS_RING0 0xC1B4 726*57e252bfSMichael Neumann # define PRIV_INSTR_INT_STAT (1 << 22) 727*57e252bfSMichael Neumann # define PRIV_REG_INT_STAT (1 << 23) 728*57e252bfSMichael Neumann # define TIME_STAMP_INT_STAT (1 << 26) 729*57e252bfSMichael Neumann # define CP_RINGID2_INT_STAT (1 << 29) 730*57e252bfSMichael Neumann # define CP_RINGID1_INT_STAT (1 << 30) 731*57e252bfSMichael Neumann # define CP_RINGID0_INT_STAT (1 << 31) 732*57e252bfSMichael Neumann 733*57e252bfSMichael Neumann #define CP_CPF_DEBUG 0xC200 734*57e252bfSMichael Neumann 735*57e252bfSMichael Neumann #define CP_PQ_WPTR_POLL_CNTL 0xC20C 736*57e252bfSMichael Neumann #define WPTR_POLL_EN (1 << 31) 737*57e252bfSMichael Neumann 738*57e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_CNTL 0xC214 739*57e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_CNTL 0xC218 740*57e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_CNTL 0xC21C 741*57e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_CNTL 0xC220 742*57e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_CNTL 0xC224 743*57e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_CNTL 0xC228 744*57e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_CNTL 0xC22C 745*57e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_CNTL 0xC230 746*57e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 747*57e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 748*57e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 749*57e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 750*57e252bfSMichael Neumann # define GENERIC2_INT_ENABLE (1 << 29) 751*57e252bfSMichael Neumann # define GENERIC1_INT_ENABLE (1 << 30) 752*57e252bfSMichael Neumann # define GENERIC0_INT_ENABLE (1 << 31) 753*57e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_STATUS 0xC214 754*57e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_STATUS 0xC218 755*57e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_STATUS 0xC21C 756*57e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_STATUS 0xC220 757*57e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_STATUS 0xC224 758*57e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_STATUS 0xC228 759*57e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_STATUS 0xC22C 760*57e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_STATUS 0xC230 761*57e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 762*57e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 763*57e252bfSMichael Neumann # define PRIV_REG_INT_STATUS (1 << 23) 764*57e252bfSMichael Neumann # define TIME_STAMP_INT_STATUS (1 << 26) 765*57e252bfSMichael Neumann # define GENERIC2_INT_STATUS (1 << 29) 766*57e252bfSMichael Neumann # define GENERIC1_INT_STATUS (1 << 30) 767*57e252bfSMichael Neumann # define GENERIC0_INT_STATUS (1 << 31) 768*57e252bfSMichael Neumann 769*57e252bfSMichael Neumann #define CP_MAX_CONTEXT 0xC2B8 770*57e252bfSMichael Neumann 771*57e252bfSMichael Neumann #define CP_RB0_BASE_HI 0xC2C4 772*57e252bfSMichael Neumann 773*57e252bfSMichael Neumann #define RLC_CNTL 0xC300 774*57e252bfSMichael Neumann # define RLC_ENABLE (1 << 0) 775*57e252bfSMichael Neumann 776*57e252bfSMichael Neumann #define RLC_MC_CNTL 0xC30C 777*57e252bfSMichael Neumann 778*57e252bfSMichael Neumann #define RLC_LB_CNTR_MAX 0xC348 779*57e252bfSMichael Neumann 780*57e252bfSMichael Neumann #define RLC_LB_CNTL 0xC364 781*57e252bfSMichael Neumann 782*57e252bfSMichael Neumann #define RLC_LB_CNTR_INIT 0xC36C 783*57e252bfSMichael Neumann 784*57e252bfSMichael Neumann #define RLC_SAVE_AND_RESTORE_BASE 0xC374 785*57e252bfSMichael Neumann #define RLC_DRIVER_DMA_STATUS 0xC378 786*57e252bfSMichael Neumann 787*57e252bfSMichael Neumann #define RLC_GPM_UCODE_ADDR 0xC388 788*57e252bfSMichael Neumann #define RLC_GPM_UCODE_DATA 0xC38C 789*57e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 790*57e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 791*57e252bfSMichael Neumann #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 792*57e252bfSMichael Neumann #define RLC_UCODE_CNTL 0xC39C 793*57e252bfSMichael Neumann 794*57e252bfSMichael Neumann #define RLC_CGCG_CGLS_CTRL 0xC424 795*57e252bfSMichael Neumann 796*57e252bfSMichael Neumann #define RLC_LB_INIT_CU_MASK 0xC43C 797*57e252bfSMichael Neumann 798*57e252bfSMichael Neumann #define RLC_LB_PARAMS 0xC444 799*57e252bfSMichael Neumann 800*57e252bfSMichael Neumann #define RLC_SERDES_CU_MASTER_BUSY 0xC484 801*57e252bfSMichael Neumann #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 802*57e252bfSMichael Neumann # define SE_MASTER_BUSY_MASK 0x0000ffff 803*57e252bfSMichael Neumann # define GC_MASTER_BUSY (1 << 16) 804*57e252bfSMichael Neumann # define TC0_MASTER_BUSY (1 << 17) 805*57e252bfSMichael Neumann # define TC1_MASTER_BUSY (1 << 18) 806*57e252bfSMichael Neumann 807*57e252bfSMichael Neumann #define RLC_GPM_SCRATCH_ADDR 0xC4B0 808*57e252bfSMichael Neumann #define RLC_GPM_SCRATCH_DATA 0xC4B4 809*57e252bfSMichael Neumann 810*57e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR 0xC904 811*57e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 812*57e252bfSMichael Neumann #define CP_HPD_EOP_VMID 0xC90C 813*57e252bfSMichael Neumann #define CP_HPD_EOP_CONTROL 0xC910 814*57e252bfSMichael Neumann #define EOP_SIZE(x) ((x) << 0) 815*57e252bfSMichael Neumann #define EOP_SIZE_MASK (0x3f << 0) 816*57e252bfSMichael Neumann #define CP_MQD_BASE_ADDR 0xC914 817*57e252bfSMichael Neumann #define CP_MQD_BASE_ADDR_HI 0xC918 818*57e252bfSMichael Neumann #define CP_HQD_ACTIVE 0xC91C 819*57e252bfSMichael Neumann #define CP_HQD_VMID 0xC920 820*57e252bfSMichael Neumann 821*57e252bfSMichael Neumann #define CP_HQD_PQ_BASE 0xC934 822*57e252bfSMichael Neumann #define CP_HQD_PQ_BASE_HI 0xC938 823*57e252bfSMichael Neumann #define CP_HQD_PQ_RPTR 0xC93C 824*57e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 825*57e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 826*57e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 827*57e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 828*57e252bfSMichael Neumann #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 829*57e252bfSMichael Neumann #define DOORBELL_OFFSET(x) ((x) << 2) 830*57e252bfSMichael Neumann #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 831*57e252bfSMichael Neumann #define DOORBELL_SOURCE (1 << 28) 832*57e252bfSMichael Neumann #define DOORBELL_SCHD_HIT (1 << 29) 833*57e252bfSMichael Neumann #define DOORBELL_EN (1 << 30) 834*57e252bfSMichael Neumann #define DOORBELL_HIT (1 << 31) 835*57e252bfSMichael Neumann #define CP_HQD_PQ_WPTR 0xC954 836*57e252bfSMichael Neumann #define CP_HQD_PQ_CONTROL 0xC958 837*57e252bfSMichael Neumann #define QUEUE_SIZE(x) ((x) << 0) 838*57e252bfSMichael Neumann #define QUEUE_SIZE_MASK (0x3f << 0) 839*57e252bfSMichael Neumann #define RPTR_BLOCK_SIZE(x) ((x) << 8) 840*57e252bfSMichael Neumann #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 841*57e252bfSMichael Neumann #define PQ_VOLATILE (1 << 26) 842*57e252bfSMichael Neumann #define NO_UPDATE_RPTR (1 << 27) 843*57e252bfSMichael Neumann #define UNORD_DISPATCH (1 << 28) 844*57e252bfSMichael Neumann #define ROQ_PQ_IB_FLIP (1 << 29) 845*57e252bfSMichael Neumann #define PRIV_STATE (1 << 30) 846*57e252bfSMichael Neumann #define KMD_QUEUE (1 << 31) 847*57e252bfSMichael Neumann 848*57e252bfSMichael Neumann #define CP_HQD_DEQUEUE_REQUEST 0xC974 849*57e252bfSMichael Neumann 850*57e252bfSMichael Neumann #define CP_MQD_CONTROL 0xC99C 851*57e252bfSMichael Neumann #define MQD_VMID(x) ((x) << 0) 852*57e252bfSMichael Neumann #define MQD_VMID_MASK (0xf << 0) 853*57e252bfSMichael Neumann 854*57e252bfSMichael Neumann #define PA_SC_RASTER_CONFIG 0x28350 855*57e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_0 0 856*57e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_1 1 857*57e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_2 2 858*57e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_3 3 859*57e252bfSMichael Neumann 860*57e252bfSMichael Neumann #define VGT_EVENT_INITIATOR 0x28a90 861*57e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 862*57e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 863*57e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 864*57e252bfSMichael Neumann # define CACHE_FLUSH_TS (4 << 0) 865*57e252bfSMichael Neumann # define CACHE_FLUSH (6 << 0) 866*57e252bfSMichael Neumann # define CS_PARTIAL_FLUSH (7 << 0) 867*57e252bfSMichael Neumann # define VGT_STREAMOUT_RESET (10 << 0) 868*57e252bfSMichael Neumann # define END_OF_PIPE_INCR_DE (11 << 0) 869*57e252bfSMichael Neumann # define END_OF_PIPE_IB_END (12 << 0) 870*57e252bfSMichael Neumann # define RST_PIX_CNT (13 << 0) 871*57e252bfSMichael Neumann # define VS_PARTIAL_FLUSH (15 << 0) 872*57e252bfSMichael Neumann # define PS_PARTIAL_FLUSH (16 << 0) 873*57e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 874*57e252bfSMichael Neumann # define ZPASS_DONE (21 << 0) 875*57e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 876*57e252bfSMichael Neumann # define PERFCOUNTER_START (23 << 0) 877*57e252bfSMichael Neumann # define PERFCOUNTER_STOP (24 << 0) 878*57e252bfSMichael Neumann # define PIPELINESTAT_START (25 << 0) 879*57e252bfSMichael Neumann # define PIPELINESTAT_STOP (26 << 0) 880*57e252bfSMichael Neumann # define PERFCOUNTER_SAMPLE (27 << 0) 881*57e252bfSMichael Neumann # define SAMPLE_PIPELINESTAT (30 << 0) 882*57e252bfSMichael Neumann # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 883*57e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS (32 << 0) 884*57e252bfSMichael Neumann # define RESET_VTX_CNT (33 << 0) 885*57e252bfSMichael Neumann # define VGT_FLUSH (36 << 0) 886*57e252bfSMichael Neumann # define BOTTOM_OF_PIPE_TS (40 << 0) 887*57e252bfSMichael Neumann # define DB_CACHE_FLUSH_AND_INV (42 << 0) 888*57e252bfSMichael Neumann # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 889*57e252bfSMichael Neumann # define FLUSH_AND_INV_DB_META (44 << 0) 890*57e252bfSMichael Neumann # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 891*57e252bfSMichael Neumann # define FLUSH_AND_INV_CB_META (46 << 0) 892*57e252bfSMichael Neumann # define CS_DONE (47 << 0) 893*57e252bfSMichael Neumann # define PS_DONE (48 << 0) 894*57e252bfSMichael Neumann # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 895*57e252bfSMichael Neumann # define THREAD_TRACE_START (51 << 0) 896*57e252bfSMichael Neumann # define THREAD_TRACE_STOP (52 << 0) 897*57e252bfSMichael Neumann # define THREAD_TRACE_FLUSH (54 << 0) 898*57e252bfSMichael Neumann # define THREAD_TRACE_FINISH (55 << 0) 899*57e252bfSMichael Neumann # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 900*57e252bfSMichael Neumann # define PIXEL_PIPE_STAT_DUMP (57 << 0) 901*57e252bfSMichael Neumann # define PIXEL_PIPE_STAT_RESET (58 << 0) 902*57e252bfSMichael Neumann 903*57e252bfSMichael Neumann #define SCRATCH_REG0 0x30100 904*57e252bfSMichael Neumann #define SCRATCH_REG1 0x30104 905*57e252bfSMichael Neumann #define SCRATCH_REG2 0x30108 906*57e252bfSMichael Neumann #define SCRATCH_REG3 0x3010C 907*57e252bfSMichael Neumann #define SCRATCH_REG4 0x30110 908*57e252bfSMichael Neumann #define SCRATCH_REG5 0x30114 909*57e252bfSMichael Neumann #define SCRATCH_REG6 0x30118 910*57e252bfSMichael Neumann #define SCRATCH_REG7 0x3011C 911*57e252bfSMichael Neumann 912*57e252bfSMichael Neumann #define SCRATCH_UMSK 0x30140 913*57e252bfSMichael Neumann #define SCRATCH_ADDR 0x30144 914*57e252bfSMichael Neumann 915*57e252bfSMichael Neumann #define CP_SEM_WAIT_TIMER 0x301BC 916*57e252bfSMichael Neumann 917*57e252bfSMichael Neumann #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 918*57e252bfSMichael Neumann 919*57e252bfSMichael Neumann #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 920*57e252bfSMichael Neumann 921*57e252bfSMichael Neumann #define GRBM_GFX_INDEX 0x30800 922*57e252bfSMichael Neumann #define INSTANCE_INDEX(x) ((x) << 0) 923*57e252bfSMichael Neumann #define SH_INDEX(x) ((x) << 8) 924*57e252bfSMichael Neumann #define SE_INDEX(x) ((x) << 16) 925*57e252bfSMichael Neumann #define SH_BROADCAST_WRITES (1 << 29) 926*57e252bfSMichael Neumann #define INSTANCE_BROADCAST_WRITES (1 << 30) 927*57e252bfSMichael Neumann #define SE_BROADCAST_WRITES (1 << 31) 928*57e252bfSMichael Neumann 929*57e252bfSMichael Neumann #define VGT_ESGS_RING_SIZE 0x30900 930*57e252bfSMichael Neumann #define VGT_GSVS_RING_SIZE 0x30904 931*57e252bfSMichael Neumann #define VGT_PRIMITIVE_TYPE 0x30908 932*57e252bfSMichael Neumann #define VGT_INDEX_TYPE 0x3090C 933*57e252bfSMichael Neumann 934*57e252bfSMichael Neumann #define VGT_NUM_INDICES 0x30930 935*57e252bfSMichael Neumann #define VGT_NUM_INSTANCES 0x30934 936*57e252bfSMichael Neumann #define VGT_TF_RING_SIZE 0x30938 937*57e252bfSMichael Neumann #define VGT_HS_OFFCHIP_PARAM 0x3093C 938*57e252bfSMichael Neumann #define VGT_TF_MEMORY_BASE 0x30940 939*57e252bfSMichael Neumann 940*57e252bfSMichael Neumann #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 941*57e252bfSMichael Neumann #define PA_SC_LINE_STIPPLE_STATE 0x30a04 942*57e252bfSMichael Neumann 943*57e252bfSMichael Neumann #define SQC_CACHES 0x30d20 944*57e252bfSMichael Neumann 945*57e252bfSMichael Neumann #define CP_PERFMON_CNTL 0x36020 946*57e252bfSMichael Neumann 947*57e252bfSMichael Neumann #define CGTS_TCC_DISABLE 0x3c00c 948*57e252bfSMichael Neumann #define CGTS_USER_TCC_DISABLE 0x3c010 949*57e252bfSMichael Neumann #define TCC_DISABLE_MASK 0xFFFF0000 950*57e252bfSMichael Neumann #define TCC_DISABLE_SHIFT 16 951*57e252bfSMichael Neumann 952*57e252bfSMichael Neumann #define CB_CGTT_SCLK_CTRL 0x3c2a0 953*57e252bfSMichael Neumann 954*57e252bfSMichael Neumann /* 955*57e252bfSMichael Neumann * PM4 956*57e252bfSMichael Neumann */ 957*57e252bfSMichael Neumann #define PACKET_TYPE0 0 958*57e252bfSMichael Neumann #define PACKET_TYPE1 1 959*57e252bfSMichael Neumann #define PACKET_TYPE2 2 960*57e252bfSMichael Neumann #define PACKET_TYPE3 3 961*57e252bfSMichael Neumann 962*57e252bfSMichael Neumann #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 963*57e252bfSMichael Neumann #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 964*57e252bfSMichael Neumann #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 965*57e252bfSMichael Neumann #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 966*57e252bfSMichael Neumann #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 967*57e252bfSMichael Neumann (((reg) >> 2) & 0xFFFF) | \ 968*57e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 969*57e252bfSMichael Neumann #define CP_PACKET2 0x80000000 970*57e252bfSMichael Neumann #define PACKET2_PAD_SHIFT 0 971*57e252bfSMichael Neumann #define PACKET2_PAD_MASK (0x3fffffff << 0) 972*57e252bfSMichael Neumann 973*57e252bfSMichael Neumann #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 974*57e252bfSMichael Neumann 975*57e252bfSMichael Neumann #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 976*57e252bfSMichael Neumann (((op) & 0xFF) << 8) | \ 977*57e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 978*57e252bfSMichael Neumann 979*57e252bfSMichael Neumann #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 980*57e252bfSMichael Neumann 981*57e252bfSMichael Neumann /* Packet 3 types */ 982*57e252bfSMichael Neumann #define PACKET3_NOP 0x10 983*57e252bfSMichael Neumann #define PACKET3_SET_BASE 0x11 984*57e252bfSMichael Neumann #define PACKET3_BASE_INDEX(x) ((x) << 0) 985*57e252bfSMichael Neumann #define CE_PARTITION_BASE 3 986*57e252bfSMichael Neumann #define PACKET3_CLEAR_STATE 0x12 987*57e252bfSMichael Neumann #define PACKET3_INDEX_BUFFER_SIZE 0x13 988*57e252bfSMichael Neumann #define PACKET3_DISPATCH_DIRECT 0x15 989*57e252bfSMichael Neumann #define PACKET3_DISPATCH_INDIRECT 0x16 990*57e252bfSMichael Neumann #define PACKET3_ATOMIC_GDS 0x1D 991*57e252bfSMichael Neumann #define PACKET3_ATOMIC_MEM 0x1E 992*57e252bfSMichael Neumann #define PACKET3_OCCLUSION_QUERY 0x1F 993*57e252bfSMichael Neumann #define PACKET3_SET_PREDICATION 0x20 994*57e252bfSMichael Neumann #define PACKET3_REG_RMW 0x21 995*57e252bfSMichael Neumann #define PACKET3_COND_EXEC 0x22 996*57e252bfSMichael Neumann #define PACKET3_PRED_EXEC 0x23 997*57e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT 0x24 998*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT 0x25 999*57e252bfSMichael Neumann #define PACKET3_INDEX_BASE 0x26 1000*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_2 0x27 1001*57e252bfSMichael Neumann #define PACKET3_CONTEXT_CONTROL 0x28 1002*57e252bfSMichael Neumann #define PACKET3_INDEX_TYPE 0x2A 1003*57e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1004*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_AUTO 0x2D 1005*57e252bfSMichael Neumann #define PACKET3_NUM_INSTANCES 0x2F 1006*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1007*57e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1008*57e252bfSMichael Neumann #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1009*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1010*57e252bfSMichael Neumann #define PACKET3_DRAW_PREAMBLE 0x36 1011*57e252bfSMichael Neumann #define PACKET3_WRITE_DATA 0x37 1012*57e252bfSMichael Neumann #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1013*57e252bfSMichael Neumann /* 0 - register 1014*57e252bfSMichael Neumann * 1 - memory (sync - via GRBM) 1015*57e252bfSMichael Neumann * 2 - gl2 1016*57e252bfSMichael Neumann * 3 - gds 1017*57e252bfSMichael Neumann * 4 - reserved 1018*57e252bfSMichael Neumann * 5 - memory (async - direct) 1019*57e252bfSMichael Neumann */ 1020*57e252bfSMichael Neumann #define WR_ONE_ADDR (1 << 16) 1021*57e252bfSMichael Neumann #define WR_CONFIRM (1 << 20) 1022*57e252bfSMichael Neumann #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 1023*57e252bfSMichael Neumann /* 0 - LRU 1024*57e252bfSMichael Neumann * 1 - Stream 1025*57e252bfSMichael Neumann */ 1026*57e252bfSMichael Neumann #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1027*57e252bfSMichael Neumann /* 0 - me 1028*57e252bfSMichael Neumann * 1 - pfp 1029*57e252bfSMichael Neumann * 2 - ce 1030*57e252bfSMichael Neumann */ 1031*57e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1032*57e252bfSMichael Neumann #define PACKET3_MEM_SEMAPHORE 0x39 1033*57e252bfSMichael Neumann # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 1034*57e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 1035*57e252bfSMichael Neumann # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 1036*57e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1037*57e252bfSMichael Neumann # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1038*57e252bfSMichael Neumann #define PACKET3_COPY_DW 0x3B 1039*57e252bfSMichael Neumann #define PACKET3_WAIT_REG_MEM 0x3C 1040*57e252bfSMichael Neumann #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1041*57e252bfSMichael Neumann /* 0 - always 1042*57e252bfSMichael Neumann * 1 - < 1043*57e252bfSMichael Neumann * 2 - <= 1044*57e252bfSMichael Neumann * 3 - == 1045*57e252bfSMichael Neumann * 4 - != 1046*57e252bfSMichael Neumann * 5 - >= 1047*57e252bfSMichael Neumann * 6 - > 1048*57e252bfSMichael Neumann */ 1049*57e252bfSMichael Neumann #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1050*57e252bfSMichael Neumann /* 0 - reg 1051*57e252bfSMichael Neumann * 1 - mem 1052*57e252bfSMichael Neumann */ 1053*57e252bfSMichael Neumann #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 1054*57e252bfSMichael Neumann /* 0 - wait_reg_mem 1055*57e252bfSMichael Neumann * 1 - wr_wait_wr_reg 1056*57e252bfSMichael Neumann */ 1057*57e252bfSMichael Neumann #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1058*57e252bfSMichael Neumann /* 0 - me 1059*57e252bfSMichael Neumann * 1 - pfp 1060*57e252bfSMichael Neumann */ 1061*57e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER 0x3F 1062*57e252bfSMichael Neumann #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 1063*57e252bfSMichael Neumann #define INDIRECT_BUFFER_VALID (1 << 23) 1064*57e252bfSMichael Neumann #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 1065*57e252bfSMichael Neumann /* 0 - LRU 1066*57e252bfSMichael Neumann * 1 - Stream 1067*57e252bfSMichael Neumann * 2 - Bypass 1068*57e252bfSMichael Neumann */ 1069*57e252bfSMichael Neumann #define PACKET3_COPY_DATA 0x40 1070*57e252bfSMichael Neumann #define PACKET3_PFP_SYNC_ME 0x42 1071*57e252bfSMichael Neumann #define PACKET3_SURFACE_SYNC 0x43 1072*57e252bfSMichael Neumann # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1073*57e252bfSMichael Neumann # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1074*57e252bfSMichael Neumann # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1075*57e252bfSMichael Neumann # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1076*57e252bfSMichael Neumann # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1077*57e252bfSMichael Neumann # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1078*57e252bfSMichael Neumann # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1079*57e252bfSMichael Neumann # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1080*57e252bfSMichael Neumann # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1081*57e252bfSMichael Neumann # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1082*57e252bfSMichael Neumann # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1083*57e252bfSMichael Neumann # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1084*57e252bfSMichael Neumann # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1085*57e252bfSMichael Neumann # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1086*57e252bfSMichael Neumann # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1087*57e252bfSMichael Neumann # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1088*57e252bfSMichael Neumann # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1089*57e252bfSMichael Neumann # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1090*57e252bfSMichael Neumann # define PACKET3_CB_ACTION_ENA (1 << 25) 1091*57e252bfSMichael Neumann # define PACKET3_DB_ACTION_ENA (1 << 26) 1092*57e252bfSMichael Neumann # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1093*57e252bfSMichael Neumann # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1094*57e252bfSMichael Neumann # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1095*57e252bfSMichael Neumann #define PACKET3_COND_WRITE 0x45 1096*57e252bfSMichael Neumann #define PACKET3_EVENT_WRITE 0x46 1097*57e252bfSMichael Neumann #define EVENT_TYPE(x) ((x) << 0) 1098*57e252bfSMichael Neumann #define EVENT_INDEX(x) ((x) << 8) 1099*57e252bfSMichael Neumann /* 0 - any non-TS event 1100*57e252bfSMichael Neumann * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1101*57e252bfSMichael Neumann * 2 - SAMPLE_PIPELINESTAT 1102*57e252bfSMichael Neumann * 3 - SAMPLE_STREAMOUTSTAT* 1103*57e252bfSMichael Neumann * 4 - *S_PARTIAL_FLUSH 1104*57e252bfSMichael Neumann * 5 - EOP events 1105*57e252bfSMichael Neumann * 6 - EOS events 1106*57e252bfSMichael Neumann */ 1107*57e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOP 0x47 1108*57e252bfSMichael Neumann #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1109*57e252bfSMichael Neumann #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1110*57e252bfSMichael Neumann #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1111*57e252bfSMichael Neumann #define EOP_TCL1_ACTION_EN (1 << 16) 1112*57e252bfSMichael Neumann #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1113*57e252bfSMichael Neumann #define EOP_CACHE_POLICY(x) ((x) << 25) 1114*57e252bfSMichael Neumann /* 0 - LRU 1115*57e252bfSMichael Neumann * 1 - Stream 1116*57e252bfSMichael Neumann * 2 - Bypass 1117*57e252bfSMichael Neumann */ 1118*57e252bfSMichael Neumann #define EOP_TCL2_VOLATILE (1 << 27) 1119*57e252bfSMichael Neumann #define DATA_SEL(x) ((x) << 29) 1120*57e252bfSMichael Neumann /* 0 - discard 1121*57e252bfSMichael Neumann * 1 - send low 32bit data 1122*57e252bfSMichael Neumann * 2 - send 64bit data 1123*57e252bfSMichael Neumann * 3 - send 64bit GPU counter value 1124*57e252bfSMichael Neumann * 4 - send 64bit sys counter value 1125*57e252bfSMichael Neumann */ 1126*57e252bfSMichael Neumann #define INT_SEL(x) ((x) << 24) 1127*57e252bfSMichael Neumann /* 0 - none 1128*57e252bfSMichael Neumann * 1 - interrupt only (DATA_SEL = 0) 1129*57e252bfSMichael Neumann * 2 - interrupt when data write is confirmed 1130*57e252bfSMichael Neumann */ 1131*57e252bfSMichael Neumann #define DST_SEL(x) ((x) << 16) 1132*57e252bfSMichael Neumann /* 0 - MC 1133*57e252bfSMichael Neumann * 1 - TC/L2 1134*57e252bfSMichael Neumann */ 1135*57e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOS 0x48 1136*57e252bfSMichael Neumann #define PACKET3_RELEASE_MEM 0x49 1137*57e252bfSMichael Neumann #define PACKET3_PREAMBLE_CNTL 0x4A 1138*57e252bfSMichael Neumann # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1139*57e252bfSMichael Neumann # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1140*57e252bfSMichael Neumann #define PACKET3_DMA_DATA 0x50 1141*57e252bfSMichael Neumann #define PACKET3_AQUIRE_MEM 0x58 1142*57e252bfSMichael Neumann #define PACKET3_REWIND 0x59 1143*57e252bfSMichael Neumann #define PACKET3_LOAD_UCONFIG_REG 0x5E 1144*57e252bfSMichael Neumann #define PACKET3_LOAD_SH_REG 0x5F 1145*57e252bfSMichael Neumann #define PACKET3_LOAD_CONFIG_REG 0x60 1146*57e252bfSMichael Neumann #define PACKET3_LOAD_CONTEXT_REG 0x61 1147*57e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG 0x68 1148*57e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_START 0x00008000 1149*57e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1150*57e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG 0x69 1151*57e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1152*57e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1153*57e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1154*57e252bfSMichael Neumann #define PACKET3_SET_SH_REG 0x76 1155*57e252bfSMichael Neumann #define PACKET3_SET_SH_REG_START 0x0000b000 1156*57e252bfSMichael Neumann #define PACKET3_SET_SH_REG_END 0x0000c000 1157*57e252bfSMichael Neumann #define PACKET3_SET_SH_REG_OFFSET 0x77 1158*57e252bfSMichael Neumann #define PACKET3_SET_QUEUE_REG 0x78 1159*57e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG 0x79 1160*57e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_START 0x00030000 1161*57e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1162*57e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1163*57e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_READ 0x7E 1164*57e252bfSMichael Neumann #define PACKET3_LOAD_CONST_RAM 0x80 1165*57e252bfSMichael Neumann #define PACKET3_WRITE_CONST_RAM 0x81 1166*57e252bfSMichael Neumann #define PACKET3_DUMP_CONST_RAM 0x83 1167*57e252bfSMichael Neumann #define PACKET3_INCREMENT_CE_COUNTER 0x84 1168*57e252bfSMichael Neumann #define PACKET3_INCREMENT_DE_COUNTER 0x85 1169*57e252bfSMichael Neumann #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1170*57e252bfSMichael Neumann #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1171*57e252bfSMichael Neumann #define PACKET3_SWITCH_BUFFER 0x8B 1172*57e252bfSMichael Neumann 1173*57e252bfSMichael Neumann /* SDMA - first instance at 0xd000, second at 0xd800 */ 1174*57e252bfSMichael Neumann #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 1175*57e252bfSMichael Neumann #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 1176*57e252bfSMichael Neumann 1177*57e252bfSMichael Neumann #define SDMA0_UCODE_ADDR 0xD000 1178*57e252bfSMichael Neumann #define SDMA0_UCODE_DATA 0xD004 1179*57e252bfSMichael Neumann 1180*57e252bfSMichael Neumann #define SDMA0_CNTL 0xD010 1181*57e252bfSMichael Neumann # define TRAP_ENABLE (1 << 0) 1182*57e252bfSMichael Neumann # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1183*57e252bfSMichael Neumann # define SEM_WAIT_INT_ENABLE (1 << 2) 1184*57e252bfSMichael Neumann # define DATA_SWAP_ENABLE (1 << 3) 1185*57e252bfSMichael Neumann # define FENCE_SWAP_ENABLE (1 << 4) 1186*57e252bfSMichael Neumann # define AUTO_CTXSW_ENABLE (1 << 18) 1187*57e252bfSMichael Neumann # define CTXEMPTY_INT_ENABLE (1 << 28) 1188*57e252bfSMichael Neumann 1189*57e252bfSMichael Neumann #define SDMA0_TILING_CONFIG 0xD018 1190*57e252bfSMichael Neumann 1191*57e252bfSMichael Neumann #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 1192*57e252bfSMichael Neumann #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 1193*57e252bfSMichael Neumann 1194*57e252bfSMichael Neumann #define SDMA0_STATUS_REG 0xd034 1195*57e252bfSMichael Neumann # define SDMA_IDLE (1 << 0) 1196*57e252bfSMichael Neumann 1197*57e252bfSMichael Neumann #define SDMA0_ME_CNTL 0xD048 1198*57e252bfSMichael Neumann # define SDMA_HALT (1 << 0) 1199*57e252bfSMichael Neumann 1200*57e252bfSMichael Neumann #define SDMA0_GFX_RB_CNTL 0xD200 1201*57e252bfSMichael Neumann # define SDMA_RB_ENABLE (1 << 0) 1202*57e252bfSMichael Neumann # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1203*57e252bfSMichael Neumann # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1204*57e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1205*57e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1206*57e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1207*57e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE 0xD204 1208*57e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE_HI 0xD208 1209*57e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR 0xD20C 1210*57e252bfSMichael Neumann #define SDMA0_GFX_RB_WPTR 0xD210 1211*57e252bfSMichael Neumann 1212*57e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 1213*57e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 1214*57e252bfSMichael Neumann #define SDMA0_GFX_IB_CNTL 0xD228 1215*57e252bfSMichael Neumann # define SDMA_IB_ENABLE (1 << 0) 1216*57e252bfSMichael Neumann # define SDMA_IB_SWAP_ENABLE (1 << 4) 1217*57e252bfSMichael Neumann # define SDMA_SWITCH_INSIDE_IB (1 << 8) 1218*57e252bfSMichael Neumann # define SDMA_CMD_VMID(x) ((x) << 16) 1219*57e252bfSMichael Neumann 1220*57e252bfSMichael Neumann #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 1221*57e252bfSMichael Neumann #define SDMA0_GFX_APE1_CNTL 0xD2A0 1222*57e252bfSMichael Neumann 1223*57e252bfSMichael Neumann #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 1224*57e252bfSMichael Neumann (((sub_op) & 0xFF) << 8) | \ 1225*57e252bfSMichael Neumann (((op) & 0xFF) << 0)) 1226*57e252bfSMichael Neumann /* sDMA opcodes */ 1227*57e252bfSMichael Neumann #define SDMA_OPCODE_NOP 0 1228*57e252bfSMichael Neumann #define SDMA_OPCODE_COPY 1 1229*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR 0 1230*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED 1 1231*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_SOA 3 1232*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 1233*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 1234*57e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 1235*57e252bfSMichael Neumann #define SDMA_OPCODE_WRITE 2 1236*57e252bfSMichael Neumann # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 1237*57e252bfSMichael Neumann # define SDMA_WRTIE_SUB_OPCODE_TILED 1 1238*57e252bfSMichael Neumann #define SDMA_OPCODE_INDIRECT_BUFFER 4 1239*57e252bfSMichael Neumann #define SDMA_OPCODE_FENCE 5 1240*57e252bfSMichael Neumann #define SDMA_OPCODE_TRAP 6 1241*57e252bfSMichael Neumann #define SDMA_OPCODE_SEMAPHORE 7 1242*57e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 1243*57e252bfSMichael Neumann /* 0 - increment 1244*57e252bfSMichael Neumann * 1 - write 1 1245*57e252bfSMichael Neumann */ 1246*57e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 1247*57e252bfSMichael Neumann /* 0 - wait 1248*57e252bfSMichael Neumann * 1 - signal 1249*57e252bfSMichael Neumann */ 1250*57e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 1251*57e252bfSMichael Neumann /* mailbox */ 1252*57e252bfSMichael Neumann #define SDMA_OPCODE_POLL_REG_MEM 8 1253*57e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 1254*57e252bfSMichael Neumann /* 0 - wait_reg_mem 1255*57e252bfSMichael Neumann * 1 - wr_wait_wr_reg 1256*57e252bfSMichael Neumann */ 1257*57e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 1258*57e252bfSMichael Neumann /* 0 - always 1259*57e252bfSMichael Neumann * 1 - < 1260*57e252bfSMichael Neumann * 2 - <= 1261*57e252bfSMichael Neumann * 3 - == 1262*57e252bfSMichael Neumann * 4 - != 1263*57e252bfSMichael Neumann * 5 - >= 1264*57e252bfSMichael Neumann * 6 - > 1265*57e252bfSMichael Neumann */ 1266*57e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 1267*57e252bfSMichael Neumann /* 0 = register 1268*57e252bfSMichael Neumann * 1 = memory 1269*57e252bfSMichael Neumann */ 1270*57e252bfSMichael Neumann #define SDMA_OPCODE_COND_EXEC 9 1271*57e252bfSMichael Neumann #define SDMA_OPCODE_CONSTANT_FILL 11 1272*57e252bfSMichael Neumann # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 1273*57e252bfSMichael Neumann /* 0 = byte fill 1274*57e252bfSMichael Neumann * 2 = DW fill 1275*57e252bfSMichael Neumann */ 1276*57e252bfSMichael Neumann #define SDMA_OPCODE_GENERATE_PTE_PDE 12 1277*57e252bfSMichael Neumann #define SDMA_OPCODE_TIMESTAMP 13 1278*57e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 1279*57e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 1280*57e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 1281*57e252bfSMichael Neumann #define SDMA_OPCODE_SRBM_WRITE 14 1282*57e252bfSMichael Neumann # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 1283*57e252bfSMichael Neumann /* byte mask */ 1284*57e252bfSMichael Neumann 1285*57e252bfSMichael Neumann /* UVD */ 1286*57e252bfSMichael Neumann 1287*57e252bfSMichael Neumann #define UVD_UDEC_ADDR_CONFIG 0xef4c 1288*57e252bfSMichael Neumann #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1289*57e252bfSMichael Neumann #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1290*57e252bfSMichael Neumann 1291*57e252bfSMichael Neumann #define UVD_LMI_EXT40_ADDR 0xf498 1292*57e252bfSMichael Neumann #define UVD_LMI_ADDR_EXT 0xf594 1293*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET0 0xf608 1294*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE0 0xf60c 1295*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET1 0xf610 1296*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE1 0xf614 1297*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET2 0xf618 1298*57e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE2 0xf61c 1299*57e252bfSMichael Neumann 1300*57e252bfSMichael Neumann #define UVD_RBC_RB_RPTR 0xf690 1301*57e252bfSMichael Neumann #define UVD_RBC_RB_WPTR 0xf694 1302*57e252bfSMichael Neumann 1303*57e252bfSMichael Neumann /* UVD clocks */ 1304*57e252bfSMichael Neumann 1305*57e252bfSMichael Neumann #define CG_DCLK_CNTL 0xC050009C 1306*57e252bfSMichael Neumann # define DCLK_DIVIDER_MASK 0x7f 1307*57e252bfSMichael Neumann # define DCLK_DIR_CNTL_EN (1 << 8) 1308*57e252bfSMichael Neumann #define CG_DCLK_STATUS 0xC05000A0 1309*57e252bfSMichael Neumann # define DCLK_STATUS (1 << 0) 1310*57e252bfSMichael Neumann #define CG_VCLK_CNTL 0xC05000A4 1311*57e252bfSMichael Neumann #define CG_VCLK_STATUS 0xC05000A8 1312*57e252bfSMichael Neumann 1313*57e252bfSMichael Neumann #endif 1314