157e252bfSMichael Neumann /* 257e252bfSMichael Neumann * Copyright 2012 Advanced Micro Devices, Inc. 357e252bfSMichael Neumann * 457e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 557e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 657e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 757e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 857e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 957e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 1057e252bfSMichael Neumann * 1157e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 1257e252bfSMichael Neumann * all copies or substantial portions of the Software. 1357e252bfSMichael Neumann * 1457e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1557e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1657e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1757e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1857e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1957e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2057e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 2157e252bfSMichael Neumann * 2257e252bfSMichael Neumann * Authors: Alex Deucher 2357e252bfSMichael Neumann */ 2457e252bfSMichael Neumann #ifndef CIK_H 2557e252bfSMichael Neumann #define CIK_H 2657e252bfSMichael Neumann 2757e252bfSMichael Neumann #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28c6f73aabSFrançois Tigeot #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 2957e252bfSMichael Neumann 3057e252bfSMichael Neumann #define CIK_RB_BITMAP_WIDTH_PER_SH 2 31c6f73aabSFrançois Tigeot #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 3257e252bfSMichael Neumann 33*7dcf36dcSFrançois Tigeot #define RADEON_NUM_OF_VMIDS 8 34*7dcf36dcSFrançois Tigeot 354cd92098Szrj /* DIDT IND registers */ 364cd92098Szrj #define DIDT_SQ_CTRL0 0x0 374cd92098Szrj # define DIDT_CTRL_EN (1 << 0) 384cd92098Szrj #define DIDT_DB_CTRL0 0x20 394cd92098Szrj #define DIDT_TD_CTRL0 0x40 404cd92098Szrj #define DIDT_TCP_CTRL0 0x60 4157e252bfSMichael Neumann 424cd92098Szrj /* SMC IND registers */ 434cd92098Szrj #define DPM_TABLE_475 0x3F768 444cd92098Szrj # define SamuBootLevel(x) ((x) << 0) 454cd92098Szrj # define SamuBootLevel_MASK 0x000000ff 464cd92098Szrj # define SamuBootLevel_SHIFT 0 474cd92098Szrj # define AcpBootLevel(x) ((x) << 8) 484cd92098Szrj # define AcpBootLevel_MASK 0x0000ff00 494cd92098Szrj # define AcpBootLevel_SHIFT 8 504cd92098Szrj # define VceBootLevel(x) ((x) << 16) 514cd92098Szrj # define VceBootLevel_MASK 0x00ff0000 524cd92098Szrj # define VceBootLevel_SHIFT 16 534cd92098Szrj # define UvdBootLevel(x) ((x) << 24) 544cd92098Szrj # define UvdBootLevel_MASK 0xff000000 554cd92098Szrj # define UvdBootLevel_SHIFT 24 564cd92098Szrj 574cd92098Szrj #define FIRMWARE_FLAGS 0x3F800 584cd92098Szrj # define INTERRUPTS_ENABLED (1 << 0) 594cd92098Szrj 604cd92098Szrj #define NB_DPM_CONFIG_1 0x3F9E8 614cd92098Szrj # define Dpm0PgNbPsLo(x) ((x) << 0) 624cd92098Szrj # define Dpm0PgNbPsLo_MASK 0x000000ff 634cd92098Szrj # define Dpm0PgNbPsLo_SHIFT 0 644cd92098Szrj # define Dpm0PgNbPsHi(x) ((x) << 8) 654cd92098Szrj # define Dpm0PgNbPsHi_MASK 0x0000ff00 664cd92098Szrj # define Dpm0PgNbPsHi_SHIFT 8 674cd92098Szrj # define DpmXNbPsLo(x) ((x) << 16) 684cd92098Szrj # define DpmXNbPsLo_MASK 0x00ff0000 694cd92098Szrj # define DpmXNbPsLo_SHIFT 16 704cd92098Szrj # define DpmXNbPsHi(x) ((x) << 24) 714cd92098Szrj # define DpmXNbPsHi_MASK 0xff000000 724cd92098Szrj # define DpmXNbPsHi_SHIFT 24 734cd92098Szrj 744cd92098Szrj #define SMC_SYSCON_RESET_CNTL 0x80000000 754cd92098Szrj # define RST_REG (1 << 0) 764cd92098Szrj #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 774cd92098Szrj # define CK_DISABLE (1 << 0) 784cd92098Szrj # define CKEN (1 << 24) 794cd92098Szrj 804cd92098Szrj #define SMC_SYSCON_MISC_CNTL 0x80000010 814cd92098Szrj 824cd92098Szrj #define SMC_SYSCON_MSG_ARG_0 0x80000068 834cd92098Szrj 844cd92098Szrj #define SMC_PC_C 0x80000370 854cd92098Szrj 864cd92098Szrj #define SMC_SCRATCH9 0x80000424 874cd92098Szrj 884cd92098Szrj #define RCU_UC_EVENTS 0xC0000004 894cd92098Szrj # define BOOT_SEQ_DONE (1 << 7) 904cd92098Szrj 914cd92098Szrj #define GENERAL_PWRMGT 0xC0200000 924cd92098Szrj # define GLOBAL_PWRMGT_EN (1 << 0) 934cd92098Szrj # define STATIC_PM_EN (1 << 1) 944cd92098Szrj # define THERMAL_PROTECTION_DIS (1 << 2) 954cd92098Szrj # define THERMAL_PROTECTION_TYPE (1 << 3) 964cd92098Szrj # define SW_SMIO_INDEX(x) ((x) << 6) 974cd92098Szrj # define SW_SMIO_INDEX_MASK (1 << 6) 984cd92098Szrj # define SW_SMIO_INDEX_SHIFT 6 994cd92098Szrj # define VOLT_PWRMGT_EN (1 << 10) 1004cd92098Szrj # define GPU_COUNTER_CLK (1 << 15) 1014cd92098Szrj # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 1024cd92098Szrj 1034cd92098Szrj #define CNB_PWRMGT_CNTL 0xC0200004 1044cd92098Szrj # define GNB_SLOW_MODE(x) ((x) << 0) 1054cd92098Szrj # define GNB_SLOW_MODE_MASK (3 << 0) 1064cd92098Szrj # define GNB_SLOW_MODE_SHIFT 0 1074cd92098Szrj # define GNB_SLOW (1 << 2) 1084cd92098Szrj # define FORCE_NB_PS1 (1 << 3) 1094cd92098Szrj # define DPM_ENABLED (1 << 4) 1104cd92098Szrj 1114cd92098Szrj #define SCLK_PWRMGT_CNTL 0xC0200008 1124cd92098Szrj # define SCLK_PWRMGT_OFF (1 << 0) 1134cd92098Szrj # define RESET_BUSY_CNT (1 << 4) 1144cd92098Szrj # define RESET_SCLK_CNT (1 << 5) 1154cd92098Szrj # define DYNAMIC_PM_EN (1 << 21) 1164cd92098Szrj 1174cd92098Szrj #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 1184cd92098Szrj # define CURRENT_STATE_MASK (0xf << 4) 1194cd92098Szrj # define CURRENT_STATE_SHIFT 4 1204cd92098Szrj # define CURR_MCLK_INDEX_MASK (0xf << 8) 1214cd92098Szrj # define CURR_MCLK_INDEX_SHIFT 8 1224cd92098Szrj # define CURR_SCLK_INDEX_MASK (0x1f << 16) 1234cd92098Szrj # define CURR_SCLK_INDEX_SHIFT 16 1244cd92098Szrj 1254cd92098Szrj #define CG_SSP 0xC0200044 1264cd92098Szrj # define SST(x) ((x) << 0) 1274cd92098Szrj # define SST_MASK (0xffff << 0) 1284cd92098Szrj # define SSTU(x) ((x) << 16) 1294cd92098Szrj # define SSTU_MASK (0xf << 16) 1304cd92098Szrj 1314cd92098Szrj #define CG_DISPLAY_GAP_CNTL 0xC0200060 1324cd92098Szrj # define DISP_GAP(x) ((x) << 0) 1334cd92098Szrj # define DISP_GAP_MASK (3 << 0) 1344cd92098Szrj # define VBI_TIMER_COUNT(x) ((x) << 4) 1354cd92098Szrj # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 1364cd92098Szrj # define VBI_TIMER_UNIT(x) ((x) << 20) 1374cd92098Szrj # define VBI_TIMER_UNIT_MASK (7 << 20) 1384cd92098Szrj # define DISP_GAP_MCHG(x) ((x) << 24) 1394cd92098Szrj # define DISP_GAP_MCHG_MASK (3 << 24) 1404cd92098Szrj 1414cd92098Szrj #define SMU_VOLTAGE_STATUS 0xC0200094 1424cd92098Szrj # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 1434cd92098Szrj # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 1444cd92098Szrj 1454cd92098Szrj #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 1464cd92098Szrj # define CURR_PCIE_INDEX_MASK (0xf << 24) 1474cd92098Szrj # define CURR_PCIE_INDEX_SHIFT 24 1484cd92098Szrj 1494cd92098Szrj #define CG_ULV_PARAMETER 0xC0200158 1504cd92098Szrj 1514cd92098Szrj #define CG_FTV_0 0xC02001A8 1524cd92098Szrj #define CG_FTV_1 0xC02001AC 1534cd92098Szrj #define CG_FTV_2 0xC02001B0 1544cd92098Szrj #define CG_FTV_3 0xC02001B4 1554cd92098Szrj #define CG_FTV_4 0xC02001B8 1564cd92098Szrj #define CG_FTV_5 0xC02001BC 1574cd92098Szrj #define CG_FTV_6 0xC02001C0 1584cd92098Szrj #define CG_FTV_7 0xC02001C4 1594cd92098Szrj 1604cd92098Szrj #define CG_DISPLAY_GAP_CNTL2 0xC0200230 1614cd92098Szrj 1624cd92098Szrj #define LCAC_SX0_OVR_SEL 0xC0400D04 1634cd92098Szrj #define LCAC_SX0_OVR_VAL 0xC0400D08 1644cd92098Szrj 1654cd92098Szrj #define LCAC_MC0_CNTL 0xC0400D30 1664cd92098Szrj #define LCAC_MC0_OVR_SEL 0xC0400D34 1674cd92098Szrj #define LCAC_MC0_OVR_VAL 0xC0400D38 1684cd92098Szrj #define LCAC_MC1_CNTL 0xC0400D3C 1694cd92098Szrj #define LCAC_MC1_OVR_SEL 0xC0400D40 1704cd92098Szrj #define LCAC_MC1_OVR_VAL 0xC0400D44 1714cd92098Szrj 1724cd92098Szrj #define LCAC_MC2_OVR_SEL 0xC0400D4C 1734cd92098Szrj #define LCAC_MC2_OVR_VAL 0xC0400D50 1744cd92098Szrj 1754cd92098Szrj #define LCAC_MC3_OVR_SEL 0xC0400D58 1764cd92098Szrj #define LCAC_MC3_OVR_VAL 0xC0400D5C 1774cd92098Szrj 1784cd92098Szrj #define LCAC_CPL_CNTL 0xC0400D80 1794cd92098Szrj #define LCAC_CPL_OVR_SEL 0xC0400D84 1804cd92098Szrj #define LCAC_CPL_OVR_VAL 0xC0400D88 1814cd92098Szrj 1824cd92098Szrj /* dGPU */ 1834cd92098Szrj #define CG_THERMAL_CTRL 0xC0300004 1844cd92098Szrj #define DPM_EVENT_SRC(x) ((x) << 0) 1854cd92098Szrj #define DPM_EVENT_SRC_MASK (7 << 0) 1864cd92098Szrj #define DIG_THERM_DPM(x) ((x) << 14) 1874cd92098Szrj #define DIG_THERM_DPM_MASK 0x003FC000 1884cd92098Szrj #define DIG_THERM_DPM_SHIFT 14 189*7dcf36dcSFrançois Tigeot #define CG_THERMAL_STATUS 0xC0300008 190*7dcf36dcSFrançois Tigeot #define FDO_PWM_DUTY(x) ((x) << 9) 191*7dcf36dcSFrançois Tigeot #define FDO_PWM_DUTY_MASK (0xff << 9) 192*7dcf36dcSFrançois Tigeot #define FDO_PWM_DUTY_SHIFT 9 1934cd92098Szrj #define CG_THERMAL_INT 0xC030000C 1944cd92098Szrj #define CI_DIG_THERM_INTH(x) ((x) << 8) 1954cd92098Szrj #define CI_DIG_THERM_INTH_MASK 0x0000FF00 1964cd92098Szrj #define CI_DIG_THERM_INTH_SHIFT 8 1974cd92098Szrj #define CI_DIG_THERM_INTL(x) ((x) << 16) 1984cd92098Szrj #define CI_DIG_THERM_INTL_MASK 0x00FF0000 1994cd92098Szrj #define CI_DIG_THERM_INTL_SHIFT 16 2004cd92098Szrj #define THERM_INT_MASK_HIGH (1 << 24) 2014cd92098Szrj #define THERM_INT_MASK_LOW (1 << 25) 202*7dcf36dcSFrançois Tigeot #define CG_MULT_THERMAL_CTRL 0xC0300010 203*7dcf36dcSFrançois Tigeot #define TEMP_SEL(x) ((x) << 20) 204*7dcf36dcSFrançois Tigeot #define TEMP_SEL_MASK (0xff << 20) 205*7dcf36dcSFrançois Tigeot #define TEMP_SEL_SHIFT 20 2064cd92098Szrj #define CG_MULT_THERMAL_STATUS 0xC0300014 2074cd92098Szrj #define ASIC_MAX_TEMP(x) ((x) << 0) 2084cd92098Szrj #define ASIC_MAX_TEMP_MASK 0x000001ff 2094cd92098Szrj #define ASIC_MAX_TEMP_SHIFT 0 2104cd92098Szrj #define CTF_TEMP(x) ((x) << 9) 2114cd92098Szrj #define CTF_TEMP_MASK 0x0003fe00 2124cd92098Szrj #define CTF_TEMP_SHIFT 9 2134cd92098Szrj 214*7dcf36dcSFrançois Tigeot #define CG_FDO_CTRL0 0xC0300064 215*7dcf36dcSFrançois Tigeot #define FDO_STATIC_DUTY(x) ((x) << 0) 216*7dcf36dcSFrançois Tigeot #define FDO_STATIC_DUTY_MASK 0x000000FF 217*7dcf36dcSFrançois Tigeot #define FDO_STATIC_DUTY_SHIFT 0 218*7dcf36dcSFrançois Tigeot #define CG_FDO_CTRL1 0xC0300068 219*7dcf36dcSFrançois Tigeot #define FMAX_DUTY100(x) ((x) << 0) 220*7dcf36dcSFrançois Tigeot #define FMAX_DUTY100_MASK 0x000000FF 221*7dcf36dcSFrançois Tigeot #define FMAX_DUTY100_SHIFT 0 222*7dcf36dcSFrançois Tigeot #define CG_FDO_CTRL2 0xC030006C 223*7dcf36dcSFrançois Tigeot #define TMIN(x) ((x) << 0) 224*7dcf36dcSFrançois Tigeot #define TMIN_MASK 0x000000FF 225*7dcf36dcSFrançois Tigeot #define TMIN_SHIFT 0 226*7dcf36dcSFrançois Tigeot #define FDO_PWM_MODE(x) ((x) << 11) 227*7dcf36dcSFrançois Tigeot #define FDO_PWM_MODE_MASK (7 << 11) 228*7dcf36dcSFrançois Tigeot #define FDO_PWM_MODE_SHIFT 11 229*7dcf36dcSFrançois Tigeot #define TACH_PWM_RESP_RATE(x) ((x) << 25) 230*7dcf36dcSFrançois Tigeot #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 231*7dcf36dcSFrançois Tigeot #define TACH_PWM_RESP_RATE_SHIFT 25 232*7dcf36dcSFrançois Tigeot #define CG_TACH_CTRL 0xC0300070 233*7dcf36dcSFrançois Tigeot # define EDGE_PER_REV(x) ((x) << 0) 234*7dcf36dcSFrançois Tigeot # define EDGE_PER_REV_MASK (0x7 << 0) 235*7dcf36dcSFrançois Tigeot # define EDGE_PER_REV_SHIFT 0 236*7dcf36dcSFrançois Tigeot # define TARGET_PERIOD(x) ((x) << 3) 237*7dcf36dcSFrançois Tigeot # define TARGET_PERIOD_MASK 0xfffffff8 238*7dcf36dcSFrançois Tigeot # define TARGET_PERIOD_SHIFT 3 239*7dcf36dcSFrançois Tigeot #define CG_TACH_STATUS 0xC0300074 240*7dcf36dcSFrançois Tigeot # define TACH_PERIOD(x) ((x) << 0) 241*7dcf36dcSFrançois Tigeot # define TACH_PERIOD_MASK 0xffffffff 242*7dcf36dcSFrançois Tigeot # define TACH_PERIOD_SHIFT 0 243*7dcf36dcSFrançois Tigeot 244c6f73aabSFrançois Tigeot #define CG_ECLK_CNTL 0xC05000AC 245c6f73aabSFrançois Tigeot # define ECLK_DIVIDER_MASK 0x7f 246c6f73aabSFrançois Tigeot # define ECLK_DIR_CNTL_EN (1 << 8) 247c6f73aabSFrançois Tigeot #define CG_ECLK_STATUS 0xC05000B0 248c6f73aabSFrançois Tigeot # define ECLK_STATUS (1 << 0) 249c6f73aabSFrançois Tigeot 2504cd92098Szrj #define CG_SPLL_FUNC_CNTL 0xC0500140 2514cd92098Szrj #define SPLL_RESET (1 << 0) 2524cd92098Szrj #define SPLL_PWRON (1 << 1) 2534cd92098Szrj #define SPLL_BYPASS_EN (1 << 3) 2544cd92098Szrj #define SPLL_REF_DIV(x) ((x) << 5) 2554cd92098Szrj #define SPLL_REF_DIV_MASK (0x3f << 5) 2564cd92098Szrj #define SPLL_PDIV_A(x) ((x) << 20) 2574cd92098Szrj #define SPLL_PDIV_A_MASK (0x7f << 20) 2584cd92098Szrj #define SPLL_PDIV_A_SHIFT 20 2594cd92098Szrj #define CG_SPLL_FUNC_CNTL_2 0xC0500144 2604cd92098Szrj #define SCLK_MUX_SEL(x) ((x) << 0) 2614cd92098Szrj #define SCLK_MUX_SEL_MASK (0x1ff << 0) 2624cd92098Szrj #define CG_SPLL_FUNC_CNTL_3 0xC0500148 2634cd92098Szrj #define SPLL_FB_DIV(x) ((x) << 0) 2644cd92098Szrj #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 2654cd92098Szrj #define SPLL_FB_DIV_SHIFT 0 2664cd92098Szrj #define SPLL_DITHEN (1 << 28) 2674cd92098Szrj #define CG_SPLL_FUNC_CNTL_4 0xC050014C 2684cd92098Szrj 2694cd92098Szrj #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 2704cd92098Szrj #define SSEN (1 << 0) 2714cd92098Szrj #define CLK_S(x) ((x) << 4) 2724cd92098Szrj #define CLK_S_MASK (0xfff << 4) 2734cd92098Szrj #define CLK_S_SHIFT 4 2744cd92098Szrj #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 2754cd92098Szrj #define CLK_V(x) ((x) << 0) 2764cd92098Szrj #define CLK_V_MASK (0x3ffffff << 0) 2774cd92098Szrj #define CLK_V_SHIFT 0 2784cd92098Szrj 2794cd92098Szrj #define MPLL_BYPASSCLK_SEL 0xC050019C 2804cd92098Szrj # define MPLL_CLKOUT_SEL(x) ((x) << 8) 2814cd92098Szrj # define MPLL_CLKOUT_SEL_MASK 0xFF00 28257e252bfSMichael Neumann #define CG_CLKPIN_CNTL 0xC05001A0 28357e252bfSMichael Neumann # define XTALIN_DIVIDE (1 << 1) 2844cd92098Szrj # define BCLK_AS_XCLK (1 << 2) 2854cd92098Szrj #define CG_CLKPIN_CNTL_2 0xC05001A4 2864cd92098Szrj # define FORCE_BIF_REFCLK_EN (1 << 3) 2874cd92098Szrj # define MUX_TCLK_TO_XCLK (1 << 8) 2884cd92098Szrj #define THM_CLK_CNTL 0xC05001A8 2894cd92098Szrj # define CMON_CLK_SEL(x) ((x) << 0) 2904cd92098Szrj # define CMON_CLK_SEL_MASK 0xFF 2914cd92098Szrj # define TMON_CLK_SEL(x) ((x) << 8) 2924cd92098Szrj # define TMON_CLK_SEL_MASK 0xFF00 2934cd92098Szrj #define MISC_CLK_CTRL 0xC05001AC 2944cd92098Szrj # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 2954cd92098Szrj # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 2964cd92098Szrj # define ZCLK_SEL(x) ((x) << 8) 2974cd92098Szrj # define ZCLK_SEL_MASK 0xFF00 29857e252bfSMichael Neumann 2994cd92098Szrj /* KV/KB */ 3004cd92098Szrj #define CG_THERMAL_INT_CTRL 0xC2100028 3014cd92098Szrj #define DIG_THERM_INTH(x) ((x) << 0) 3024cd92098Szrj #define DIG_THERM_INTH_MASK 0x000000FF 3034cd92098Szrj #define DIG_THERM_INTH_SHIFT 0 3044cd92098Szrj #define DIG_THERM_INTL(x) ((x) << 8) 3054cd92098Szrj #define DIG_THERM_INTL_MASK 0x0000FF00 3064cd92098Szrj #define DIG_THERM_INTL_SHIFT 8 3074cd92098Szrj #define THERM_INTH_MASK (1 << 24) 3084cd92098Szrj #define THERM_INTL_MASK (1 << 25) 3094cd92098Szrj 3104cd92098Szrj /* PCIE registers idx/data 0x38/0x3c */ 3114cd92098Szrj #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 3124cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 3134cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 3144cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 3154cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 3164cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 3174cd92098Szrj # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 3184cd92098Szrj # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 3194cd92098Szrj # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 3204cd92098Szrj # define PLL_RAMP_UP_TIME_0_SHIFT 24 3214cd92098Szrj #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 3224cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 3234cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 3244cd92098Szrj # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 3254cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 3264cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 3274cd92098Szrj # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 3284cd92098Szrj # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 3294cd92098Szrj # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 3304cd92098Szrj # define PLL_RAMP_UP_TIME_1_SHIFT 24 3314cd92098Szrj 3324cd92098Szrj #define PCIE_CNTL2 0x1001001c /* PCIE */ 3334cd92098Szrj # define SLV_MEM_LS_EN (1 << 16) 3344cd92098Szrj # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 3354cd92098Szrj # define MST_MEM_LS_EN (1 << 18) 3364cd92098Szrj # define REPLAY_MEM_LS_EN (1 << 19) 3374cd92098Szrj 3384cd92098Szrj #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 3394cd92098Szrj # define LC_REVERSE_RCVR (1 << 0) 3404cd92098Szrj # define LC_REVERSE_XMIT (1 << 1) 3414cd92098Szrj # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 3424cd92098Szrj # define LC_OPERATING_LINK_WIDTH_SHIFT 2 3434cd92098Szrj # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 3444cd92098Szrj # define LC_DETECTED_LINK_WIDTH_SHIFT 5 3454cd92098Szrj 3464cd92098Szrj #define PCIE_P_CNTL 0x1400040 /* PCIE */ 3474cd92098Szrj # define P_IGNORE_EDB_ERR (1 << 6) 3484cd92098Szrj 3494cd92098Szrj #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 3504cd92098Szrj #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 3514cd92098Szrj 3524cd92098Szrj #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 3534cd92098Szrj # define LC_L0S_INACTIVITY(x) ((x) << 8) 3544cd92098Szrj # define LC_L0S_INACTIVITY_MASK (0xf << 8) 3554cd92098Szrj # define LC_L0S_INACTIVITY_SHIFT 8 3564cd92098Szrj # define LC_L1_INACTIVITY(x) ((x) << 12) 3574cd92098Szrj # define LC_L1_INACTIVITY_MASK (0xf << 12) 3584cd92098Szrj # define LC_L1_INACTIVITY_SHIFT 12 3594cd92098Szrj # define LC_PMI_TO_L1_DIS (1 << 16) 3604cd92098Szrj # define LC_ASPM_TO_L1_DIS (1 << 24) 3614cd92098Szrj 3624cd92098Szrj #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 3634cd92098Szrj # define LC_LINK_WIDTH_SHIFT 0 3644cd92098Szrj # define LC_LINK_WIDTH_MASK 0x7 3654cd92098Szrj # define LC_LINK_WIDTH_X0 0 3664cd92098Szrj # define LC_LINK_WIDTH_X1 1 3674cd92098Szrj # define LC_LINK_WIDTH_X2 2 3684cd92098Szrj # define LC_LINK_WIDTH_X4 3 3694cd92098Szrj # define LC_LINK_WIDTH_X8 4 3704cd92098Szrj # define LC_LINK_WIDTH_X16 6 3714cd92098Szrj # define LC_LINK_WIDTH_RD_SHIFT 4 3724cd92098Szrj # define LC_LINK_WIDTH_RD_MASK 0x70 3734cd92098Szrj # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 3744cd92098Szrj # define LC_RECONFIG_NOW (1 << 8) 3754cd92098Szrj # define LC_RENEGOTIATION_SUPPORT (1 << 9) 3764cd92098Szrj # define LC_RENEGOTIATE_EN (1 << 10) 3774cd92098Szrj # define LC_SHORT_RECONFIG_EN (1 << 11) 3784cd92098Szrj # define LC_UPCONFIGURE_SUPPORT (1 << 12) 3794cd92098Szrj # define LC_UPCONFIGURE_DIS (1 << 13) 3804cd92098Szrj # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 3814cd92098Szrj # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 3824cd92098Szrj # define LC_DYN_LANES_PWR_STATE_SHIFT 21 3834cd92098Szrj #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 3844cd92098Szrj # define LC_XMIT_N_FTS(x) ((x) << 0) 3854cd92098Szrj # define LC_XMIT_N_FTS_MASK (0xff << 0) 3864cd92098Szrj # define LC_XMIT_N_FTS_SHIFT 0 3874cd92098Szrj # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 3884cd92098Szrj # define LC_N_FTS_MASK (0xff << 24) 3894cd92098Szrj #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 3904cd92098Szrj # define LC_GEN2_EN_STRAP (1 << 0) 3914cd92098Szrj # define LC_GEN3_EN_STRAP (1 << 1) 3924cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 3934cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 3944cd92098Szrj # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 3954cd92098Szrj # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 3964cd92098Szrj # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 3974cd92098Szrj # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 3984cd92098Szrj # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 3994cd92098Szrj # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 4004cd92098Szrj # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 4014cd92098Szrj # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 4024cd92098Szrj # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 4034cd92098Szrj # define LC_CURRENT_DATA_RATE_SHIFT 13 4044cd92098Szrj # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 4054cd92098Szrj # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 4064cd92098Szrj # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 4074cd92098Szrj # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 4084cd92098Szrj # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 4094cd92098Szrj 4104cd92098Szrj #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 4114cd92098Szrj # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 4124cd92098Szrj # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 4134cd92098Szrj 4144cd92098Szrj #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 4154cd92098Szrj # define LC_GO_TO_RECOVERY (1 << 30) 4164cd92098Szrj #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 4174cd92098Szrj # define LC_REDO_EQ (1 << 5) 4184cd92098Szrj # define LC_SET_QUIESCE (1 << 13) 4194cd92098Szrj 4204cd92098Szrj /* direct registers */ 42157e252bfSMichael Neumann #define PCIE_INDEX 0x38 42257e252bfSMichael Neumann #define PCIE_DATA 0x3C 42357e252bfSMichael Neumann 4244cd92098Szrj #define SMC_IND_INDEX_0 0x200 4254cd92098Szrj #define SMC_IND_DATA_0 0x204 4264cd92098Szrj 4274cd92098Szrj #define SMC_IND_ACCESS_CNTL 0x240 4284cd92098Szrj #define AUTO_INCREMENT_IND_0 (1 << 0) 4294cd92098Szrj 4304cd92098Szrj #define SMC_MESSAGE_0 0x250 4314cd92098Szrj #define SMC_MSG_MASK 0xffff 4324cd92098Szrj #define SMC_RESP_0 0x254 4334cd92098Szrj #define SMC_RESP_MASK 0xffff 4344cd92098Szrj 4354cd92098Szrj #define SMC_MSG_ARG_0 0x290 4364cd92098Szrj 43757e252bfSMichael Neumann #define VGA_HDP_CONTROL 0x328 43857e252bfSMichael Neumann #define VGA_MEMORY_DISABLE (1 << 4) 43957e252bfSMichael Neumann 44057e252bfSMichael Neumann #define DMIF_ADDR_CALC 0xC00 44157e252bfSMichael Neumann 4424cd92098Szrj #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 4434cd92098Szrj # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 4444cd92098Szrj # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 4454cd92098Szrj 44657e252bfSMichael Neumann #define SRBM_GFX_CNTL 0xE44 44757e252bfSMichael Neumann #define PIPEID(x) ((x) << 0) 44857e252bfSMichael Neumann #define MEID(x) ((x) << 2) 44957e252bfSMichael Neumann #define VMID(x) ((x) << 4) 45057e252bfSMichael Neumann #define QUEUEID(x) ((x) << 8) 45157e252bfSMichael Neumann 45257e252bfSMichael Neumann #define SRBM_STATUS2 0xE4C 45357e252bfSMichael Neumann #define SDMA_BUSY (1 << 5) 45457e252bfSMichael Neumann #define SDMA1_BUSY (1 << 6) 45557e252bfSMichael Neumann #define SRBM_STATUS 0xE50 45657e252bfSMichael Neumann #define UVD_RQ_PENDING (1 << 1) 45757e252bfSMichael Neumann #define GRBM_RQ_PENDING (1 << 5) 45857e252bfSMichael Neumann #define VMC_BUSY (1 << 8) 45957e252bfSMichael Neumann #define MCB_BUSY (1 << 9) 46057e252bfSMichael Neumann #define MCB_NON_DISPLAY_BUSY (1 << 10) 46157e252bfSMichael Neumann #define MCC_BUSY (1 << 11) 46257e252bfSMichael Neumann #define MCD_BUSY (1 << 12) 46357e252bfSMichael Neumann #define SEM_BUSY (1 << 14) 46457e252bfSMichael Neumann #define IH_BUSY (1 << 17) 46557e252bfSMichael Neumann #define UVD_BUSY (1 << 19) 46657e252bfSMichael Neumann 46757e252bfSMichael Neumann #define SRBM_SOFT_RESET 0xE60 46857e252bfSMichael Neumann #define SOFT_RESET_BIF (1 << 1) 46957e252bfSMichael Neumann #define SOFT_RESET_R0PLL (1 << 4) 47057e252bfSMichael Neumann #define SOFT_RESET_DC (1 << 5) 47157e252bfSMichael Neumann #define SOFT_RESET_SDMA1 (1 << 6) 47257e252bfSMichael Neumann #define SOFT_RESET_GRBM (1 << 8) 47357e252bfSMichael Neumann #define SOFT_RESET_HDP (1 << 9) 47457e252bfSMichael Neumann #define SOFT_RESET_IH (1 << 10) 47557e252bfSMichael Neumann #define SOFT_RESET_MC (1 << 11) 47657e252bfSMichael Neumann #define SOFT_RESET_ROM (1 << 14) 47757e252bfSMichael Neumann #define SOFT_RESET_SEM (1 << 15) 47857e252bfSMichael Neumann #define SOFT_RESET_VMC (1 << 17) 47957e252bfSMichael Neumann #define SOFT_RESET_SDMA (1 << 20) 48057e252bfSMichael Neumann #define SOFT_RESET_TST (1 << 21) 48157e252bfSMichael Neumann #define SOFT_RESET_REGBB (1 << 22) 48257e252bfSMichael Neumann #define SOFT_RESET_ORB (1 << 23) 48357e252bfSMichael Neumann #define SOFT_RESET_VCE (1 << 24) 48457e252bfSMichael Neumann 48557e252bfSMichael Neumann #define VM_L2_CNTL 0x1400 48657e252bfSMichael Neumann #define ENABLE_L2_CACHE (1 << 0) 48757e252bfSMichael Neumann #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 48857e252bfSMichael Neumann #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 48957e252bfSMichael Neumann #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 49057e252bfSMichael Neumann #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 49157e252bfSMichael Neumann #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 49257e252bfSMichael Neumann #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 49357e252bfSMichael Neumann #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 49457e252bfSMichael Neumann #define VM_L2_CNTL2 0x1404 49557e252bfSMichael Neumann #define INVALIDATE_ALL_L1_TLBS (1 << 0) 49657e252bfSMichael Neumann #define INVALIDATE_L2_CACHE (1 << 1) 49757e252bfSMichael Neumann #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 49857e252bfSMichael Neumann #define INVALIDATE_PTE_AND_PDE_CACHES 0 49957e252bfSMichael Neumann #define INVALIDATE_ONLY_PTE_CACHES 1 50057e252bfSMichael Neumann #define INVALIDATE_ONLY_PDE_CACHES 2 50157e252bfSMichael Neumann #define VM_L2_CNTL3 0x1408 50257e252bfSMichael Neumann #define BANK_SELECT(x) ((x) << 0) 50357e252bfSMichael Neumann #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 50457e252bfSMichael Neumann #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 50557e252bfSMichael Neumann #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 50657e252bfSMichael Neumann #define VM_L2_STATUS 0x140C 50757e252bfSMichael Neumann #define L2_BUSY (1 << 0) 50857e252bfSMichael Neumann #define VM_CONTEXT0_CNTL 0x1410 50957e252bfSMichael Neumann #define ENABLE_CONTEXT (1 << 0) 51057e252bfSMichael Neumann #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 51157e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 51257e252bfSMichael Neumann #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 51357e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 51457e252bfSMichael Neumann #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 51557e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 51657e252bfSMichael Neumann #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 51757e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 51857e252bfSMichael Neumann #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 51957e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 52057e252bfSMichael Neumann #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 52157e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 52257e252bfSMichael Neumann #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 523c6f73aabSFrançois Tigeot #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 52457e252bfSMichael Neumann #define VM_CONTEXT1_CNTL 0x1414 52557e252bfSMichael Neumann #define VM_CONTEXT0_CNTL2 0x1430 52657e252bfSMichael Neumann #define VM_CONTEXT1_CNTL2 0x1434 52757e252bfSMichael Neumann #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 52857e252bfSMichael Neumann #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 52957e252bfSMichael Neumann #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 53057e252bfSMichael Neumann #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 53157e252bfSMichael Neumann #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 53257e252bfSMichael Neumann #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 53357e252bfSMichael Neumann #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 53457e252bfSMichael Neumann #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 53557e252bfSMichael Neumann 53657e252bfSMichael Neumann #define VM_INVALIDATE_REQUEST 0x1478 53757e252bfSMichael Neumann #define VM_INVALIDATE_RESPONSE 0x147c 53857e252bfSMichael Neumann 53957e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 54057e252bfSMichael Neumann #define PROTECTIONS_MASK (0xf << 0) 54157e252bfSMichael Neumann #define PROTECTIONS_SHIFT 0 54257e252bfSMichael Neumann /* bit 0: range 54357e252bfSMichael Neumann * bit 1: pde0 54457e252bfSMichael Neumann * bit 2: valid 54557e252bfSMichael Neumann * bit 3: read 54657e252bfSMichael Neumann * bit 4: write 54757e252bfSMichael Neumann */ 54857e252bfSMichael Neumann #define MEMORY_CLIENT_ID_MASK (0xff << 12) 549c6f73aabSFrançois Tigeot #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 55057e252bfSMichael Neumann #define MEMORY_CLIENT_ID_SHIFT 12 55157e252bfSMichael Neumann #define MEMORY_CLIENT_RW_MASK (1 << 24) 55257e252bfSMichael Neumann #define MEMORY_CLIENT_RW_SHIFT 24 55357e252bfSMichael Neumann #define FAULT_VMID_MASK (0xf << 25) 55457e252bfSMichael Neumann #define FAULT_VMID_SHIFT 25 55557e252bfSMichael Neumann 55657e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 55757e252bfSMichael Neumann 55857e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 55957e252bfSMichael Neumann 56057e252bfSMichael Neumann #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 56157e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 56257e252bfSMichael Neumann 56357e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 56457e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 56557e252bfSMichael Neumann #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 56657e252bfSMichael Neumann #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 56757e252bfSMichael Neumann #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 56857e252bfSMichael Neumann #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 56957e252bfSMichael Neumann #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 57057e252bfSMichael Neumann #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 57157e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 57257e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 57357e252bfSMichael Neumann 57457e252bfSMichael Neumann #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 57557e252bfSMichael Neumann #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 57657e252bfSMichael Neumann 5774cd92098Szrj #define VM_L2_CG 0x15c0 5784cd92098Szrj #define MC_CG_ENABLE (1 << 18) 5794cd92098Szrj #define MC_LS_ENABLE (1 << 19) 5804cd92098Szrj 58157e252bfSMichael Neumann #define MC_SHARED_CHMAP 0x2004 58257e252bfSMichael Neumann #define NOOFCHAN_SHIFT 12 58357e252bfSMichael Neumann #define NOOFCHAN_MASK 0x0000f000 58457e252bfSMichael Neumann #define MC_SHARED_CHREMAP 0x2008 58557e252bfSMichael Neumann 58657e252bfSMichael Neumann #define CHUB_CONTROL 0x1864 58757e252bfSMichael Neumann #define BYPASS_VM (1 << 0) 58857e252bfSMichael Neumann 58957e252bfSMichael Neumann #define MC_VM_FB_LOCATION 0x2024 59057e252bfSMichael Neumann #define MC_VM_AGP_TOP 0x2028 59157e252bfSMichael Neumann #define MC_VM_AGP_BOT 0x202C 59257e252bfSMichael Neumann #define MC_VM_AGP_BASE 0x2030 59357e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 59457e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 59557e252bfSMichael Neumann #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 59657e252bfSMichael Neumann 59757e252bfSMichael Neumann #define MC_VM_MX_L1_TLB_CNTL 0x2064 59857e252bfSMichael Neumann #define ENABLE_L1_TLB (1 << 0) 59957e252bfSMichael Neumann #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 60057e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 60157e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 60257e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 60357e252bfSMichael Neumann #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 60457e252bfSMichael Neumann #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 60557e252bfSMichael Neumann #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 60657e252bfSMichael Neumann #define MC_VM_FB_OFFSET 0x2068 60757e252bfSMichael Neumann 60857e252bfSMichael Neumann #define MC_SHARED_BLACKOUT_CNTL 0x20ac 60957e252bfSMichael Neumann 6104cd92098Szrj #define MC_HUB_MISC_HUB_CG 0x20b8 6114cd92098Szrj #define MC_HUB_MISC_VM_CG 0x20bc 6124cd92098Szrj 6134cd92098Szrj #define MC_HUB_MISC_SIP_CG 0x20c0 6144cd92098Szrj 6154cd92098Szrj #define MC_XPB_CLK_GAT 0x2478 6164cd92098Szrj 6174cd92098Szrj #define MC_CITF_MISC_RD_CG 0x2648 6184cd92098Szrj #define MC_CITF_MISC_WR_CG 0x264c 6194cd92098Szrj #define MC_CITF_MISC_VM_CG 0x2650 6204cd92098Szrj 62157e252bfSMichael Neumann #define MC_ARB_RAMCFG 0x2760 62257e252bfSMichael Neumann #define NOOFBANK_SHIFT 0 62357e252bfSMichael Neumann #define NOOFBANK_MASK 0x00000003 62457e252bfSMichael Neumann #define NOOFRANK_SHIFT 2 62557e252bfSMichael Neumann #define NOOFRANK_MASK 0x00000004 62657e252bfSMichael Neumann #define NOOFROWS_SHIFT 3 62757e252bfSMichael Neumann #define NOOFROWS_MASK 0x00000038 62857e252bfSMichael Neumann #define NOOFCOLS_SHIFT 6 62957e252bfSMichael Neumann #define NOOFCOLS_MASK 0x000000C0 63057e252bfSMichael Neumann #define CHANSIZE_SHIFT 8 63157e252bfSMichael Neumann #define CHANSIZE_MASK 0x00000100 63257e252bfSMichael Neumann #define NOOFGROUPS_SHIFT 12 63357e252bfSMichael Neumann #define NOOFGROUPS_MASK 0x00001000 63457e252bfSMichael Neumann 6354cd92098Szrj #define MC_ARB_DRAM_TIMING 0x2774 6364cd92098Szrj #define MC_ARB_DRAM_TIMING2 0x2778 6374cd92098Szrj 6384cd92098Szrj #define MC_ARB_BURST_TIME 0x2808 6394cd92098Szrj #define STATE0(x) ((x) << 0) 6404cd92098Szrj #define STATE0_MASK (0x1f << 0) 6414cd92098Szrj #define STATE0_SHIFT 0 6424cd92098Szrj #define STATE1(x) ((x) << 5) 6434cd92098Szrj #define STATE1_MASK (0x1f << 5) 6444cd92098Szrj #define STATE1_SHIFT 5 6454cd92098Szrj #define STATE2(x) ((x) << 10) 6464cd92098Szrj #define STATE2_MASK (0x1f << 10) 6474cd92098Szrj #define STATE2_SHIFT 10 6484cd92098Szrj #define STATE3(x) ((x) << 15) 6494cd92098Szrj #define STATE3_MASK (0x1f << 15) 6504cd92098Szrj #define STATE3_SHIFT 15 6514cd92098Szrj 6524cd92098Szrj #define MC_SEQ_RAS_TIMING 0x28a0 6534cd92098Szrj #define MC_SEQ_CAS_TIMING 0x28a4 6544cd92098Szrj #define MC_SEQ_MISC_TIMING 0x28a8 6554cd92098Szrj #define MC_SEQ_MISC_TIMING2 0x28ac 6564cd92098Szrj #define MC_SEQ_PMG_TIMING 0x28b0 6574cd92098Szrj #define MC_SEQ_RD_CTL_D0 0x28b4 6584cd92098Szrj #define MC_SEQ_RD_CTL_D1 0x28b8 6594cd92098Szrj #define MC_SEQ_WR_CTL_D0 0x28bc 6604cd92098Szrj #define MC_SEQ_WR_CTL_D1 0x28c0 6614cd92098Szrj 66257e252bfSMichael Neumann #define MC_SEQ_SUP_CNTL 0x28c8 66357e252bfSMichael Neumann #define RUN_MASK (1 << 0) 66457e252bfSMichael Neumann #define MC_SEQ_SUP_PGM 0x28cc 6654cd92098Szrj #define MC_PMG_AUTO_CMD 0x28d0 66657e252bfSMichael Neumann 66757e252bfSMichael Neumann #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 66857e252bfSMichael Neumann #define TRAIN_DONE_D0 (1 << 30) 66957e252bfSMichael Neumann #define TRAIN_DONE_D1 (1 << 31) 67057e252bfSMichael Neumann 67157e252bfSMichael Neumann #define MC_IO_PAD_CNTL_D0 0x29d0 67257e252bfSMichael Neumann #define MEM_FALL_OUT_CMD (1 << 8) 67357e252bfSMichael Neumann 6744cd92098Szrj #define MC_SEQ_MISC0 0x2a00 6754cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 6764cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 6774cd92098Szrj #define MC_SEQ_MISC0_VEN_ID_VALUE 3 6784cd92098Szrj #define MC_SEQ_MISC0_REV_ID_SHIFT 12 6794cd92098Szrj #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 6804cd92098Szrj #define MC_SEQ_MISC0_REV_ID_VALUE 1 6814cd92098Szrj #define MC_SEQ_MISC0_GDDR5_SHIFT 28 6824cd92098Szrj #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 6834cd92098Szrj #define MC_SEQ_MISC0_GDDR5_VALUE 5 6844cd92098Szrj #define MC_SEQ_MISC1 0x2a04 6854cd92098Szrj #define MC_SEQ_RESERVE_M 0x2a08 6864cd92098Szrj #define MC_PMG_CMD_EMRS 0x2a0c 6874cd92098Szrj 68857e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 68957e252bfSMichael Neumann #define MC_SEQ_IO_DEBUG_DATA 0x2a48 69057e252bfSMichael Neumann 6914cd92098Szrj #define MC_SEQ_MISC5 0x2a54 6924cd92098Szrj #define MC_SEQ_MISC6 0x2a58 6934cd92098Szrj 6944cd92098Szrj #define MC_SEQ_MISC7 0x2a64 6954cd92098Szrj 6964cd92098Szrj #define MC_SEQ_RAS_TIMING_LP 0x2a6c 6974cd92098Szrj #define MC_SEQ_CAS_TIMING_LP 0x2a70 6984cd92098Szrj #define MC_SEQ_MISC_TIMING_LP 0x2a74 6994cd92098Szrj #define MC_SEQ_MISC_TIMING2_LP 0x2a78 7004cd92098Szrj #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 7014cd92098Szrj #define MC_SEQ_WR_CTL_D1_LP 0x2a80 7024cd92098Szrj #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 7034cd92098Szrj #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 7044cd92098Szrj 7054cd92098Szrj #define MC_PMG_CMD_MRS 0x2aac 7064cd92098Szrj 7074cd92098Szrj #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 7084cd92098Szrj #define MC_SEQ_RD_CTL_D1_LP 0x2b20 7094cd92098Szrj 7104cd92098Szrj #define MC_PMG_CMD_MRS1 0x2b44 7114cd92098Szrj #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 7124cd92098Szrj #define MC_SEQ_PMG_TIMING_LP 0x2b4c 7134cd92098Szrj 7144cd92098Szrj #define MC_SEQ_WR_CTL_2 0x2b54 7154cd92098Szrj #define MC_SEQ_WR_CTL_2_LP 0x2b58 7164cd92098Szrj #define MC_PMG_CMD_MRS2 0x2b5c 7174cd92098Szrj #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 7184cd92098Szrj 7194cd92098Szrj #define MCLK_PWRMGT_CNTL 0x2ba0 7204cd92098Szrj # define DLL_SPEED(x) ((x) << 0) 7214cd92098Szrj # define DLL_SPEED_MASK (0x1f << 0) 7224cd92098Szrj # define DLL_READY (1 << 6) 7234cd92098Szrj # define MC_INT_CNTL (1 << 7) 7244cd92098Szrj # define MRDCK0_PDNB (1 << 8) 7254cd92098Szrj # define MRDCK1_PDNB (1 << 9) 7264cd92098Szrj # define MRDCK0_RESET (1 << 16) 7274cd92098Szrj # define MRDCK1_RESET (1 << 17) 7284cd92098Szrj # define DLL_READY_READ (1 << 24) 7294cd92098Szrj #define DLL_CNTL 0x2ba4 7304cd92098Szrj # define MRDCK0_BYPASS (1 << 24) 7314cd92098Szrj # define MRDCK1_BYPASS (1 << 25) 7324cd92098Szrj 7334cd92098Szrj #define MPLL_FUNC_CNTL 0x2bb4 7344cd92098Szrj #define BWCTRL(x) ((x) << 20) 7354cd92098Szrj #define BWCTRL_MASK (0xff << 20) 7364cd92098Szrj #define MPLL_FUNC_CNTL_1 0x2bb8 7374cd92098Szrj #define VCO_MODE(x) ((x) << 0) 7384cd92098Szrj #define VCO_MODE_MASK (3 << 0) 7394cd92098Szrj #define CLKFRAC(x) ((x) << 4) 7404cd92098Szrj #define CLKFRAC_MASK (0xfff << 4) 7414cd92098Szrj #define CLKF(x) ((x) << 16) 7424cd92098Szrj #define CLKF_MASK (0xfff << 16) 7434cd92098Szrj #define MPLL_FUNC_CNTL_2 0x2bbc 7444cd92098Szrj #define MPLL_AD_FUNC_CNTL 0x2bc0 7454cd92098Szrj #define YCLK_POST_DIV(x) ((x) << 0) 7464cd92098Szrj #define YCLK_POST_DIV_MASK (7 << 0) 7474cd92098Szrj #define MPLL_DQ_FUNC_CNTL 0x2bc4 7484cd92098Szrj #define YCLK_SEL(x) ((x) << 4) 7494cd92098Szrj #define YCLK_SEL_MASK (1 << 4) 7504cd92098Szrj 7514cd92098Szrj #define MPLL_SS1 0x2bcc 7524cd92098Szrj #define CLKV(x) ((x) << 0) 7534cd92098Szrj #define CLKV_MASK (0x3ffffff << 0) 7544cd92098Szrj #define MPLL_SS2 0x2bd0 7554cd92098Szrj #define CLKS(x) ((x) << 0) 7564cd92098Szrj #define CLKS_MASK (0xfff << 0) 7574cd92098Szrj 75857e252bfSMichael Neumann #define HDP_HOST_PATH_CNTL 0x2C00 7594cd92098Szrj #define CLOCK_GATING_DIS (1 << 23) 76057e252bfSMichael Neumann #define HDP_NONSURFACE_BASE 0x2C04 76157e252bfSMichael Neumann #define HDP_NONSURFACE_INFO 0x2C08 76257e252bfSMichael Neumann #define HDP_NONSURFACE_SIZE 0x2C0C 76357e252bfSMichael Neumann 76457e252bfSMichael Neumann #define HDP_ADDR_CONFIG 0x2F48 76557e252bfSMichael Neumann #define HDP_MISC_CNTL 0x2F4C 76657e252bfSMichael Neumann #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 7674cd92098Szrj #define HDP_MEM_POWER_LS 0x2F50 7684cd92098Szrj #define HDP_LS_ENABLE (1 << 0) 7694cd92098Szrj 7704cd92098Szrj #define ATC_MISC_CG 0x3350 7714cd92098Szrj 772c6f73aabSFrançois Tigeot #define GMCON_RENG_EXECUTE 0x3508 773c6f73aabSFrançois Tigeot #define RENG_EXECUTE_ON_PWR_UP (1 << 0) 774c6f73aabSFrançois Tigeot #define GMCON_MISC 0x350c 775c6f73aabSFrançois Tigeot #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11) 776c6f73aabSFrançois Tigeot #define STCTRL_STUTTER_EN (1 << 16) 777c6f73aabSFrançois Tigeot 778c6f73aabSFrançois Tigeot #define GMCON_PGFSM_CONFIG 0x3538 779c6f73aabSFrançois Tigeot #define GMCON_PGFSM_WRITE 0x353c 780c6f73aabSFrançois Tigeot #define GMCON_PGFSM_READ 0x3540 781c6f73aabSFrançois Tigeot #define GMCON_MISC3 0x3544 782c6f73aabSFrançois Tigeot 7834cd92098Szrj #define MC_SEQ_CNTL_3 0x3600 7844cd92098Szrj # define CAC_EN (1 << 31) 7854cd92098Szrj #define MC_SEQ_G5PDX_CTRL 0x3604 7864cd92098Szrj #define MC_SEQ_G5PDX_CTRL_LP 0x3608 7874cd92098Szrj #define MC_SEQ_G5PDX_CMD0 0x360c 7884cd92098Szrj #define MC_SEQ_G5PDX_CMD0_LP 0x3610 7894cd92098Szrj #define MC_SEQ_G5PDX_CMD1 0x3614 7904cd92098Szrj #define MC_SEQ_G5PDX_CMD1_LP 0x3618 7914cd92098Szrj 7924cd92098Szrj #define MC_SEQ_PMG_DVS_CTL 0x3628 7934cd92098Szrj #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 7944cd92098Szrj #define MC_SEQ_PMG_DVS_CMD 0x3630 7954cd92098Szrj #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 7964cd92098Szrj #define MC_SEQ_DLL_STBY 0x3638 7974cd92098Szrj #define MC_SEQ_DLL_STBY_LP 0x363c 79857e252bfSMichael Neumann 79957e252bfSMichael Neumann #define IH_RB_CNTL 0x3e00 80057e252bfSMichael Neumann # define IH_RB_ENABLE (1 << 0) 80157e252bfSMichael Neumann # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 80257e252bfSMichael Neumann # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 80357e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 80457e252bfSMichael Neumann # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 80557e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 80657e252bfSMichael Neumann # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 80757e252bfSMichael Neumann #define IH_RB_BASE 0x3e04 80857e252bfSMichael Neumann #define IH_RB_RPTR 0x3e08 80957e252bfSMichael Neumann #define IH_RB_WPTR 0x3e0c 81057e252bfSMichael Neumann # define RB_OVERFLOW (1 << 0) 81157e252bfSMichael Neumann # define WPTR_OFFSET_MASK 0x3fffc 81257e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_HI 0x3e10 81357e252bfSMichael Neumann #define IH_RB_WPTR_ADDR_LO 0x3e14 81457e252bfSMichael Neumann #define IH_CNTL 0x3e18 81557e252bfSMichael Neumann # define ENABLE_INTR (1 << 0) 81657e252bfSMichael Neumann # define IH_MC_SWAP(x) ((x) << 1) 81757e252bfSMichael Neumann # define IH_MC_SWAP_NONE 0 81857e252bfSMichael Neumann # define IH_MC_SWAP_16BIT 1 81957e252bfSMichael Neumann # define IH_MC_SWAP_32BIT 2 82057e252bfSMichael Neumann # define IH_MC_SWAP_64BIT 3 82157e252bfSMichael Neumann # define RPTR_REARM (1 << 4) 82257e252bfSMichael Neumann # define MC_WRREQ_CREDIT(x) ((x) << 15) 82357e252bfSMichael Neumann # define MC_WR_CLEAN_CNT(x) ((x) << 20) 82457e252bfSMichael Neumann # define MC_VMID(x) ((x) << 25) 82557e252bfSMichael Neumann 8264cd92098Szrj #define BIF_LNCNT_RESET 0x5220 8274cd92098Szrj # define RESET_LNCNT_EN (1 << 0) 8284cd92098Szrj 82957e252bfSMichael Neumann #define CONFIG_MEMSIZE 0x5428 83057e252bfSMichael Neumann 83157e252bfSMichael Neumann #define INTERRUPT_CNTL 0x5468 83257e252bfSMichael Neumann # define IH_DUMMY_RD_OVERRIDE (1 << 0) 83357e252bfSMichael Neumann # define IH_DUMMY_RD_EN (1 << 1) 83457e252bfSMichael Neumann # define IH_REQ_NONSNOOP_EN (1 << 3) 83557e252bfSMichael Neumann # define GEN_IH_INT_EN (1 << 8) 83657e252bfSMichael Neumann #define INTERRUPT_CNTL2 0x546c 83757e252bfSMichael Neumann 83857e252bfSMichael Neumann #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 83957e252bfSMichael Neumann 84057e252bfSMichael Neumann #define BIF_FB_EN 0x5490 84157e252bfSMichael Neumann #define FB_READ_EN (1 << 0) 84257e252bfSMichael Neumann #define FB_WRITE_EN (1 << 1) 84357e252bfSMichael Neumann 84457e252bfSMichael Neumann #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 84557e252bfSMichael Neumann 84657e252bfSMichael Neumann #define GPU_HDP_FLUSH_REQ 0x54DC 84757e252bfSMichael Neumann #define GPU_HDP_FLUSH_DONE 0x54E0 84857e252bfSMichael Neumann #define CP0 (1 << 0) 84957e252bfSMichael Neumann #define CP1 (1 << 1) 85057e252bfSMichael Neumann #define CP2 (1 << 2) 85157e252bfSMichael Neumann #define CP3 (1 << 3) 85257e252bfSMichael Neumann #define CP4 (1 << 4) 85357e252bfSMichael Neumann #define CP5 (1 << 5) 85457e252bfSMichael Neumann #define CP6 (1 << 6) 85557e252bfSMichael Neumann #define CP7 (1 << 7) 85657e252bfSMichael Neumann #define CP8 (1 << 8) 85757e252bfSMichael Neumann #define CP9 (1 << 9) 85857e252bfSMichael Neumann #define SDMA0 (1 << 10) 85957e252bfSMichael Neumann #define SDMA1 (1 << 11) 86057e252bfSMichael Neumann 86157e252bfSMichael Neumann /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 86257e252bfSMichael Neumann #define LB_MEMORY_CTRL 0x6b04 86357e252bfSMichael Neumann #define LB_MEMORY_SIZE(x) ((x) << 0) 86457e252bfSMichael Neumann #define LB_MEMORY_CONFIG(x) ((x) << 20) 86557e252bfSMichael Neumann 86657e252bfSMichael Neumann #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 86757e252bfSMichael Neumann # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 86857e252bfSMichael Neumann #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 86957e252bfSMichael Neumann # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 87057e252bfSMichael Neumann # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 87157e252bfSMichael Neumann 87257e252bfSMichael Neumann /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 87357e252bfSMichael Neumann #define LB_VLINE_STATUS 0x6b24 87457e252bfSMichael Neumann # define VLINE_OCCURRED (1 << 0) 87557e252bfSMichael Neumann # define VLINE_ACK (1 << 4) 87657e252bfSMichael Neumann # define VLINE_STAT (1 << 12) 87757e252bfSMichael Neumann # define VLINE_INTERRUPT (1 << 16) 87857e252bfSMichael Neumann # define VLINE_INTERRUPT_TYPE (1 << 17) 87957e252bfSMichael Neumann /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 88057e252bfSMichael Neumann #define LB_VBLANK_STATUS 0x6b2c 88157e252bfSMichael Neumann # define VBLANK_OCCURRED (1 << 0) 88257e252bfSMichael Neumann # define VBLANK_ACK (1 << 4) 88357e252bfSMichael Neumann # define VBLANK_STAT (1 << 12) 88457e252bfSMichael Neumann # define VBLANK_INTERRUPT (1 << 16) 88557e252bfSMichael Neumann # define VBLANK_INTERRUPT_TYPE (1 << 17) 88657e252bfSMichael Neumann 88757e252bfSMichael Neumann /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 88857e252bfSMichael Neumann #define LB_INTERRUPT_MASK 0x6b20 88957e252bfSMichael Neumann # define VBLANK_INTERRUPT_MASK (1 << 0) 89057e252bfSMichael Neumann # define VLINE_INTERRUPT_MASK (1 << 4) 89157e252bfSMichael Neumann # define VLINE2_INTERRUPT_MASK (1 << 8) 89257e252bfSMichael Neumann 89357e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS 0x60f4 89457e252bfSMichael Neumann # define LB_D1_VLINE_INTERRUPT (1 << 2) 89557e252bfSMichael Neumann # define LB_D1_VBLANK_INTERRUPT (1 << 3) 89657e252bfSMichael Neumann # define DC_HPD1_INTERRUPT (1 << 17) 89757e252bfSMichael Neumann # define DC_HPD1_RX_INTERRUPT (1 << 18) 89857e252bfSMichael Neumann # define DACA_AUTODETECT_INTERRUPT (1 << 22) 89957e252bfSMichael Neumann # define DACB_AUTODETECT_INTERRUPT (1 << 23) 90057e252bfSMichael Neumann # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 90157e252bfSMichael Neumann # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 90257e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 90357e252bfSMichael Neumann # define LB_D2_VLINE_INTERRUPT (1 << 2) 90457e252bfSMichael Neumann # define LB_D2_VBLANK_INTERRUPT (1 << 3) 90557e252bfSMichael Neumann # define DC_HPD2_INTERRUPT (1 << 17) 90657e252bfSMichael Neumann # define DC_HPD2_RX_INTERRUPT (1 << 18) 90757e252bfSMichael Neumann # define DISP_TIMER_INTERRUPT (1 << 24) 90857e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 90957e252bfSMichael Neumann # define LB_D3_VLINE_INTERRUPT (1 << 2) 91057e252bfSMichael Neumann # define LB_D3_VBLANK_INTERRUPT (1 << 3) 91157e252bfSMichael Neumann # define DC_HPD3_INTERRUPT (1 << 17) 91257e252bfSMichael Neumann # define DC_HPD3_RX_INTERRUPT (1 << 18) 91357e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 91457e252bfSMichael Neumann # define LB_D4_VLINE_INTERRUPT (1 << 2) 91557e252bfSMichael Neumann # define LB_D4_VBLANK_INTERRUPT (1 << 3) 91657e252bfSMichael Neumann # define DC_HPD4_INTERRUPT (1 << 17) 91757e252bfSMichael Neumann # define DC_HPD4_RX_INTERRUPT (1 << 18) 91857e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 91957e252bfSMichael Neumann # define LB_D5_VLINE_INTERRUPT (1 << 2) 92057e252bfSMichael Neumann # define LB_D5_VBLANK_INTERRUPT (1 << 3) 92157e252bfSMichael Neumann # define DC_HPD5_INTERRUPT (1 << 17) 92257e252bfSMichael Neumann # define DC_HPD5_RX_INTERRUPT (1 << 18) 92357e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 92457e252bfSMichael Neumann # define LB_D6_VLINE_INTERRUPT (1 << 2) 92557e252bfSMichael Neumann # define LB_D6_VBLANK_INTERRUPT (1 << 3) 92657e252bfSMichael Neumann # define DC_HPD6_INTERRUPT (1 << 17) 92757e252bfSMichael Neumann # define DC_HPD6_RX_INTERRUPT (1 << 18) 92857e252bfSMichael Neumann #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 92957e252bfSMichael Neumann 930c6f73aabSFrançois Tigeot /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 931c6f73aabSFrançois Tigeot #define GRPH_INT_STATUS 0x6858 932c6f73aabSFrançois Tigeot # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 933c6f73aabSFrançois Tigeot # define GRPH_PFLIP_INT_CLEAR (1 << 8) 934c6f73aabSFrançois Tigeot /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 935c6f73aabSFrançois Tigeot #define GRPH_INT_CONTROL 0x685c 936c6f73aabSFrançois Tigeot # define GRPH_PFLIP_INT_MASK (1 << 0) 937c6f73aabSFrançois Tigeot # define GRPH_PFLIP_INT_TYPE (1 << 8) 938c6f73aabSFrançois Tigeot 93957e252bfSMichael Neumann #define DAC_AUTODETECT_INT_CONTROL 0x67c8 94057e252bfSMichael Neumann 94157e252bfSMichael Neumann #define DC_HPD1_INT_STATUS 0x601c 94257e252bfSMichael Neumann #define DC_HPD2_INT_STATUS 0x6028 94357e252bfSMichael Neumann #define DC_HPD3_INT_STATUS 0x6034 94457e252bfSMichael Neumann #define DC_HPD4_INT_STATUS 0x6040 94557e252bfSMichael Neumann #define DC_HPD5_INT_STATUS 0x604c 94657e252bfSMichael Neumann #define DC_HPD6_INT_STATUS 0x6058 94757e252bfSMichael Neumann # define DC_HPDx_INT_STATUS (1 << 0) 94857e252bfSMichael Neumann # define DC_HPDx_SENSE (1 << 1) 94957e252bfSMichael Neumann # define DC_HPDx_SENSE_DELAYED (1 << 4) 95057e252bfSMichael Neumann # define DC_HPDx_RX_INT_STATUS (1 << 8) 95157e252bfSMichael Neumann 95257e252bfSMichael Neumann #define DC_HPD1_INT_CONTROL 0x6020 95357e252bfSMichael Neumann #define DC_HPD2_INT_CONTROL 0x602c 95457e252bfSMichael Neumann #define DC_HPD3_INT_CONTROL 0x6038 95557e252bfSMichael Neumann #define DC_HPD4_INT_CONTROL 0x6044 95657e252bfSMichael Neumann #define DC_HPD5_INT_CONTROL 0x6050 95757e252bfSMichael Neumann #define DC_HPD6_INT_CONTROL 0x605c 95857e252bfSMichael Neumann # define DC_HPDx_INT_ACK (1 << 0) 95957e252bfSMichael Neumann # define DC_HPDx_INT_POLARITY (1 << 8) 96057e252bfSMichael Neumann # define DC_HPDx_INT_EN (1 << 16) 96157e252bfSMichael Neumann # define DC_HPDx_RX_INT_ACK (1 << 20) 96257e252bfSMichael Neumann # define DC_HPDx_RX_INT_EN (1 << 24) 96357e252bfSMichael Neumann 96457e252bfSMichael Neumann #define DC_HPD1_CONTROL 0x6024 96557e252bfSMichael Neumann #define DC_HPD2_CONTROL 0x6030 96657e252bfSMichael Neumann #define DC_HPD3_CONTROL 0x603c 96757e252bfSMichael Neumann #define DC_HPD4_CONTROL 0x6048 96857e252bfSMichael Neumann #define DC_HPD5_CONTROL 0x6054 96957e252bfSMichael Neumann #define DC_HPD6_CONTROL 0x6060 97057e252bfSMichael Neumann # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 97157e252bfSMichael Neumann # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 97257e252bfSMichael Neumann # define DC_HPDx_EN (1 << 28) 97357e252bfSMichael Neumann 9744cd92098Szrj #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 9754cd92098Szrj # define STUTTER_ENABLE (1 << 0) 9764cd92098Szrj 977c6f73aabSFrançois Tigeot /* DCE8 FMT blocks */ 978c6f73aabSFrançois Tigeot #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 979c6f73aabSFrançois Tigeot # define FMT_DYNAMIC_EXP_EN (1 << 0) 980c6f73aabSFrançois Tigeot # define FMT_DYNAMIC_EXP_MODE (1 << 4) 981c6f73aabSFrançois Tigeot /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 982c6f73aabSFrançois Tigeot #define FMT_CONTROL 0x6fb8 983c6f73aabSFrançois Tigeot # define FMT_PIXEL_ENCODING (1 << 16) 984c6f73aabSFrançois Tigeot /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 985c6f73aabSFrançois Tigeot #define FMT_BIT_DEPTH_CONTROL 0x6fc8 986c6f73aabSFrançois Tigeot # define FMT_TRUNCATE_EN (1 << 0) 987c6f73aabSFrançois Tigeot # define FMT_TRUNCATE_MODE (1 << 1) 988c6f73aabSFrançois Tigeot # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 989c6f73aabSFrançois Tigeot # define FMT_SPATIAL_DITHER_EN (1 << 8) 990c6f73aabSFrançois Tigeot # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 991c6f73aabSFrançois Tigeot # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 992c6f73aabSFrançois Tigeot # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 993c6f73aabSFrançois Tigeot # define FMT_RGB_RANDOM_ENABLE (1 << 14) 994c6f73aabSFrançois Tigeot # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 995c6f73aabSFrançois Tigeot # define FMT_TEMPORAL_DITHER_EN (1 << 16) 996c6f73aabSFrançois Tigeot # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 997c6f73aabSFrançois Tigeot # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 998c6f73aabSFrançois Tigeot # define FMT_TEMPORAL_LEVEL (1 << 24) 999c6f73aabSFrançois Tigeot # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1000c6f73aabSFrançois Tigeot # define FMT_25FRC_SEL(x) ((x) << 26) 1001c6f73aabSFrançois Tigeot # define FMT_50FRC_SEL(x) ((x) << 28) 1002c6f73aabSFrançois Tigeot # define FMT_75FRC_SEL(x) ((x) << 30) 1003c6f73aabSFrançois Tigeot #define FMT_CLAMP_CONTROL 0x6fe4 1004c6f73aabSFrançois Tigeot # define FMT_CLAMP_DATA_EN (1 << 0) 1005c6f73aabSFrançois Tigeot # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1006c6f73aabSFrançois Tigeot # define FMT_CLAMP_6BPC 0 1007c6f73aabSFrançois Tigeot # define FMT_CLAMP_8BPC 1 1008c6f73aabSFrançois Tigeot # define FMT_CLAMP_10BPC 2 1009c6f73aabSFrançois Tigeot 101057e252bfSMichael Neumann #define GRBM_CNTL 0x8000 101157e252bfSMichael Neumann #define GRBM_READ_TIMEOUT(x) ((x) << 0) 101257e252bfSMichael Neumann 101357e252bfSMichael Neumann #define GRBM_STATUS2 0x8008 101457e252bfSMichael Neumann #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 101557e252bfSMichael Neumann #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 101657e252bfSMichael Neumann #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 101757e252bfSMichael Neumann #define ME1PIPE0_RQ_PENDING (1 << 6) 101857e252bfSMichael Neumann #define ME1PIPE1_RQ_PENDING (1 << 7) 101957e252bfSMichael Neumann #define ME1PIPE2_RQ_PENDING (1 << 8) 102057e252bfSMichael Neumann #define ME1PIPE3_RQ_PENDING (1 << 9) 102157e252bfSMichael Neumann #define ME2PIPE0_RQ_PENDING (1 << 10) 102257e252bfSMichael Neumann #define ME2PIPE1_RQ_PENDING (1 << 11) 102357e252bfSMichael Neumann #define ME2PIPE2_RQ_PENDING (1 << 12) 102457e252bfSMichael Neumann #define ME2PIPE3_RQ_PENDING (1 << 13) 102557e252bfSMichael Neumann #define RLC_RQ_PENDING (1 << 14) 102657e252bfSMichael Neumann #define RLC_BUSY (1 << 24) 102757e252bfSMichael Neumann #define TC_BUSY (1 << 25) 102857e252bfSMichael Neumann #define CPF_BUSY (1 << 28) 102957e252bfSMichael Neumann #define CPC_BUSY (1 << 29) 103057e252bfSMichael Neumann #define CPG_BUSY (1 << 30) 103157e252bfSMichael Neumann 103257e252bfSMichael Neumann #define GRBM_STATUS 0x8010 103357e252bfSMichael Neumann #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 103457e252bfSMichael Neumann #define SRBM_RQ_PENDING (1 << 5) 103557e252bfSMichael Neumann #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 103657e252bfSMichael Neumann #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 103757e252bfSMichael Neumann #define GDS_DMA_RQ_PENDING (1 << 9) 103857e252bfSMichael Neumann #define DB_CLEAN (1 << 12) 103957e252bfSMichael Neumann #define CB_CLEAN (1 << 13) 104057e252bfSMichael Neumann #define TA_BUSY (1 << 14) 104157e252bfSMichael Neumann #define GDS_BUSY (1 << 15) 104257e252bfSMichael Neumann #define WD_BUSY_NO_DMA (1 << 16) 104357e252bfSMichael Neumann #define VGT_BUSY (1 << 17) 104457e252bfSMichael Neumann #define IA_BUSY_NO_DMA (1 << 18) 104557e252bfSMichael Neumann #define IA_BUSY (1 << 19) 104657e252bfSMichael Neumann #define SX_BUSY (1 << 20) 104757e252bfSMichael Neumann #define WD_BUSY (1 << 21) 104857e252bfSMichael Neumann #define SPI_BUSY (1 << 22) 104957e252bfSMichael Neumann #define BCI_BUSY (1 << 23) 105057e252bfSMichael Neumann #define SC_BUSY (1 << 24) 105157e252bfSMichael Neumann #define PA_BUSY (1 << 25) 105257e252bfSMichael Neumann #define DB_BUSY (1 << 26) 105357e252bfSMichael Neumann #define CP_COHERENCY_BUSY (1 << 28) 105457e252bfSMichael Neumann #define CP_BUSY (1 << 29) 105557e252bfSMichael Neumann #define CB_BUSY (1 << 30) 105657e252bfSMichael Neumann #define GUI_ACTIVE (1 << 31) 105757e252bfSMichael Neumann #define GRBM_STATUS_SE0 0x8014 105857e252bfSMichael Neumann #define GRBM_STATUS_SE1 0x8018 105957e252bfSMichael Neumann #define GRBM_STATUS_SE2 0x8038 106057e252bfSMichael Neumann #define GRBM_STATUS_SE3 0x803C 106157e252bfSMichael Neumann #define SE_DB_CLEAN (1 << 1) 106257e252bfSMichael Neumann #define SE_CB_CLEAN (1 << 2) 106357e252bfSMichael Neumann #define SE_BCI_BUSY (1 << 22) 106457e252bfSMichael Neumann #define SE_VGT_BUSY (1 << 23) 106557e252bfSMichael Neumann #define SE_PA_BUSY (1 << 24) 106657e252bfSMichael Neumann #define SE_TA_BUSY (1 << 25) 106757e252bfSMichael Neumann #define SE_SX_BUSY (1 << 26) 106857e252bfSMichael Neumann #define SE_SPI_BUSY (1 << 27) 106957e252bfSMichael Neumann #define SE_SC_BUSY (1 << 29) 107057e252bfSMichael Neumann #define SE_DB_BUSY (1 << 30) 107157e252bfSMichael Neumann #define SE_CB_BUSY (1 << 31) 107257e252bfSMichael Neumann 107357e252bfSMichael Neumann #define GRBM_SOFT_RESET 0x8020 107457e252bfSMichael Neumann #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 107557e252bfSMichael Neumann #define SOFT_RESET_RLC (1 << 2) /* RLC */ 107657e252bfSMichael Neumann #define SOFT_RESET_GFX (1 << 16) /* GFX */ 107757e252bfSMichael Neumann #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 107857e252bfSMichael Neumann #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 107957e252bfSMichael Neumann #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 108057e252bfSMichael Neumann 108157e252bfSMichael Neumann #define GRBM_INT_CNTL 0x8060 108257e252bfSMichael Neumann # define RDERR_INT_ENABLE (1 << 0) 108357e252bfSMichael Neumann # define GUI_IDLE_INT_ENABLE (1 << 19) 108457e252bfSMichael Neumann 108557e252bfSMichael Neumann #define CP_CPC_STATUS 0x8210 108657e252bfSMichael Neumann #define CP_CPC_BUSY_STAT 0x8214 108757e252bfSMichael Neumann #define CP_CPC_STALLED_STAT1 0x8218 108857e252bfSMichael Neumann #define CP_CPF_STATUS 0x821c 108957e252bfSMichael Neumann #define CP_CPF_BUSY_STAT 0x8220 109057e252bfSMichael Neumann #define CP_CPF_STALLED_STAT1 0x8224 109157e252bfSMichael Neumann 109257e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 109357e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 109457e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 109557e252bfSMichael Neumann 109657e252bfSMichael Neumann #define CP_MEC_CNTL 0x8234 109757e252bfSMichael Neumann #define MEC_ME2_HALT (1 << 28) 109857e252bfSMichael Neumann #define MEC_ME1_HALT (1 << 30) 109957e252bfSMichael Neumann 110057e252bfSMichael Neumann #define CP_STALLED_STAT3 0x8670 110157e252bfSMichael Neumann #define CP_STALLED_STAT1 0x8674 110257e252bfSMichael Neumann #define CP_STALLED_STAT2 0x8678 110357e252bfSMichael Neumann 110457e252bfSMichael Neumann #define CP_STAT 0x8680 110557e252bfSMichael Neumann 110657e252bfSMichael Neumann #define CP_ME_CNTL 0x86D8 110757e252bfSMichael Neumann #define CP_CE_HALT (1 << 24) 110857e252bfSMichael Neumann #define CP_PFP_HALT (1 << 26) 110957e252bfSMichael Neumann #define CP_ME_HALT (1 << 28) 111057e252bfSMichael Neumann 111157e252bfSMichael Neumann #define CP_RB0_RPTR 0x8700 111257e252bfSMichael Neumann #define CP_RB_WPTR_DELAY 0x8704 11134cd92098Szrj #define CP_RB_WPTR_POLL_CNTL 0x8708 11144cd92098Szrj #define IDLE_POLL_COUNT(x) ((x) << 16) 11154cd92098Szrj #define IDLE_POLL_COUNT_MASK (0xffff << 16) 111657e252bfSMichael Neumann 111757e252bfSMichael Neumann #define CP_MEQ_THRESHOLDS 0x8764 111857e252bfSMichael Neumann #define MEQ1_START(x) ((x) << 0) 111957e252bfSMichael Neumann #define MEQ2_START(x) ((x) << 8) 112057e252bfSMichael Neumann 112157e252bfSMichael Neumann #define VGT_VTX_VECT_EJECT_REG 0x88B0 112257e252bfSMichael Neumann 112357e252bfSMichael Neumann #define VGT_CACHE_INVALIDATION 0x88C4 112457e252bfSMichael Neumann #define CACHE_INVALIDATION(x) ((x) << 0) 112557e252bfSMichael Neumann #define VC_ONLY 0 112657e252bfSMichael Neumann #define TC_ONLY 1 112757e252bfSMichael Neumann #define VC_AND_TC 2 112857e252bfSMichael Neumann #define AUTO_INVLD_EN(x) ((x) << 6) 112957e252bfSMichael Neumann #define NO_AUTO 0 113057e252bfSMichael Neumann #define ES_AUTO 1 113157e252bfSMichael Neumann #define GS_AUTO 2 113257e252bfSMichael Neumann #define ES_AND_GS_AUTO 3 113357e252bfSMichael Neumann 113457e252bfSMichael Neumann #define VGT_GS_VERTEX_REUSE 0x88D4 113557e252bfSMichael Neumann 113657e252bfSMichael Neumann #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 113757e252bfSMichael Neumann #define INACTIVE_CUS_MASK 0xFFFF0000 113857e252bfSMichael Neumann #define INACTIVE_CUS_SHIFT 16 113957e252bfSMichael Neumann #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 114057e252bfSMichael Neumann 114157e252bfSMichael Neumann #define PA_CL_ENHANCE 0x8A14 114257e252bfSMichael Neumann #define CLIP_VTX_REORDER_ENA (1 << 0) 114357e252bfSMichael Neumann #define NUM_CLIP_SEQ(x) ((x) << 1) 114457e252bfSMichael Neumann 114557e252bfSMichael Neumann #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 114657e252bfSMichael Neumann #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 114757e252bfSMichael Neumann #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 114857e252bfSMichael Neumann 114957e252bfSMichael Neumann #define PA_SC_FIFO_SIZE 0x8BCC 115057e252bfSMichael Neumann #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 115157e252bfSMichael Neumann #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 115257e252bfSMichael Neumann #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 115357e252bfSMichael Neumann #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 115457e252bfSMichael Neumann 115557e252bfSMichael Neumann #define PA_SC_ENHANCE 0x8BF0 115657e252bfSMichael Neumann #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 115757e252bfSMichael Neumann #define DISABLE_PA_SC_GUIDANCE (1 << 13) 115857e252bfSMichael Neumann 115957e252bfSMichael Neumann #define SQ_CONFIG 0x8C00 116057e252bfSMichael Neumann 116157e252bfSMichael Neumann #define SH_MEM_BASES 0x8C28 116257e252bfSMichael Neumann /* if PTR32, these are the bases for scratch and lds */ 116357e252bfSMichael Neumann #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 116457e252bfSMichael Neumann #define SHARED_BASE(x) ((x) << 16) /* LDS */ 116557e252bfSMichael Neumann #define SH_MEM_APE1_BASE 0x8C2C 116657e252bfSMichael Neumann /* if PTR32, this is the base location of GPUVM */ 116757e252bfSMichael Neumann #define SH_MEM_APE1_LIMIT 0x8C30 116857e252bfSMichael Neumann /* if PTR32, this is the upper limit of GPUVM */ 116957e252bfSMichael Neumann #define SH_MEM_CONFIG 0x8C34 117057e252bfSMichael Neumann #define PTR32 (1 << 0) 117157e252bfSMichael Neumann #define ALIGNMENT_MODE(x) ((x) << 2) 117257e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD 0 117357e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 117457e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_STRICT 2 117557e252bfSMichael Neumann #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 117657e252bfSMichael Neumann #define DEFAULT_MTYPE(x) ((x) << 4) 117757e252bfSMichael Neumann #define APE1_MTYPE(x) ((x) << 7) 1178*7dcf36dcSFrançois Tigeot /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 1179*7dcf36dcSFrançois Tigeot #define MTYPE_CACHED 0 1180*7dcf36dcSFrançois Tigeot #define MTYPE_NONCACHED 3 118157e252bfSMichael Neumann 118257e252bfSMichael Neumann #define SX_DEBUG_1 0x9060 118357e252bfSMichael Neumann 118457e252bfSMichael Neumann #define SPI_CONFIG_CNTL 0x9100 118557e252bfSMichael Neumann 118657e252bfSMichael Neumann #define SPI_CONFIG_CNTL_1 0x913C 118757e252bfSMichael Neumann #define VTX_DONE_DELAY(x) ((x) << 0) 118857e252bfSMichael Neumann #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 118957e252bfSMichael Neumann 119057e252bfSMichael Neumann #define TA_CNTL_AUX 0x9508 119157e252bfSMichael Neumann 119257e252bfSMichael Neumann #define DB_DEBUG 0x9830 119357e252bfSMichael Neumann #define DB_DEBUG2 0x9834 119457e252bfSMichael Neumann #define DB_DEBUG3 0x9838 119557e252bfSMichael Neumann 119657e252bfSMichael Neumann #define CC_RB_BACKEND_DISABLE 0x98F4 119757e252bfSMichael Neumann #define BACKEND_DISABLE(x) ((x) << 16) 119857e252bfSMichael Neumann #define GB_ADDR_CONFIG 0x98F8 119957e252bfSMichael Neumann #define NUM_PIPES(x) ((x) << 0) 120057e252bfSMichael Neumann #define NUM_PIPES_MASK 0x00000007 120157e252bfSMichael Neumann #define NUM_PIPES_SHIFT 0 120257e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 120357e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 120457e252bfSMichael Neumann #define PIPE_INTERLEAVE_SIZE_SHIFT 4 120557e252bfSMichael Neumann #define NUM_SHADER_ENGINES(x) ((x) << 12) 120657e252bfSMichael Neumann #define NUM_SHADER_ENGINES_MASK 0x00003000 120757e252bfSMichael Neumann #define NUM_SHADER_ENGINES_SHIFT 12 120857e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 120957e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 121057e252bfSMichael Neumann #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 121157e252bfSMichael Neumann #define ROW_SIZE(x) ((x) << 28) 121257e252bfSMichael Neumann #define ROW_SIZE_MASK 0x30000000 121357e252bfSMichael Neumann #define ROW_SIZE_SHIFT 28 121457e252bfSMichael Neumann 121557e252bfSMichael Neumann #define GB_TILE_MODE0 0x9910 121657e252bfSMichael Neumann # define ARRAY_MODE(x) ((x) << 2) 121757e252bfSMichael Neumann # define ARRAY_LINEAR_GENERAL 0 121857e252bfSMichael Neumann # define ARRAY_LINEAR_ALIGNED 1 121957e252bfSMichael Neumann # define ARRAY_1D_TILED_THIN1 2 122057e252bfSMichael Neumann # define ARRAY_2D_TILED_THIN1 4 122157e252bfSMichael Neumann # define ARRAY_PRT_TILED_THIN1 5 122257e252bfSMichael Neumann # define ARRAY_PRT_2D_TILED_THIN1 6 122357e252bfSMichael Neumann # define PIPE_CONFIG(x) ((x) << 6) 122457e252bfSMichael Neumann # define ADDR_SURF_P2 0 122557e252bfSMichael Neumann # define ADDR_SURF_P4_8x16 4 122657e252bfSMichael Neumann # define ADDR_SURF_P4_16x16 5 122757e252bfSMichael Neumann # define ADDR_SURF_P4_16x32 6 122857e252bfSMichael Neumann # define ADDR_SURF_P4_32x32 7 122957e252bfSMichael Neumann # define ADDR_SURF_P8_16x16_8x16 8 123057e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_8x16 9 123157e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_8x16 10 123257e252bfSMichael Neumann # define ADDR_SURF_P8_16x32_16x16 11 123357e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x16 12 123457e252bfSMichael Neumann # define ADDR_SURF_P8_32x32_16x32 13 123557e252bfSMichael Neumann # define ADDR_SURF_P8_32x64_32x32 14 1236c6f73aabSFrançois Tigeot # define ADDR_SURF_P16_32x32_8x16 16 1237c6f73aabSFrançois Tigeot # define ADDR_SURF_P16_32x32_16x16 17 123857e252bfSMichael Neumann # define TILE_SPLIT(x) ((x) << 11) 123957e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_64B 0 124057e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_128B 1 124157e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_256B 2 124257e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_512B 3 124357e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_1KB 4 124457e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_2KB 5 124557e252bfSMichael Neumann # define ADDR_SURF_TILE_SPLIT_4KB 6 124657e252bfSMichael Neumann # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 124757e252bfSMichael Neumann # define ADDR_SURF_DISPLAY_MICRO_TILING 0 124857e252bfSMichael Neumann # define ADDR_SURF_THIN_MICRO_TILING 1 124957e252bfSMichael Neumann # define ADDR_SURF_DEPTH_MICRO_TILING 2 125057e252bfSMichael Neumann # define ADDR_SURF_ROTATED_MICRO_TILING 3 125157e252bfSMichael Neumann # define SAMPLE_SPLIT(x) ((x) << 25) 125257e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_1 0 125357e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_2 1 125457e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_4 2 125557e252bfSMichael Neumann # define ADDR_SURF_SAMPLE_SPLIT_8 3 125657e252bfSMichael Neumann 125757e252bfSMichael Neumann #define GB_MACROTILE_MODE0 0x9990 125857e252bfSMichael Neumann # define BANK_WIDTH(x) ((x) << 0) 125957e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_1 0 126057e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_2 1 126157e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_4 2 126257e252bfSMichael Neumann # define ADDR_SURF_BANK_WIDTH_8 3 126357e252bfSMichael Neumann # define BANK_HEIGHT(x) ((x) << 2) 126457e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_1 0 126557e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_2 1 126657e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_4 2 126757e252bfSMichael Neumann # define ADDR_SURF_BANK_HEIGHT_8 3 126857e252bfSMichael Neumann # define MACRO_TILE_ASPECT(x) ((x) << 4) 126957e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_1 0 127057e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_2 1 127157e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_4 2 127257e252bfSMichael Neumann # define ADDR_SURF_MACRO_ASPECT_8 3 127357e252bfSMichael Neumann # define NUM_BANKS(x) ((x) << 6) 127457e252bfSMichael Neumann # define ADDR_SURF_2_BANK 0 127557e252bfSMichael Neumann # define ADDR_SURF_4_BANK 1 127657e252bfSMichael Neumann # define ADDR_SURF_8_BANK 2 127757e252bfSMichael Neumann # define ADDR_SURF_16_BANK 3 127857e252bfSMichael Neumann 127957e252bfSMichael Neumann #define CB_HW_CONTROL 0x9A10 128057e252bfSMichael Neumann 128157e252bfSMichael Neumann #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 128257e252bfSMichael Neumann #define BACKEND_DISABLE_MASK 0x00FF0000 128357e252bfSMichael Neumann #define BACKEND_DISABLE_SHIFT 16 128457e252bfSMichael Neumann 128557e252bfSMichael Neumann #define TCP_CHAN_STEER_LO 0xac0c 128657e252bfSMichael Neumann #define TCP_CHAN_STEER_HI 0xac10 128757e252bfSMichael Neumann 128857e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY0 0xAC68 128957e252bfSMichael Neumann #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 129057e252bfSMichael Neumann #define TC_CFG_L1_STORE_POLICY 0xAC70 129157e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY0 0xAC74 129257e252bfSMichael Neumann #define TC_CFG_L2_LOAD_POLICY1 0xAC78 129357e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY0 0xAC7C 129457e252bfSMichael Neumann #define TC_CFG_L2_STORE_POLICY1 0xAC80 129557e252bfSMichael Neumann #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 129657e252bfSMichael Neumann #define TC_CFG_L1_VOLATILE 0xAC88 129757e252bfSMichael Neumann #define TC_CFG_L2_VOLATILE 0xAC8C 129857e252bfSMichael Neumann 129957e252bfSMichael Neumann #define CP_RB0_BASE 0xC100 130057e252bfSMichael Neumann #define CP_RB0_CNTL 0xC104 130157e252bfSMichael Neumann #define RB_BUFSZ(x) ((x) << 0) 130257e252bfSMichael Neumann #define RB_BLKSZ(x) ((x) << 8) 130357e252bfSMichael Neumann #define BUF_SWAP_32BIT (2 << 16) 130457e252bfSMichael Neumann #define RB_NO_UPDATE (1 << 27) 130557e252bfSMichael Neumann #define RB_RPTR_WR_ENA (1 << 31) 130657e252bfSMichael Neumann 130757e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR 0xC10C 130857e252bfSMichael Neumann #define RB_RPTR_SWAP_32BIT (2 << 0) 130957e252bfSMichael Neumann #define CP_RB0_RPTR_ADDR_HI 0xC110 131057e252bfSMichael Neumann #define CP_RB0_WPTR 0xC114 131157e252bfSMichael Neumann 131257e252bfSMichael Neumann #define CP_DEVICE_ID 0xC12C 131357e252bfSMichael Neumann #define CP_ENDIAN_SWAP 0xC140 131457e252bfSMichael Neumann #define CP_RB_VMID 0xC144 131557e252bfSMichael Neumann 131657e252bfSMichael Neumann #define CP_PFP_UCODE_ADDR 0xC150 131757e252bfSMichael Neumann #define CP_PFP_UCODE_DATA 0xC154 131857e252bfSMichael Neumann #define CP_ME_RAM_RADDR 0xC158 131957e252bfSMichael Neumann #define CP_ME_RAM_WADDR 0xC15C 132057e252bfSMichael Neumann #define CP_ME_RAM_DATA 0xC160 132157e252bfSMichael Neumann 132257e252bfSMichael Neumann #define CP_CE_UCODE_ADDR 0xC168 132357e252bfSMichael Neumann #define CP_CE_UCODE_DATA 0xC16C 132457e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_ADDR 0xC170 132557e252bfSMichael Neumann #define CP_MEC_ME1_UCODE_DATA 0xC174 132657e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_ADDR 0xC178 132757e252bfSMichael Neumann #define CP_MEC_ME2_UCODE_DATA 0xC17C 132857e252bfSMichael Neumann 132957e252bfSMichael Neumann #define CP_INT_CNTL_RING0 0xC1A8 133057e252bfSMichael Neumann # define CNTX_BUSY_INT_ENABLE (1 << 19) 133157e252bfSMichael Neumann # define CNTX_EMPTY_INT_ENABLE (1 << 20) 133257e252bfSMichael Neumann # define PRIV_INSTR_INT_ENABLE (1 << 22) 133357e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 133457e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 133557e252bfSMichael Neumann # define CP_RINGID2_INT_ENABLE (1 << 29) 133657e252bfSMichael Neumann # define CP_RINGID1_INT_ENABLE (1 << 30) 133757e252bfSMichael Neumann # define CP_RINGID0_INT_ENABLE (1 << 31) 133857e252bfSMichael Neumann 133957e252bfSMichael Neumann #define CP_INT_STATUS_RING0 0xC1B4 134057e252bfSMichael Neumann # define PRIV_INSTR_INT_STAT (1 << 22) 134157e252bfSMichael Neumann # define PRIV_REG_INT_STAT (1 << 23) 134257e252bfSMichael Neumann # define TIME_STAMP_INT_STAT (1 << 26) 134357e252bfSMichael Neumann # define CP_RINGID2_INT_STAT (1 << 29) 134457e252bfSMichael Neumann # define CP_RINGID1_INT_STAT (1 << 30) 134557e252bfSMichael Neumann # define CP_RINGID0_INT_STAT (1 << 31) 134657e252bfSMichael Neumann 13474cd92098Szrj #define CP_MEM_SLP_CNTL 0xC1E4 13484cd92098Szrj # define CP_MEM_LS_EN (1 << 0) 13494cd92098Szrj 135057e252bfSMichael Neumann #define CP_CPF_DEBUG 0xC200 135157e252bfSMichael Neumann 135257e252bfSMichael Neumann #define CP_PQ_WPTR_POLL_CNTL 0xC20C 135357e252bfSMichael Neumann #define WPTR_POLL_EN (1 << 31) 135457e252bfSMichael Neumann 135557e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_CNTL 0xC214 135657e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_CNTL 0xC218 135757e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_CNTL 0xC21C 135857e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_CNTL 0xC220 135957e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_CNTL 0xC224 136057e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_CNTL 0xC228 136157e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_CNTL 0xC22C 136257e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_CNTL 0xC230 136357e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 136457e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 136557e252bfSMichael Neumann # define PRIV_REG_INT_ENABLE (1 << 23) 136657e252bfSMichael Neumann # define TIME_STAMP_INT_ENABLE (1 << 26) 136757e252bfSMichael Neumann # define GENERIC2_INT_ENABLE (1 << 29) 136857e252bfSMichael Neumann # define GENERIC1_INT_ENABLE (1 << 30) 136957e252bfSMichael Neumann # define GENERIC0_INT_ENABLE (1 << 31) 137057e252bfSMichael Neumann #define CP_ME1_PIPE0_INT_STATUS 0xC214 137157e252bfSMichael Neumann #define CP_ME1_PIPE1_INT_STATUS 0xC218 137257e252bfSMichael Neumann #define CP_ME1_PIPE2_INT_STATUS 0xC21C 137357e252bfSMichael Neumann #define CP_ME1_PIPE3_INT_STATUS 0xC220 137457e252bfSMichael Neumann #define CP_ME2_PIPE0_INT_STATUS 0xC224 137557e252bfSMichael Neumann #define CP_ME2_PIPE1_INT_STATUS 0xC228 137657e252bfSMichael Neumann #define CP_ME2_PIPE2_INT_STATUS 0xC22C 137757e252bfSMichael Neumann #define CP_ME2_PIPE3_INT_STATUS 0xC230 137857e252bfSMichael Neumann # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 137957e252bfSMichael Neumann # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 138057e252bfSMichael Neumann # define PRIV_REG_INT_STATUS (1 << 23) 138157e252bfSMichael Neumann # define TIME_STAMP_INT_STATUS (1 << 26) 138257e252bfSMichael Neumann # define GENERIC2_INT_STATUS (1 << 29) 138357e252bfSMichael Neumann # define GENERIC1_INT_STATUS (1 << 30) 138457e252bfSMichael Neumann # define GENERIC0_INT_STATUS (1 << 31) 138557e252bfSMichael Neumann 138657e252bfSMichael Neumann #define CP_MAX_CONTEXT 0xC2B8 138757e252bfSMichael Neumann 138857e252bfSMichael Neumann #define CP_RB0_BASE_HI 0xC2C4 138957e252bfSMichael Neumann 139057e252bfSMichael Neumann #define RLC_CNTL 0xC300 139157e252bfSMichael Neumann # define RLC_ENABLE (1 << 0) 139257e252bfSMichael Neumann 139357e252bfSMichael Neumann #define RLC_MC_CNTL 0xC30C 139457e252bfSMichael Neumann 13954cd92098Szrj #define RLC_MEM_SLP_CNTL 0xC318 13964cd92098Szrj # define RLC_MEM_LS_EN (1 << 0) 13974cd92098Szrj 139857e252bfSMichael Neumann #define RLC_LB_CNTR_MAX 0xC348 139957e252bfSMichael Neumann 140057e252bfSMichael Neumann #define RLC_LB_CNTL 0xC364 14014cd92098Szrj # define LOAD_BALANCE_ENABLE (1 << 0) 140257e252bfSMichael Neumann 140357e252bfSMichael Neumann #define RLC_LB_CNTR_INIT 0xC36C 140457e252bfSMichael Neumann 140557e252bfSMichael Neumann #define RLC_SAVE_AND_RESTORE_BASE 0xC374 14064cd92098Szrj #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 14074cd92098Szrj #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 14084cd92098Szrj #define RLC_PG_DELAY_2 0xC37C 140957e252bfSMichael Neumann 141057e252bfSMichael Neumann #define RLC_GPM_UCODE_ADDR 0xC388 141157e252bfSMichael Neumann #define RLC_GPM_UCODE_DATA 0xC38C 141257e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 141357e252bfSMichael Neumann #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 141457e252bfSMichael Neumann #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 141557e252bfSMichael Neumann #define RLC_UCODE_CNTL 0xC39C 141657e252bfSMichael Neumann 14174cd92098Szrj #define RLC_GPM_STAT 0xC400 14184cd92098Szrj # define RLC_GPM_BUSY (1 << 0) 14194cd92098Szrj # define GFX_POWER_STATUS (1 << 1) 14204cd92098Szrj # define GFX_CLOCK_STATUS (1 << 2) 14214cd92098Szrj 14224cd92098Szrj #define RLC_PG_CNTL 0xC40C 14234cd92098Szrj # define GFX_PG_ENABLE (1 << 0) 14244cd92098Szrj # define GFX_PG_SRC (1 << 1) 14254cd92098Szrj # define DYN_PER_CU_PG_ENABLE (1 << 2) 14264cd92098Szrj # define STATIC_PER_CU_PG_ENABLE (1 << 3) 14274cd92098Szrj # define DISABLE_GDS_PG (1 << 13) 14284cd92098Szrj # define DISABLE_CP_PG (1 << 15) 14294cd92098Szrj # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 14304cd92098Szrj # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 14314cd92098Szrj 14324cd92098Szrj #define RLC_CGTT_MGCG_OVERRIDE 0xC420 143357e252bfSMichael Neumann #define RLC_CGCG_CGLS_CTRL 0xC424 14344cd92098Szrj # define CGCG_EN (1 << 0) 14354cd92098Szrj # define CGLS_EN (1 << 1) 14364cd92098Szrj 14374cd92098Szrj #define RLC_PG_DELAY 0xC434 143857e252bfSMichael Neumann 143957e252bfSMichael Neumann #define RLC_LB_INIT_CU_MASK 0xC43C 144057e252bfSMichael Neumann 144157e252bfSMichael Neumann #define RLC_LB_PARAMS 0xC444 144257e252bfSMichael Neumann 14434cd92098Szrj #define RLC_PG_AO_CU_MASK 0xC44C 14444cd92098Szrj 14454cd92098Szrj #define RLC_MAX_PG_CU 0xC450 14464cd92098Szrj # define MAX_PU_CU(x) ((x) << 0) 14474cd92098Szrj # define MAX_PU_CU_MASK (0xff << 0) 14484cd92098Szrj #define RLC_AUTO_PG_CTRL 0xC454 14494cd92098Szrj # define AUTO_PG_EN (1 << 0) 14504cd92098Szrj # define GRBM_REG_SGIT(x) ((x) << 3) 14514cd92098Szrj # define GRBM_REG_SGIT_MASK (0xffff << 3) 14524cd92098Szrj 14534cd92098Szrj #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 14544cd92098Szrj #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 14554cd92098Szrj #define RLC_SERDES_WR_CTRL 0xC47C 14564cd92098Szrj #define BPM_ADDR(x) ((x) << 0) 14574cd92098Szrj #define BPM_ADDR_MASK (0xff << 0) 14584cd92098Szrj #define CGLS_ENABLE (1 << 16) 14594cd92098Szrj #define CGCG_OVERRIDE_0 (1 << 20) 14604cd92098Szrj #define MGCG_OVERRIDE_0 (1 << 22) 14614cd92098Szrj #define MGCG_OVERRIDE_1 (1 << 23) 14624cd92098Szrj 146357e252bfSMichael Neumann #define RLC_SERDES_CU_MASTER_BUSY 0xC484 146457e252bfSMichael Neumann #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 146557e252bfSMichael Neumann # define SE_MASTER_BUSY_MASK 0x0000ffff 146657e252bfSMichael Neumann # define GC_MASTER_BUSY (1 << 16) 146757e252bfSMichael Neumann # define TC0_MASTER_BUSY (1 << 17) 146857e252bfSMichael Neumann # define TC1_MASTER_BUSY (1 << 18) 146957e252bfSMichael Neumann 147057e252bfSMichael Neumann #define RLC_GPM_SCRATCH_ADDR 0xC4B0 147157e252bfSMichael Neumann #define RLC_GPM_SCRATCH_DATA 0xC4B4 147257e252bfSMichael Neumann 14734cd92098Szrj #define RLC_GPR_REG2 0xC4E8 14744cd92098Szrj #define REQ 0x00000001 14754cd92098Szrj #define MESSAGE(x) ((x) << 1) 14764cd92098Szrj #define MESSAGE_MASK 0x0000001e 14774cd92098Szrj #define MSG_ENTER_RLC_SAFE_MODE 1 14784cd92098Szrj #define MSG_EXIT_RLC_SAFE_MODE 0 14794cd92098Szrj 148057e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR 0xC904 148157e252bfSMichael Neumann #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 148257e252bfSMichael Neumann #define CP_HPD_EOP_VMID 0xC90C 148357e252bfSMichael Neumann #define CP_HPD_EOP_CONTROL 0xC910 148457e252bfSMichael Neumann #define EOP_SIZE(x) ((x) << 0) 148557e252bfSMichael Neumann #define EOP_SIZE_MASK (0x3f << 0) 148657e252bfSMichael Neumann #define CP_MQD_BASE_ADDR 0xC914 148757e252bfSMichael Neumann #define CP_MQD_BASE_ADDR_HI 0xC918 148857e252bfSMichael Neumann #define CP_HQD_ACTIVE 0xC91C 148957e252bfSMichael Neumann #define CP_HQD_VMID 0xC920 149057e252bfSMichael Neumann 1491*7dcf36dcSFrançois Tigeot #define CP_HQD_PERSISTENT_STATE 0xC924u 1492*7dcf36dcSFrançois Tigeot #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) 1493*7dcf36dcSFrançois Tigeot 1494*7dcf36dcSFrançois Tigeot #define CP_HQD_PIPE_PRIORITY 0xC928u 1495*7dcf36dcSFrançois Tigeot #define CP_HQD_QUEUE_PRIORITY 0xC92Cu 1496*7dcf36dcSFrançois Tigeot #define CP_HQD_QUANTUM 0xC930u 1497*7dcf36dcSFrançois Tigeot #define QUANTUM_EN 1U 1498*7dcf36dcSFrançois Tigeot #define QUANTUM_SCALE_1MS (1U << 4) 1499*7dcf36dcSFrançois Tigeot #define QUANTUM_DURATION(x) ((x) << 8) 1500*7dcf36dcSFrançois Tigeot 150157e252bfSMichael Neumann #define CP_HQD_PQ_BASE 0xC934 150257e252bfSMichael Neumann #define CP_HQD_PQ_BASE_HI 0xC938 150357e252bfSMichael Neumann #define CP_HQD_PQ_RPTR 0xC93C 150457e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 150557e252bfSMichael Neumann #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 150657e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 150757e252bfSMichael Neumann #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 150857e252bfSMichael Neumann #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 150957e252bfSMichael Neumann #define DOORBELL_OFFSET(x) ((x) << 2) 151057e252bfSMichael Neumann #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 151157e252bfSMichael Neumann #define DOORBELL_SOURCE (1 << 28) 151257e252bfSMichael Neumann #define DOORBELL_SCHD_HIT (1 << 29) 151357e252bfSMichael Neumann #define DOORBELL_EN (1 << 30) 151457e252bfSMichael Neumann #define DOORBELL_HIT (1 << 31) 151557e252bfSMichael Neumann #define CP_HQD_PQ_WPTR 0xC954 151657e252bfSMichael Neumann #define CP_HQD_PQ_CONTROL 0xC958 151757e252bfSMichael Neumann #define QUEUE_SIZE(x) ((x) << 0) 151857e252bfSMichael Neumann #define QUEUE_SIZE_MASK (0x3f << 0) 151957e252bfSMichael Neumann #define RPTR_BLOCK_SIZE(x) ((x) << 8) 152057e252bfSMichael Neumann #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 152157e252bfSMichael Neumann #define PQ_VOLATILE (1 << 26) 152257e252bfSMichael Neumann #define NO_UPDATE_RPTR (1 << 27) 152357e252bfSMichael Neumann #define UNORD_DISPATCH (1 << 28) 152457e252bfSMichael Neumann #define ROQ_PQ_IB_FLIP (1 << 29) 152557e252bfSMichael Neumann #define PRIV_STATE (1 << 30) 152657e252bfSMichael Neumann #define KMD_QUEUE (1 << 31) 152757e252bfSMichael Neumann 1528*7dcf36dcSFrançois Tigeot #define CP_HQD_IB_BASE_ADDR 0xC95Cu 1529*7dcf36dcSFrançois Tigeot #define CP_HQD_IB_BASE_ADDR_HI 0xC960u 1530*7dcf36dcSFrançois Tigeot #define CP_HQD_IB_RPTR 0xC964u 1531*7dcf36dcSFrançois Tigeot #define CP_HQD_IB_CONTROL 0xC968u 1532*7dcf36dcSFrançois Tigeot #define IB_ATC_EN (1U << 23) 1533*7dcf36dcSFrançois Tigeot #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) 1534*7dcf36dcSFrançois Tigeot 153557e252bfSMichael Neumann #define CP_HQD_DEQUEUE_REQUEST 0xC974 1536*7dcf36dcSFrançois Tigeot #define DEQUEUE_REQUEST_DRAIN 1 1537*7dcf36dcSFrançois Tigeot #define DEQUEUE_REQUEST_RESET 2 153857e252bfSMichael Neumann 153957e252bfSMichael Neumann #define CP_MQD_CONTROL 0xC99C 154057e252bfSMichael Neumann #define MQD_VMID(x) ((x) << 0) 154157e252bfSMichael Neumann #define MQD_VMID_MASK (0xf << 0) 154257e252bfSMichael Neumann 1543*7dcf36dcSFrançois Tigeot #define CP_HQD_SEMA_CMD 0xC97Cu 1544*7dcf36dcSFrançois Tigeot #define CP_HQD_MSG_TYPE 0xC980u 1545*7dcf36dcSFrançois Tigeot #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u 1546*7dcf36dcSFrançois Tigeot #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u 1547*7dcf36dcSFrançois Tigeot #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu 1548*7dcf36dcSFrançois Tigeot #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u 1549*7dcf36dcSFrançois Tigeot #define CP_HQD_HQ_SCHEDULER0 0xC994u 1550*7dcf36dcSFrançois Tigeot #define CP_HQD_HQ_SCHEDULER1 0xC998u 1551*7dcf36dcSFrançois Tigeot 1552*7dcf36dcSFrançois Tigeot #define SH_STATIC_MEM_CONFIG 0x9604u 1553*7dcf36dcSFrançois Tigeot 15544cd92098Szrj #define DB_RENDER_CONTROL 0x28000 15554cd92098Szrj 155657e252bfSMichael Neumann #define PA_SC_RASTER_CONFIG 0x28350 155757e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_0 0 155857e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_1 1 155957e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_2 2 156057e252bfSMichael Neumann # define RASTER_CONFIG_RB_MAP_3 3 1561c6f73aabSFrançois Tigeot #define PKR_MAP(x) ((x) << 8) 156257e252bfSMichael Neumann 156357e252bfSMichael Neumann #define VGT_EVENT_INITIATOR 0x28a90 156457e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 156557e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 156657e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 156757e252bfSMichael Neumann # define CACHE_FLUSH_TS (4 << 0) 156857e252bfSMichael Neumann # define CACHE_FLUSH (6 << 0) 156957e252bfSMichael Neumann # define CS_PARTIAL_FLUSH (7 << 0) 157057e252bfSMichael Neumann # define VGT_STREAMOUT_RESET (10 << 0) 157157e252bfSMichael Neumann # define END_OF_PIPE_INCR_DE (11 << 0) 157257e252bfSMichael Neumann # define END_OF_PIPE_IB_END (12 << 0) 157357e252bfSMichael Neumann # define RST_PIX_CNT (13 << 0) 157457e252bfSMichael Neumann # define VS_PARTIAL_FLUSH (15 << 0) 157557e252bfSMichael Neumann # define PS_PARTIAL_FLUSH (16 << 0) 157657e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 157757e252bfSMichael Neumann # define ZPASS_DONE (21 << 0) 157857e252bfSMichael Neumann # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 157957e252bfSMichael Neumann # define PERFCOUNTER_START (23 << 0) 158057e252bfSMichael Neumann # define PERFCOUNTER_STOP (24 << 0) 158157e252bfSMichael Neumann # define PIPELINESTAT_START (25 << 0) 158257e252bfSMichael Neumann # define PIPELINESTAT_STOP (26 << 0) 158357e252bfSMichael Neumann # define PERFCOUNTER_SAMPLE (27 << 0) 158457e252bfSMichael Neumann # define SAMPLE_PIPELINESTAT (30 << 0) 158557e252bfSMichael Neumann # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 158657e252bfSMichael Neumann # define SAMPLE_STREAMOUTSTATS (32 << 0) 158757e252bfSMichael Neumann # define RESET_VTX_CNT (33 << 0) 158857e252bfSMichael Neumann # define VGT_FLUSH (36 << 0) 158957e252bfSMichael Neumann # define BOTTOM_OF_PIPE_TS (40 << 0) 159057e252bfSMichael Neumann # define DB_CACHE_FLUSH_AND_INV (42 << 0) 159157e252bfSMichael Neumann # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 159257e252bfSMichael Neumann # define FLUSH_AND_INV_DB_META (44 << 0) 159357e252bfSMichael Neumann # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 159457e252bfSMichael Neumann # define FLUSH_AND_INV_CB_META (46 << 0) 159557e252bfSMichael Neumann # define CS_DONE (47 << 0) 159657e252bfSMichael Neumann # define PS_DONE (48 << 0) 159757e252bfSMichael Neumann # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 159857e252bfSMichael Neumann # define THREAD_TRACE_START (51 << 0) 159957e252bfSMichael Neumann # define THREAD_TRACE_STOP (52 << 0) 160057e252bfSMichael Neumann # define THREAD_TRACE_FLUSH (54 << 0) 160157e252bfSMichael Neumann # define THREAD_TRACE_FINISH (55 << 0) 160257e252bfSMichael Neumann # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 160357e252bfSMichael Neumann # define PIXEL_PIPE_STAT_DUMP (57 << 0) 160457e252bfSMichael Neumann # define PIXEL_PIPE_STAT_RESET (58 << 0) 160557e252bfSMichael Neumann 160657e252bfSMichael Neumann #define SCRATCH_REG0 0x30100 160757e252bfSMichael Neumann #define SCRATCH_REG1 0x30104 160857e252bfSMichael Neumann #define SCRATCH_REG2 0x30108 160957e252bfSMichael Neumann #define SCRATCH_REG3 0x3010C 161057e252bfSMichael Neumann #define SCRATCH_REG4 0x30110 161157e252bfSMichael Neumann #define SCRATCH_REG5 0x30114 161257e252bfSMichael Neumann #define SCRATCH_REG6 0x30118 161357e252bfSMichael Neumann #define SCRATCH_REG7 0x3011C 161457e252bfSMichael Neumann 161557e252bfSMichael Neumann #define SCRATCH_UMSK 0x30140 161657e252bfSMichael Neumann #define SCRATCH_ADDR 0x30144 161757e252bfSMichael Neumann 161857e252bfSMichael Neumann #define CP_SEM_WAIT_TIMER 0x301BC 161957e252bfSMichael Neumann 162057e252bfSMichael Neumann #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 162157e252bfSMichael Neumann 162257e252bfSMichael Neumann #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 162357e252bfSMichael Neumann 162457e252bfSMichael Neumann #define GRBM_GFX_INDEX 0x30800 162557e252bfSMichael Neumann #define INSTANCE_INDEX(x) ((x) << 0) 162657e252bfSMichael Neumann #define SH_INDEX(x) ((x) << 8) 162757e252bfSMichael Neumann #define SE_INDEX(x) ((x) << 16) 162857e252bfSMichael Neumann #define SH_BROADCAST_WRITES (1 << 29) 162957e252bfSMichael Neumann #define INSTANCE_BROADCAST_WRITES (1 << 30) 163057e252bfSMichael Neumann #define SE_BROADCAST_WRITES (1 << 31) 163157e252bfSMichael Neumann 163257e252bfSMichael Neumann #define VGT_ESGS_RING_SIZE 0x30900 163357e252bfSMichael Neumann #define VGT_GSVS_RING_SIZE 0x30904 163457e252bfSMichael Neumann #define VGT_PRIMITIVE_TYPE 0x30908 163557e252bfSMichael Neumann #define VGT_INDEX_TYPE 0x3090C 163657e252bfSMichael Neumann 163757e252bfSMichael Neumann #define VGT_NUM_INDICES 0x30930 163857e252bfSMichael Neumann #define VGT_NUM_INSTANCES 0x30934 163957e252bfSMichael Neumann #define VGT_TF_RING_SIZE 0x30938 164057e252bfSMichael Neumann #define VGT_HS_OFFCHIP_PARAM 0x3093C 164157e252bfSMichael Neumann #define VGT_TF_MEMORY_BASE 0x30940 164257e252bfSMichael Neumann 164357e252bfSMichael Neumann #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 164457e252bfSMichael Neumann #define PA_SC_LINE_STIPPLE_STATE 0x30a04 164557e252bfSMichael Neumann 164657e252bfSMichael Neumann #define SQC_CACHES 0x30d20 164757e252bfSMichael Neumann 164857e252bfSMichael Neumann #define CP_PERFMON_CNTL 0x36020 164957e252bfSMichael Neumann 16504cd92098Szrj #define CGTS_SM_CTRL_REG 0x3c000 16514cd92098Szrj #define SM_MODE(x) ((x) << 17) 16524cd92098Szrj #define SM_MODE_MASK (0x7 << 17) 16534cd92098Szrj #define SM_MODE_ENABLE (1 << 20) 16544cd92098Szrj #define CGTS_OVERRIDE (1 << 21) 16554cd92098Szrj #define CGTS_LS_OVERRIDE (1 << 22) 16564cd92098Szrj #define ON_MONITOR_ADD_EN (1 << 23) 16574cd92098Szrj #define ON_MONITOR_ADD(x) ((x) << 24) 16584cd92098Szrj #define ON_MONITOR_ADD_MASK (0xff << 24) 16594cd92098Szrj 166057e252bfSMichael Neumann #define CGTS_TCC_DISABLE 0x3c00c 166157e252bfSMichael Neumann #define CGTS_USER_TCC_DISABLE 0x3c010 166257e252bfSMichael Neumann #define TCC_DISABLE_MASK 0xFFFF0000 166357e252bfSMichael Neumann #define TCC_DISABLE_SHIFT 16 166457e252bfSMichael Neumann 166557e252bfSMichael Neumann #define CB_CGTT_SCLK_CTRL 0x3c2a0 166657e252bfSMichael Neumann 166757e252bfSMichael Neumann /* 166857e252bfSMichael Neumann * PM4 166957e252bfSMichael Neumann */ 167057e252bfSMichael Neumann #define PACKET_TYPE0 0 167157e252bfSMichael Neumann #define PACKET_TYPE1 1 167257e252bfSMichael Neumann #define PACKET_TYPE2 2 167357e252bfSMichael Neumann #define PACKET_TYPE3 3 167457e252bfSMichael Neumann 167557e252bfSMichael Neumann #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 167657e252bfSMichael Neumann #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 167757e252bfSMichael Neumann #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 167857e252bfSMichael Neumann #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 167957e252bfSMichael Neumann #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 168057e252bfSMichael Neumann (((reg) >> 2) & 0xFFFF) | \ 168157e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 168257e252bfSMichael Neumann #define CP_PACKET2 0x80000000 168357e252bfSMichael Neumann #define PACKET2_PAD_SHIFT 0 168457e252bfSMichael Neumann #define PACKET2_PAD_MASK (0x3fffffff << 0) 168557e252bfSMichael Neumann 168657e252bfSMichael Neumann #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 168757e252bfSMichael Neumann 168857e252bfSMichael Neumann #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 168957e252bfSMichael Neumann (((op) & 0xFF) << 8) | \ 169057e252bfSMichael Neumann ((n) & 0x3FFF) << 16) 169157e252bfSMichael Neumann 169257e252bfSMichael Neumann #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 169357e252bfSMichael Neumann 169457e252bfSMichael Neumann /* Packet 3 types */ 169557e252bfSMichael Neumann #define PACKET3_NOP 0x10 169657e252bfSMichael Neumann #define PACKET3_SET_BASE 0x11 169757e252bfSMichael Neumann #define PACKET3_BASE_INDEX(x) ((x) << 0) 169857e252bfSMichael Neumann #define CE_PARTITION_BASE 3 169957e252bfSMichael Neumann #define PACKET3_CLEAR_STATE 0x12 170057e252bfSMichael Neumann #define PACKET3_INDEX_BUFFER_SIZE 0x13 170157e252bfSMichael Neumann #define PACKET3_DISPATCH_DIRECT 0x15 170257e252bfSMichael Neumann #define PACKET3_DISPATCH_INDIRECT 0x16 170357e252bfSMichael Neumann #define PACKET3_ATOMIC_GDS 0x1D 170457e252bfSMichael Neumann #define PACKET3_ATOMIC_MEM 0x1E 170557e252bfSMichael Neumann #define PACKET3_OCCLUSION_QUERY 0x1F 170657e252bfSMichael Neumann #define PACKET3_SET_PREDICATION 0x20 170757e252bfSMichael Neumann #define PACKET3_REG_RMW 0x21 170857e252bfSMichael Neumann #define PACKET3_COND_EXEC 0x22 170957e252bfSMichael Neumann #define PACKET3_PRED_EXEC 0x23 171057e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT 0x24 171157e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT 0x25 171257e252bfSMichael Neumann #define PACKET3_INDEX_BASE 0x26 171357e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_2 0x27 171457e252bfSMichael Neumann #define PACKET3_CONTEXT_CONTROL 0x28 171557e252bfSMichael Neumann #define PACKET3_INDEX_TYPE 0x2A 171657e252bfSMichael Neumann #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 171757e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_AUTO 0x2D 171857e252bfSMichael Neumann #define PACKET3_NUM_INSTANCES 0x2F 171957e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 172057e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER_CONST 0x33 172157e252bfSMichael Neumann #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 172257e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 172357e252bfSMichael Neumann #define PACKET3_DRAW_PREAMBLE 0x36 172457e252bfSMichael Neumann #define PACKET3_WRITE_DATA 0x37 172557e252bfSMichael Neumann #define WRITE_DATA_DST_SEL(x) ((x) << 8) 172657e252bfSMichael Neumann /* 0 - register 172757e252bfSMichael Neumann * 1 - memory (sync - via GRBM) 172857e252bfSMichael Neumann * 2 - gl2 172957e252bfSMichael Neumann * 3 - gds 173057e252bfSMichael Neumann * 4 - reserved 173157e252bfSMichael Neumann * 5 - memory (async - direct) 173257e252bfSMichael Neumann */ 173357e252bfSMichael Neumann #define WR_ONE_ADDR (1 << 16) 173457e252bfSMichael Neumann #define WR_CONFIRM (1 << 20) 173557e252bfSMichael Neumann #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 173657e252bfSMichael Neumann /* 0 - LRU 173757e252bfSMichael Neumann * 1 - Stream 173857e252bfSMichael Neumann */ 173957e252bfSMichael Neumann #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 174057e252bfSMichael Neumann /* 0 - me 174157e252bfSMichael Neumann * 1 - pfp 174257e252bfSMichael Neumann * 2 - ce 174357e252bfSMichael Neumann */ 174457e252bfSMichael Neumann #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 174557e252bfSMichael Neumann #define PACKET3_MEM_SEMAPHORE 0x39 174657e252bfSMichael Neumann # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 174757e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 174857e252bfSMichael Neumann # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 174957e252bfSMichael Neumann # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 175057e252bfSMichael Neumann # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 175157e252bfSMichael Neumann #define PACKET3_COPY_DW 0x3B 175257e252bfSMichael Neumann #define PACKET3_WAIT_REG_MEM 0x3C 175357e252bfSMichael Neumann #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 175457e252bfSMichael Neumann /* 0 - always 175557e252bfSMichael Neumann * 1 - < 175657e252bfSMichael Neumann * 2 - <= 175757e252bfSMichael Neumann * 3 - == 175857e252bfSMichael Neumann * 4 - != 175957e252bfSMichael Neumann * 5 - >= 176057e252bfSMichael Neumann * 6 - > 176157e252bfSMichael Neumann */ 176257e252bfSMichael Neumann #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 176357e252bfSMichael Neumann /* 0 - reg 176457e252bfSMichael Neumann * 1 - mem 176557e252bfSMichael Neumann */ 176657e252bfSMichael Neumann #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 176757e252bfSMichael Neumann /* 0 - wait_reg_mem 176857e252bfSMichael Neumann * 1 - wr_wait_wr_reg 176957e252bfSMichael Neumann */ 177057e252bfSMichael Neumann #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 177157e252bfSMichael Neumann /* 0 - me 177257e252bfSMichael Neumann * 1 - pfp 177357e252bfSMichael Neumann */ 177457e252bfSMichael Neumann #define PACKET3_INDIRECT_BUFFER 0x3F 177557e252bfSMichael Neumann #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 177657e252bfSMichael Neumann #define INDIRECT_BUFFER_VALID (1 << 23) 177757e252bfSMichael Neumann #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 177857e252bfSMichael Neumann /* 0 - LRU 177957e252bfSMichael Neumann * 1 - Stream 178057e252bfSMichael Neumann * 2 - Bypass 178157e252bfSMichael Neumann */ 178257e252bfSMichael Neumann #define PACKET3_COPY_DATA 0x40 178357e252bfSMichael Neumann #define PACKET3_PFP_SYNC_ME 0x42 178457e252bfSMichael Neumann #define PACKET3_SURFACE_SYNC 0x43 178557e252bfSMichael Neumann # define PACKET3_DEST_BASE_0_ENA (1 << 0) 178657e252bfSMichael Neumann # define PACKET3_DEST_BASE_1_ENA (1 << 1) 178757e252bfSMichael Neumann # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 178857e252bfSMichael Neumann # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 178957e252bfSMichael Neumann # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 179057e252bfSMichael Neumann # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 179157e252bfSMichael Neumann # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 179257e252bfSMichael Neumann # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 179357e252bfSMichael Neumann # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 179457e252bfSMichael Neumann # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 179557e252bfSMichael Neumann # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 179657e252bfSMichael Neumann # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 179757e252bfSMichael Neumann # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 179857e252bfSMichael Neumann # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 179957e252bfSMichael Neumann # define PACKET3_DEST_BASE_2_ENA (1 << 19) 180057e252bfSMichael Neumann # define PACKET3_DEST_BASE_3_ENA (1 << 21) 180157e252bfSMichael Neumann # define PACKET3_TCL1_ACTION_ENA (1 << 22) 180257e252bfSMichael Neumann # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 180357e252bfSMichael Neumann # define PACKET3_CB_ACTION_ENA (1 << 25) 180457e252bfSMichael Neumann # define PACKET3_DB_ACTION_ENA (1 << 26) 180557e252bfSMichael Neumann # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 180657e252bfSMichael Neumann # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 180757e252bfSMichael Neumann # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 180857e252bfSMichael Neumann #define PACKET3_COND_WRITE 0x45 180957e252bfSMichael Neumann #define PACKET3_EVENT_WRITE 0x46 181057e252bfSMichael Neumann #define EVENT_TYPE(x) ((x) << 0) 181157e252bfSMichael Neumann #define EVENT_INDEX(x) ((x) << 8) 181257e252bfSMichael Neumann /* 0 - any non-TS event 181357e252bfSMichael Neumann * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 181457e252bfSMichael Neumann * 2 - SAMPLE_PIPELINESTAT 181557e252bfSMichael Neumann * 3 - SAMPLE_STREAMOUTSTAT* 181657e252bfSMichael Neumann * 4 - *S_PARTIAL_FLUSH 181757e252bfSMichael Neumann * 5 - EOP events 181857e252bfSMichael Neumann * 6 - EOS events 181957e252bfSMichael Neumann */ 182057e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOP 0x47 182157e252bfSMichael Neumann #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 182257e252bfSMichael Neumann #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 182357e252bfSMichael Neumann #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 182457e252bfSMichael Neumann #define EOP_TCL1_ACTION_EN (1 << 16) 182557e252bfSMichael Neumann #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1826c6f73aabSFrançois Tigeot #define EOP_TCL2_VOLATILE (1 << 24) 182757e252bfSMichael Neumann #define EOP_CACHE_POLICY(x) ((x) << 25) 182857e252bfSMichael Neumann /* 0 - LRU 182957e252bfSMichael Neumann * 1 - Stream 183057e252bfSMichael Neumann * 2 - Bypass 183157e252bfSMichael Neumann */ 183257e252bfSMichael Neumann #define DATA_SEL(x) ((x) << 29) 183357e252bfSMichael Neumann /* 0 - discard 183457e252bfSMichael Neumann * 1 - send low 32bit data 183557e252bfSMichael Neumann * 2 - send 64bit data 183657e252bfSMichael Neumann * 3 - send 64bit GPU counter value 183757e252bfSMichael Neumann * 4 - send 64bit sys counter value 183857e252bfSMichael Neumann */ 183957e252bfSMichael Neumann #define INT_SEL(x) ((x) << 24) 184057e252bfSMichael Neumann /* 0 - none 184157e252bfSMichael Neumann * 1 - interrupt only (DATA_SEL = 0) 184257e252bfSMichael Neumann * 2 - interrupt when data write is confirmed 184357e252bfSMichael Neumann */ 184457e252bfSMichael Neumann #define DST_SEL(x) ((x) << 16) 184557e252bfSMichael Neumann /* 0 - MC 184657e252bfSMichael Neumann * 1 - TC/L2 184757e252bfSMichael Neumann */ 184857e252bfSMichael Neumann #define PACKET3_EVENT_WRITE_EOS 0x48 184957e252bfSMichael Neumann #define PACKET3_RELEASE_MEM 0x49 185057e252bfSMichael Neumann #define PACKET3_PREAMBLE_CNTL 0x4A 185157e252bfSMichael Neumann # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 185257e252bfSMichael Neumann # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 185357e252bfSMichael Neumann #define PACKET3_DMA_DATA 0x50 1854c6f73aabSFrançois Tigeot /* 1. header 1855c6f73aabSFrançois Tigeot * 2. CONTROL 1856c6f73aabSFrançois Tigeot * 3. SRC_ADDR_LO or DATA [31:0] 1857c6f73aabSFrançois Tigeot * 4. SRC_ADDR_HI [31:0] 1858c6f73aabSFrançois Tigeot * 5. DST_ADDR_LO [31:0] 1859c6f73aabSFrançois Tigeot * 6. DST_ADDR_HI [7:0] 1860c6f73aabSFrançois Tigeot * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 1861c6f73aabSFrançois Tigeot */ 1862c6f73aabSFrançois Tigeot /* CONTROL */ 1863c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 1864c6f73aabSFrançois Tigeot /* 0 - ME 1865c6f73aabSFrançois Tigeot * 1 - PFP 1866c6f73aabSFrançois Tigeot */ 1867c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 1868c6f73aabSFrançois Tigeot /* 0 - LRU 1869c6f73aabSFrançois Tigeot * 1 - Stream 1870c6f73aabSFrançois Tigeot * 2 - Bypass 1871c6f73aabSFrançois Tigeot */ 1872c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 1873c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 1874c6f73aabSFrançois Tigeot /* 0 - DST_ADDR using DAS 1875c6f73aabSFrançois Tigeot * 1 - GDS 1876c6f73aabSFrançois Tigeot * 3 - DST_ADDR using L2 1877c6f73aabSFrançois Tigeot */ 1878c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 1879c6f73aabSFrançois Tigeot /* 0 - LRU 1880c6f73aabSFrançois Tigeot * 1 - Stream 1881c6f73aabSFrançois Tigeot * 2 - Bypass 1882c6f73aabSFrançois Tigeot */ 1883c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 1884c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 1885c6f73aabSFrançois Tigeot /* 0 - SRC_ADDR using SAS 1886c6f73aabSFrançois Tigeot * 1 - GDS 1887c6f73aabSFrançois Tigeot * 2 - DATA 1888c6f73aabSFrançois Tigeot * 3 - SRC_ADDR using L2 1889c6f73aabSFrançois Tigeot */ 1890c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 1891c6f73aabSFrançois Tigeot /* COMMAND */ 1892c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 1893c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 1894c6f73aabSFrançois Tigeot /* 0 - none 1895c6f73aabSFrançois Tigeot * 1 - 8 in 16 1896c6f73aabSFrançois Tigeot * 2 - 8 in 32 1897c6f73aabSFrançois Tigeot * 3 - 8 in 64 1898c6f73aabSFrançois Tigeot */ 1899c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 1900c6f73aabSFrançois Tigeot /* 0 - none 1901c6f73aabSFrançois Tigeot * 1 - 8 in 16 1902c6f73aabSFrançois Tigeot * 2 - 8 in 32 1903c6f73aabSFrançois Tigeot * 3 - 8 in 64 1904c6f73aabSFrançois Tigeot */ 1905c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 1906c6f73aabSFrançois Tigeot /* 0 - memory 1907c6f73aabSFrançois Tigeot * 1 - register 1908c6f73aabSFrançois Tigeot */ 1909c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 1910c6f73aabSFrançois Tigeot /* 0 - memory 1911c6f73aabSFrançois Tigeot * 1 - register 1912c6f73aabSFrançois Tigeot */ 1913c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 1914c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 1915c6f73aabSFrançois Tigeot # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 191657e252bfSMichael Neumann #define PACKET3_AQUIRE_MEM 0x58 191757e252bfSMichael Neumann #define PACKET3_REWIND 0x59 191857e252bfSMichael Neumann #define PACKET3_LOAD_UCONFIG_REG 0x5E 191957e252bfSMichael Neumann #define PACKET3_LOAD_SH_REG 0x5F 192057e252bfSMichael Neumann #define PACKET3_LOAD_CONFIG_REG 0x60 192157e252bfSMichael Neumann #define PACKET3_LOAD_CONTEXT_REG 0x61 192257e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG 0x68 192357e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_START 0x00008000 192457e252bfSMichael Neumann #define PACKET3_SET_CONFIG_REG_END 0x0000b000 192557e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG 0x69 192657e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_START 0x00028000 192757e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_END 0x00029000 192857e252bfSMichael Neumann #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 192957e252bfSMichael Neumann #define PACKET3_SET_SH_REG 0x76 193057e252bfSMichael Neumann #define PACKET3_SET_SH_REG_START 0x0000b000 193157e252bfSMichael Neumann #define PACKET3_SET_SH_REG_END 0x0000c000 193257e252bfSMichael Neumann #define PACKET3_SET_SH_REG_OFFSET 0x77 193357e252bfSMichael Neumann #define PACKET3_SET_QUEUE_REG 0x78 193457e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG 0x79 193557e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_START 0x00030000 193657e252bfSMichael Neumann #define PACKET3_SET_UCONFIG_REG_END 0x00031000 193757e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_WRITE 0x7D 193857e252bfSMichael Neumann #define PACKET3_SCRATCH_RAM_READ 0x7E 193957e252bfSMichael Neumann #define PACKET3_LOAD_CONST_RAM 0x80 194057e252bfSMichael Neumann #define PACKET3_WRITE_CONST_RAM 0x81 194157e252bfSMichael Neumann #define PACKET3_DUMP_CONST_RAM 0x83 194257e252bfSMichael Neumann #define PACKET3_INCREMENT_CE_COUNTER 0x84 194357e252bfSMichael Neumann #define PACKET3_INCREMENT_DE_COUNTER 0x85 194457e252bfSMichael Neumann #define PACKET3_WAIT_ON_CE_COUNTER 0x86 194557e252bfSMichael Neumann #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 194657e252bfSMichael Neumann #define PACKET3_SWITCH_BUFFER 0x8B 194757e252bfSMichael Neumann 194857e252bfSMichael Neumann /* SDMA - first instance at 0xd000, second at 0xd800 */ 194957e252bfSMichael Neumann #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 195057e252bfSMichael Neumann #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 195157e252bfSMichael Neumann 195257e252bfSMichael Neumann #define SDMA0_UCODE_ADDR 0xD000 195357e252bfSMichael Neumann #define SDMA0_UCODE_DATA 0xD004 19544cd92098Szrj #define SDMA0_POWER_CNTL 0xD008 19554cd92098Szrj #define SDMA0_CLK_CTRL 0xD00C 195657e252bfSMichael Neumann 195757e252bfSMichael Neumann #define SDMA0_CNTL 0xD010 195857e252bfSMichael Neumann # define TRAP_ENABLE (1 << 0) 195957e252bfSMichael Neumann # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 196057e252bfSMichael Neumann # define SEM_WAIT_INT_ENABLE (1 << 2) 196157e252bfSMichael Neumann # define DATA_SWAP_ENABLE (1 << 3) 196257e252bfSMichael Neumann # define FENCE_SWAP_ENABLE (1 << 4) 196357e252bfSMichael Neumann # define AUTO_CTXSW_ENABLE (1 << 18) 196457e252bfSMichael Neumann # define CTXEMPTY_INT_ENABLE (1 << 28) 196557e252bfSMichael Neumann 196657e252bfSMichael Neumann #define SDMA0_TILING_CONFIG 0xD018 196757e252bfSMichael Neumann 196857e252bfSMichael Neumann #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 196957e252bfSMichael Neumann #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 197057e252bfSMichael Neumann 197157e252bfSMichael Neumann #define SDMA0_STATUS_REG 0xd034 197257e252bfSMichael Neumann # define SDMA_IDLE (1 << 0) 197357e252bfSMichael Neumann 197457e252bfSMichael Neumann #define SDMA0_ME_CNTL 0xD048 197557e252bfSMichael Neumann # define SDMA_HALT (1 << 0) 197657e252bfSMichael Neumann 197757e252bfSMichael Neumann #define SDMA0_GFX_RB_CNTL 0xD200 197857e252bfSMichael Neumann # define SDMA_RB_ENABLE (1 << 0) 197957e252bfSMichael Neumann # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 198057e252bfSMichael Neumann # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 198157e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 198257e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 198357e252bfSMichael Neumann # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 198457e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE 0xD204 198557e252bfSMichael Neumann #define SDMA0_GFX_RB_BASE_HI 0xD208 198657e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR 0xD20C 198757e252bfSMichael Neumann #define SDMA0_GFX_RB_WPTR 0xD210 198857e252bfSMichael Neumann 198957e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 199057e252bfSMichael Neumann #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 199157e252bfSMichael Neumann #define SDMA0_GFX_IB_CNTL 0xD228 199257e252bfSMichael Neumann # define SDMA_IB_ENABLE (1 << 0) 199357e252bfSMichael Neumann # define SDMA_IB_SWAP_ENABLE (1 << 4) 199457e252bfSMichael Neumann # define SDMA_SWITCH_INSIDE_IB (1 << 8) 199557e252bfSMichael Neumann # define SDMA_CMD_VMID(x) ((x) << 16) 199657e252bfSMichael Neumann 199757e252bfSMichael Neumann #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 199857e252bfSMichael Neumann #define SDMA0_GFX_APE1_CNTL 0xD2A0 199957e252bfSMichael Neumann 200057e252bfSMichael Neumann #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 200157e252bfSMichael Neumann (((sub_op) & 0xFF) << 8) | \ 200257e252bfSMichael Neumann (((op) & 0xFF) << 0)) 200357e252bfSMichael Neumann /* sDMA opcodes */ 200457e252bfSMichael Neumann #define SDMA_OPCODE_NOP 0 200557e252bfSMichael Neumann #define SDMA_OPCODE_COPY 1 200657e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR 0 200757e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED 1 200857e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_SOA 3 200957e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 201057e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 201157e252bfSMichael Neumann # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 201257e252bfSMichael Neumann #define SDMA_OPCODE_WRITE 2 201357e252bfSMichael Neumann # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 201457e252bfSMichael Neumann # define SDMA_WRTIE_SUB_OPCODE_TILED 1 201557e252bfSMichael Neumann #define SDMA_OPCODE_INDIRECT_BUFFER 4 201657e252bfSMichael Neumann #define SDMA_OPCODE_FENCE 5 201757e252bfSMichael Neumann #define SDMA_OPCODE_TRAP 6 201857e252bfSMichael Neumann #define SDMA_OPCODE_SEMAPHORE 7 201957e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 202057e252bfSMichael Neumann /* 0 - increment 202157e252bfSMichael Neumann * 1 - write 1 202257e252bfSMichael Neumann */ 202357e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 202457e252bfSMichael Neumann /* 0 - wait 202557e252bfSMichael Neumann * 1 - signal 202657e252bfSMichael Neumann */ 202757e252bfSMichael Neumann # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 202857e252bfSMichael Neumann /* mailbox */ 202957e252bfSMichael Neumann #define SDMA_OPCODE_POLL_REG_MEM 8 203057e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 203157e252bfSMichael Neumann /* 0 - wait_reg_mem 203257e252bfSMichael Neumann * 1 - wr_wait_wr_reg 203357e252bfSMichael Neumann */ 203457e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 203557e252bfSMichael Neumann /* 0 - always 203657e252bfSMichael Neumann * 1 - < 203757e252bfSMichael Neumann * 2 - <= 203857e252bfSMichael Neumann * 3 - == 203957e252bfSMichael Neumann * 4 - != 204057e252bfSMichael Neumann * 5 - >= 204157e252bfSMichael Neumann * 6 - > 204257e252bfSMichael Neumann */ 204357e252bfSMichael Neumann # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 204457e252bfSMichael Neumann /* 0 = register 204557e252bfSMichael Neumann * 1 = memory 204657e252bfSMichael Neumann */ 204757e252bfSMichael Neumann #define SDMA_OPCODE_COND_EXEC 9 204857e252bfSMichael Neumann #define SDMA_OPCODE_CONSTANT_FILL 11 204957e252bfSMichael Neumann # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 205057e252bfSMichael Neumann /* 0 = byte fill 205157e252bfSMichael Neumann * 2 = DW fill 205257e252bfSMichael Neumann */ 205357e252bfSMichael Neumann #define SDMA_OPCODE_GENERATE_PTE_PDE 12 205457e252bfSMichael Neumann #define SDMA_OPCODE_TIMESTAMP 13 205557e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 205657e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 205757e252bfSMichael Neumann # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 205857e252bfSMichael Neumann #define SDMA_OPCODE_SRBM_WRITE 14 205957e252bfSMichael Neumann # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 206057e252bfSMichael Neumann /* byte mask */ 206157e252bfSMichael Neumann 206257e252bfSMichael Neumann /* UVD */ 206357e252bfSMichael Neumann 206457e252bfSMichael Neumann #define UVD_UDEC_ADDR_CONFIG 0xef4c 206557e252bfSMichael Neumann #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 206657e252bfSMichael Neumann #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 206757e252bfSMichael Neumann 206857e252bfSMichael Neumann #define UVD_LMI_EXT40_ADDR 0xf498 206957e252bfSMichael Neumann #define UVD_LMI_ADDR_EXT 0xf594 207057e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET0 0xf608 207157e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE0 0xf60c 207257e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET1 0xf610 207357e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE1 0xf614 207457e252bfSMichael Neumann #define UVD_VCPU_CACHE_OFFSET2 0xf618 207557e252bfSMichael Neumann #define UVD_VCPU_CACHE_SIZE2 0xf61c 207657e252bfSMichael Neumann 207757e252bfSMichael Neumann #define UVD_RBC_RB_RPTR 0xf690 207857e252bfSMichael Neumann #define UVD_RBC_RB_WPTR 0xf694 207957e252bfSMichael Neumann 20804cd92098Szrj #define UVD_CGC_CTRL 0xF4B0 20814cd92098Szrj # define DCM (1 << 0) 20824cd92098Szrj # define CG_DT(x) ((x) << 2) 20834cd92098Szrj # define CG_DT_MASK (0xf << 2) 20844cd92098Szrj # define CLK_OD(x) ((x) << 6) 20854cd92098Szrj # define CLK_OD_MASK (0x1f << 6) 20864cd92098Szrj 208757e252bfSMichael Neumann /* UVD clocks */ 208857e252bfSMichael Neumann 208957e252bfSMichael Neumann #define CG_DCLK_CNTL 0xC050009C 209057e252bfSMichael Neumann # define DCLK_DIVIDER_MASK 0x7f 209157e252bfSMichael Neumann # define DCLK_DIR_CNTL_EN (1 << 8) 209257e252bfSMichael Neumann #define CG_DCLK_STATUS 0xC05000A0 209357e252bfSMichael Neumann # define DCLK_STATUS (1 << 0) 209457e252bfSMichael Neumann #define CG_VCLK_CNTL 0xC05000A4 209557e252bfSMichael Neumann #define CG_VCLK_STATUS 0xC05000A8 209657e252bfSMichael Neumann 20974cd92098Szrj /* UVD CTX indirect */ 20984cd92098Szrj #define UVD_CGC_MEM_CTRL 0xC0 20994cd92098Szrj 2100c6f73aabSFrançois Tigeot /* VCE */ 2101c6f73aabSFrançois Tigeot 2102c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_OFFSET0 0x20024 2103c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_SIZE0 0x20028 2104c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_OFFSET1 0x2002c 2105c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_SIZE1 0x20030 2106c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_OFFSET2 0x20034 2107c6f73aabSFrançois Tigeot #define VCE_VCPU_CACHE_SIZE2 0x20038 2108c6f73aabSFrançois Tigeot #define VCE_RB_RPTR2 0x20178 2109c6f73aabSFrançois Tigeot #define VCE_RB_WPTR2 0x2017c 2110c6f73aabSFrançois Tigeot #define VCE_RB_RPTR 0x2018c 2111c6f73aabSFrançois Tigeot #define VCE_RB_WPTR 0x20190 2112c6f73aabSFrançois Tigeot #define VCE_CLOCK_GATING_A 0x202f8 2113c6f73aabSFrançois Tigeot # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0) 2114c6f73aabSFrançois Tigeot # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) 2115c6f73aabSFrançois Tigeot # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4) 2116c6f73aabSFrançois Tigeot # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4) 2117c6f73aabSFrançois Tigeot # define CGC_UENC_WAIT_AWAKE (1 << 18) 2118c6f73aabSFrançois Tigeot #define VCE_CLOCK_GATING_B 0x202fc 2119c6f73aabSFrançois Tigeot #define VCE_CGTT_CLK_OVERRIDE 0x207a0 2120c6f73aabSFrançois Tigeot #define VCE_UENC_CLOCK_GATING 0x207bc 2121c6f73aabSFrançois Tigeot # define CLOCK_ON_DELAY_MASK (0xf << 0) 2122c6f73aabSFrançois Tigeot # define CLOCK_ON_DELAY(x) ((x) << 0) 2123c6f73aabSFrançois Tigeot # define CLOCK_OFF_DELAY_MASK (0xff << 4) 2124c6f73aabSFrançois Tigeot # define CLOCK_OFF_DELAY(x) ((x) << 4) 2125c6f73aabSFrançois Tigeot #define VCE_UENC_REG_CLOCK_GATING 0x207c0 2126c6f73aabSFrançois Tigeot #define VCE_SYS_INT_EN 0x21300 2127c6f73aabSFrançois Tigeot # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) 2128c6f73aabSFrançois Tigeot #define VCE_LMI_CTRL2 0x21474 2129c6f73aabSFrançois Tigeot #define VCE_LMI_CTRL 0x21498 2130c6f73aabSFrançois Tigeot #define VCE_LMI_VM_CTRL 0x214a0 2131c6f73aabSFrançois Tigeot #define VCE_LMI_SWAP_CNTL 0x214b4 2132c6f73aabSFrançois Tigeot #define VCE_LMI_SWAP_CNTL1 0x214b8 2133c6f73aabSFrançois Tigeot #define VCE_LMI_CACHE_CTRL 0x214f4 2134c6f73aabSFrançois Tigeot 2135c6f73aabSFrançois Tigeot #define VCE_CMD_NO_OP 0x00000000 2136c6f73aabSFrançois Tigeot #define VCE_CMD_END 0x00000001 2137c6f73aabSFrançois Tigeot #define VCE_CMD_IB 0x00000002 2138c6f73aabSFrançois Tigeot #define VCE_CMD_FENCE 0x00000003 2139c6f73aabSFrançois Tigeot #define VCE_CMD_TRAP 0x00000004 2140c6f73aabSFrançois Tigeot #define VCE_CMD_IB_AUTO 0x00000005 2141c6f73aabSFrançois Tigeot #define VCE_CMD_SEMAPHORE 0x00000006 2142c6f73aabSFrançois Tigeot 2143*7dcf36dcSFrançois Tigeot #define ATC_VMID0_PASID_MAPPING 0x339Cu 2144*7dcf36dcSFrançois Tigeot #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u 2145*7dcf36dcSFrançois Tigeot #define ATC_VMID_PASID_MAPPING_VALID (1U << 31) 2146*7dcf36dcSFrançois Tigeot 2147*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE0_CNTL 0x3310u 2148*7dcf36dcSFrançois Tigeot #define ATS_ACCESS_MODE_NEVER 0 2149*7dcf36dcSFrançois Tigeot #define ATS_ACCESS_MODE_ALWAYS 1 2150*7dcf36dcSFrançois Tigeot 2151*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE0_CNTL2 0x3318u 2152*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u 2153*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u 2154*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE1_CNTL 0x3314u 2155*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE1_CNTL2 0x331Cu 2156*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu 2157*7dcf36dcSFrançois Tigeot #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u 2158*7dcf36dcSFrançois Tigeot 2159*7dcf36dcSFrançois Tigeot #define IH_VMID_0_LUT 0x3D40u 2160*7dcf36dcSFrançois Tigeot 216157e252bfSMichael Neumann #endif 2162