1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef CIK_H 25 #define CIK_H 26 27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 29 30 #define CIK_RB_BITMAP_WIDTH_PER_SH 2 31 #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 32 33 /* DIDT IND registers */ 34 #define DIDT_SQ_CTRL0 0x0 35 # define DIDT_CTRL_EN (1 << 0) 36 #define DIDT_DB_CTRL0 0x20 37 #define DIDT_TD_CTRL0 0x40 38 #define DIDT_TCP_CTRL0 0x60 39 40 /* SMC IND registers */ 41 #define DPM_TABLE_475 0x3F768 42 # define SamuBootLevel(x) ((x) << 0) 43 # define SamuBootLevel_MASK 0x000000ff 44 # define SamuBootLevel_SHIFT 0 45 # define AcpBootLevel(x) ((x) << 8) 46 # define AcpBootLevel_MASK 0x0000ff00 47 # define AcpBootLevel_SHIFT 8 48 # define VceBootLevel(x) ((x) << 16) 49 # define VceBootLevel_MASK 0x00ff0000 50 # define VceBootLevel_SHIFT 16 51 # define UvdBootLevel(x) ((x) << 24) 52 # define UvdBootLevel_MASK 0xff000000 53 # define UvdBootLevel_SHIFT 24 54 55 #define FIRMWARE_FLAGS 0x3F800 56 # define INTERRUPTS_ENABLED (1 << 0) 57 58 #define NB_DPM_CONFIG_1 0x3F9E8 59 # define Dpm0PgNbPsLo(x) ((x) << 0) 60 # define Dpm0PgNbPsLo_MASK 0x000000ff 61 # define Dpm0PgNbPsLo_SHIFT 0 62 # define Dpm0PgNbPsHi(x) ((x) << 8) 63 # define Dpm0PgNbPsHi_MASK 0x0000ff00 64 # define Dpm0PgNbPsHi_SHIFT 8 65 # define DpmXNbPsLo(x) ((x) << 16) 66 # define DpmXNbPsLo_MASK 0x00ff0000 67 # define DpmXNbPsLo_SHIFT 16 68 # define DpmXNbPsHi(x) ((x) << 24) 69 # define DpmXNbPsHi_MASK 0xff000000 70 # define DpmXNbPsHi_SHIFT 24 71 72 #define SMC_SYSCON_RESET_CNTL 0x80000000 73 # define RST_REG (1 << 0) 74 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 75 # define CK_DISABLE (1 << 0) 76 # define CKEN (1 << 24) 77 78 #define SMC_SYSCON_MISC_CNTL 0x80000010 79 80 #define SMC_SYSCON_MSG_ARG_0 0x80000068 81 82 #define SMC_PC_C 0x80000370 83 84 #define SMC_SCRATCH9 0x80000424 85 86 #define RCU_UC_EVENTS 0xC0000004 87 # define BOOT_SEQ_DONE (1 << 7) 88 89 #define GENERAL_PWRMGT 0xC0200000 90 # define GLOBAL_PWRMGT_EN (1 << 0) 91 # define STATIC_PM_EN (1 << 1) 92 # define THERMAL_PROTECTION_DIS (1 << 2) 93 # define THERMAL_PROTECTION_TYPE (1 << 3) 94 # define SW_SMIO_INDEX(x) ((x) << 6) 95 # define SW_SMIO_INDEX_MASK (1 << 6) 96 # define SW_SMIO_INDEX_SHIFT 6 97 # define VOLT_PWRMGT_EN (1 << 10) 98 # define GPU_COUNTER_CLK (1 << 15) 99 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 100 101 #define CNB_PWRMGT_CNTL 0xC0200004 102 # define GNB_SLOW_MODE(x) ((x) << 0) 103 # define GNB_SLOW_MODE_MASK (3 << 0) 104 # define GNB_SLOW_MODE_SHIFT 0 105 # define GNB_SLOW (1 << 2) 106 # define FORCE_NB_PS1 (1 << 3) 107 # define DPM_ENABLED (1 << 4) 108 109 #define SCLK_PWRMGT_CNTL 0xC0200008 110 # define SCLK_PWRMGT_OFF (1 << 0) 111 # define RESET_BUSY_CNT (1 << 4) 112 # define RESET_SCLK_CNT (1 << 5) 113 # define DYNAMIC_PM_EN (1 << 21) 114 115 #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 116 # define CURRENT_STATE_MASK (0xf << 4) 117 # define CURRENT_STATE_SHIFT 4 118 # define CURR_MCLK_INDEX_MASK (0xf << 8) 119 # define CURR_MCLK_INDEX_SHIFT 8 120 # define CURR_SCLK_INDEX_MASK (0x1f << 16) 121 # define CURR_SCLK_INDEX_SHIFT 16 122 123 #define CG_SSP 0xC0200044 124 # define SST(x) ((x) << 0) 125 # define SST_MASK (0xffff << 0) 126 # define SSTU(x) ((x) << 16) 127 # define SSTU_MASK (0xf << 16) 128 129 #define CG_DISPLAY_GAP_CNTL 0xC0200060 130 # define DISP_GAP(x) ((x) << 0) 131 # define DISP_GAP_MASK (3 << 0) 132 # define VBI_TIMER_COUNT(x) ((x) << 4) 133 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 134 # define VBI_TIMER_UNIT(x) ((x) << 20) 135 # define VBI_TIMER_UNIT_MASK (7 << 20) 136 # define DISP_GAP_MCHG(x) ((x) << 24) 137 # define DISP_GAP_MCHG_MASK (3 << 24) 138 139 #define SMU_VOLTAGE_STATUS 0xC0200094 140 # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 141 # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 142 143 #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 144 # define CURR_PCIE_INDEX_MASK (0xf << 24) 145 # define CURR_PCIE_INDEX_SHIFT 24 146 147 #define CG_ULV_PARAMETER 0xC0200158 148 149 #define CG_FTV_0 0xC02001A8 150 #define CG_FTV_1 0xC02001AC 151 #define CG_FTV_2 0xC02001B0 152 #define CG_FTV_3 0xC02001B4 153 #define CG_FTV_4 0xC02001B8 154 #define CG_FTV_5 0xC02001BC 155 #define CG_FTV_6 0xC02001C0 156 #define CG_FTV_7 0xC02001C4 157 158 #define CG_DISPLAY_GAP_CNTL2 0xC0200230 159 160 #define LCAC_SX0_OVR_SEL 0xC0400D04 161 #define LCAC_SX0_OVR_VAL 0xC0400D08 162 163 #define LCAC_MC0_CNTL 0xC0400D30 164 #define LCAC_MC0_OVR_SEL 0xC0400D34 165 #define LCAC_MC0_OVR_VAL 0xC0400D38 166 #define LCAC_MC1_CNTL 0xC0400D3C 167 #define LCAC_MC1_OVR_SEL 0xC0400D40 168 #define LCAC_MC1_OVR_VAL 0xC0400D44 169 170 #define LCAC_MC2_OVR_SEL 0xC0400D4C 171 #define LCAC_MC2_OVR_VAL 0xC0400D50 172 173 #define LCAC_MC3_OVR_SEL 0xC0400D58 174 #define LCAC_MC3_OVR_VAL 0xC0400D5C 175 176 #define LCAC_CPL_CNTL 0xC0400D80 177 #define LCAC_CPL_OVR_SEL 0xC0400D84 178 #define LCAC_CPL_OVR_VAL 0xC0400D88 179 180 /* dGPU */ 181 #define CG_THERMAL_CTRL 0xC0300004 182 #define DPM_EVENT_SRC(x) ((x) << 0) 183 #define DPM_EVENT_SRC_MASK (7 << 0) 184 #define DIG_THERM_DPM(x) ((x) << 14) 185 #define DIG_THERM_DPM_MASK 0x003FC000 186 #define DIG_THERM_DPM_SHIFT 14 187 188 #define CG_THERMAL_INT 0xC030000C 189 #define CI_DIG_THERM_INTH(x) ((x) << 8) 190 #define CI_DIG_THERM_INTH_MASK 0x0000FF00 191 #define CI_DIG_THERM_INTH_SHIFT 8 192 #define CI_DIG_THERM_INTL(x) ((x) << 16) 193 #define CI_DIG_THERM_INTL_MASK 0x00FF0000 194 #define CI_DIG_THERM_INTL_SHIFT 16 195 #define THERM_INT_MASK_HIGH (1 << 24) 196 #define THERM_INT_MASK_LOW (1 << 25) 197 198 #define CG_MULT_THERMAL_STATUS 0xC0300014 199 #define ASIC_MAX_TEMP(x) ((x) << 0) 200 #define ASIC_MAX_TEMP_MASK 0x000001ff 201 #define ASIC_MAX_TEMP_SHIFT 0 202 #define CTF_TEMP(x) ((x) << 9) 203 #define CTF_TEMP_MASK 0x0003fe00 204 #define CTF_TEMP_SHIFT 9 205 206 #define CG_ECLK_CNTL 0xC05000AC 207 # define ECLK_DIVIDER_MASK 0x7f 208 # define ECLK_DIR_CNTL_EN (1 << 8) 209 #define CG_ECLK_STATUS 0xC05000B0 210 # define ECLK_STATUS (1 << 0) 211 212 #define CG_SPLL_FUNC_CNTL 0xC0500140 213 #define SPLL_RESET (1 << 0) 214 #define SPLL_PWRON (1 << 1) 215 #define SPLL_BYPASS_EN (1 << 3) 216 #define SPLL_REF_DIV(x) ((x) << 5) 217 #define SPLL_REF_DIV_MASK (0x3f << 5) 218 #define SPLL_PDIV_A(x) ((x) << 20) 219 #define SPLL_PDIV_A_MASK (0x7f << 20) 220 #define SPLL_PDIV_A_SHIFT 20 221 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 222 #define SCLK_MUX_SEL(x) ((x) << 0) 223 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 224 #define CG_SPLL_FUNC_CNTL_3 0xC0500148 225 #define SPLL_FB_DIV(x) ((x) << 0) 226 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 227 #define SPLL_FB_DIV_SHIFT 0 228 #define SPLL_DITHEN (1 << 28) 229 #define CG_SPLL_FUNC_CNTL_4 0xC050014C 230 231 #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 232 #define SSEN (1 << 0) 233 #define CLK_S(x) ((x) << 4) 234 #define CLK_S_MASK (0xfff << 4) 235 #define CLK_S_SHIFT 4 236 #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 237 #define CLK_V(x) ((x) << 0) 238 #define CLK_V_MASK (0x3ffffff << 0) 239 #define CLK_V_SHIFT 0 240 241 #define MPLL_BYPASSCLK_SEL 0xC050019C 242 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 243 # define MPLL_CLKOUT_SEL_MASK 0xFF00 244 #define CG_CLKPIN_CNTL 0xC05001A0 245 # define XTALIN_DIVIDE (1 << 1) 246 # define BCLK_AS_XCLK (1 << 2) 247 #define CG_CLKPIN_CNTL_2 0xC05001A4 248 # define FORCE_BIF_REFCLK_EN (1 << 3) 249 # define MUX_TCLK_TO_XCLK (1 << 8) 250 #define THM_CLK_CNTL 0xC05001A8 251 # define CMON_CLK_SEL(x) ((x) << 0) 252 # define CMON_CLK_SEL_MASK 0xFF 253 # define TMON_CLK_SEL(x) ((x) << 8) 254 # define TMON_CLK_SEL_MASK 0xFF00 255 #define MISC_CLK_CTRL 0xC05001AC 256 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 257 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 258 # define ZCLK_SEL(x) ((x) << 8) 259 # define ZCLK_SEL_MASK 0xFF00 260 261 /* KV/KB */ 262 #define CG_THERMAL_INT_CTRL 0xC2100028 263 #define DIG_THERM_INTH(x) ((x) << 0) 264 #define DIG_THERM_INTH_MASK 0x000000FF 265 #define DIG_THERM_INTH_SHIFT 0 266 #define DIG_THERM_INTL(x) ((x) << 8) 267 #define DIG_THERM_INTL_MASK 0x0000FF00 268 #define DIG_THERM_INTL_SHIFT 8 269 #define THERM_INTH_MASK (1 << 24) 270 #define THERM_INTL_MASK (1 << 25) 271 272 /* PCIE registers idx/data 0x38/0x3c */ 273 #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 274 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 275 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 276 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 277 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 278 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 279 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 280 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 281 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 282 # define PLL_RAMP_UP_TIME_0_SHIFT 24 283 #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 284 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 285 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 286 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 287 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 288 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 289 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 290 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 291 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 292 # define PLL_RAMP_UP_TIME_1_SHIFT 24 293 294 #define PCIE_CNTL2 0x1001001c /* PCIE */ 295 # define SLV_MEM_LS_EN (1 << 16) 296 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 297 # define MST_MEM_LS_EN (1 << 18) 298 # define REPLAY_MEM_LS_EN (1 << 19) 299 300 #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 301 # define LC_REVERSE_RCVR (1 << 0) 302 # define LC_REVERSE_XMIT (1 << 1) 303 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 304 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 305 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 306 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 307 308 #define PCIE_P_CNTL 0x1400040 /* PCIE */ 309 # define P_IGNORE_EDB_ERR (1 << 6) 310 311 #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 312 #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 313 314 #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 315 # define LC_L0S_INACTIVITY(x) ((x) << 8) 316 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 317 # define LC_L0S_INACTIVITY_SHIFT 8 318 # define LC_L1_INACTIVITY(x) ((x) << 12) 319 # define LC_L1_INACTIVITY_MASK (0xf << 12) 320 # define LC_L1_INACTIVITY_SHIFT 12 321 # define LC_PMI_TO_L1_DIS (1 << 16) 322 # define LC_ASPM_TO_L1_DIS (1 << 24) 323 324 #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 325 # define LC_LINK_WIDTH_SHIFT 0 326 # define LC_LINK_WIDTH_MASK 0x7 327 # define LC_LINK_WIDTH_X0 0 328 # define LC_LINK_WIDTH_X1 1 329 # define LC_LINK_WIDTH_X2 2 330 # define LC_LINK_WIDTH_X4 3 331 # define LC_LINK_WIDTH_X8 4 332 # define LC_LINK_WIDTH_X16 6 333 # define LC_LINK_WIDTH_RD_SHIFT 4 334 # define LC_LINK_WIDTH_RD_MASK 0x70 335 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 336 # define LC_RECONFIG_NOW (1 << 8) 337 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 338 # define LC_RENEGOTIATE_EN (1 << 10) 339 # define LC_SHORT_RECONFIG_EN (1 << 11) 340 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 341 # define LC_UPCONFIGURE_DIS (1 << 13) 342 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 343 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 344 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 345 #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 346 # define LC_XMIT_N_FTS(x) ((x) << 0) 347 # define LC_XMIT_N_FTS_MASK (0xff << 0) 348 # define LC_XMIT_N_FTS_SHIFT 0 349 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 350 # define LC_N_FTS_MASK (0xff << 24) 351 #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 352 # define LC_GEN2_EN_STRAP (1 << 0) 353 # define LC_GEN3_EN_STRAP (1 << 1) 354 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 355 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 356 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 357 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 358 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 359 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 360 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 361 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 362 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 363 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 364 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 365 # define LC_CURRENT_DATA_RATE_SHIFT 13 366 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 367 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 368 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 369 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 370 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 371 372 #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 373 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 374 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 375 376 #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 377 # define LC_GO_TO_RECOVERY (1 << 30) 378 #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 379 # define LC_REDO_EQ (1 << 5) 380 # define LC_SET_QUIESCE (1 << 13) 381 382 /* direct registers */ 383 #define PCIE_INDEX 0x38 384 #define PCIE_DATA 0x3C 385 386 #define SMC_IND_INDEX_0 0x200 387 #define SMC_IND_DATA_0 0x204 388 389 #define SMC_IND_ACCESS_CNTL 0x240 390 #define AUTO_INCREMENT_IND_0 (1 << 0) 391 392 #define SMC_MESSAGE_0 0x250 393 #define SMC_MSG_MASK 0xffff 394 #define SMC_RESP_0 0x254 395 #define SMC_RESP_MASK 0xffff 396 397 #define SMC_MSG_ARG_0 0x290 398 399 #define VGA_HDP_CONTROL 0x328 400 #define VGA_MEMORY_DISABLE (1 << 4) 401 402 #define DMIF_ADDR_CALC 0xC00 403 404 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 405 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 406 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 407 408 #define SRBM_GFX_CNTL 0xE44 409 #define PIPEID(x) ((x) << 0) 410 #define MEID(x) ((x) << 2) 411 #define VMID(x) ((x) << 4) 412 #define QUEUEID(x) ((x) << 8) 413 414 #define SRBM_STATUS2 0xE4C 415 #define SDMA_BUSY (1 << 5) 416 #define SDMA1_BUSY (1 << 6) 417 #define SRBM_STATUS 0xE50 418 #define UVD_RQ_PENDING (1 << 1) 419 #define GRBM_RQ_PENDING (1 << 5) 420 #define VMC_BUSY (1 << 8) 421 #define MCB_BUSY (1 << 9) 422 #define MCB_NON_DISPLAY_BUSY (1 << 10) 423 #define MCC_BUSY (1 << 11) 424 #define MCD_BUSY (1 << 12) 425 #define SEM_BUSY (1 << 14) 426 #define IH_BUSY (1 << 17) 427 #define UVD_BUSY (1 << 19) 428 429 #define SRBM_SOFT_RESET 0xE60 430 #define SOFT_RESET_BIF (1 << 1) 431 #define SOFT_RESET_R0PLL (1 << 4) 432 #define SOFT_RESET_DC (1 << 5) 433 #define SOFT_RESET_SDMA1 (1 << 6) 434 #define SOFT_RESET_GRBM (1 << 8) 435 #define SOFT_RESET_HDP (1 << 9) 436 #define SOFT_RESET_IH (1 << 10) 437 #define SOFT_RESET_MC (1 << 11) 438 #define SOFT_RESET_ROM (1 << 14) 439 #define SOFT_RESET_SEM (1 << 15) 440 #define SOFT_RESET_VMC (1 << 17) 441 #define SOFT_RESET_SDMA (1 << 20) 442 #define SOFT_RESET_TST (1 << 21) 443 #define SOFT_RESET_REGBB (1 << 22) 444 #define SOFT_RESET_ORB (1 << 23) 445 #define SOFT_RESET_VCE (1 << 24) 446 447 #define VM_L2_CNTL 0x1400 448 #define ENABLE_L2_CACHE (1 << 0) 449 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 450 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 451 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 452 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 453 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 454 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 455 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 456 #define VM_L2_CNTL2 0x1404 457 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 458 #define INVALIDATE_L2_CACHE (1 << 1) 459 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 460 #define INVALIDATE_PTE_AND_PDE_CACHES 0 461 #define INVALIDATE_ONLY_PTE_CACHES 1 462 #define INVALIDATE_ONLY_PDE_CACHES 2 463 #define VM_L2_CNTL3 0x1408 464 #define BANK_SELECT(x) ((x) << 0) 465 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 466 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 467 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 468 #define VM_L2_STATUS 0x140C 469 #define L2_BUSY (1 << 0) 470 #define VM_CONTEXT0_CNTL 0x1410 471 #define ENABLE_CONTEXT (1 << 0) 472 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 473 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 474 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 475 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 476 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 477 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 478 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 479 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 480 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 481 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 482 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 483 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 484 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 485 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 486 #define VM_CONTEXT1_CNTL 0x1414 487 #define VM_CONTEXT0_CNTL2 0x1430 488 #define VM_CONTEXT1_CNTL2 0x1434 489 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 490 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 491 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 492 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 493 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 494 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 495 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 496 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 497 498 #define VM_INVALIDATE_REQUEST 0x1478 499 #define VM_INVALIDATE_RESPONSE 0x147c 500 501 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 502 #define PROTECTIONS_MASK (0xf << 0) 503 #define PROTECTIONS_SHIFT 0 504 /* bit 0: range 505 * bit 1: pde0 506 * bit 2: valid 507 * bit 3: read 508 * bit 4: write 509 */ 510 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 511 #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 512 #define MEMORY_CLIENT_ID_SHIFT 12 513 #define MEMORY_CLIENT_RW_MASK (1 << 24) 514 #define MEMORY_CLIENT_RW_SHIFT 24 515 #define FAULT_VMID_MASK (0xf << 25) 516 #define FAULT_VMID_SHIFT 25 517 518 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 519 520 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 521 522 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 523 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 524 525 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 526 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 527 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 528 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 529 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 530 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 531 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 532 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 533 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 534 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 535 536 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 537 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 538 539 #define VM_L2_CG 0x15c0 540 #define MC_CG_ENABLE (1 << 18) 541 #define MC_LS_ENABLE (1 << 19) 542 543 #define MC_SHARED_CHMAP 0x2004 544 #define NOOFCHAN_SHIFT 12 545 #define NOOFCHAN_MASK 0x0000f000 546 #define MC_SHARED_CHREMAP 0x2008 547 548 #define CHUB_CONTROL 0x1864 549 #define BYPASS_VM (1 << 0) 550 551 #define MC_VM_FB_LOCATION 0x2024 552 #define MC_VM_AGP_TOP 0x2028 553 #define MC_VM_AGP_BOT 0x202C 554 #define MC_VM_AGP_BASE 0x2030 555 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 556 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 557 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 558 559 #define MC_VM_MX_L1_TLB_CNTL 0x2064 560 #define ENABLE_L1_TLB (1 << 0) 561 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 562 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 563 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 564 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 565 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 566 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 567 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 568 #define MC_VM_FB_OFFSET 0x2068 569 570 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 571 572 #define MC_HUB_MISC_HUB_CG 0x20b8 573 #define MC_HUB_MISC_VM_CG 0x20bc 574 575 #define MC_HUB_MISC_SIP_CG 0x20c0 576 577 #define MC_XPB_CLK_GAT 0x2478 578 579 #define MC_CITF_MISC_RD_CG 0x2648 580 #define MC_CITF_MISC_WR_CG 0x264c 581 #define MC_CITF_MISC_VM_CG 0x2650 582 583 #define MC_ARB_RAMCFG 0x2760 584 #define NOOFBANK_SHIFT 0 585 #define NOOFBANK_MASK 0x00000003 586 #define NOOFRANK_SHIFT 2 587 #define NOOFRANK_MASK 0x00000004 588 #define NOOFROWS_SHIFT 3 589 #define NOOFROWS_MASK 0x00000038 590 #define NOOFCOLS_SHIFT 6 591 #define NOOFCOLS_MASK 0x000000C0 592 #define CHANSIZE_SHIFT 8 593 #define CHANSIZE_MASK 0x00000100 594 #define NOOFGROUPS_SHIFT 12 595 #define NOOFGROUPS_MASK 0x00001000 596 597 #define MC_ARB_DRAM_TIMING 0x2774 598 #define MC_ARB_DRAM_TIMING2 0x2778 599 600 #define MC_ARB_BURST_TIME 0x2808 601 #define STATE0(x) ((x) << 0) 602 #define STATE0_MASK (0x1f << 0) 603 #define STATE0_SHIFT 0 604 #define STATE1(x) ((x) << 5) 605 #define STATE1_MASK (0x1f << 5) 606 #define STATE1_SHIFT 5 607 #define STATE2(x) ((x) << 10) 608 #define STATE2_MASK (0x1f << 10) 609 #define STATE2_SHIFT 10 610 #define STATE3(x) ((x) << 15) 611 #define STATE3_MASK (0x1f << 15) 612 #define STATE3_SHIFT 15 613 614 #define MC_SEQ_RAS_TIMING 0x28a0 615 #define MC_SEQ_CAS_TIMING 0x28a4 616 #define MC_SEQ_MISC_TIMING 0x28a8 617 #define MC_SEQ_MISC_TIMING2 0x28ac 618 #define MC_SEQ_PMG_TIMING 0x28b0 619 #define MC_SEQ_RD_CTL_D0 0x28b4 620 #define MC_SEQ_RD_CTL_D1 0x28b8 621 #define MC_SEQ_WR_CTL_D0 0x28bc 622 #define MC_SEQ_WR_CTL_D1 0x28c0 623 624 #define MC_SEQ_SUP_CNTL 0x28c8 625 #define RUN_MASK (1 << 0) 626 #define MC_SEQ_SUP_PGM 0x28cc 627 #define MC_PMG_AUTO_CMD 0x28d0 628 629 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 630 #define TRAIN_DONE_D0 (1 << 30) 631 #define TRAIN_DONE_D1 (1 << 31) 632 633 #define MC_IO_PAD_CNTL_D0 0x29d0 634 #define MEM_FALL_OUT_CMD (1 << 8) 635 636 #define MC_SEQ_MISC0 0x2a00 637 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 638 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 639 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 640 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 641 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 642 #define MC_SEQ_MISC0_REV_ID_VALUE 1 643 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 644 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 645 #define MC_SEQ_MISC0_GDDR5_VALUE 5 646 #define MC_SEQ_MISC1 0x2a04 647 #define MC_SEQ_RESERVE_M 0x2a08 648 #define MC_PMG_CMD_EMRS 0x2a0c 649 650 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 651 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 652 653 #define MC_SEQ_MISC5 0x2a54 654 #define MC_SEQ_MISC6 0x2a58 655 656 #define MC_SEQ_MISC7 0x2a64 657 658 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 659 #define MC_SEQ_CAS_TIMING_LP 0x2a70 660 #define MC_SEQ_MISC_TIMING_LP 0x2a74 661 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 662 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 663 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 664 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 665 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 666 667 #define MC_PMG_CMD_MRS 0x2aac 668 669 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 670 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 671 672 #define MC_PMG_CMD_MRS1 0x2b44 673 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 674 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 675 676 #define MC_SEQ_WR_CTL_2 0x2b54 677 #define MC_SEQ_WR_CTL_2_LP 0x2b58 678 #define MC_PMG_CMD_MRS2 0x2b5c 679 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 680 681 #define MCLK_PWRMGT_CNTL 0x2ba0 682 # define DLL_SPEED(x) ((x) << 0) 683 # define DLL_SPEED_MASK (0x1f << 0) 684 # define DLL_READY (1 << 6) 685 # define MC_INT_CNTL (1 << 7) 686 # define MRDCK0_PDNB (1 << 8) 687 # define MRDCK1_PDNB (1 << 9) 688 # define MRDCK0_RESET (1 << 16) 689 # define MRDCK1_RESET (1 << 17) 690 # define DLL_READY_READ (1 << 24) 691 #define DLL_CNTL 0x2ba4 692 # define MRDCK0_BYPASS (1 << 24) 693 # define MRDCK1_BYPASS (1 << 25) 694 695 #define MPLL_FUNC_CNTL 0x2bb4 696 #define BWCTRL(x) ((x) << 20) 697 #define BWCTRL_MASK (0xff << 20) 698 #define MPLL_FUNC_CNTL_1 0x2bb8 699 #define VCO_MODE(x) ((x) << 0) 700 #define VCO_MODE_MASK (3 << 0) 701 #define CLKFRAC(x) ((x) << 4) 702 #define CLKFRAC_MASK (0xfff << 4) 703 #define CLKF(x) ((x) << 16) 704 #define CLKF_MASK (0xfff << 16) 705 #define MPLL_FUNC_CNTL_2 0x2bbc 706 #define MPLL_AD_FUNC_CNTL 0x2bc0 707 #define YCLK_POST_DIV(x) ((x) << 0) 708 #define YCLK_POST_DIV_MASK (7 << 0) 709 #define MPLL_DQ_FUNC_CNTL 0x2bc4 710 #define YCLK_SEL(x) ((x) << 4) 711 #define YCLK_SEL_MASK (1 << 4) 712 713 #define MPLL_SS1 0x2bcc 714 #define CLKV(x) ((x) << 0) 715 #define CLKV_MASK (0x3ffffff << 0) 716 #define MPLL_SS2 0x2bd0 717 #define CLKS(x) ((x) << 0) 718 #define CLKS_MASK (0xfff << 0) 719 720 #define HDP_HOST_PATH_CNTL 0x2C00 721 #define CLOCK_GATING_DIS (1 << 23) 722 #define HDP_NONSURFACE_BASE 0x2C04 723 #define HDP_NONSURFACE_INFO 0x2C08 724 #define HDP_NONSURFACE_SIZE 0x2C0C 725 726 #define HDP_ADDR_CONFIG 0x2F48 727 #define HDP_MISC_CNTL 0x2F4C 728 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 729 #define HDP_MEM_POWER_LS 0x2F50 730 #define HDP_LS_ENABLE (1 << 0) 731 732 #define ATC_MISC_CG 0x3350 733 734 #define GMCON_RENG_EXECUTE 0x3508 735 #define RENG_EXECUTE_ON_PWR_UP (1 << 0) 736 #define GMCON_MISC 0x350c 737 #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11) 738 #define STCTRL_STUTTER_EN (1 << 16) 739 740 #define GMCON_PGFSM_CONFIG 0x3538 741 #define GMCON_PGFSM_WRITE 0x353c 742 #define GMCON_PGFSM_READ 0x3540 743 #define GMCON_MISC3 0x3544 744 745 #define MC_SEQ_CNTL_3 0x3600 746 # define CAC_EN (1 << 31) 747 #define MC_SEQ_G5PDX_CTRL 0x3604 748 #define MC_SEQ_G5PDX_CTRL_LP 0x3608 749 #define MC_SEQ_G5PDX_CMD0 0x360c 750 #define MC_SEQ_G5PDX_CMD0_LP 0x3610 751 #define MC_SEQ_G5PDX_CMD1 0x3614 752 #define MC_SEQ_G5PDX_CMD1_LP 0x3618 753 754 #define MC_SEQ_PMG_DVS_CTL 0x3628 755 #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 756 #define MC_SEQ_PMG_DVS_CMD 0x3630 757 #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 758 #define MC_SEQ_DLL_STBY 0x3638 759 #define MC_SEQ_DLL_STBY_LP 0x363c 760 761 #define IH_RB_CNTL 0x3e00 762 # define IH_RB_ENABLE (1 << 0) 763 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 764 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 765 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 766 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 767 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 768 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 769 #define IH_RB_BASE 0x3e04 770 #define IH_RB_RPTR 0x3e08 771 #define IH_RB_WPTR 0x3e0c 772 # define RB_OVERFLOW (1 << 0) 773 # define WPTR_OFFSET_MASK 0x3fffc 774 #define IH_RB_WPTR_ADDR_HI 0x3e10 775 #define IH_RB_WPTR_ADDR_LO 0x3e14 776 #define IH_CNTL 0x3e18 777 # define ENABLE_INTR (1 << 0) 778 # define IH_MC_SWAP(x) ((x) << 1) 779 # define IH_MC_SWAP_NONE 0 780 # define IH_MC_SWAP_16BIT 1 781 # define IH_MC_SWAP_32BIT 2 782 # define IH_MC_SWAP_64BIT 3 783 # define RPTR_REARM (1 << 4) 784 # define MC_WRREQ_CREDIT(x) ((x) << 15) 785 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 786 # define MC_VMID(x) ((x) << 25) 787 788 #define BIF_LNCNT_RESET 0x5220 789 # define RESET_LNCNT_EN (1 << 0) 790 791 #define CONFIG_MEMSIZE 0x5428 792 793 #define INTERRUPT_CNTL 0x5468 794 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 795 # define IH_DUMMY_RD_EN (1 << 1) 796 # define IH_REQ_NONSNOOP_EN (1 << 3) 797 # define GEN_IH_INT_EN (1 << 8) 798 #define INTERRUPT_CNTL2 0x546c 799 800 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 801 802 #define BIF_FB_EN 0x5490 803 #define FB_READ_EN (1 << 0) 804 #define FB_WRITE_EN (1 << 1) 805 806 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 807 808 #define GPU_HDP_FLUSH_REQ 0x54DC 809 #define GPU_HDP_FLUSH_DONE 0x54E0 810 #define CP0 (1 << 0) 811 #define CP1 (1 << 1) 812 #define CP2 (1 << 2) 813 #define CP3 (1 << 3) 814 #define CP4 (1 << 4) 815 #define CP5 (1 << 5) 816 #define CP6 (1 << 6) 817 #define CP7 (1 << 7) 818 #define CP8 (1 << 8) 819 #define CP9 (1 << 9) 820 #define SDMA0 (1 << 10) 821 #define SDMA1 (1 << 11) 822 823 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 824 #define LB_MEMORY_CTRL 0x6b04 825 #define LB_MEMORY_SIZE(x) ((x) << 0) 826 #define LB_MEMORY_CONFIG(x) ((x) << 20) 827 828 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 829 # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 830 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 831 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 832 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 833 834 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 835 #define LB_VLINE_STATUS 0x6b24 836 # define VLINE_OCCURRED (1 << 0) 837 # define VLINE_ACK (1 << 4) 838 # define VLINE_STAT (1 << 12) 839 # define VLINE_INTERRUPT (1 << 16) 840 # define VLINE_INTERRUPT_TYPE (1 << 17) 841 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 842 #define LB_VBLANK_STATUS 0x6b2c 843 # define VBLANK_OCCURRED (1 << 0) 844 # define VBLANK_ACK (1 << 4) 845 # define VBLANK_STAT (1 << 12) 846 # define VBLANK_INTERRUPT (1 << 16) 847 # define VBLANK_INTERRUPT_TYPE (1 << 17) 848 849 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 850 #define LB_INTERRUPT_MASK 0x6b20 851 # define VBLANK_INTERRUPT_MASK (1 << 0) 852 # define VLINE_INTERRUPT_MASK (1 << 4) 853 # define VLINE2_INTERRUPT_MASK (1 << 8) 854 855 #define DISP_INTERRUPT_STATUS 0x60f4 856 # define LB_D1_VLINE_INTERRUPT (1 << 2) 857 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 858 # define DC_HPD1_INTERRUPT (1 << 17) 859 # define DC_HPD1_RX_INTERRUPT (1 << 18) 860 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 861 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 862 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 863 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 864 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 865 # define LB_D2_VLINE_INTERRUPT (1 << 2) 866 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 867 # define DC_HPD2_INTERRUPT (1 << 17) 868 # define DC_HPD2_RX_INTERRUPT (1 << 18) 869 # define DISP_TIMER_INTERRUPT (1 << 24) 870 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 871 # define LB_D3_VLINE_INTERRUPT (1 << 2) 872 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 873 # define DC_HPD3_INTERRUPT (1 << 17) 874 # define DC_HPD3_RX_INTERRUPT (1 << 18) 875 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 876 # define LB_D4_VLINE_INTERRUPT (1 << 2) 877 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 878 # define DC_HPD4_INTERRUPT (1 << 17) 879 # define DC_HPD4_RX_INTERRUPT (1 << 18) 880 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 881 # define LB_D5_VLINE_INTERRUPT (1 << 2) 882 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 883 # define DC_HPD5_INTERRUPT (1 << 17) 884 # define DC_HPD5_RX_INTERRUPT (1 << 18) 885 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 886 # define LB_D6_VLINE_INTERRUPT (1 << 2) 887 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 888 # define DC_HPD6_INTERRUPT (1 << 17) 889 # define DC_HPD6_RX_INTERRUPT (1 << 18) 890 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 891 892 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 893 #define GRPH_INT_STATUS 0x6858 894 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 895 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 896 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 897 #define GRPH_INT_CONTROL 0x685c 898 # define GRPH_PFLIP_INT_MASK (1 << 0) 899 # define GRPH_PFLIP_INT_TYPE (1 << 8) 900 901 #define DAC_AUTODETECT_INT_CONTROL 0x67c8 902 903 #define DC_HPD1_INT_STATUS 0x601c 904 #define DC_HPD2_INT_STATUS 0x6028 905 #define DC_HPD3_INT_STATUS 0x6034 906 #define DC_HPD4_INT_STATUS 0x6040 907 #define DC_HPD5_INT_STATUS 0x604c 908 #define DC_HPD6_INT_STATUS 0x6058 909 # define DC_HPDx_INT_STATUS (1 << 0) 910 # define DC_HPDx_SENSE (1 << 1) 911 # define DC_HPDx_SENSE_DELAYED (1 << 4) 912 # define DC_HPDx_RX_INT_STATUS (1 << 8) 913 914 #define DC_HPD1_INT_CONTROL 0x6020 915 #define DC_HPD2_INT_CONTROL 0x602c 916 #define DC_HPD3_INT_CONTROL 0x6038 917 #define DC_HPD4_INT_CONTROL 0x6044 918 #define DC_HPD5_INT_CONTROL 0x6050 919 #define DC_HPD6_INT_CONTROL 0x605c 920 # define DC_HPDx_INT_ACK (1 << 0) 921 # define DC_HPDx_INT_POLARITY (1 << 8) 922 # define DC_HPDx_INT_EN (1 << 16) 923 # define DC_HPDx_RX_INT_ACK (1 << 20) 924 # define DC_HPDx_RX_INT_EN (1 << 24) 925 926 #define DC_HPD1_CONTROL 0x6024 927 #define DC_HPD2_CONTROL 0x6030 928 #define DC_HPD3_CONTROL 0x603c 929 #define DC_HPD4_CONTROL 0x6048 930 #define DC_HPD5_CONTROL 0x6054 931 #define DC_HPD6_CONTROL 0x6060 932 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 933 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 934 # define DC_HPDx_EN (1 << 28) 935 936 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 937 # define STUTTER_ENABLE (1 << 0) 938 939 /* DCE8 FMT blocks */ 940 #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 941 # define FMT_DYNAMIC_EXP_EN (1 << 0) 942 # define FMT_DYNAMIC_EXP_MODE (1 << 4) 943 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 944 #define FMT_CONTROL 0x6fb8 945 # define FMT_PIXEL_ENCODING (1 << 16) 946 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 947 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 948 # define FMT_TRUNCATE_EN (1 << 0) 949 # define FMT_TRUNCATE_MODE (1 << 1) 950 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 951 # define FMT_SPATIAL_DITHER_EN (1 << 8) 952 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 953 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 954 # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 955 # define FMT_RGB_RANDOM_ENABLE (1 << 14) 956 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 957 # define FMT_TEMPORAL_DITHER_EN (1 << 16) 958 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 959 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 960 # define FMT_TEMPORAL_LEVEL (1 << 24) 961 # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 962 # define FMT_25FRC_SEL(x) ((x) << 26) 963 # define FMT_50FRC_SEL(x) ((x) << 28) 964 # define FMT_75FRC_SEL(x) ((x) << 30) 965 #define FMT_CLAMP_CONTROL 0x6fe4 966 # define FMT_CLAMP_DATA_EN (1 << 0) 967 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 968 # define FMT_CLAMP_6BPC 0 969 # define FMT_CLAMP_8BPC 1 970 # define FMT_CLAMP_10BPC 2 971 972 #define GRBM_CNTL 0x8000 973 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 974 975 #define GRBM_STATUS2 0x8008 976 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 977 #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 978 #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 979 #define ME1PIPE0_RQ_PENDING (1 << 6) 980 #define ME1PIPE1_RQ_PENDING (1 << 7) 981 #define ME1PIPE2_RQ_PENDING (1 << 8) 982 #define ME1PIPE3_RQ_PENDING (1 << 9) 983 #define ME2PIPE0_RQ_PENDING (1 << 10) 984 #define ME2PIPE1_RQ_PENDING (1 << 11) 985 #define ME2PIPE2_RQ_PENDING (1 << 12) 986 #define ME2PIPE3_RQ_PENDING (1 << 13) 987 #define RLC_RQ_PENDING (1 << 14) 988 #define RLC_BUSY (1 << 24) 989 #define TC_BUSY (1 << 25) 990 #define CPF_BUSY (1 << 28) 991 #define CPC_BUSY (1 << 29) 992 #define CPG_BUSY (1 << 30) 993 994 #define GRBM_STATUS 0x8010 995 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 996 #define SRBM_RQ_PENDING (1 << 5) 997 #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 998 #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 999 #define GDS_DMA_RQ_PENDING (1 << 9) 1000 #define DB_CLEAN (1 << 12) 1001 #define CB_CLEAN (1 << 13) 1002 #define TA_BUSY (1 << 14) 1003 #define GDS_BUSY (1 << 15) 1004 #define WD_BUSY_NO_DMA (1 << 16) 1005 #define VGT_BUSY (1 << 17) 1006 #define IA_BUSY_NO_DMA (1 << 18) 1007 #define IA_BUSY (1 << 19) 1008 #define SX_BUSY (1 << 20) 1009 #define WD_BUSY (1 << 21) 1010 #define SPI_BUSY (1 << 22) 1011 #define BCI_BUSY (1 << 23) 1012 #define SC_BUSY (1 << 24) 1013 #define PA_BUSY (1 << 25) 1014 #define DB_BUSY (1 << 26) 1015 #define CP_COHERENCY_BUSY (1 << 28) 1016 #define CP_BUSY (1 << 29) 1017 #define CB_BUSY (1 << 30) 1018 #define GUI_ACTIVE (1 << 31) 1019 #define GRBM_STATUS_SE0 0x8014 1020 #define GRBM_STATUS_SE1 0x8018 1021 #define GRBM_STATUS_SE2 0x8038 1022 #define GRBM_STATUS_SE3 0x803C 1023 #define SE_DB_CLEAN (1 << 1) 1024 #define SE_CB_CLEAN (1 << 2) 1025 #define SE_BCI_BUSY (1 << 22) 1026 #define SE_VGT_BUSY (1 << 23) 1027 #define SE_PA_BUSY (1 << 24) 1028 #define SE_TA_BUSY (1 << 25) 1029 #define SE_SX_BUSY (1 << 26) 1030 #define SE_SPI_BUSY (1 << 27) 1031 #define SE_SC_BUSY (1 << 29) 1032 #define SE_DB_BUSY (1 << 30) 1033 #define SE_CB_BUSY (1 << 31) 1034 1035 #define GRBM_SOFT_RESET 0x8020 1036 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 1037 #define SOFT_RESET_RLC (1 << 2) /* RLC */ 1038 #define SOFT_RESET_GFX (1 << 16) /* GFX */ 1039 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 1040 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 1041 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 1042 1043 #define GRBM_INT_CNTL 0x8060 1044 # define RDERR_INT_ENABLE (1 << 0) 1045 # define GUI_IDLE_INT_ENABLE (1 << 19) 1046 1047 #define CP_CPC_STATUS 0x8210 1048 #define CP_CPC_BUSY_STAT 0x8214 1049 #define CP_CPC_STALLED_STAT1 0x8218 1050 #define CP_CPF_STATUS 0x821c 1051 #define CP_CPF_BUSY_STAT 0x8220 1052 #define CP_CPF_STALLED_STAT1 0x8224 1053 1054 #define CP_MEC_CNTL 0x8234 1055 #define MEC_ME2_HALT (1 << 28) 1056 #define MEC_ME1_HALT (1 << 30) 1057 1058 #define CP_MEC_CNTL 0x8234 1059 #define MEC_ME2_HALT (1 << 28) 1060 #define MEC_ME1_HALT (1 << 30) 1061 1062 #define CP_STALLED_STAT3 0x8670 1063 #define CP_STALLED_STAT1 0x8674 1064 #define CP_STALLED_STAT2 0x8678 1065 1066 #define CP_STAT 0x8680 1067 1068 #define CP_ME_CNTL 0x86D8 1069 #define CP_CE_HALT (1 << 24) 1070 #define CP_PFP_HALT (1 << 26) 1071 #define CP_ME_HALT (1 << 28) 1072 1073 #define CP_RB0_RPTR 0x8700 1074 #define CP_RB_WPTR_DELAY 0x8704 1075 #define CP_RB_WPTR_POLL_CNTL 0x8708 1076 #define IDLE_POLL_COUNT(x) ((x) << 16) 1077 #define IDLE_POLL_COUNT_MASK (0xffff << 16) 1078 1079 #define CP_MEQ_THRESHOLDS 0x8764 1080 #define MEQ1_START(x) ((x) << 0) 1081 #define MEQ2_START(x) ((x) << 8) 1082 1083 #define VGT_VTX_VECT_EJECT_REG 0x88B0 1084 1085 #define VGT_CACHE_INVALIDATION 0x88C4 1086 #define CACHE_INVALIDATION(x) ((x) << 0) 1087 #define VC_ONLY 0 1088 #define TC_ONLY 1 1089 #define VC_AND_TC 2 1090 #define AUTO_INVLD_EN(x) ((x) << 6) 1091 #define NO_AUTO 0 1092 #define ES_AUTO 1 1093 #define GS_AUTO 2 1094 #define ES_AND_GS_AUTO 3 1095 1096 #define VGT_GS_VERTEX_REUSE 0x88D4 1097 1098 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 1099 #define INACTIVE_CUS_MASK 0xFFFF0000 1100 #define INACTIVE_CUS_SHIFT 16 1101 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 1102 1103 #define PA_CL_ENHANCE 0x8A14 1104 #define CLIP_VTX_REORDER_ENA (1 << 0) 1105 #define NUM_CLIP_SEQ(x) ((x) << 1) 1106 1107 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 1108 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1109 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1110 1111 #define PA_SC_FIFO_SIZE 0x8BCC 1112 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1113 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1114 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1115 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1116 1117 #define PA_SC_ENHANCE 0x8BF0 1118 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 1119 #define DISABLE_PA_SC_GUIDANCE (1 << 13) 1120 1121 #define SQ_CONFIG 0x8C00 1122 1123 #define SH_MEM_BASES 0x8C28 1124 /* if PTR32, these are the bases for scratch and lds */ 1125 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 1126 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 1127 #define SH_MEM_APE1_BASE 0x8C2C 1128 /* if PTR32, this is the base location of GPUVM */ 1129 #define SH_MEM_APE1_LIMIT 0x8C30 1130 /* if PTR32, this is the upper limit of GPUVM */ 1131 #define SH_MEM_CONFIG 0x8C34 1132 #define PTR32 (1 << 0) 1133 #define ALIGNMENT_MODE(x) ((x) << 2) 1134 #define SH_MEM_ALIGNMENT_MODE_DWORD 0 1135 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 1136 #define SH_MEM_ALIGNMENT_MODE_STRICT 2 1137 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 1138 #define DEFAULT_MTYPE(x) ((x) << 4) 1139 #define APE1_MTYPE(x) ((x) << 7) 1140 1141 #define SX_DEBUG_1 0x9060 1142 1143 #define SPI_CONFIG_CNTL 0x9100 1144 1145 #define SPI_CONFIG_CNTL_1 0x913C 1146 #define VTX_DONE_DELAY(x) ((x) << 0) 1147 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1148 1149 #define TA_CNTL_AUX 0x9508 1150 1151 #define DB_DEBUG 0x9830 1152 #define DB_DEBUG2 0x9834 1153 #define DB_DEBUG3 0x9838 1154 1155 #define CC_RB_BACKEND_DISABLE 0x98F4 1156 #define BACKEND_DISABLE(x) ((x) << 16) 1157 #define GB_ADDR_CONFIG 0x98F8 1158 #define NUM_PIPES(x) ((x) << 0) 1159 #define NUM_PIPES_MASK 0x00000007 1160 #define NUM_PIPES_SHIFT 0 1161 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1162 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1163 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1164 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1165 #define NUM_SHADER_ENGINES_MASK 0x00003000 1166 #define NUM_SHADER_ENGINES_SHIFT 12 1167 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1168 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1169 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1170 #define ROW_SIZE(x) ((x) << 28) 1171 #define ROW_SIZE_MASK 0x30000000 1172 #define ROW_SIZE_SHIFT 28 1173 1174 #define GB_TILE_MODE0 0x9910 1175 # define ARRAY_MODE(x) ((x) << 2) 1176 # define ARRAY_LINEAR_GENERAL 0 1177 # define ARRAY_LINEAR_ALIGNED 1 1178 # define ARRAY_1D_TILED_THIN1 2 1179 # define ARRAY_2D_TILED_THIN1 4 1180 # define ARRAY_PRT_TILED_THIN1 5 1181 # define ARRAY_PRT_2D_TILED_THIN1 6 1182 # define PIPE_CONFIG(x) ((x) << 6) 1183 # define ADDR_SURF_P2 0 1184 # define ADDR_SURF_P4_8x16 4 1185 # define ADDR_SURF_P4_16x16 5 1186 # define ADDR_SURF_P4_16x32 6 1187 # define ADDR_SURF_P4_32x32 7 1188 # define ADDR_SURF_P8_16x16_8x16 8 1189 # define ADDR_SURF_P8_16x32_8x16 9 1190 # define ADDR_SURF_P8_32x32_8x16 10 1191 # define ADDR_SURF_P8_16x32_16x16 11 1192 # define ADDR_SURF_P8_32x32_16x16 12 1193 # define ADDR_SURF_P8_32x32_16x32 13 1194 # define ADDR_SURF_P8_32x64_32x32 14 1195 # define ADDR_SURF_P16_32x32_8x16 16 1196 # define ADDR_SURF_P16_32x32_16x16 17 1197 # define TILE_SPLIT(x) ((x) << 11) 1198 # define ADDR_SURF_TILE_SPLIT_64B 0 1199 # define ADDR_SURF_TILE_SPLIT_128B 1 1200 # define ADDR_SURF_TILE_SPLIT_256B 2 1201 # define ADDR_SURF_TILE_SPLIT_512B 3 1202 # define ADDR_SURF_TILE_SPLIT_1KB 4 1203 # define ADDR_SURF_TILE_SPLIT_2KB 5 1204 # define ADDR_SURF_TILE_SPLIT_4KB 6 1205 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 1206 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1207 # define ADDR_SURF_THIN_MICRO_TILING 1 1208 # define ADDR_SURF_DEPTH_MICRO_TILING 2 1209 # define ADDR_SURF_ROTATED_MICRO_TILING 3 1210 # define SAMPLE_SPLIT(x) ((x) << 25) 1211 # define ADDR_SURF_SAMPLE_SPLIT_1 0 1212 # define ADDR_SURF_SAMPLE_SPLIT_2 1 1213 # define ADDR_SURF_SAMPLE_SPLIT_4 2 1214 # define ADDR_SURF_SAMPLE_SPLIT_8 3 1215 1216 #define GB_MACROTILE_MODE0 0x9990 1217 # define BANK_WIDTH(x) ((x) << 0) 1218 # define ADDR_SURF_BANK_WIDTH_1 0 1219 # define ADDR_SURF_BANK_WIDTH_2 1 1220 # define ADDR_SURF_BANK_WIDTH_4 2 1221 # define ADDR_SURF_BANK_WIDTH_8 3 1222 # define BANK_HEIGHT(x) ((x) << 2) 1223 # define ADDR_SURF_BANK_HEIGHT_1 0 1224 # define ADDR_SURF_BANK_HEIGHT_2 1 1225 # define ADDR_SURF_BANK_HEIGHT_4 2 1226 # define ADDR_SURF_BANK_HEIGHT_8 3 1227 # define MACRO_TILE_ASPECT(x) ((x) << 4) 1228 # define ADDR_SURF_MACRO_ASPECT_1 0 1229 # define ADDR_SURF_MACRO_ASPECT_2 1 1230 # define ADDR_SURF_MACRO_ASPECT_4 2 1231 # define ADDR_SURF_MACRO_ASPECT_8 3 1232 # define NUM_BANKS(x) ((x) << 6) 1233 # define ADDR_SURF_2_BANK 0 1234 # define ADDR_SURF_4_BANK 1 1235 # define ADDR_SURF_8_BANK 2 1236 # define ADDR_SURF_16_BANK 3 1237 1238 #define CB_HW_CONTROL 0x9A10 1239 1240 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 1241 #define BACKEND_DISABLE_MASK 0x00FF0000 1242 #define BACKEND_DISABLE_SHIFT 16 1243 1244 #define TCP_CHAN_STEER_LO 0xac0c 1245 #define TCP_CHAN_STEER_HI 0xac10 1246 1247 #define TC_CFG_L1_LOAD_POLICY0 0xAC68 1248 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 1249 #define TC_CFG_L1_STORE_POLICY 0xAC70 1250 #define TC_CFG_L2_LOAD_POLICY0 0xAC74 1251 #define TC_CFG_L2_LOAD_POLICY1 0xAC78 1252 #define TC_CFG_L2_STORE_POLICY0 0xAC7C 1253 #define TC_CFG_L2_STORE_POLICY1 0xAC80 1254 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 1255 #define TC_CFG_L1_VOLATILE 0xAC88 1256 #define TC_CFG_L2_VOLATILE 0xAC8C 1257 1258 #define CP_RB0_BASE 0xC100 1259 #define CP_RB0_CNTL 0xC104 1260 #define RB_BUFSZ(x) ((x) << 0) 1261 #define RB_BLKSZ(x) ((x) << 8) 1262 #define BUF_SWAP_32BIT (2 << 16) 1263 #define RB_NO_UPDATE (1 << 27) 1264 #define RB_RPTR_WR_ENA (1 << 31) 1265 1266 #define CP_RB0_RPTR_ADDR 0xC10C 1267 #define RB_RPTR_SWAP_32BIT (2 << 0) 1268 #define CP_RB0_RPTR_ADDR_HI 0xC110 1269 #define CP_RB0_WPTR 0xC114 1270 1271 #define CP_DEVICE_ID 0xC12C 1272 #define CP_ENDIAN_SWAP 0xC140 1273 #define CP_RB_VMID 0xC144 1274 1275 #define CP_PFP_UCODE_ADDR 0xC150 1276 #define CP_PFP_UCODE_DATA 0xC154 1277 #define CP_ME_RAM_RADDR 0xC158 1278 #define CP_ME_RAM_WADDR 0xC15C 1279 #define CP_ME_RAM_DATA 0xC160 1280 1281 #define CP_CE_UCODE_ADDR 0xC168 1282 #define CP_CE_UCODE_DATA 0xC16C 1283 #define CP_MEC_ME1_UCODE_ADDR 0xC170 1284 #define CP_MEC_ME1_UCODE_DATA 0xC174 1285 #define CP_MEC_ME2_UCODE_ADDR 0xC178 1286 #define CP_MEC_ME2_UCODE_DATA 0xC17C 1287 1288 #define CP_INT_CNTL_RING0 0xC1A8 1289 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1290 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1291 # define PRIV_INSTR_INT_ENABLE (1 << 22) 1292 # define PRIV_REG_INT_ENABLE (1 << 23) 1293 # define TIME_STAMP_INT_ENABLE (1 << 26) 1294 # define CP_RINGID2_INT_ENABLE (1 << 29) 1295 # define CP_RINGID1_INT_ENABLE (1 << 30) 1296 # define CP_RINGID0_INT_ENABLE (1 << 31) 1297 1298 #define CP_INT_STATUS_RING0 0xC1B4 1299 # define PRIV_INSTR_INT_STAT (1 << 22) 1300 # define PRIV_REG_INT_STAT (1 << 23) 1301 # define TIME_STAMP_INT_STAT (1 << 26) 1302 # define CP_RINGID2_INT_STAT (1 << 29) 1303 # define CP_RINGID1_INT_STAT (1 << 30) 1304 # define CP_RINGID0_INT_STAT (1 << 31) 1305 1306 #define CP_MEM_SLP_CNTL 0xC1E4 1307 # define CP_MEM_LS_EN (1 << 0) 1308 1309 #define CP_CPF_DEBUG 0xC200 1310 1311 #define CP_PQ_WPTR_POLL_CNTL 0xC20C 1312 #define WPTR_POLL_EN (1 << 31) 1313 1314 #define CP_ME1_PIPE0_INT_CNTL 0xC214 1315 #define CP_ME1_PIPE1_INT_CNTL 0xC218 1316 #define CP_ME1_PIPE2_INT_CNTL 0xC21C 1317 #define CP_ME1_PIPE3_INT_CNTL 0xC220 1318 #define CP_ME2_PIPE0_INT_CNTL 0xC224 1319 #define CP_ME2_PIPE1_INT_CNTL 0xC228 1320 #define CP_ME2_PIPE2_INT_CNTL 0xC22C 1321 #define CP_ME2_PIPE3_INT_CNTL 0xC230 1322 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 1323 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 1324 # define PRIV_REG_INT_ENABLE (1 << 23) 1325 # define TIME_STAMP_INT_ENABLE (1 << 26) 1326 # define GENERIC2_INT_ENABLE (1 << 29) 1327 # define GENERIC1_INT_ENABLE (1 << 30) 1328 # define GENERIC0_INT_ENABLE (1 << 31) 1329 #define CP_ME1_PIPE0_INT_STATUS 0xC214 1330 #define CP_ME1_PIPE1_INT_STATUS 0xC218 1331 #define CP_ME1_PIPE2_INT_STATUS 0xC21C 1332 #define CP_ME1_PIPE3_INT_STATUS 0xC220 1333 #define CP_ME2_PIPE0_INT_STATUS 0xC224 1334 #define CP_ME2_PIPE1_INT_STATUS 0xC228 1335 #define CP_ME2_PIPE2_INT_STATUS 0xC22C 1336 #define CP_ME2_PIPE3_INT_STATUS 0xC230 1337 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 1338 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 1339 # define PRIV_REG_INT_STATUS (1 << 23) 1340 # define TIME_STAMP_INT_STATUS (1 << 26) 1341 # define GENERIC2_INT_STATUS (1 << 29) 1342 # define GENERIC1_INT_STATUS (1 << 30) 1343 # define GENERIC0_INT_STATUS (1 << 31) 1344 1345 #define CP_MAX_CONTEXT 0xC2B8 1346 1347 #define CP_RB0_BASE_HI 0xC2C4 1348 1349 #define RLC_CNTL 0xC300 1350 # define RLC_ENABLE (1 << 0) 1351 1352 #define RLC_MC_CNTL 0xC30C 1353 1354 #define RLC_MEM_SLP_CNTL 0xC318 1355 # define RLC_MEM_LS_EN (1 << 0) 1356 1357 #define RLC_LB_CNTR_MAX 0xC348 1358 1359 #define RLC_LB_CNTL 0xC364 1360 # define LOAD_BALANCE_ENABLE (1 << 0) 1361 1362 #define RLC_LB_CNTR_INIT 0xC36C 1363 1364 #define RLC_SAVE_AND_RESTORE_BASE 0xC374 1365 #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 1366 #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 1367 #define RLC_PG_DELAY_2 0xC37C 1368 1369 #define RLC_GPM_UCODE_ADDR 0xC388 1370 #define RLC_GPM_UCODE_DATA 0xC38C 1371 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 1372 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 1373 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 1374 #define RLC_UCODE_CNTL 0xC39C 1375 1376 #define RLC_GPM_STAT 0xC400 1377 # define RLC_GPM_BUSY (1 << 0) 1378 # define GFX_POWER_STATUS (1 << 1) 1379 # define GFX_CLOCK_STATUS (1 << 2) 1380 1381 #define RLC_PG_CNTL 0xC40C 1382 # define GFX_PG_ENABLE (1 << 0) 1383 # define GFX_PG_SRC (1 << 1) 1384 # define DYN_PER_CU_PG_ENABLE (1 << 2) 1385 # define STATIC_PER_CU_PG_ENABLE (1 << 3) 1386 # define DISABLE_GDS_PG (1 << 13) 1387 # define DISABLE_CP_PG (1 << 15) 1388 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 1389 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 1390 1391 #define RLC_CGTT_MGCG_OVERRIDE 0xC420 1392 #define RLC_CGCG_CGLS_CTRL 0xC424 1393 # define CGCG_EN (1 << 0) 1394 # define CGLS_EN (1 << 1) 1395 1396 #define RLC_PG_DELAY 0xC434 1397 1398 #define RLC_LB_INIT_CU_MASK 0xC43C 1399 1400 #define RLC_LB_PARAMS 0xC444 1401 1402 #define RLC_PG_AO_CU_MASK 0xC44C 1403 1404 #define RLC_MAX_PG_CU 0xC450 1405 # define MAX_PU_CU(x) ((x) << 0) 1406 # define MAX_PU_CU_MASK (0xff << 0) 1407 #define RLC_AUTO_PG_CTRL 0xC454 1408 # define AUTO_PG_EN (1 << 0) 1409 # define GRBM_REG_SGIT(x) ((x) << 3) 1410 # define GRBM_REG_SGIT_MASK (0xffff << 3) 1411 1412 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 1413 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 1414 #define RLC_SERDES_WR_CTRL 0xC47C 1415 #define BPM_ADDR(x) ((x) << 0) 1416 #define BPM_ADDR_MASK (0xff << 0) 1417 #define CGLS_ENABLE (1 << 16) 1418 #define CGCG_OVERRIDE_0 (1 << 20) 1419 #define MGCG_OVERRIDE_0 (1 << 22) 1420 #define MGCG_OVERRIDE_1 (1 << 23) 1421 1422 #define RLC_SERDES_CU_MASTER_BUSY 0xC484 1423 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 1424 # define SE_MASTER_BUSY_MASK 0x0000ffff 1425 # define GC_MASTER_BUSY (1 << 16) 1426 # define TC0_MASTER_BUSY (1 << 17) 1427 # define TC1_MASTER_BUSY (1 << 18) 1428 1429 #define RLC_GPM_SCRATCH_ADDR 0xC4B0 1430 #define RLC_GPM_SCRATCH_DATA 0xC4B4 1431 1432 #define RLC_GPR_REG2 0xC4E8 1433 #define REQ 0x00000001 1434 #define MESSAGE(x) ((x) << 1) 1435 #define MESSAGE_MASK 0x0000001e 1436 #define MSG_ENTER_RLC_SAFE_MODE 1 1437 #define MSG_EXIT_RLC_SAFE_MODE 0 1438 1439 #define CP_HPD_EOP_BASE_ADDR 0xC904 1440 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1441 #define CP_HPD_EOP_VMID 0xC90C 1442 #define CP_HPD_EOP_CONTROL 0xC910 1443 #define EOP_SIZE(x) ((x) << 0) 1444 #define EOP_SIZE_MASK (0x3f << 0) 1445 #define CP_MQD_BASE_ADDR 0xC914 1446 #define CP_MQD_BASE_ADDR_HI 0xC918 1447 #define CP_HQD_ACTIVE 0xC91C 1448 #define CP_HQD_VMID 0xC920 1449 1450 #define CP_HQD_PQ_BASE 0xC934 1451 #define CP_HQD_PQ_BASE_HI 0xC938 1452 #define CP_HQD_PQ_RPTR 0xC93C 1453 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 1454 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 1455 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 1456 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 1457 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 1458 #define DOORBELL_OFFSET(x) ((x) << 2) 1459 #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 1460 #define DOORBELL_SOURCE (1 << 28) 1461 #define DOORBELL_SCHD_HIT (1 << 29) 1462 #define DOORBELL_EN (1 << 30) 1463 #define DOORBELL_HIT (1 << 31) 1464 #define CP_HQD_PQ_WPTR 0xC954 1465 #define CP_HQD_PQ_CONTROL 0xC958 1466 #define QUEUE_SIZE(x) ((x) << 0) 1467 #define QUEUE_SIZE_MASK (0x3f << 0) 1468 #define RPTR_BLOCK_SIZE(x) ((x) << 8) 1469 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 1470 #define PQ_VOLATILE (1 << 26) 1471 #define NO_UPDATE_RPTR (1 << 27) 1472 #define UNORD_DISPATCH (1 << 28) 1473 #define ROQ_PQ_IB_FLIP (1 << 29) 1474 #define PRIV_STATE (1 << 30) 1475 #define KMD_QUEUE (1 << 31) 1476 1477 #define CP_HQD_DEQUEUE_REQUEST 0xC974 1478 1479 #define CP_MQD_CONTROL 0xC99C 1480 #define MQD_VMID(x) ((x) << 0) 1481 #define MQD_VMID_MASK (0xf << 0) 1482 1483 #define DB_RENDER_CONTROL 0x28000 1484 1485 #define PA_SC_RASTER_CONFIG 0x28350 1486 # define RASTER_CONFIG_RB_MAP_0 0 1487 # define RASTER_CONFIG_RB_MAP_1 1 1488 # define RASTER_CONFIG_RB_MAP_2 2 1489 # define RASTER_CONFIG_RB_MAP_3 3 1490 #define PKR_MAP(x) ((x) << 8) 1491 1492 #define VGT_EVENT_INITIATOR 0x28a90 1493 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1494 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1495 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1496 # define CACHE_FLUSH_TS (4 << 0) 1497 # define CACHE_FLUSH (6 << 0) 1498 # define CS_PARTIAL_FLUSH (7 << 0) 1499 # define VGT_STREAMOUT_RESET (10 << 0) 1500 # define END_OF_PIPE_INCR_DE (11 << 0) 1501 # define END_OF_PIPE_IB_END (12 << 0) 1502 # define RST_PIX_CNT (13 << 0) 1503 # define VS_PARTIAL_FLUSH (15 << 0) 1504 # define PS_PARTIAL_FLUSH (16 << 0) 1505 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1506 # define ZPASS_DONE (21 << 0) 1507 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1508 # define PERFCOUNTER_START (23 << 0) 1509 # define PERFCOUNTER_STOP (24 << 0) 1510 # define PIPELINESTAT_START (25 << 0) 1511 # define PIPELINESTAT_STOP (26 << 0) 1512 # define PERFCOUNTER_SAMPLE (27 << 0) 1513 # define SAMPLE_PIPELINESTAT (30 << 0) 1514 # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 1515 # define SAMPLE_STREAMOUTSTATS (32 << 0) 1516 # define RESET_VTX_CNT (33 << 0) 1517 # define VGT_FLUSH (36 << 0) 1518 # define BOTTOM_OF_PIPE_TS (40 << 0) 1519 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1520 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1521 # define FLUSH_AND_INV_DB_META (44 << 0) 1522 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1523 # define FLUSH_AND_INV_CB_META (46 << 0) 1524 # define CS_DONE (47 << 0) 1525 # define PS_DONE (48 << 0) 1526 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1527 # define THREAD_TRACE_START (51 << 0) 1528 # define THREAD_TRACE_STOP (52 << 0) 1529 # define THREAD_TRACE_FLUSH (54 << 0) 1530 # define THREAD_TRACE_FINISH (55 << 0) 1531 # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 1532 # define PIXEL_PIPE_STAT_DUMP (57 << 0) 1533 # define PIXEL_PIPE_STAT_RESET (58 << 0) 1534 1535 #define SCRATCH_REG0 0x30100 1536 #define SCRATCH_REG1 0x30104 1537 #define SCRATCH_REG2 0x30108 1538 #define SCRATCH_REG3 0x3010C 1539 #define SCRATCH_REG4 0x30110 1540 #define SCRATCH_REG5 0x30114 1541 #define SCRATCH_REG6 0x30118 1542 #define SCRATCH_REG7 0x3011C 1543 1544 #define SCRATCH_UMSK 0x30140 1545 #define SCRATCH_ADDR 0x30144 1546 1547 #define CP_SEM_WAIT_TIMER 0x301BC 1548 1549 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 1550 1551 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 1552 1553 #define GRBM_GFX_INDEX 0x30800 1554 #define INSTANCE_INDEX(x) ((x) << 0) 1555 #define SH_INDEX(x) ((x) << 8) 1556 #define SE_INDEX(x) ((x) << 16) 1557 #define SH_BROADCAST_WRITES (1 << 29) 1558 #define INSTANCE_BROADCAST_WRITES (1 << 30) 1559 #define SE_BROADCAST_WRITES (1 << 31) 1560 1561 #define VGT_ESGS_RING_SIZE 0x30900 1562 #define VGT_GSVS_RING_SIZE 0x30904 1563 #define VGT_PRIMITIVE_TYPE 0x30908 1564 #define VGT_INDEX_TYPE 0x3090C 1565 1566 #define VGT_NUM_INDICES 0x30930 1567 #define VGT_NUM_INSTANCES 0x30934 1568 #define VGT_TF_RING_SIZE 0x30938 1569 #define VGT_HS_OFFCHIP_PARAM 0x3093C 1570 #define VGT_TF_MEMORY_BASE 0x30940 1571 1572 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 1573 #define PA_SC_LINE_STIPPLE_STATE 0x30a04 1574 1575 #define SQC_CACHES 0x30d20 1576 1577 #define CP_PERFMON_CNTL 0x36020 1578 1579 #define CGTS_SM_CTRL_REG 0x3c000 1580 #define SM_MODE(x) ((x) << 17) 1581 #define SM_MODE_MASK (0x7 << 17) 1582 #define SM_MODE_ENABLE (1 << 20) 1583 #define CGTS_OVERRIDE (1 << 21) 1584 #define CGTS_LS_OVERRIDE (1 << 22) 1585 #define ON_MONITOR_ADD_EN (1 << 23) 1586 #define ON_MONITOR_ADD(x) ((x) << 24) 1587 #define ON_MONITOR_ADD_MASK (0xff << 24) 1588 1589 #define CGTS_TCC_DISABLE 0x3c00c 1590 #define CGTS_USER_TCC_DISABLE 0x3c010 1591 #define TCC_DISABLE_MASK 0xFFFF0000 1592 #define TCC_DISABLE_SHIFT 16 1593 1594 #define CB_CGTT_SCLK_CTRL 0x3c2a0 1595 1596 /* 1597 * PM4 1598 */ 1599 #define PACKET_TYPE0 0 1600 #define PACKET_TYPE1 1 1601 #define PACKET_TYPE2 2 1602 #define PACKET_TYPE3 3 1603 1604 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1605 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1606 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1607 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1608 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1609 (((reg) >> 2) & 0xFFFF) | \ 1610 ((n) & 0x3FFF) << 16) 1611 #define CP_PACKET2 0x80000000 1612 #define PACKET2_PAD_SHIFT 0 1613 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1614 1615 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1616 1617 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1618 (((op) & 0xFF) << 8) | \ 1619 ((n) & 0x3FFF) << 16) 1620 1621 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1622 1623 /* Packet 3 types */ 1624 #define PACKET3_NOP 0x10 1625 #define PACKET3_SET_BASE 0x11 1626 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1627 #define CE_PARTITION_BASE 3 1628 #define PACKET3_CLEAR_STATE 0x12 1629 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1630 #define PACKET3_DISPATCH_DIRECT 0x15 1631 #define PACKET3_DISPATCH_INDIRECT 0x16 1632 #define PACKET3_ATOMIC_GDS 0x1D 1633 #define PACKET3_ATOMIC_MEM 0x1E 1634 #define PACKET3_OCCLUSION_QUERY 0x1F 1635 #define PACKET3_SET_PREDICATION 0x20 1636 #define PACKET3_REG_RMW 0x21 1637 #define PACKET3_COND_EXEC 0x22 1638 #define PACKET3_PRED_EXEC 0x23 1639 #define PACKET3_DRAW_INDIRECT 0x24 1640 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1641 #define PACKET3_INDEX_BASE 0x26 1642 #define PACKET3_DRAW_INDEX_2 0x27 1643 #define PACKET3_CONTEXT_CONTROL 0x28 1644 #define PACKET3_INDEX_TYPE 0x2A 1645 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1646 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1647 #define PACKET3_NUM_INSTANCES 0x2F 1648 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1649 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1650 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1651 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1652 #define PACKET3_DRAW_PREAMBLE 0x36 1653 #define PACKET3_WRITE_DATA 0x37 1654 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1655 /* 0 - register 1656 * 1 - memory (sync - via GRBM) 1657 * 2 - gl2 1658 * 3 - gds 1659 * 4 - reserved 1660 * 5 - memory (async - direct) 1661 */ 1662 #define WR_ONE_ADDR (1 << 16) 1663 #define WR_CONFIRM (1 << 20) 1664 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 1665 /* 0 - LRU 1666 * 1 - Stream 1667 */ 1668 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1669 /* 0 - me 1670 * 1 - pfp 1671 * 2 - ce 1672 */ 1673 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1674 #define PACKET3_MEM_SEMAPHORE 0x39 1675 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 1676 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 1677 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 1678 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1679 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1680 #define PACKET3_COPY_DW 0x3B 1681 #define PACKET3_WAIT_REG_MEM 0x3C 1682 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1683 /* 0 - always 1684 * 1 - < 1685 * 2 - <= 1686 * 3 - == 1687 * 4 - != 1688 * 5 - >= 1689 * 6 - > 1690 */ 1691 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1692 /* 0 - reg 1693 * 1 - mem 1694 */ 1695 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 1696 /* 0 - wait_reg_mem 1697 * 1 - wr_wait_wr_reg 1698 */ 1699 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1700 /* 0 - me 1701 * 1 - pfp 1702 */ 1703 #define PACKET3_INDIRECT_BUFFER 0x3F 1704 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 1705 #define INDIRECT_BUFFER_VALID (1 << 23) 1706 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 1707 /* 0 - LRU 1708 * 1 - Stream 1709 * 2 - Bypass 1710 */ 1711 #define PACKET3_COPY_DATA 0x40 1712 #define PACKET3_PFP_SYNC_ME 0x42 1713 #define PACKET3_SURFACE_SYNC 0x43 1714 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1715 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1716 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1717 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1718 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1719 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1720 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1721 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1722 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1723 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1724 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1725 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1726 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1727 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1728 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1729 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1730 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1731 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1732 # define PACKET3_CB_ACTION_ENA (1 << 25) 1733 # define PACKET3_DB_ACTION_ENA (1 << 26) 1734 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1735 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1736 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1737 #define PACKET3_COND_WRITE 0x45 1738 #define PACKET3_EVENT_WRITE 0x46 1739 #define EVENT_TYPE(x) ((x) << 0) 1740 #define EVENT_INDEX(x) ((x) << 8) 1741 /* 0 - any non-TS event 1742 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1743 * 2 - SAMPLE_PIPELINESTAT 1744 * 3 - SAMPLE_STREAMOUTSTAT* 1745 * 4 - *S_PARTIAL_FLUSH 1746 * 5 - EOP events 1747 * 6 - EOS events 1748 */ 1749 #define PACKET3_EVENT_WRITE_EOP 0x47 1750 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1751 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1752 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1753 #define EOP_TCL1_ACTION_EN (1 << 16) 1754 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1755 #define EOP_TCL2_VOLATILE (1 << 24) 1756 #define EOP_CACHE_POLICY(x) ((x) << 25) 1757 /* 0 - LRU 1758 * 1 - Stream 1759 * 2 - Bypass 1760 */ 1761 #define DATA_SEL(x) ((x) << 29) 1762 /* 0 - discard 1763 * 1 - send low 32bit data 1764 * 2 - send 64bit data 1765 * 3 - send 64bit GPU counter value 1766 * 4 - send 64bit sys counter value 1767 */ 1768 #define INT_SEL(x) ((x) << 24) 1769 /* 0 - none 1770 * 1 - interrupt only (DATA_SEL = 0) 1771 * 2 - interrupt when data write is confirmed 1772 */ 1773 #define DST_SEL(x) ((x) << 16) 1774 /* 0 - MC 1775 * 1 - TC/L2 1776 */ 1777 #define PACKET3_EVENT_WRITE_EOS 0x48 1778 #define PACKET3_RELEASE_MEM 0x49 1779 #define PACKET3_PREAMBLE_CNTL 0x4A 1780 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1781 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1782 #define PACKET3_DMA_DATA 0x50 1783 /* 1. header 1784 * 2. CONTROL 1785 * 3. SRC_ADDR_LO or DATA [31:0] 1786 * 4. SRC_ADDR_HI [31:0] 1787 * 5. DST_ADDR_LO [31:0] 1788 * 6. DST_ADDR_HI [7:0] 1789 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 1790 */ 1791 /* CONTROL */ 1792 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 1793 /* 0 - ME 1794 * 1 - PFP 1795 */ 1796 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 1797 /* 0 - LRU 1798 * 1 - Stream 1799 * 2 - Bypass 1800 */ 1801 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 1802 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 1803 /* 0 - DST_ADDR using DAS 1804 * 1 - GDS 1805 * 3 - DST_ADDR using L2 1806 */ 1807 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 1808 /* 0 - LRU 1809 * 1 - Stream 1810 * 2 - Bypass 1811 */ 1812 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 1813 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 1814 /* 0 - SRC_ADDR using SAS 1815 * 1 - GDS 1816 * 2 - DATA 1817 * 3 - SRC_ADDR using L2 1818 */ 1819 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 1820 /* COMMAND */ 1821 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 1822 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 1823 /* 0 - none 1824 * 1 - 8 in 16 1825 * 2 - 8 in 32 1826 * 3 - 8 in 64 1827 */ 1828 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 1829 /* 0 - none 1830 * 1 - 8 in 16 1831 * 2 - 8 in 32 1832 * 3 - 8 in 64 1833 */ 1834 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 1835 /* 0 - memory 1836 * 1 - register 1837 */ 1838 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 1839 /* 0 - memory 1840 * 1 - register 1841 */ 1842 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 1843 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 1844 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 1845 #define PACKET3_AQUIRE_MEM 0x58 1846 #define PACKET3_REWIND 0x59 1847 #define PACKET3_LOAD_UCONFIG_REG 0x5E 1848 #define PACKET3_LOAD_SH_REG 0x5F 1849 #define PACKET3_LOAD_CONFIG_REG 0x60 1850 #define PACKET3_LOAD_CONTEXT_REG 0x61 1851 #define PACKET3_SET_CONFIG_REG 0x68 1852 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1853 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1854 #define PACKET3_SET_CONTEXT_REG 0x69 1855 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1856 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1857 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1858 #define PACKET3_SET_SH_REG 0x76 1859 #define PACKET3_SET_SH_REG_START 0x0000b000 1860 #define PACKET3_SET_SH_REG_END 0x0000c000 1861 #define PACKET3_SET_SH_REG_OFFSET 0x77 1862 #define PACKET3_SET_QUEUE_REG 0x78 1863 #define PACKET3_SET_UCONFIG_REG 0x79 1864 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 1865 #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1866 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1867 #define PACKET3_SCRATCH_RAM_READ 0x7E 1868 #define PACKET3_LOAD_CONST_RAM 0x80 1869 #define PACKET3_WRITE_CONST_RAM 0x81 1870 #define PACKET3_DUMP_CONST_RAM 0x83 1871 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1872 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1873 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1874 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1875 #define PACKET3_SWITCH_BUFFER 0x8B 1876 1877 /* SDMA - first instance at 0xd000, second at 0xd800 */ 1878 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 1879 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 1880 1881 #define SDMA0_UCODE_ADDR 0xD000 1882 #define SDMA0_UCODE_DATA 0xD004 1883 #define SDMA0_POWER_CNTL 0xD008 1884 #define SDMA0_CLK_CTRL 0xD00C 1885 1886 #define SDMA0_CNTL 0xD010 1887 # define TRAP_ENABLE (1 << 0) 1888 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1889 # define SEM_WAIT_INT_ENABLE (1 << 2) 1890 # define DATA_SWAP_ENABLE (1 << 3) 1891 # define FENCE_SWAP_ENABLE (1 << 4) 1892 # define AUTO_CTXSW_ENABLE (1 << 18) 1893 # define CTXEMPTY_INT_ENABLE (1 << 28) 1894 1895 #define SDMA0_TILING_CONFIG 0xD018 1896 1897 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 1898 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 1899 1900 #define SDMA0_STATUS_REG 0xd034 1901 # define SDMA_IDLE (1 << 0) 1902 1903 #define SDMA0_ME_CNTL 0xD048 1904 # define SDMA_HALT (1 << 0) 1905 1906 #define SDMA0_GFX_RB_CNTL 0xD200 1907 # define SDMA_RB_ENABLE (1 << 0) 1908 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1909 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1910 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1911 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1912 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1913 #define SDMA0_GFX_RB_BASE 0xD204 1914 #define SDMA0_GFX_RB_BASE_HI 0xD208 1915 #define SDMA0_GFX_RB_RPTR 0xD20C 1916 #define SDMA0_GFX_RB_WPTR 0xD210 1917 1918 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 1919 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 1920 #define SDMA0_GFX_IB_CNTL 0xD228 1921 # define SDMA_IB_ENABLE (1 << 0) 1922 # define SDMA_IB_SWAP_ENABLE (1 << 4) 1923 # define SDMA_SWITCH_INSIDE_IB (1 << 8) 1924 # define SDMA_CMD_VMID(x) ((x) << 16) 1925 1926 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 1927 #define SDMA0_GFX_APE1_CNTL 0xD2A0 1928 1929 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 1930 (((sub_op) & 0xFF) << 8) | \ 1931 (((op) & 0xFF) << 0)) 1932 /* sDMA opcodes */ 1933 #define SDMA_OPCODE_NOP 0 1934 #define SDMA_OPCODE_COPY 1 1935 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 1936 # define SDMA_COPY_SUB_OPCODE_TILED 1 1937 # define SDMA_COPY_SUB_OPCODE_SOA 3 1938 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 1939 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 1940 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 1941 #define SDMA_OPCODE_WRITE 2 1942 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 1943 # define SDMA_WRTIE_SUB_OPCODE_TILED 1 1944 #define SDMA_OPCODE_INDIRECT_BUFFER 4 1945 #define SDMA_OPCODE_FENCE 5 1946 #define SDMA_OPCODE_TRAP 6 1947 #define SDMA_OPCODE_SEMAPHORE 7 1948 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 1949 /* 0 - increment 1950 * 1 - write 1 1951 */ 1952 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 1953 /* 0 - wait 1954 * 1 - signal 1955 */ 1956 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 1957 /* mailbox */ 1958 #define SDMA_OPCODE_POLL_REG_MEM 8 1959 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 1960 /* 0 - wait_reg_mem 1961 * 1 - wr_wait_wr_reg 1962 */ 1963 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 1964 /* 0 - always 1965 * 1 - < 1966 * 2 - <= 1967 * 3 - == 1968 * 4 - != 1969 * 5 - >= 1970 * 6 - > 1971 */ 1972 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 1973 /* 0 = register 1974 * 1 = memory 1975 */ 1976 #define SDMA_OPCODE_COND_EXEC 9 1977 #define SDMA_OPCODE_CONSTANT_FILL 11 1978 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 1979 /* 0 = byte fill 1980 * 2 = DW fill 1981 */ 1982 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 1983 #define SDMA_OPCODE_TIMESTAMP 13 1984 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 1985 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 1986 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 1987 #define SDMA_OPCODE_SRBM_WRITE 14 1988 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 1989 /* byte mask */ 1990 1991 /* UVD */ 1992 1993 #define UVD_UDEC_ADDR_CONFIG 0xef4c 1994 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1995 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1996 1997 #define UVD_LMI_EXT40_ADDR 0xf498 1998 #define UVD_LMI_ADDR_EXT 0xf594 1999 #define UVD_VCPU_CACHE_OFFSET0 0xf608 2000 #define UVD_VCPU_CACHE_SIZE0 0xf60c 2001 #define UVD_VCPU_CACHE_OFFSET1 0xf610 2002 #define UVD_VCPU_CACHE_SIZE1 0xf614 2003 #define UVD_VCPU_CACHE_OFFSET2 0xf618 2004 #define UVD_VCPU_CACHE_SIZE2 0xf61c 2005 2006 #define UVD_RBC_RB_RPTR 0xf690 2007 #define UVD_RBC_RB_WPTR 0xf694 2008 2009 #define UVD_CGC_CTRL 0xF4B0 2010 # define DCM (1 << 0) 2011 # define CG_DT(x) ((x) << 2) 2012 # define CG_DT_MASK (0xf << 2) 2013 # define CLK_OD(x) ((x) << 6) 2014 # define CLK_OD_MASK (0x1f << 6) 2015 2016 /* UVD clocks */ 2017 2018 #define CG_DCLK_CNTL 0xC050009C 2019 # define DCLK_DIVIDER_MASK 0x7f 2020 # define DCLK_DIR_CNTL_EN (1 << 8) 2021 #define CG_DCLK_STATUS 0xC05000A0 2022 # define DCLK_STATUS (1 << 0) 2023 #define CG_VCLK_CNTL 0xC05000A4 2024 #define CG_VCLK_STATUS 0xC05000A8 2025 2026 /* UVD CTX indirect */ 2027 #define UVD_CGC_MEM_CTRL 0xC0 2028 2029 /* VCE */ 2030 2031 #define VCE_VCPU_CACHE_OFFSET0 0x20024 2032 #define VCE_VCPU_CACHE_SIZE0 0x20028 2033 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 2034 #define VCE_VCPU_CACHE_SIZE1 0x20030 2035 #define VCE_VCPU_CACHE_OFFSET2 0x20034 2036 #define VCE_VCPU_CACHE_SIZE2 0x20038 2037 #define VCE_RB_RPTR2 0x20178 2038 #define VCE_RB_WPTR2 0x2017c 2039 #define VCE_RB_RPTR 0x2018c 2040 #define VCE_RB_WPTR 0x20190 2041 #define VCE_CLOCK_GATING_A 0x202f8 2042 # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0) 2043 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) 2044 # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4) 2045 # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4) 2046 # define CGC_UENC_WAIT_AWAKE (1 << 18) 2047 #define VCE_CLOCK_GATING_B 0x202fc 2048 #define VCE_CGTT_CLK_OVERRIDE 0x207a0 2049 #define VCE_UENC_CLOCK_GATING 0x207bc 2050 # define CLOCK_ON_DELAY_MASK (0xf << 0) 2051 # define CLOCK_ON_DELAY(x) ((x) << 0) 2052 # define CLOCK_OFF_DELAY_MASK (0xff << 4) 2053 # define CLOCK_OFF_DELAY(x) ((x) << 4) 2054 #define VCE_UENC_REG_CLOCK_GATING 0x207c0 2055 #define VCE_SYS_INT_EN 0x21300 2056 # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) 2057 #define VCE_LMI_CTRL2 0x21474 2058 #define VCE_LMI_CTRL 0x21498 2059 #define VCE_LMI_VM_CTRL 0x214a0 2060 #define VCE_LMI_SWAP_CNTL 0x214b4 2061 #define VCE_LMI_SWAP_CNTL1 0x214b8 2062 #define VCE_LMI_CACHE_CTRL 0x214f4 2063 2064 #define VCE_CMD_NO_OP 0x00000000 2065 #define VCE_CMD_END 0x00000001 2066 #define VCE_CMD_IB 0x00000002 2067 #define VCE_CMD_FENCE 0x00000003 2068 #define VCE_CMD_TRAP 0x00000004 2069 #define VCE_CMD_IB_AUTO 0x00000005 2070 #define VCE_CMD_SEMAPHORE 0x00000006 2071 2072 #endif 2073