1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef CIK_H 25 #define CIK_H 26 27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28 29 #define CIK_RB_BITMAP_WIDTH_PER_SH 2 30 31 /* DIDT IND registers */ 32 #define DIDT_SQ_CTRL0 0x0 33 # define DIDT_CTRL_EN (1 << 0) 34 #define DIDT_DB_CTRL0 0x20 35 #define DIDT_TD_CTRL0 0x40 36 #define DIDT_TCP_CTRL0 0x60 37 38 /* SMC IND registers */ 39 #define DPM_TABLE_475 0x3F768 40 # define SamuBootLevel(x) ((x) << 0) 41 # define SamuBootLevel_MASK 0x000000ff 42 # define SamuBootLevel_SHIFT 0 43 # define AcpBootLevel(x) ((x) << 8) 44 # define AcpBootLevel_MASK 0x0000ff00 45 # define AcpBootLevel_SHIFT 8 46 # define VceBootLevel(x) ((x) << 16) 47 # define VceBootLevel_MASK 0x00ff0000 48 # define VceBootLevel_SHIFT 16 49 # define UvdBootLevel(x) ((x) << 24) 50 # define UvdBootLevel_MASK 0xff000000 51 # define UvdBootLevel_SHIFT 24 52 53 #define FIRMWARE_FLAGS 0x3F800 54 # define INTERRUPTS_ENABLED (1 << 0) 55 56 #define NB_DPM_CONFIG_1 0x3F9E8 57 # define Dpm0PgNbPsLo(x) ((x) << 0) 58 # define Dpm0PgNbPsLo_MASK 0x000000ff 59 # define Dpm0PgNbPsLo_SHIFT 0 60 # define Dpm0PgNbPsHi(x) ((x) << 8) 61 # define Dpm0PgNbPsHi_MASK 0x0000ff00 62 # define Dpm0PgNbPsHi_SHIFT 8 63 # define DpmXNbPsLo(x) ((x) << 16) 64 # define DpmXNbPsLo_MASK 0x00ff0000 65 # define DpmXNbPsLo_SHIFT 16 66 # define DpmXNbPsHi(x) ((x) << 24) 67 # define DpmXNbPsHi_MASK 0xff000000 68 # define DpmXNbPsHi_SHIFT 24 69 70 #define SMC_SYSCON_RESET_CNTL 0x80000000 71 # define RST_REG (1 << 0) 72 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 73 # define CK_DISABLE (1 << 0) 74 # define CKEN (1 << 24) 75 76 #define SMC_SYSCON_MISC_CNTL 0x80000010 77 78 #define SMC_SYSCON_MSG_ARG_0 0x80000068 79 80 #define SMC_PC_C 0x80000370 81 82 #define SMC_SCRATCH9 0x80000424 83 84 #define RCU_UC_EVENTS 0xC0000004 85 # define BOOT_SEQ_DONE (1 << 7) 86 87 #define GENERAL_PWRMGT 0xC0200000 88 # define GLOBAL_PWRMGT_EN (1 << 0) 89 # define STATIC_PM_EN (1 << 1) 90 # define THERMAL_PROTECTION_DIS (1 << 2) 91 # define THERMAL_PROTECTION_TYPE (1 << 3) 92 # define SW_SMIO_INDEX(x) ((x) << 6) 93 # define SW_SMIO_INDEX_MASK (1 << 6) 94 # define SW_SMIO_INDEX_SHIFT 6 95 # define VOLT_PWRMGT_EN (1 << 10) 96 # define GPU_COUNTER_CLK (1 << 15) 97 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 98 99 #define CNB_PWRMGT_CNTL 0xC0200004 100 # define GNB_SLOW_MODE(x) ((x) << 0) 101 # define GNB_SLOW_MODE_MASK (3 << 0) 102 # define GNB_SLOW_MODE_SHIFT 0 103 # define GNB_SLOW (1 << 2) 104 # define FORCE_NB_PS1 (1 << 3) 105 # define DPM_ENABLED (1 << 4) 106 107 #define SCLK_PWRMGT_CNTL 0xC0200008 108 # define SCLK_PWRMGT_OFF (1 << 0) 109 # define RESET_BUSY_CNT (1 << 4) 110 # define RESET_SCLK_CNT (1 << 5) 111 # define DYNAMIC_PM_EN (1 << 21) 112 113 #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 114 # define CURRENT_STATE_MASK (0xf << 4) 115 # define CURRENT_STATE_SHIFT 4 116 # define CURR_MCLK_INDEX_MASK (0xf << 8) 117 # define CURR_MCLK_INDEX_SHIFT 8 118 # define CURR_SCLK_INDEX_MASK (0x1f << 16) 119 # define CURR_SCLK_INDEX_SHIFT 16 120 121 #define CG_SSP 0xC0200044 122 # define SST(x) ((x) << 0) 123 # define SST_MASK (0xffff << 0) 124 # define SSTU(x) ((x) << 16) 125 # define SSTU_MASK (0xf << 16) 126 127 #define CG_DISPLAY_GAP_CNTL 0xC0200060 128 # define DISP_GAP(x) ((x) << 0) 129 # define DISP_GAP_MASK (3 << 0) 130 # define VBI_TIMER_COUNT(x) ((x) << 4) 131 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 132 # define VBI_TIMER_UNIT(x) ((x) << 20) 133 # define VBI_TIMER_UNIT_MASK (7 << 20) 134 # define DISP_GAP_MCHG(x) ((x) << 24) 135 # define DISP_GAP_MCHG_MASK (3 << 24) 136 137 #define SMU_VOLTAGE_STATUS 0xC0200094 138 # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 139 # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 140 141 #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 142 # define CURR_PCIE_INDEX_MASK (0xf << 24) 143 # define CURR_PCIE_INDEX_SHIFT 24 144 145 #define CG_ULV_PARAMETER 0xC0200158 146 147 #define CG_FTV_0 0xC02001A8 148 #define CG_FTV_1 0xC02001AC 149 #define CG_FTV_2 0xC02001B0 150 #define CG_FTV_3 0xC02001B4 151 #define CG_FTV_4 0xC02001B8 152 #define CG_FTV_5 0xC02001BC 153 #define CG_FTV_6 0xC02001C0 154 #define CG_FTV_7 0xC02001C4 155 156 #define CG_DISPLAY_GAP_CNTL2 0xC0200230 157 158 #define LCAC_SX0_OVR_SEL 0xC0400D04 159 #define LCAC_SX0_OVR_VAL 0xC0400D08 160 161 #define LCAC_MC0_CNTL 0xC0400D30 162 #define LCAC_MC0_OVR_SEL 0xC0400D34 163 #define LCAC_MC0_OVR_VAL 0xC0400D38 164 #define LCAC_MC1_CNTL 0xC0400D3C 165 #define LCAC_MC1_OVR_SEL 0xC0400D40 166 #define LCAC_MC1_OVR_VAL 0xC0400D44 167 168 #define LCAC_MC2_OVR_SEL 0xC0400D4C 169 #define LCAC_MC2_OVR_VAL 0xC0400D50 170 171 #define LCAC_MC3_OVR_SEL 0xC0400D58 172 #define LCAC_MC3_OVR_VAL 0xC0400D5C 173 174 #define LCAC_CPL_CNTL 0xC0400D80 175 #define LCAC_CPL_OVR_SEL 0xC0400D84 176 #define LCAC_CPL_OVR_VAL 0xC0400D88 177 178 /* dGPU */ 179 #define CG_THERMAL_CTRL 0xC0300004 180 #define DPM_EVENT_SRC(x) ((x) << 0) 181 #define DPM_EVENT_SRC_MASK (7 << 0) 182 #define DIG_THERM_DPM(x) ((x) << 14) 183 #define DIG_THERM_DPM_MASK 0x003FC000 184 #define DIG_THERM_DPM_SHIFT 14 185 186 #define CG_THERMAL_INT 0xC030000C 187 #define CI_DIG_THERM_INTH(x) ((x) << 8) 188 #define CI_DIG_THERM_INTH_MASK 0x0000FF00 189 #define CI_DIG_THERM_INTH_SHIFT 8 190 #define CI_DIG_THERM_INTL(x) ((x) << 16) 191 #define CI_DIG_THERM_INTL_MASK 0x00FF0000 192 #define CI_DIG_THERM_INTL_SHIFT 16 193 #define THERM_INT_MASK_HIGH (1 << 24) 194 #define THERM_INT_MASK_LOW (1 << 25) 195 196 #define CG_MULT_THERMAL_STATUS 0xC0300014 197 #define ASIC_MAX_TEMP(x) ((x) << 0) 198 #define ASIC_MAX_TEMP_MASK 0x000001ff 199 #define ASIC_MAX_TEMP_SHIFT 0 200 #define CTF_TEMP(x) ((x) << 9) 201 #define CTF_TEMP_MASK 0x0003fe00 202 #define CTF_TEMP_SHIFT 9 203 204 #define CG_SPLL_FUNC_CNTL 0xC0500140 205 #define SPLL_RESET (1 << 0) 206 #define SPLL_PWRON (1 << 1) 207 #define SPLL_BYPASS_EN (1 << 3) 208 #define SPLL_REF_DIV(x) ((x) << 5) 209 #define SPLL_REF_DIV_MASK (0x3f << 5) 210 #define SPLL_PDIV_A(x) ((x) << 20) 211 #define SPLL_PDIV_A_MASK (0x7f << 20) 212 #define SPLL_PDIV_A_SHIFT 20 213 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 214 #define SCLK_MUX_SEL(x) ((x) << 0) 215 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 216 #define CG_SPLL_FUNC_CNTL_3 0xC0500148 217 #define SPLL_FB_DIV(x) ((x) << 0) 218 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 219 #define SPLL_FB_DIV_SHIFT 0 220 #define SPLL_DITHEN (1 << 28) 221 #define CG_SPLL_FUNC_CNTL_4 0xC050014C 222 223 #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 224 #define SSEN (1 << 0) 225 #define CLK_S(x) ((x) << 4) 226 #define CLK_S_MASK (0xfff << 4) 227 #define CLK_S_SHIFT 4 228 #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 229 #define CLK_V(x) ((x) << 0) 230 #define CLK_V_MASK (0x3ffffff << 0) 231 #define CLK_V_SHIFT 0 232 233 #define MPLL_BYPASSCLK_SEL 0xC050019C 234 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 235 # define MPLL_CLKOUT_SEL_MASK 0xFF00 236 #define CG_CLKPIN_CNTL 0xC05001A0 237 # define XTALIN_DIVIDE (1 << 1) 238 # define BCLK_AS_XCLK (1 << 2) 239 #define CG_CLKPIN_CNTL_2 0xC05001A4 240 # define FORCE_BIF_REFCLK_EN (1 << 3) 241 # define MUX_TCLK_TO_XCLK (1 << 8) 242 #define THM_CLK_CNTL 0xC05001A8 243 # define CMON_CLK_SEL(x) ((x) << 0) 244 # define CMON_CLK_SEL_MASK 0xFF 245 # define TMON_CLK_SEL(x) ((x) << 8) 246 # define TMON_CLK_SEL_MASK 0xFF00 247 #define MISC_CLK_CTRL 0xC05001AC 248 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 249 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 250 # define ZCLK_SEL(x) ((x) << 8) 251 # define ZCLK_SEL_MASK 0xFF00 252 253 /* KV/KB */ 254 #define CG_THERMAL_INT_CTRL 0xC2100028 255 #define DIG_THERM_INTH(x) ((x) << 0) 256 #define DIG_THERM_INTH_MASK 0x000000FF 257 #define DIG_THERM_INTH_SHIFT 0 258 #define DIG_THERM_INTL(x) ((x) << 8) 259 #define DIG_THERM_INTL_MASK 0x0000FF00 260 #define DIG_THERM_INTL_SHIFT 8 261 #define THERM_INTH_MASK (1 << 24) 262 #define THERM_INTL_MASK (1 << 25) 263 264 /* PCIE registers idx/data 0x38/0x3c */ 265 #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 266 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 267 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 268 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 269 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 270 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 271 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 272 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 273 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 274 # define PLL_RAMP_UP_TIME_0_SHIFT 24 275 #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 276 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 277 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 278 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 279 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 280 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 281 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 282 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 283 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 284 # define PLL_RAMP_UP_TIME_1_SHIFT 24 285 286 #define PCIE_CNTL2 0x1001001c /* PCIE */ 287 # define SLV_MEM_LS_EN (1 << 16) 288 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 289 # define MST_MEM_LS_EN (1 << 18) 290 # define REPLAY_MEM_LS_EN (1 << 19) 291 292 #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 293 # define LC_REVERSE_RCVR (1 << 0) 294 # define LC_REVERSE_XMIT (1 << 1) 295 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 296 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 297 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 298 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 299 300 #define PCIE_P_CNTL 0x1400040 /* PCIE */ 301 # define P_IGNORE_EDB_ERR (1 << 6) 302 303 #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 304 #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 305 306 #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 307 # define LC_L0S_INACTIVITY(x) ((x) << 8) 308 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 309 # define LC_L0S_INACTIVITY_SHIFT 8 310 # define LC_L1_INACTIVITY(x) ((x) << 12) 311 # define LC_L1_INACTIVITY_MASK (0xf << 12) 312 # define LC_L1_INACTIVITY_SHIFT 12 313 # define LC_PMI_TO_L1_DIS (1 << 16) 314 # define LC_ASPM_TO_L1_DIS (1 << 24) 315 316 #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 317 # define LC_LINK_WIDTH_SHIFT 0 318 # define LC_LINK_WIDTH_MASK 0x7 319 # define LC_LINK_WIDTH_X0 0 320 # define LC_LINK_WIDTH_X1 1 321 # define LC_LINK_WIDTH_X2 2 322 # define LC_LINK_WIDTH_X4 3 323 # define LC_LINK_WIDTH_X8 4 324 # define LC_LINK_WIDTH_X16 6 325 # define LC_LINK_WIDTH_RD_SHIFT 4 326 # define LC_LINK_WIDTH_RD_MASK 0x70 327 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 328 # define LC_RECONFIG_NOW (1 << 8) 329 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 330 # define LC_RENEGOTIATE_EN (1 << 10) 331 # define LC_SHORT_RECONFIG_EN (1 << 11) 332 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 333 # define LC_UPCONFIGURE_DIS (1 << 13) 334 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 335 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 336 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 337 #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 338 # define LC_XMIT_N_FTS(x) ((x) << 0) 339 # define LC_XMIT_N_FTS_MASK (0xff << 0) 340 # define LC_XMIT_N_FTS_SHIFT 0 341 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 342 # define LC_N_FTS_MASK (0xff << 24) 343 #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 344 # define LC_GEN2_EN_STRAP (1 << 0) 345 # define LC_GEN3_EN_STRAP (1 << 1) 346 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 347 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 348 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 349 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 350 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 351 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 352 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 353 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 354 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 355 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 356 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 357 # define LC_CURRENT_DATA_RATE_SHIFT 13 358 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 359 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 360 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 361 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 362 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 363 364 #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 365 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 366 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 367 368 #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 369 # define LC_GO_TO_RECOVERY (1 << 30) 370 #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 371 # define LC_REDO_EQ (1 << 5) 372 # define LC_SET_QUIESCE (1 << 13) 373 374 /* direct registers */ 375 #define PCIE_INDEX 0x38 376 #define PCIE_DATA 0x3C 377 378 #define SMC_IND_INDEX_0 0x200 379 #define SMC_IND_DATA_0 0x204 380 381 #define SMC_IND_ACCESS_CNTL 0x240 382 #define AUTO_INCREMENT_IND_0 (1 << 0) 383 384 #define SMC_MESSAGE_0 0x250 385 #define SMC_MSG_MASK 0xffff 386 #define SMC_RESP_0 0x254 387 #define SMC_RESP_MASK 0xffff 388 389 #define SMC_MSG_ARG_0 0x290 390 391 #define VGA_HDP_CONTROL 0x328 392 #define VGA_MEMORY_DISABLE (1 << 4) 393 394 #define DMIF_ADDR_CALC 0xC00 395 396 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 397 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 398 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 399 400 #define SRBM_GFX_CNTL 0xE44 401 #define PIPEID(x) ((x) << 0) 402 #define MEID(x) ((x) << 2) 403 #define VMID(x) ((x) << 4) 404 #define QUEUEID(x) ((x) << 8) 405 406 #define SRBM_STATUS2 0xE4C 407 #define SDMA_BUSY (1 << 5) 408 #define SDMA1_BUSY (1 << 6) 409 #define SRBM_STATUS 0xE50 410 #define UVD_RQ_PENDING (1 << 1) 411 #define GRBM_RQ_PENDING (1 << 5) 412 #define VMC_BUSY (1 << 8) 413 #define MCB_BUSY (1 << 9) 414 #define MCB_NON_DISPLAY_BUSY (1 << 10) 415 #define MCC_BUSY (1 << 11) 416 #define MCD_BUSY (1 << 12) 417 #define SEM_BUSY (1 << 14) 418 #define IH_BUSY (1 << 17) 419 #define UVD_BUSY (1 << 19) 420 421 #define SRBM_SOFT_RESET 0xE60 422 #define SOFT_RESET_BIF (1 << 1) 423 #define SOFT_RESET_R0PLL (1 << 4) 424 #define SOFT_RESET_DC (1 << 5) 425 #define SOFT_RESET_SDMA1 (1 << 6) 426 #define SOFT_RESET_GRBM (1 << 8) 427 #define SOFT_RESET_HDP (1 << 9) 428 #define SOFT_RESET_IH (1 << 10) 429 #define SOFT_RESET_MC (1 << 11) 430 #define SOFT_RESET_ROM (1 << 14) 431 #define SOFT_RESET_SEM (1 << 15) 432 #define SOFT_RESET_VMC (1 << 17) 433 #define SOFT_RESET_SDMA (1 << 20) 434 #define SOFT_RESET_TST (1 << 21) 435 #define SOFT_RESET_REGBB (1 << 22) 436 #define SOFT_RESET_ORB (1 << 23) 437 #define SOFT_RESET_VCE (1 << 24) 438 439 #define VM_L2_CNTL 0x1400 440 #define ENABLE_L2_CACHE (1 << 0) 441 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 442 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 443 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 444 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 445 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 446 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 447 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 448 #define VM_L2_CNTL2 0x1404 449 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 450 #define INVALIDATE_L2_CACHE (1 << 1) 451 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 452 #define INVALIDATE_PTE_AND_PDE_CACHES 0 453 #define INVALIDATE_ONLY_PTE_CACHES 1 454 #define INVALIDATE_ONLY_PDE_CACHES 2 455 #define VM_L2_CNTL3 0x1408 456 #define BANK_SELECT(x) ((x) << 0) 457 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 458 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 459 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 460 #define VM_L2_STATUS 0x140C 461 #define L2_BUSY (1 << 0) 462 #define VM_CONTEXT0_CNTL 0x1410 463 #define ENABLE_CONTEXT (1 << 0) 464 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 465 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 466 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 467 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 468 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 469 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 470 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 471 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 472 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 473 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 474 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 475 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 476 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 477 #define VM_CONTEXT1_CNTL 0x1414 478 #define VM_CONTEXT0_CNTL2 0x1430 479 #define VM_CONTEXT1_CNTL2 0x1434 480 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 481 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 482 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 483 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 484 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 485 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 486 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 487 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 488 489 #define VM_INVALIDATE_REQUEST 0x1478 490 #define VM_INVALIDATE_RESPONSE 0x147c 491 492 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 493 #define PROTECTIONS_MASK (0xf << 0) 494 #define PROTECTIONS_SHIFT 0 495 /* bit 0: range 496 * bit 1: pde0 497 * bit 2: valid 498 * bit 3: read 499 * bit 4: write 500 */ 501 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 502 #define MEMORY_CLIENT_ID_SHIFT 12 503 #define MEMORY_CLIENT_RW_MASK (1 << 24) 504 #define MEMORY_CLIENT_RW_SHIFT 24 505 #define FAULT_VMID_MASK (0xf << 25) 506 #define FAULT_VMID_SHIFT 25 507 508 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 509 510 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 511 512 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 513 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 514 515 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 516 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 517 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 518 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 519 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 520 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 521 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 522 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 523 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 524 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 525 526 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 527 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 528 529 #define VM_L2_CG 0x15c0 530 #define MC_CG_ENABLE (1 << 18) 531 #define MC_LS_ENABLE (1 << 19) 532 533 #define MC_SHARED_CHMAP 0x2004 534 #define NOOFCHAN_SHIFT 12 535 #define NOOFCHAN_MASK 0x0000f000 536 #define MC_SHARED_CHREMAP 0x2008 537 538 #define CHUB_CONTROL 0x1864 539 #define BYPASS_VM (1 << 0) 540 541 #define MC_VM_FB_LOCATION 0x2024 542 #define MC_VM_AGP_TOP 0x2028 543 #define MC_VM_AGP_BOT 0x202C 544 #define MC_VM_AGP_BASE 0x2030 545 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 546 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 547 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 548 549 #define MC_VM_MX_L1_TLB_CNTL 0x2064 550 #define ENABLE_L1_TLB (1 << 0) 551 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 552 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 553 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 554 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 555 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 556 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 557 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 558 #define MC_VM_FB_OFFSET 0x2068 559 560 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 561 562 #define MC_HUB_MISC_HUB_CG 0x20b8 563 #define MC_HUB_MISC_VM_CG 0x20bc 564 565 #define MC_HUB_MISC_SIP_CG 0x20c0 566 567 #define MC_XPB_CLK_GAT 0x2478 568 569 #define MC_CITF_MISC_RD_CG 0x2648 570 #define MC_CITF_MISC_WR_CG 0x264c 571 #define MC_CITF_MISC_VM_CG 0x2650 572 573 #define MC_ARB_RAMCFG 0x2760 574 #define NOOFBANK_SHIFT 0 575 #define NOOFBANK_MASK 0x00000003 576 #define NOOFRANK_SHIFT 2 577 #define NOOFRANK_MASK 0x00000004 578 #define NOOFROWS_SHIFT 3 579 #define NOOFROWS_MASK 0x00000038 580 #define NOOFCOLS_SHIFT 6 581 #define NOOFCOLS_MASK 0x000000C0 582 #define CHANSIZE_SHIFT 8 583 #define CHANSIZE_MASK 0x00000100 584 #define NOOFGROUPS_SHIFT 12 585 #define NOOFGROUPS_MASK 0x00001000 586 587 #define MC_ARB_DRAM_TIMING 0x2774 588 #define MC_ARB_DRAM_TIMING2 0x2778 589 590 #define MC_ARB_BURST_TIME 0x2808 591 #define STATE0(x) ((x) << 0) 592 #define STATE0_MASK (0x1f << 0) 593 #define STATE0_SHIFT 0 594 #define STATE1(x) ((x) << 5) 595 #define STATE1_MASK (0x1f << 5) 596 #define STATE1_SHIFT 5 597 #define STATE2(x) ((x) << 10) 598 #define STATE2_MASK (0x1f << 10) 599 #define STATE2_SHIFT 10 600 #define STATE3(x) ((x) << 15) 601 #define STATE3_MASK (0x1f << 15) 602 #define STATE3_SHIFT 15 603 604 #define MC_SEQ_RAS_TIMING 0x28a0 605 #define MC_SEQ_CAS_TIMING 0x28a4 606 #define MC_SEQ_MISC_TIMING 0x28a8 607 #define MC_SEQ_MISC_TIMING2 0x28ac 608 #define MC_SEQ_PMG_TIMING 0x28b0 609 #define MC_SEQ_RD_CTL_D0 0x28b4 610 #define MC_SEQ_RD_CTL_D1 0x28b8 611 #define MC_SEQ_WR_CTL_D0 0x28bc 612 #define MC_SEQ_WR_CTL_D1 0x28c0 613 614 #define MC_SEQ_SUP_CNTL 0x28c8 615 #define RUN_MASK (1 << 0) 616 #define MC_SEQ_SUP_PGM 0x28cc 617 #define MC_PMG_AUTO_CMD 0x28d0 618 619 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 620 #define TRAIN_DONE_D0 (1 << 30) 621 #define TRAIN_DONE_D1 (1 << 31) 622 623 #define MC_IO_PAD_CNTL_D0 0x29d0 624 #define MEM_FALL_OUT_CMD (1 << 8) 625 626 #define MC_SEQ_MISC0 0x2a00 627 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 628 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 629 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 630 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 631 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 632 #define MC_SEQ_MISC0_REV_ID_VALUE 1 633 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 634 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 635 #define MC_SEQ_MISC0_GDDR5_VALUE 5 636 #define MC_SEQ_MISC1 0x2a04 637 #define MC_SEQ_RESERVE_M 0x2a08 638 #define MC_PMG_CMD_EMRS 0x2a0c 639 640 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 641 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 642 643 #define MC_SEQ_MISC5 0x2a54 644 #define MC_SEQ_MISC6 0x2a58 645 646 #define MC_SEQ_MISC7 0x2a64 647 648 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 649 #define MC_SEQ_CAS_TIMING_LP 0x2a70 650 #define MC_SEQ_MISC_TIMING_LP 0x2a74 651 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 652 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 653 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 654 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 655 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 656 657 #define MC_PMG_CMD_MRS 0x2aac 658 659 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 660 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 661 662 #define MC_PMG_CMD_MRS1 0x2b44 663 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 664 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 665 666 #define MC_SEQ_WR_CTL_2 0x2b54 667 #define MC_SEQ_WR_CTL_2_LP 0x2b58 668 #define MC_PMG_CMD_MRS2 0x2b5c 669 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 670 671 #define MCLK_PWRMGT_CNTL 0x2ba0 672 # define DLL_SPEED(x) ((x) << 0) 673 # define DLL_SPEED_MASK (0x1f << 0) 674 # define DLL_READY (1 << 6) 675 # define MC_INT_CNTL (1 << 7) 676 # define MRDCK0_PDNB (1 << 8) 677 # define MRDCK1_PDNB (1 << 9) 678 # define MRDCK0_RESET (1 << 16) 679 # define MRDCK1_RESET (1 << 17) 680 # define DLL_READY_READ (1 << 24) 681 #define DLL_CNTL 0x2ba4 682 # define MRDCK0_BYPASS (1 << 24) 683 # define MRDCK1_BYPASS (1 << 25) 684 685 #define MPLL_FUNC_CNTL 0x2bb4 686 #define BWCTRL(x) ((x) << 20) 687 #define BWCTRL_MASK (0xff << 20) 688 #define MPLL_FUNC_CNTL_1 0x2bb8 689 #define VCO_MODE(x) ((x) << 0) 690 #define VCO_MODE_MASK (3 << 0) 691 #define CLKFRAC(x) ((x) << 4) 692 #define CLKFRAC_MASK (0xfff << 4) 693 #define CLKF(x) ((x) << 16) 694 #define CLKF_MASK (0xfff << 16) 695 #define MPLL_FUNC_CNTL_2 0x2bbc 696 #define MPLL_AD_FUNC_CNTL 0x2bc0 697 #define YCLK_POST_DIV(x) ((x) << 0) 698 #define YCLK_POST_DIV_MASK (7 << 0) 699 #define MPLL_DQ_FUNC_CNTL 0x2bc4 700 #define YCLK_SEL(x) ((x) << 4) 701 #define YCLK_SEL_MASK (1 << 4) 702 703 #define MPLL_SS1 0x2bcc 704 #define CLKV(x) ((x) << 0) 705 #define CLKV_MASK (0x3ffffff << 0) 706 #define MPLL_SS2 0x2bd0 707 #define CLKS(x) ((x) << 0) 708 #define CLKS_MASK (0xfff << 0) 709 710 #define HDP_HOST_PATH_CNTL 0x2C00 711 #define CLOCK_GATING_DIS (1 << 23) 712 #define HDP_NONSURFACE_BASE 0x2C04 713 #define HDP_NONSURFACE_INFO 0x2C08 714 #define HDP_NONSURFACE_SIZE 0x2C0C 715 716 #define HDP_ADDR_CONFIG 0x2F48 717 #define HDP_MISC_CNTL 0x2F4C 718 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 719 #define HDP_MEM_POWER_LS 0x2F50 720 #define HDP_LS_ENABLE (1 << 0) 721 722 #define ATC_MISC_CG 0x3350 723 724 #define MC_SEQ_CNTL_3 0x3600 725 # define CAC_EN (1 << 31) 726 #define MC_SEQ_G5PDX_CTRL 0x3604 727 #define MC_SEQ_G5PDX_CTRL_LP 0x3608 728 #define MC_SEQ_G5PDX_CMD0 0x360c 729 #define MC_SEQ_G5PDX_CMD0_LP 0x3610 730 #define MC_SEQ_G5PDX_CMD1 0x3614 731 #define MC_SEQ_G5PDX_CMD1_LP 0x3618 732 733 #define MC_SEQ_PMG_DVS_CTL 0x3628 734 #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 735 #define MC_SEQ_PMG_DVS_CMD 0x3630 736 #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 737 #define MC_SEQ_DLL_STBY 0x3638 738 #define MC_SEQ_DLL_STBY_LP 0x363c 739 740 #define IH_RB_CNTL 0x3e00 741 # define IH_RB_ENABLE (1 << 0) 742 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 743 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 744 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 745 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 746 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 747 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 748 #define IH_RB_BASE 0x3e04 749 #define IH_RB_RPTR 0x3e08 750 #define IH_RB_WPTR 0x3e0c 751 # define RB_OVERFLOW (1 << 0) 752 # define WPTR_OFFSET_MASK 0x3fffc 753 #define IH_RB_WPTR_ADDR_HI 0x3e10 754 #define IH_RB_WPTR_ADDR_LO 0x3e14 755 #define IH_CNTL 0x3e18 756 # define ENABLE_INTR (1 << 0) 757 # define IH_MC_SWAP(x) ((x) << 1) 758 # define IH_MC_SWAP_NONE 0 759 # define IH_MC_SWAP_16BIT 1 760 # define IH_MC_SWAP_32BIT 2 761 # define IH_MC_SWAP_64BIT 3 762 # define RPTR_REARM (1 << 4) 763 # define MC_WRREQ_CREDIT(x) ((x) << 15) 764 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 765 # define MC_VMID(x) ((x) << 25) 766 767 #define BIF_LNCNT_RESET 0x5220 768 # define RESET_LNCNT_EN (1 << 0) 769 770 #define CONFIG_MEMSIZE 0x5428 771 772 #define INTERRUPT_CNTL 0x5468 773 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 774 # define IH_DUMMY_RD_EN (1 << 1) 775 # define IH_REQ_NONSNOOP_EN (1 << 3) 776 # define GEN_IH_INT_EN (1 << 8) 777 #define INTERRUPT_CNTL2 0x546c 778 779 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 780 781 #define BIF_FB_EN 0x5490 782 #define FB_READ_EN (1 << 0) 783 #define FB_WRITE_EN (1 << 1) 784 785 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 786 787 #define GPU_HDP_FLUSH_REQ 0x54DC 788 #define GPU_HDP_FLUSH_DONE 0x54E0 789 #define CP0 (1 << 0) 790 #define CP1 (1 << 1) 791 #define CP2 (1 << 2) 792 #define CP3 (1 << 3) 793 #define CP4 (1 << 4) 794 #define CP5 (1 << 5) 795 #define CP6 (1 << 6) 796 #define CP7 (1 << 7) 797 #define CP8 (1 << 8) 798 #define CP9 (1 << 9) 799 #define SDMA0 (1 << 10) 800 #define SDMA1 (1 << 11) 801 802 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 803 #define LB_MEMORY_CTRL 0x6b04 804 #define LB_MEMORY_SIZE(x) ((x) << 0) 805 #define LB_MEMORY_CONFIG(x) ((x) << 20) 806 807 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 808 # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 809 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 810 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 811 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 812 813 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 814 #define LB_VLINE_STATUS 0x6b24 815 # define VLINE_OCCURRED (1 << 0) 816 # define VLINE_ACK (1 << 4) 817 # define VLINE_STAT (1 << 12) 818 # define VLINE_INTERRUPT (1 << 16) 819 # define VLINE_INTERRUPT_TYPE (1 << 17) 820 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 821 #define LB_VBLANK_STATUS 0x6b2c 822 # define VBLANK_OCCURRED (1 << 0) 823 # define VBLANK_ACK (1 << 4) 824 # define VBLANK_STAT (1 << 12) 825 # define VBLANK_INTERRUPT (1 << 16) 826 # define VBLANK_INTERRUPT_TYPE (1 << 17) 827 828 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 829 #define LB_INTERRUPT_MASK 0x6b20 830 # define VBLANK_INTERRUPT_MASK (1 << 0) 831 # define VLINE_INTERRUPT_MASK (1 << 4) 832 # define VLINE2_INTERRUPT_MASK (1 << 8) 833 834 #define DISP_INTERRUPT_STATUS 0x60f4 835 # define LB_D1_VLINE_INTERRUPT (1 << 2) 836 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 837 # define DC_HPD1_INTERRUPT (1 << 17) 838 # define DC_HPD1_RX_INTERRUPT (1 << 18) 839 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 840 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 841 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 842 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 843 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 844 # define LB_D2_VLINE_INTERRUPT (1 << 2) 845 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 846 # define DC_HPD2_INTERRUPT (1 << 17) 847 # define DC_HPD2_RX_INTERRUPT (1 << 18) 848 # define DISP_TIMER_INTERRUPT (1 << 24) 849 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 850 # define LB_D3_VLINE_INTERRUPT (1 << 2) 851 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 852 # define DC_HPD3_INTERRUPT (1 << 17) 853 # define DC_HPD3_RX_INTERRUPT (1 << 18) 854 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 855 # define LB_D4_VLINE_INTERRUPT (1 << 2) 856 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 857 # define DC_HPD4_INTERRUPT (1 << 17) 858 # define DC_HPD4_RX_INTERRUPT (1 << 18) 859 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 860 # define LB_D5_VLINE_INTERRUPT (1 << 2) 861 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 862 # define DC_HPD5_INTERRUPT (1 << 17) 863 # define DC_HPD5_RX_INTERRUPT (1 << 18) 864 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 865 # define LB_D6_VLINE_INTERRUPT (1 << 2) 866 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 867 # define DC_HPD6_INTERRUPT (1 << 17) 868 # define DC_HPD6_RX_INTERRUPT (1 << 18) 869 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 870 871 #define DAC_AUTODETECT_INT_CONTROL 0x67c8 872 873 #define DC_HPD1_INT_STATUS 0x601c 874 #define DC_HPD2_INT_STATUS 0x6028 875 #define DC_HPD3_INT_STATUS 0x6034 876 #define DC_HPD4_INT_STATUS 0x6040 877 #define DC_HPD5_INT_STATUS 0x604c 878 #define DC_HPD6_INT_STATUS 0x6058 879 # define DC_HPDx_INT_STATUS (1 << 0) 880 # define DC_HPDx_SENSE (1 << 1) 881 # define DC_HPDx_SENSE_DELAYED (1 << 4) 882 # define DC_HPDx_RX_INT_STATUS (1 << 8) 883 884 #define DC_HPD1_INT_CONTROL 0x6020 885 #define DC_HPD2_INT_CONTROL 0x602c 886 #define DC_HPD3_INT_CONTROL 0x6038 887 #define DC_HPD4_INT_CONTROL 0x6044 888 #define DC_HPD5_INT_CONTROL 0x6050 889 #define DC_HPD6_INT_CONTROL 0x605c 890 # define DC_HPDx_INT_ACK (1 << 0) 891 # define DC_HPDx_INT_POLARITY (1 << 8) 892 # define DC_HPDx_INT_EN (1 << 16) 893 # define DC_HPDx_RX_INT_ACK (1 << 20) 894 # define DC_HPDx_RX_INT_EN (1 << 24) 895 896 #define DC_HPD1_CONTROL 0x6024 897 #define DC_HPD2_CONTROL 0x6030 898 #define DC_HPD3_CONTROL 0x603c 899 #define DC_HPD4_CONTROL 0x6048 900 #define DC_HPD5_CONTROL 0x6054 901 #define DC_HPD6_CONTROL 0x6060 902 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 903 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 904 # define DC_HPDx_EN (1 << 28) 905 906 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 907 # define STUTTER_ENABLE (1 << 0) 908 909 #define GRBM_CNTL 0x8000 910 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 911 912 #define GRBM_STATUS2 0x8008 913 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 914 #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 915 #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 916 #define ME1PIPE0_RQ_PENDING (1 << 6) 917 #define ME1PIPE1_RQ_PENDING (1 << 7) 918 #define ME1PIPE2_RQ_PENDING (1 << 8) 919 #define ME1PIPE3_RQ_PENDING (1 << 9) 920 #define ME2PIPE0_RQ_PENDING (1 << 10) 921 #define ME2PIPE1_RQ_PENDING (1 << 11) 922 #define ME2PIPE2_RQ_PENDING (1 << 12) 923 #define ME2PIPE3_RQ_PENDING (1 << 13) 924 #define RLC_RQ_PENDING (1 << 14) 925 #define RLC_BUSY (1 << 24) 926 #define TC_BUSY (1 << 25) 927 #define CPF_BUSY (1 << 28) 928 #define CPC_BUSY (1 << 29) 929 #define CPG_BUSY (1 << 30) 930 931 #define GRBM_STATUS 0x8010 932 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 933 #define SRBM_RQ_PENDING (1 << 5) 934 #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 935 #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 936 #define GDS_DMA_RQ_PENDING (1 << 9) 937 #define DB_CLEAN (1 << 12) 938 #define CB_CLEAN (1 << 13) 939 #define TA_BUSY (1 << 14) 940 #define GDS_BUSY (1 << 15) 941 #define WD_BUSY_NO_DMA (1 << 16) 942 #define VGT_BUSY (1 << 17) 943 #define IA_BUSY_NO_DMA (1 << 18) 944 #define IA_BUSY (1 << 19) 945 #define SX_BUSY (1 << 20) 946 #define WD_BUSY (1 << 21) 947 #define SPI_BUSY (1 << 22) 948 #define BCI_BUSY (1 << 23) 949 #define SC_BUSY (1 << 24) 950 #define PA_BUSY (1 << 25) 951 #define DB_BUSY (1 << 26) 952 #define CP_COHERENCY_BUSY (1 << 28) 953 #define CP_BUSY (1 << 29) 954 #define CB_BUSY (1 << 30) 955 #define GUI_ACTIVE (1 << 31) 956 #define GRBM_STATUS_SE0 0x8014 957 #define GRBM_STATUS_SE1 0x8018 958 #define GRBM_STATUS_SE2 0x8038 959 #define GRBM_STATUS_SE3 0x803C 960 #define SE_DB_CLEAN (1 << 1) 961 #define SE_CB_CLEAN (1 << 2) 962 #define SE_BCI_BUSY (1 << 22) 963 #define SE_VGT_BUSY (1 << 23) 964 #define SE_PA_BUSY (1 << 24) 965 #define SE_TA_BUSY (1 << 25) 966 #define SE_SX_BUSY (1 << 26) 967 #define SE_SPI_BUSY (1 << 27) 968 #define SE_SC_BUSY (1 << 29) 969 #define SE_DB_BUSY (1 << 30) 970 #define SE_CB_BUSY (1 << 31) 971 972 #define GRBM_SOFT_RESET 0x8020 973 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 974 #define SOFT_RESET_RLC (1 << 2) /* RLC */ 975 #define SOFT_RESET_GFX (1 << 16) /* GFX */ 976 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 977 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 978 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 979 980 #define GRBM_INT_CNTL 0x8060 981 # define RDERR_INT_ENABLE (1 << 0) 982 # define GUI_IDLE_INT_ENABLE (1 << 19) 983 984 #define CP_CPC_STATUS 0x8210 985 #define CP_CPC_BUSY_STAT 0x8214 986 #define CP_CPC_STALLED_STAT1 0x8218 987 #define CP_CPF_STATUS 0x821c 988 #define CP_CPF_BUSY_STAT 0x8220 989 #define CP_CPF_STALLED_STAT1 0x8224 990 991 #define CP_MEC_CNTL 0x8234 992 #define MEC_ME2_HALT (1 << 28) 993 #define MEC_ME1_HALT (1 << 30) 994 995 #define CP_MEC_CNTL 0x8234 996 #define MEC_ME2_HALT (1 << 28) 997 #define MEC_ME1_HALT (1 << 30) 998 999 #define CP_STALLED_STAT3 0x8670 1000 #define CP_STALLED_STAT1 0x8674 1001 #define CP_STALLED_STAT2 0x8678 1002 1003 #define CP_STAT 0x8680 1004 1005 #define CP_ME_CNTL 0x86D8 1006 #define CP_CE_HALT (1 << 24) 1007 #define CP_PFP_HALT (1 << 26) 1008 #define CP_ME_HALT (1 << 28) 1009 1010 #define CP_RB0_RPTR 0x8700 1011 #define CP_RB_WPTR_DELAY 0x8704 1012 #define CP_RB_WPTR_POLL_CNTL 0x8708 1013 #define IDLE_POLL_COUNT(x) ((x) << 16) 1014 #define IDLE_POLL_COUNT_MASK (0xffff << 16) 1015 1016 #define CP_MEQ_THRESHOLDS 0x8764 1017 #define MEQ1_START(x) ((x) << 0) 1018 #define MEQ2_START(x) ((x) << 8) 1019 1020 #define VGT_VTX_VECT_EJECT_REG 0x88B0 1021 1022 #define VGT_CACHE_INVALIDATION 0x88C4 1023 #define CACHE_INVALIDATION(x) ((x) << 0) 1024 #define VC_ONLY 0 1025 #define TC_ONLY 1 1026 #define VC_AND_TC 2 1027 #define AUTO_INVLD_EN(x) ((x) << 6) 1028 #define NO_AUTO 0 1029 #define ES_AUTO 1 1030 #define GS_AUTO 2 1031 #define ES_AND_GS_AUTO 3 1032 1033 #define VGT_GS_VERTEX_REUSE 0x88D4 1034 1035 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 1036 #define INACTIVE_CUS_MASK 0xFFFF0000 1037 #define INACTIVE_CUS_SHIFT 16 1038 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 1039 1040 #define PA_CL_ENHANCE 0x8A14 1041 #define CLIP_VTX_REORDER_ENA (1 << 0) 1042 #define NUM_CLIP_SEQ(x) ((x) << 1) 1043 1044 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 1045 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1046 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1047 1048 #define PA_SC_FIFO_SIZE 0x8BCC 1049 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1050 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1051 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1052 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1053 1054 #define PA_SC_ENHANCE 0x8BF0 1055 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 1056 #define DISABLE_PA_SC_GUIDANCE (1 << 13) 1057 1058 #define SQ_CONFIG 0x8C00 1059 1060 #define SH_MEM_BASES 0x8C28 1061 /* if PTR32, these are the bases for scratch and lds */ 1062 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 1063 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 1064 #define SH_MEM_APE1_BASE 0x8C2C 1065 /* if PTR32, this is the base location of GPUVM */ 1066 #define SH_MEM_APE1_LIMIT 0x8C30 1067 /* if PTR32, this is the upper limit of GPUVM */ 1068 #define SH_MEM_CONFIG 0x8C34 1069 #define PTR32 (1 << 0) 1070 #define ALIGNMENT_MODE(x) ((x) << 2) 1071 #define SH_MEM_ALIGNMENT_MODE_DWORD 0 1072 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 1073 #define SH_MEM_ALIGNMENT_MODE_STRICT 2 1074 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 1075 #define DEFAULT_MTYPE(x) ((x) << 4) 1076 #define APE1_MTYPE(x) ((x) << 7) 1077 1078 #define SX_DEBUG_1 0x9060 1079 1080 #define SPI_CONFIG_CNTL 0x9100 1081 1082 #define SPI_CONFIG_CNTL_1 0x913C 1083 #define VTX_DONE_DELAY(x) ((x) << 0) 1084 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1085 1086 #define TA_CNTL_AUX 0x9508 1087 1088 #define DB_DEBUG 0x9830 1089 #define DB_DEBUG2 0x9834 1090 #define DB_DEBUG3 0x9838 1091 1092 #define CC_RB_BACKEND_DISABLE 0x98F4 1093 #define BACKEND_DISABLE(x) ((x) << 16) 1094 #define GB_ADDR_CONFIG 0x98F8 1095 #define NUM_PIPES(x) ((x) << 0) 1096 #define NUM_PIPES_MASK 0x00000007 1097 #define NUM_PIPES_SHIFT 0 1098 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1099 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1100 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1101 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1102 #define NUM_SHADER_ENGINES_MASK 0x00003000 1103 #define NUM_SHADER_ENGINES_SHIFT 12 1104 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1105 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1106 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1107 #define ROW_SIZE(x) ((x) << 28) 1108 #define ROW_SIZE_MASK 0x30000000 1109 #define ROW_SIZE_SHIFT 28 1110 1111 #define GB_TILE_MODE0 0x9910 1112 # define ARRAY_MODE(x) ((x) << 2) 1113 # define ARRAY_LINEAR_GENERAL 0 1114 # define ARRAY_LINEAR_ALIGNED 1 1115 # define ARRAY_1D_TILED_THIN1 2 1116 # define ARRAY_2D_TILED_THIN1 4 1117 # define ARRAY_PRT_TILED_THIN1 5 1118 # define ARRAY_PRT_2D_TILED_THIN1 6 1119 # define PIPE_CONFIG(x) ((x) << 6) 1120 # define ADDR_SURF_P2 0 1121 # define ADDR_SURF_P4_8x16 4 1122 # define ADDR_SURF_P4_16x16 5 1123 # define ADDR_SURF_P4_16x32 6 1124 # define ADDR_SURF_P4_32x32 7 1125 # define ADDR_SURF_P8_16x16_8x16 8 1126 # define ADDR_SURF_P8_16x32_8x16 9 1127 # define ADDR_SURF_P8_32x32_8x16 10 1128 # define ADDR_SURF_P8_16x32_16x16 11 1129 # define ADDR_SURF_P8_32x32_16x16 12 1130 # define ADDR_SURF_P8_32x32_16x32 13 1131 # define ADDR_SURF_P8_32x64_32x32 14 1132 # define TILE_SPLIT(x) ((x) << 11) 1133 # define ADDR_SURF_TILE_SPLIT_64B 0 1134 # define ADDR_SURF_TILE_SPLIT_128B 1 1135 # define ADDR_SURF_TILE_SPLIT_256B 2 1136 # define ADDR_SURF_TILE_SPLIT_512B 3 1137 # define ADDR_SURF_TILE_SPLIT_1KB 4 1138 # define ADDR_SURF_TILE_SPLIT_2KB 5 1139 # define ADDR_SURF_TILE_SPLIT_4KB 6 1140 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 1141 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1142 # define ADDR_SURF_THIN_MICRO_TILING 1 1143 # define ADDR_SURF_DEPTH_MICRO_TILING 2 1144 # define ADDR_SURF_ROTATED_MICRO_TILING 3 1145 # define SAMPLE_SPLIT(x) ((x) << 25) 1146 # define ADDR_SURF_SAMPLE_SPLIT_1 0 1147 # define ADDR_SURF_SAMPLE_SPLIT_2 1 1148 # define ADDR_SURF_SAMPLE_SPLIT_4 2 1149 # define ADDR_SURF_SAMPLE_SPLIT_8 3 1150 1151 #define GB_MACROTILE_MODE0 0x9990 1152 # define BANK_WIDTH(x) ((x) << 0) 1153 # define ADDR_SURF_BANK_WIDTH_1 0 1154 # define ADDR_SURF_BANK_WIDTH_2 1 1155 # define ADDR_SURF_BANK_WIDTH_4 2 1156 # define ADDR_SURF_BANK_WIDTH_8 3 1157 # define BANK_HEIGHT(x) ((x) << 2) 1158 # define ADDR_SURF_BANK_HEIGHT_1 0 1159 # define ADDR_SURF_BANK_HEIGHT_2 1 1160 # define ADDR_SURF_BANK_HEIGHT_4 2 1161 # define ADDR_SURF_BANK_HEIGHT_8 3 1162 # define MACRO_TILE_ASPECT(x) ((x) << 4) 1163 # define ADDR_SURF_MACRO_ASPECT_1 0 1164 # define ADDR_SURF_MACRO_ASPECT_2 1 1165 # define ADDR_SURF_MACRO_ASPECT_4 2 1166 # define ADDR_SURF_MACRO_ASPECT_8 3 1167 # define NUM_BANKS(x) ((x) << 6) 1168 # define ADDR_SURF_2_BANK 0 1169 # define ADDR_SURF_4_BANK 1 1170 # define ADDR_SURF_8_BANK 2 1171 # define ADDR_SURF_16_BANK 3 1172 1173 #define CB_HW_CONTROL 0x9A10 1174 1175 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 1176 #define BACKEND_DISABLE_MASK 0x00FF0000 1177 #define BACKEND_DISABLE_SHIFT 16 1178 1179 #define TCP_CHAN_STEER_LO 0xac0c 1180 #define TCP_CHAN_STEER_HI 0xac10 1181 1182 #define TC_CFG_L1_LOAD_POLICY0 0xAC68 1183 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 1184 #define TC_CFG_L1_STORE_POLICY 0xAC70 1185 #define TC_CFG_L2_LOAD_POLICY0 0xAC74 1186 #define TC_CFG_L2_LOAD_POLICY1 0xAC78 1187 #define TC_CFG_L2_STORE_POLICY0 0xAC7C 1188 #define TC_CFG_L2_STORE_POLICY1 0xAC80 1189 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 1190 #define TC_CFG_L1_VOLATILE 0xAC88 1191 #define TC_CFG_L2_VOLATILE 0xAC8C 1192 1193 #define CP_RB0_BASE 0xC100 1194 #define CP_RB0_CNTL 0xC104 1195 #define RB_BUFSZ(x) ((x) << 0) 1196 #define RB_BLKSZ(x) ((x) << 8) 1197 #define BUF_SWAP_32BIT (2 << 16) 1198 #define RB_NO_UPDATE (1 << 27) 1199 #define RB_RPTR_WR_ENA (1 << 31) 1200 1201 #define CP_RB0_RPTR_ADDR 0xC10C 1202 #define RB_RPTR_SWAP_32BIT (2 << 0) 1203 #define CP_RB0_RPTR_ADDR_HI 0xC110 1204 #define CP_RB0_WPTR 0xC114 1205 1206 #define CP_DEVICE_ID 0xC12C 1207 #define CP_ENDIAN_SWAP 0xC140 1208 #define CP_RB_VMID 0xC144 1209 1210 #define CP_PFP_UCODE_ADDR 0xC150 1211 #define CP_PFP_UCODE_DATA 0xC154 1212 #define CP_ME_RAM_RADDR 0xC158 1213 #define CP_ME_RAM_WADDR 0xC15C 1214 #define CP_ME_RAM_DATA 0xC160 1215 1216 #define CP_CE_UCODE_ADDR 0xC168 1217 #define CP_CE_UCODE_DATA 0xC16C 1218 #define CP_MEC_ME1_UCODE_ADDR 0xC170 1219 #define CP_MEC_ME1_UCODE_DATA 0xC174 1220 #define CP_MEC_ME2_UCODE_ADDR 0xC178 1221 #define CP_MEC_ME2_UCODE_DATA 0xC17C 1222 1223 #define CP_INT_CNTL_RING0 0xC1A8 1224 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1225 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1226 # define PRIV_INSTR_INT_ENABLE (1 << 22) 1227 # define PRIV_REG_INT_ENABLE (1 << 23) 1228 # define TIME_STAMP_INT_ENABLE (1 << 26) 1229 # define CP_RINGID2_INT_ENABLE (1 << 29) 1230 # define CP_RINGID1_INT_ENABLE (1 << 30) 1231 # define CP_RINGID0_INT_ENABLE (1 << 31) 1232 1233 #define CP_INT_STATUS_RING0 0xC1B4 1234 # define PRIV_INSTR_INT_STAT (1 << 22) 1235 # define PRIV_REG_INT_STAT (1 << 23) 1236 # define TIME_STAMP_INT_STAT (1 << 26) 1237 # define CP_RINGID2_INT_STAT (1 << 29) 1238 # define CP_RINGID1_INT_STAT (1 << 30) 1239 # define CP_RINGID0_INT_STAT (1 << 31) 1240 1241 #define CP_MEM_SLP_CNTL 0xC1E4 1242 # define CP_MEM_LS_EN (1 << 0) 1243 1244 #define CP_CPF_DEBUG 0xC200 1245 1246 #define CP_PQ_WPTR_POLL_CNTL 0xC20C 1247 #define WPTR_POLL_EN (1 << 31) 1248 1249 #define CP_ME1_PIPE0_INT_CNTL 0xC214 1250 #define CP_ME1_PIPE1_INT_CNTL 0xC218 1251 #define CP_ME1_PIPE2_INT_CNTL 0xC21C 1252 #define CP_ME1_PIPE3_INT_CNTL 0xC220 1253 #define CP_ME2_PIPE0_INT_CNTL 0xC224 1254 #define CP_ME2_PIPE1_INT_CNTL 0xC228 1255 #define CP_ME2_PIPE2_INT_CNTL 0xC22C 1256 #define CP_ME2_PIPE3_INT_CNTL 0xC230 1257 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 1258 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 1259 # define PRIV_REG_INT_ENABLE (1 << 23) 1260 # define TIME_STAMP_INT_ENABLE (1 << 26) 1261 # define GENERIC2_INT_ENABLE (1 << 29) 1262 # define GENERIC1_INT_ENABLE (1 << 30) 1263 # define GENERIC0_INT_ENABLE (1 << 31) 1264 #define CP_ME1_PIPE0_INT_STATUS 0xC214 1265 #define CP_ME1_PIPE1_INT_STATUS 0xC218 1266 #define CP_ME1_PIPE2_INT_STATUS 0xC21C 1267 #define CP_ME1_PIPE3_INT_STATUS 0xC220 1268 #define CP_ME2_PIPE0_INT_STATUS 0xC224 1269 #define CP_ME2_PIPE1_INT_STATUS 0xC228 1270 #define CP_ME2_PIPE2_INT_STATUS 0xC22C 1271 #define CP_ME2_PIPE3_INT_STATUS 0xC230 1272 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 1273 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 1274 # define PRIV_REG_INT_STATUS (1 << 23) 1275 # define TIME_STAMP_INT_STATUS (1 << 26) 1276 # define GENERIC2_INT_STATUS (1 << 29) 1277 # define GENERIC1_INT_STATUS (1 << 30) 1278 # define GENERIC0_INT_STATUS (1 << 31) 1279 1280 #define CP_MAX_CONTEXT 0xC2B8 1281 1282 #define CP_RB0_BASE_HI 0xC2C4 1283 1284 #define RLC_CNTL 0xC300 1285 # define RLC_ENABLE (1 << 0) 1286 1287 #define RLC_MC_CNTL 0xC30C 1288 1289 #define RLC_MEM_SLP_CNTL 0xC318 1290 # define RLC_MEM_LS_EN (1 << 0) 1291 1292 #define RLC_LB_CNTR_MAX 0xC348 1293 1294 #define RLC_LB_CNTL 0xC364 1295 # define LOAD_BALANCE_ENABLE (1 << 0) 1296 1297 #define RLC_LB_CNTR_INIT 0xC36C 1298 1299 #define RLC_SAVE_AND_RESTORE_BASE 0xC374 1300 #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 1301 #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 1302 #define RLC_PG_DELAY_2 0xC37C 1303 1304 #define RLC_GPM_UCODE_ADDR 0xC388 1305 #define RLC_GPM_UCODE_DATA 0xC38C 1306 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 1307 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 1308 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 1309 #define RLC_UCODE_CNTL 0xC39C 1310 1311 #define RLC_GPM_STAT 0xC400 1312 # define RLC_GPM_BUSY (1 << 0) 1313 # define GFX_POWER_STATUS (1 << 1) 1314 # define GFX_CLOCK_STATUS (1 << 2) 1315 1316 #define RLC_PG_CNTL 0xC40C 1317 # define GFX_PG_ENABLE (1 << 0) 1318 # define GFX_PG_SRC (1 << 1) 1319 # define DYN_PER_CU_PG_ENABLE (1 << 2) 1320 # define STATIC_PER_CU_PG_ENABLE (1 << 3) 1321 # define DISABLE_GDS_PG (1 << 13) 1322 # define DISABLE_CP_PG (1 << 15) 1323 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 1324 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 1325 1326 #define RLC_CGTT_MGCG_OVERRIDE 0xC420 1327 #define RLC_CGCG_CGLS_CTRL 0xC424 1328 # define CGCG_EN (1 << 0) 1329 # define CGLS_EN (1 << 1) 1330 1331 #define RLC_PG_DELAY 0xC434 1332 1333 #define RLC_LB_INIT_CU_MASK 0xC43C 1334 1335 #define RLC_LB_PARAMS 0xC444 1336 1337 #define RLC_PG_AO_CU_MASK 0xC44C 1338 1339 #define RLC_MAX_PG_CU 0xC450 1340 # define MAX_PU_CU(x) ((x) << 0) 1341 # define MAX_PU_CU_MASK (0xff << 0) 1342 #define RLC_AUTO_PG_CTRL 0xC454 1343 # define AUTO_PG_EN (1 << 0) 1344 # define GRBM_REG_SGIT(x) ((x) << 3) 1345 # define GRBM_REG_SGIT_MASK (0xffff << 3) 1346 1347 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 1348 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 1349 #define RLC_SERDES_WR_CTRL 0xC47C 1350 #define BPM_ADDR(x) ((x) << 0) 1351 #define BPM_ADDR_MASK (0xff << 0) 1352 #define CGLS_ENABLE (1 << 16) 1353 #define CGCG_OVERRIDE_0 (1 << 20) 1354 #define MGCG_OVERRIDE_0 (1 << 22) 1355 #define MGCG_OVERRIDE_1 (1 << 23) 1356 1357 #define RLC_SERDES_CU_MASTER_BUSY 0xC484 1358 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 1359 # define SE_MASTER_BUSY_MASK 0x0000ffff 1360 # define GC_MASTER_BUSY (1 << 16) 1361 # define TC0_MASTER_BUSY (1 << 17) 1362 # define TC1_MASTER_BUSY (1 << 18) 1363 1364 #define RLC_GPM_SCRATCH_ADDR 0xC4B0 1365 #define RLC_GPM_SCRATCH_DATA 0xC4B4 1366 1367 #define RLC_GPR_REG2 0xC4E8 1368 #define REQ 0x00000001 1369 #define MESSAGE(x) ((x) << 1) 1370 #define MESSAGE_MASK 0x0000001e 1371 #define MSG_ENTER_RLC_SAFE_MODE 1 1372 #define MSG_EXIT_RLC_SAFE_MODE 0 1373 1374 #define CP_HPD_EOP_BASE_ADDR 0xC904 1375 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1376 #define CP_HPD_EOP_VMID 0xC90C 1377 #define CP_HPD_EOP_CONTROL 0xC910 1378 #define EOP_SIZE(x) ((x) << 0) 1379 #define EOP_SIZE_MASK (0x3f << 0) 1380 #define CP_MQD_BASE_ADDR 0xC914 1381 #define CP_MQD_BASE_ADDR_HI 0xC918 1382 #define CP_HQD_ACTIVE 0xC91C 1383 #define CP_HQD_VMID 0xC920 1384 1385 #define CP_HQD_PQ_BASE 0xC934 1386 #define CP_HQD_PQ_BASE_HI 0xC938 1387 #define CP_HQD_PQ_RPTR 0xC93C 1388 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 1389 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 1390 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 1391 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 1392 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 1393 #define DOORBELL_OFFSET(x) ((x) << 2) 1394 #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 1395 #define DOORBELL_SOURCE (1 << 28) 1396 #define DOORBELL_SCHD_HIT (1 << 29) 1397 #define DOORBELL_EN (1 << 30) 1398 #define DOORBELL_HIT (1 << 31) 1399 #define CP_HQD_PQ_WPTR 0xC954 1400 #define CP_HQD_PQ_CONTROL 0xC958 1401 #define QUEUE_SIZE(x) ((x) << 0) 1402 #define QUEUE_SIZE_MASK (0x3f << 0) 1403 #define RPTR_BLOCK_SIZE(x) ((x) << 8) 1404 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 1405 #define PQ_VOLATILE (1 << 26) 1406 #define NO_UPDATE_RPTR (1 << 27) 1407 #define UNORD_DISPATCH (1 << 28) 1408 #define ROQ_PQ_IB_FLIP (1 << 29) 1409 #define PRIV_STATE (1 << 30) 1410 #define KMD_QUEUE (1 << 31) 1411 1412 #define CP_HQD_DEQUEUE_REQUEST 0xC974 1413 1414 #define CP_MQD_CONTROL 0xC99C 1415 #define MQD_VMID(x) ((x) << 0) 1416 #define MQD_VMID_MASK (0xf << 0) 1417 1418 #define DB_RENDER_CONTROL 0x28000 1419 1420 #define PA_SC_RASTER_CONFIG 0x28350 1421 # define RASTER_CONFIG_RB_MAP_0 0 1422 # define RASTER_CONFIG_RB_MAP_1 1 1423 # define RASTER_CONFIG_RB_MAP_2 2 1424 # define RASTER_CONFIG_RB_MAP_3 3 1425 1426 #define VGT_EVENT_INITIATOR 0x28a90 1427 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1428 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1429 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1430 # define CACHE_FLUSH_TS (4 << 0) 1431 # define CACHE_FLUSH (6 << 0) 1432 # define CS_PARTIAL_FLUSH (7 << 0) 1433 # define VGT_STREAMOUT_RESET (10 << 0) 1434 # define END_OF_PIPE_INCR_DE (11 << 0) 1435 # define END_OF_PIPE_IB_END (12 << 0) 1436 # define RST_PIX_CNT (13 << 0) 1437 # define VS_PARTIAL_FLUSH (15 << 0) 1438 # define PS_PARTIAL_FLUSH (16 << 0) 1439 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1440 # define ZPASS_DONE (21 << 0) 1441 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1442 # define PERFCOUNTER_START (23 << 0) 1443 # define PERFCOUNTER_STOP (24 << 0) 1444 # define PIPELINESTAT_START (25 << 0) 1445 # define PIPELINESTAT_STOP (26 << 0) 1446 # define PERFCOUNTER_SAMPLE (27 << 0) 1447 # define SAMPLE_PIPELINESTAT (30 << 0) 1448 # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 1449 # define SAMPLE_STREAMOUTSTATS (32 << 0) 1450 # define RESET_VTX_CNT (33 << 0) 1451 # define VGT_FLUSH (36 << 0) 1452 # define BOTTOM_OF_PIPE_TS (40 << 0) 1453 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1454 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1455 # define FLUSH_AND_INV_DB_META (44 << 0) 1456 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1457 # define FLUSH_AND_INV_CB_META (46 << 0) 1458 # define CS_DONE (47 << 0) 1459 # define PS_DONE (48 << 0) 1460 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1461 # define THREAD_TRACE_START (51 << 0) 1462 # define THREAD_TRACE_STOP (52 << 0) 1463 # define THREAD_TRACE_FLUSH (54 << 0) 1464 # define THREAD_TRACE_FINISH (55 << 0) 1465 # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 1466 # define PIXEL_PIPE_STAT_DUMP (57 << 0) 1467 # define PIXEL_PIPE_STAT_RESET (58 << 0) 1468 1469 #define SCRATCH_REG0 0x30100 1470 #define SCRATCH_REG1 0x30104 1471 #define SCRATCH_REG2 0x30108 1472 #define SCRATCH_REG3 0x3010C 1473 #define SCRATCH_REG4 0x30110 1474 #define SCRATCH_REG5 0x30114 1475 #define SCRATCH_REG6 0x30118 1476 #define SCRATCH_REG7 0x3011C 1477 1478 #define SCRATCH_UMSK 0x30140 1479 #define SCRATCH_ADDR 0x30144 1480 1481 #define CP_SEM_WAIT_TIMER 0x301BC 1482 1483 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 1484 1485 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 1486 1487 #define GRBM_GFX_INDEX 0x30800 1488 #define INSTANCE_INDEX(x) ((x) << 0) 1489 #define SH_INDEX(x) ((x) << 8) 1490 #define SE_INDEX(x) ((x) << 16) 1491 #define SH_BROADCAST_WRITES (1 << 29) 1492 #define INSTANCE_BROADCAST_WRITES (1 << 30) 1493 #define SE_BROADCAST_WRITES (1 << 31) 1494 1495 #define VGT_ESGS_RING_SIZE 0x30900 1496 #define VGT_GSVS_RING_SIZE 0x30904 1497 #define VGT_PRIMITIVE_TYPE 0x30908 1498 #define VGT_INDEX_TYPE 0x3090C 1499 1500 #define VGT_NUM_INDICES 0x30930 1501 #define VGT_NUM_INSTANCES 0x30934 1502 #define VGT_TF_RING_SIZE 0x30938 1503 #define VGT_HS_OFFCHIP_PARAM 0x3093C 1504 #define VGT_TF_MEMORY_BASE 0x30940 1505 1506 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 1507 #define PA_SC_LINE_STIPPLE_STATE 0x30a04 1508 1509 #define SQC_CACHES 0x30d20 1510 1511 #define CP_PERFMON_CNTL 0x36020 1512 1513 #define CGTS_SM_CTRL_REG 0x3c000 1514 #define SM_MODE(x) ((x) << 17) 1515 #define SM_MODE_MASK (0x7 << 17) 1516 #define SM_MODE_ENABLE (1 << 20) 1517 #define CGTS_OVERRIDE (1 << 21) 1518 #define CGTS_LS_OVERRIDE (1 << 22) 1519 #define ON_MONITOR_ADD_EN (1 << 23) 1520 #define ON_MONITOR_ADD(x) ((x) << 24) 1521 #define ON_MONITOR_ADD_MASK (0xff << 24) 1522 1523 #define CGTS_TCC_DISABLE 0x3c00c 1524 #define CGTS_USER_TCC_DISABLE 0x3c010 1525 #define TCC_DISABLE_MASK 0xFFFF0000 1526 #define TCC_DISABLE_SHIFT 16 1527 1528 #define CB_CGTT_SCLK_CTRL 0x3c2a0 1529 1530 /* 1531 * PM4 1532 */ 1533 #define PACKET_TYPE0 0 1534 #define PACKET_TYPE1 1 1535 #define PACKET_TYPE2 2 1536 #define PACKET_TYPE3 3 1537 1538 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1539 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1540 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1541 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1542 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1543 (((reg) >> 2) & 0xFFFF) | \ 1544 ((n) & 0x3FFF) << 16) 1545 #define CP_PACKET2 0x80000000 1546 #define PACKET2_PAD_SHIFT 0 1547 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1548 1549 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1550 1551 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1552 (((op) & 0xFF) << 8) | \ 1553 ((n) & 0x3FFF) << 16) 1554 1555 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1556 1557 /* Packet 3 types */ 1558 #define PACKET3_NOP 0x10 1559 #define PACKET3_SET_BASE 0x11 1560 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1561 #define CE_PARTITION_BASE 3 1562 #define PACKET3_CLEAR_STATE 0x12 1563 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1564 #define PACKET3_DISPATCH_DIRECT 0x15 1565 #define PACKET3_DISPATCH_INDIRECT 0x16 1566 #define PACKET3_ATOMIC_GDS 0x1D 1567 #define PACKET3_ATOMIC_MEM 0x1E 1568 #define PACKET3_OCCLUSION_QUERY 0x1F 1569 #define PACKET3_SET_PREDICATION 0x20 1570 #define PACKET3_REG_RMW 0x21 1571 #define PACKET3_COND_EXEC 0x22 1572 #define PACKET3_PRED_EXEC 0x23 1573 #define PACKET3_DRAW_INDIRECT 0x24 1574 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1575 #define PACKET3_INDEX_BASE 0x26 1576 #define PACKET3_DRAW_INDEX_2 0x27 1577 #define PACKET3_CONTEXT_CONTROL 0x28 1578 #define PACKET3_INDEX_TYPE 0x2A 1579 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1580 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1581 #define PACKET3_NUM_INSTANCES 0x2F 1582 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1583 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1584 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1585 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1586 #define PACKET3_DRAW_PREAMBLE 0x36 1587 #define PACKET3_WRITE_DATA 0x37 1588 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1589 /* 0 - register 1590 * 1 - memory (sync - via GRBM) 1591 * 2 - gl2 1592 * 3 - gds 1593 * 4 - reserved 1594 * 5 - memory (async - direct) 1595 */ 1596 #define WR_ONE_ADDR (1 << 16) 1597 #define WR_CONFIRM (1 << 20) 1598 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 1599 /* 0 - LRU 1600 * 1 - Stream 1601 */ 1602 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1603 /* 0 - me 1604 * 1 - pfp 1605 * 2 - ce 1606 */ 1607 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1608 #define PACKET3_MEM_SEMAPHORE 0x39 1609 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 1610 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 1611 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 1612 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1613 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1614 #define PACKET3_COPY_DW 0x3B 1615 #define PACKET3_WAIT_REG_MEM 0x3C 1616 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1617 /* 0 - always 1618 * 1 - < 1619 * 2 - <= 1620 * 3 - == 1621 * 4 - != 1622 * 5 - >= 1623 * 6 - > 1624 */ 1625 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1626 /* 0 - reg 1627 * 1 - mem 1628 */ 1629 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 1630 /* 0 - wait_reg_mem 1631 * 1 - wr_wait_wr_reg 1632 */ 1633 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1634 /* 0 - me 1635 * 1 - pfp 1636 */ 1637 #define PACKET3_INDIRECT_BUFFER 0x3F 1638 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 1639 #define INDIRECT_BUFFER_VALID (1 << 23) 1640 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 1641 /* 0 - LRU 1642 * 1 - Stream 1643 * 2 - Bypass 1644 */ 1645 #define PACKET3_COPY_DATA 0x40 1646 #define PACKET3_PFP_SYNC_ME 0x42 1647 #define PACKET3_SURFACE_SYNC 0x43 1648 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1649 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1650 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1651 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1652 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1653 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1654 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1655 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1656 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1657 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1658 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1659 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1660 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1661 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1662 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1663 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1664 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1665 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1666 # define PACKET3_CB_ACTION_ENA (1 << 25) 1667 # define PACKET3_DB_ACTION_ENA (1 << 26) 1668 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1669 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1670 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1671 #define PACKET3_COND_WRITE 0x45 1672 #define PACKET3_EVENT_WRITE 0x46 1673 #define EVENT_TYPE(x) ((x) << 0) 1674 #define EVENT_INDEX(x) ((x) << 8) 1675 /* 0 - any non-TS event 1676 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1677 * 2 - SAMPLE_PIPELINESTAT 1678 * 3 - SAMPLE_STREAMOUTSTAT* 1679 * 4 - *S_PARTIAL_FLUSH 1680 * 5 - EOP events 1681 * 6 - EOS events 1682 */ 1683 #define PACKET3_EVENT_WRITE_EOP 0x47 1684 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1685 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1686 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1687 #define EOP_TCL1_ACTION_EN (1 << 16) 1688 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1689 #define EOP_CACHE_POLICY(x) ((x) << 25) 1690 /* 0 - LRU 1691 * 1 - Stream 1692 * 2 - Bypass 1693 */ 1694 #define EOP_TCL2_VOLATILE (1 << 27) 1695 #define DATA_SEL(x) ((x) << 29) 1696 /* 0 - discard 1697 * 1 - send low 32bit data 1698 * 2 - send 64bit data 1699 * 3 - send 64bit GPU counter value 1700 * 4 - send 64bit sys counter value 1701 */ 1702 #define INT_SEL(x) ((x) << 24) 1703 /* 0 - none 1704 * 1 - interrupt only (DATA_SEL = 0) 1705 * 2 - interrupt when data write is confirmed 1706 */ 1707 #define DST_SEL(x) ((x) << 16) 1708 /* 0 - MC 1709 * 1 - TC/L2 1710 */ 1711 #define PACKET3_EVENT_WRITE_EOS 0x48 1712 #define PACKET3_RELEASE_MEM 0x49 1713 #define PACKET3_PREAMBLE_CNTL 0x4A 1714 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1715 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1716 #define PACKET3_DMA_DATA 0x50 1717 #define PACKET3_AQUIRE_MEM 0x58 1718 #define PACKET3_REWIND 0x59 1719 #define PACKET3_LOAD_UCONFIG_REG 0x5E 1720 #define PACKET3_LOAD_SH_REG 0x5F 1721 #define PACKET3_LOAD_CONFIG_REG 0x60 1722 #define PACKET3_LOAD_CONTEXT_REG 0x61 1723 #define PACKET3_SET_CONFIG_REG 0x68 1724 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1725 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1726 #define PACKET3_SET_CONTEXT_REG 0x69 1727 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1728 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1729 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1730 #define PACKET3_SET_SH_REG 0x76 1731 #define PACKET3_SET_SH_REG_START 0x0000b000 1732 #define PACKET3_SET_SH_REG_END 0x0000c000 1733 #define PACKET3_SET_SH_REG_OFFSET 0x77 1734 #define PACKET3_SET_QUEUE_REG 0x78 1735 #define PACKET3_SET_UCONFIG_REG 0x79 1736 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 1737 #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1738 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1739 #define PACKET3_SCRATCH_RAM_READ 0x7E 1740 #define PACKET3_LOAD_CONST_RAM 0x80 1741 #define PACKET3_WRITE_CONST_RAM 0x81 1742 #define PACKET3_DUMP_CONST_RAM 0x83 1743 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1744 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1745 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1746 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1747 #define PACKET3_SWITCH_BUFFER 0x8B 1748 1749 /* SDMA - first instance at 0xd000, second at 0xd800 */ 1750 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 1751 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 1752 1753 #define SDMA0_UCODE_ADDR 0xD000 1754 #define SDMA0_UCODE_DATA 0xD004 1755 #define SDMA0_POWER_CNTL 0xD008 1756 #define SDMA0_CLK_CTRL 0xD00C 1757 1758 #define SDMA0_CNTL 0xD010 1759 # define TRAP_ENABLE (1 << 0) 1760 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1761 # define SEM_WAIT_INT_ENABLE (1 << 2) 1762 # define DATA_SWAP_ENABLE (1 << 3) 1763 # define FENCE_SWAP_ENABLE (1 << 4) 1764 # define AUTO_CTXSW_ENABLE (1 << 18) 1765 # define CTXEMPTY_INT_ENABLE (1 << 28) 1766 1767 #define SDMA0_TILING_CONFIG 0xD018 1768 1769 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 1770 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 1771 1772 #define SDMA0_STATUS_REG 0xd034 1773 # define SDMA_IDLE (1 << 0) 1774 1775 #define SDMA0_ME_CNTL 0xD048 1776 # define SDMA_HALT (1 << 0) 1777 1778 #define SDMA0_GFX_RB_CNTL 0xD200 1779 # define SDMA_RB_ENABLE (1 << 0) 1780 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1781 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1782 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1783 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1784 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1785 #define SDMA0_GFX_RB_BASE 0xD204 1786 #define SDMA0_GFX_RB_BASE_HI 0xD208 1787 #define SDMA0_GFX_RB_RPTR 0xD20C 1788 #define SDMA0_GFX_RB_WPTR 0xD210 1789 1790 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 1791 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 1792 #define SDMA0_GFX_IB_CNTL 0xD228 1793 # define SDMA_IB_ENABLE (1 << 0) 1794 # define SDMA_IB_SWAP_ENABLE (1 << 4) 1795 # define SDMA_SWITCH_INSIDE_IB (1 << 8) 1796 # define SDMA_CMD_VMID(x) ((x) << 16) 1797 1798 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 1799 #define SDMA0_GFX_APE1_CNTL 0xD2A0 1800 1801 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 1802 (((sub_op) & 0xFF) << 8) | \ 1803 (((op) & 0xFF) << 0)) 1804 /* sDMA opcodes */ 1805 #define SDMA_OPCODE_NOP 0 1806 #define SDMA_OPCODE_COPY 1 1807 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 1808 # define SDMA_COPY_SUB_OPCODE_TILED 1 1809 # define SDMA_COPY_SUB_OPCODE_SOA 3 1810 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 1811 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 1812 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 1813 #define SDMA_OPCODE_WRITE 2 1814 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 1815 # define SDMA_WRTIE_SUB_OPCODE_TILED 1 1816 #define SDMA_OPCODE_INDIRECT_BUFFER 4 1817 #define SDMA_OPCODE_FENCE 5 1818 #define SDMA_OPCODE_TRAP 6 1819 #define SDMA_OPCODE_SEMAPHORE 7 1820 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 1821 /* 0 - increment 1822 * 1 - write 1 1823 */ 1824 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 1825 /* 0 - wait 1826 * 1 - signal 1827 */ 1828 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 1829 /* mailbox */ 1830 #define SDMA_OPCODE_POLL_REG_MEM 8 1831 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 1832 /* 0 - wait_reg_mem 1833 * 1 - wr_wait_wr_reg 1834 */ 1835 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 1836 /* 0 - always 1837 * 1 - < 1838 * 2 - <= 1839 * 3 - == 1840 * 4 - != 1841 * 5 - >= 1842 * 6 - > 1843 */ 1844 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 1845 /* 0 = register 1846 * 1 = memory 1847 */ 1848 #define SDMA_OPCODE_COND_EXEC 9 1849 #define SDMA_OPCODE_CONSTANT_FILL 11 1850 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 1851 /* 0 = byte fill 1852 * 2 = DW fill 1853 */ 1854 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 1855 #define SDMA_OPCODE_TIMESTAMP 13 1856 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 1857 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 1858 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 1859 #define SDMA_OPCODE_SRBM_WRITE 14 1860 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 1861 /* byte mask */ 1862 1863 /* UVD */ 1864 1865 #define UVD_UDEC_ADDR_CONFIG 0xef4c 1866 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1867 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1868 1869 #define UVD_LMI_EXT40_ADDR 0xf498 1870 #define UVD_LMI_ADDR_EXT 0xf594 1871 #define UVD_VCPU_CACHE_OFFSET0 0xf608 1872 #define UVD_VCPU_CACHE_SIZE0 0xf60c 1873 #define UVD_VCPU_CACHE_OFFSET1 0xf610 1874 #define UVD_VCPU_CACHE_SIZE1 0xf614 1875 #define UVD_VCPU_CACHE_OFFSET2 0xf618 1876 #define UVD_VCPU_CACHE_SIZE2 0xf61c 1877 1878 #define UVD_RBC_RB_RPTR 0xf690 1879 #define UVD_RBC_RB_WPTR 0xf694 1880 1881 #define UVD_CGC_CTRL 0xF4B0 1882 # define DCM (1 << 0) 1883 # define CG_DT(x) ((x) << 2) 1884 # define CG_DT_MASK (0xf << 2) 1885 # define CLK_OD(x) ((x) << 6) 1886 # define CLK_OD_MASK (0x1f << 6) 1887 1888 /* UVD clocks */ 1889 1890 #define CG_DCLK_CNTL 0xC050009C 1891 # define DCLK_DIVIDER_MASK 0x7f 1892 # define DCLK_DIR_CNTL_EN (1 << 8) 1893 #define CG_DCLK_STATUS 0xC05000A0 1894 # define DCLK_STATUS (1 << 0) 1895 #define CG_VCLK_CNTL 0xC05000A4 1896 #define CG_VCLK_STATUS 0xC05000A8 1897 1898 /* UVD CTX indirect */ 1899 #define UVD_CGC_MEM_CTRL 0xC0 1900 1901 #endif 1902