157e252bfSMichael Neumann /* 257e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 357e252bfSMichael Neumann * 457e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 557e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 657e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 757e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 857e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 957e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 1057e252bfSMichael Neumann * 1157e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 1257e252bfSMichael Neumann * all copies or substantial portions of the Software. 1357e252bfSMichael Neumann * 1457e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1557e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1657e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1757e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1857e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1957e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2057e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 2157e252bfSMichael Neumann * 2257e252bfSMichael Neumann * Authors: Alex Deucher 2357e252bfSMichael Neumann */ 2457e252bfSMichael Neumann 2557e252bfSMichael Neumann #include <drm/drmP.h> 2657e252bfSMichael Neumann #include "radeon.h" 2757e252bfSMichael Neumann #include "evergreend.h" 2857e252bfSMichael Neumann #include "r600_dpm.h" 2957e252bfSMichael Neumann #include "cypress_dpm.h" 3057e252bfSMichael Neumann #include "atom.h" 3157e252bfSMichael Neumann #include "radeon_asic.h" 3257e252bfSMichael Neumann 3357e252bfSMichael Neumann #define SMC_RAM_END 0x8000 3457e252bfSMichael Neumann 3557e252bfSMichael Neumann #define MC_CG_ARB_FREQ_F0 0x0a 3657e252bfSMichael Neumann #define MC_CG_ARB_FREQ_F1 0x0b 3757e252bfSMichael Neumann #define MC_CG_ARB_FREQ_F2 0x0c 3857e252bfSMichael Neumann #define MC_CG_ARB_FREQ_F3 0x0d 3957e252bfSMichael Neumann 4057e252bfSMichael Neumann #define MC_CG_SEQ_DRAMCONF_S0 0x05 4157e252bfSMichael Neumann #define MC_CG_SEQ_DRAMCONF_S1 0x06 4257e252bfSMichael Neumann #define MC_CG_SEQ_YCLK_SUSPEND 0x04 4357e252bfSMichael Neumann #define MC_CG_SEQ_YCLK_RESUME 0x0a 4457e252bfSMichael Neumann 4557e252bfSMichael Neumann struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); 4657e252bfSMichael Neumann struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 4757e252bfSMichael Neumann struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 4857e252bfSMichael Neumann void cypress_dpm_reset_asic(struct radeon_device *rdev); 4957e252bfSMichael Neumann 5057e252bfSMichael Neumann static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, 5157e252bfSMichael Neumann bool enable) 5257e252bfSMichael Neumann { 5357e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5457e252bfSMichael Neumann u32 tmp, bif; 5557e252bfSMichael Neumann 5657e252bfSMichael Neumann tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 5757e252bfSMichael Neumann if (enable) { 5857e252bfSMichael Neumann if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && 5957e252bfSMichael Neumann (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 6057e252bfSMichael Neumann if (!pi->boot_in_gen2) { 6157e252bfSMichael Neumann bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; 6257e252bfSMichael Neumann bif |= CG_CLIENT_REQ(0xd); 6357e252bfSMichael Neumann WREG32(CG_BIF_REQ_AND_RSP, bif); 6457e252bfSMichael Neumann 6557e252bfSMichael Neumann tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 6657e252bfSMichael Neumann tmp |= LC_HW_VOLTAGE_IF_CONTROL(1); 6757e252bfSMichael Neumann tmp |= LC_GEN2_EN_STRAP; 6857e252bfSMichael Neumann 6957e252bfSMichael Neumann tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT; 7057e252bfSMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 71c4ef309bSzrj udelay(10); 7257e252bfSMichael Neumann tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 7357e252bfSMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 7457e252bfSMichael Neumann } 7557e252bfSMichael Neumann } 7657e252bfSMichael Neumann } else { 7757e252bfSMichael Neumann if (!pi->boot_in_gen2) { 7857e252bfSMichael Neumann tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 7957e252bfSMichael Neumann tmp &= ~LC_GEN2_EN_STRAP; 8057e252bfSMichael Neumann } 8157e252bfSMichael Neumann if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) || 8257e252bfSMichael Neumann (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) 8357e252bfSMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 8457e252bfSMichael Neumann } 8557e252bfSMichael Neumann } 8657e252bfSMichael Neumann 8757e252bfSMichael Neumann static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev, 8857e252bfSMichael Neumann bool enable) 8957e252bfSMichael Neumann { 9057e252bfSMichael Neumann cypress_enable_bif_dynamic_pcie_gen2(rdev, enable); 9157e252bfSMichael Neumann 9257e252bfSMichael Neumann if (enable) 9357e252bfSMichael Neumann WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); 9457e252bfSMichael Neumann else 9557e252bfSMichael Neumann WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); 9657e252bfSMichael Neumann } 9757e252bfSMichael Neumann 9857e252bfSMichael Neumann #if 0 9957e252bfSMichael Neumann static int cypress_enter_ulp_state(struct radeon_device *rdev) 10057e252bfSMichael Neumann { 10157e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 10257e252bfSMichael Neumann 10357e252bfSMichael Neumann if (pi->gfx_clock_gating) { 10457e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 10557e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 10657e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 10757e252bfSMichael Neumann 10857e252bfSMichael Neumann RREG32(GB_ADDR_CONFIG); 10957e252bfSMichael Neumann } 11057e252bfSMichael Neumann 11157e252bfSMichael Neumann WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), 11257e252bfSMichael Neumann ~HOST_SMC_MSG_MASK); 11357e252bfSMichael Neumann 114c4ef309bSzrj udelay(7000); 11557e252bfSMichael Neumann 11657e252bfSMichael Neumann return 0; 11757e252bfSMichael Neumann } 11857e252bfSMichael Neumann #endif 11957e252bfSMichael Neumann 12057e252bfSMichael Neumann static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev, 12157e252bfSMichael Neumann bool enable) 12257e252bfSMichael Neumann { 12357e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 12457e252bfSMichael Neumann 12557e252bfSMichael Neumann if (enable) { 12657e252bfSMichael Neumann if (eg_pi->light_sleep) { 12757e252bfSMichael Neumann WREG32(GRBM_GFX_INDEX, 0xC0000000); 12857e252bfSMichael Neumann 12957e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF); 13057e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF); 13157e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF); 13257e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF); 13357e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF); 13457e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF); 13557e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF); 13657e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF); 13757e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF); 13857e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF); 13957e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF); 14057e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF); 14157e252bfSMichael Neumann 14257e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); 14357e252bfSMichael Neumann } 14457e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 14557e252bfSMichael Neumann } else { 14657e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 14757e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 14857e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 14957e252bfSMichael Neumann RREG32(GB_ADDR_CONFIG); 15057e252bfSMichael Neumann 15157e252bfSMichael Neumann if (eg_pi->light_sleep) { 15257e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN); 15357e252bfSMichael Neumann 15457e252bfSMichael Neumann WREG32(GRBM_GFX_INDEX, 0xC0000000); 15557e252bfSMichael Neumann 15657e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_0, 0); 15757e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_1, 0); 15857e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_2, 0); 15957e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_3, 0); 16057e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_4, 0); 16157e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_5, 0); 16257e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_6, 0); 16357e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_7, 0); 16457e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_8, 0); 16557e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_9, 0); 16657e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_10, 0); 16757e252bfSMichael Neumann WREG32_CG(CG_CGLS_TILE_11, 0); 16857e252bfSMichael Neumann } 16957e252bfSMichael Neumann } 17057e252bfSMichael Neumann } 17157e252bfSMichael Neumann 17257e252bfSMichael Neumann static void cypress_mg_clock_gating_enable(struct radeon_device *rdev, 17357e252bfSMichael Neumann bool enable) 17457e252bfSMichael Neumann { 17557e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 17657e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 17757e252bfSMichael Neumann 17857e252bfSMichael Neumann if (enable) { 17957e252bfSMichael Neumann u32 cgts_sm_ctrl_reg; 18057e252bfSMichael Neumann 18157e252bfSMichael Neumann if (rdev->family == CHIP_CEDAR) 18257e252bfSMichael Neumann cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT; 18357e252bfSMichael Neumann else if (rdev->family == CHIP_REDWOOD) 18457e252bfSMichael Neumann cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT; 18557e252bfSMichael Neumann else 18657e252bfSMichael Neumann cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT; 18757e252bfSMichael Neumann 18857e252bfSMichael Neumann WREG32(GRBM_GFX_INDEX, 0xC0000000); 18957e252bfSMichael Neumann 19057e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT); 19157e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF); 19257e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT); 19357e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT); 19457e252bfSMichael Neumann 19557e252bfSMichael Neumann if (pi->mgcgtssm) 19657e252bfSMichael Neumann WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 19757e252bfSMichael Neumann 19857e252bfSMichael Neumann if (eg_pi->mcls) { 19957e252bfSMichael Neumann WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20057e252bfSMichael Neumann WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20157e252bfSMichael Neumann WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20257e252bfSMichael Neumann WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20357e252bfSMichael Neumann WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20457e252bfSMichael Neumann WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20557e252bfSMichael Neumann WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20657e252bfSMichael Neumann WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); 20757e252bfSMichael Neumann } 20857e252bfSMichael Neumann } else { 20957e252bfSMichael Neumann WREG32(GRBM_GFX_INDEX, 0xC0000000); 21057e252bfSMichael Neumann 21157e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF); 21257e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF); 21357e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF); 21457e252bfSMichael Neumann WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF); 21557e252bfSMichael Neumann 21657e252bfSMichael Neumann if (pi->mgcgtssm) 21757e252bfSMichael Neumann WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0); 21857e252bfSMichael Neumann } 21957e252bfSMichael Neumann } 22057e252bfSMichael Neumann 22157e252bfSMichael Neumann void cypress_enable_spread_spectrum(struct radeon_device *rdev, 22257e252bfSMichael Neumann bool enable) 22357e252bfSMichael Neumann { 22457e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 22557e252bfSMichael Neumann 22657e252bfSMichael Neumann if (enable) { 22757e252bfSMichael Neumann if (pi->sclk_ss) 22857e252bfSMichael Neumann WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 22957e252bfSMichael Neumann 23057e252bfSMichael Neumann if (pi->mclk_ss) 23157e252bfSMichael Neumann WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); 23257e252bfSMichael Neumann } else { 23357e252bfSMichael Neumann WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 23457e252bfSMichael Neumann WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 23557e252bfSMichael Neumann WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); 23657e252bfSMichael Neumann WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); 23757e252bfSMichael Neumann } 23857e252bfSMichael Neumann } 23957e252bfSMichael Neumann 24057e252bfSMichael Neumann void cypress_start_dpm(struct radeon_device *rdev) 24157e252bfSMichael Neumann { 24257e252bfSMichael Neumann WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 24357e252bfSMichael Neumann } 24457e252bfSMichael Neumann 24557e252bfSMichael Neumann void cypress_enable_sclk_control(struct radeon_device *rdev, 24657e252bfSMichael Neumann bool enable) 24757e252bfSMichael Neumann { 24857e252bfSMichael Neumann if (enable) 24957e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 25057e252bfSMichael Neumann else 25157e252bfSMichael Neumann WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 25257e252bfSMichael Neumann } 25357e252bfSMichael Neumann 25457e252bfSMichael Neumann void cypress_enable_mclk_control(struct radeon_device *rdev, 25557e252bfSMichael Neumann bool enable) 25657e252bfSMichael Neumann { 25757e252bfSMichael Neumann if (enable) 25857e252bfSMichael Neumann WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); 25957e252bfSMichael Neumann else 26057e252bfSMichael Neumann WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); 26157e252bfSMichael Neumann } 26257e252bfSMichael Neumann 26357e252bfSMichael Neumann int cypress_notify_smc_display_change(struct radeon_device *rdev, 26457e252bfSMichael Neumann bool has_display) 26557e252bfSMichael Neumann { 26657e252bfSMichael Neumann PPSMC_Msg msg = has_display ? 26757e252bfSMichael Neumann (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay; 26857e252bfSMichael Neumann 26957e252bfSMichael Neumann if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK) 27057e252bfSMichael Neumann return -EINVAL; 27157e252bfSMichael Neumann 27257e252bfSMichael Neumann return 0; 27357e252bfSMichael Neumann } 27457e252bfSMichael Neumann 27557e252bfSMichael Neumann void cypress_program_response_times(struct radeon_device *rdev) 27657e252bfSMichael Neumann { 27757e252bfSMichael Neumann u32 reference_clock; 27857e252bfSMichael Neumann u32 mclk_switch_limit; 27957e252bfSMichael Neumann 28057e252bfSMichael Neumann reference_clock = radeon_get_xclk(rdev); 28157e252bfSMichael Neumann mclk_switch_limit = (460 * reference_clock) / 100; 28257e252bfSMichael Neumann 28357e252bfSMichael Neumann rv770_write_smc_soft_register(rdev, 28457e252bfSMichael Neumann RV770_SMC_SOFT_REGISTER_mclk_switch_lim, 28557e252bfSMichael Neumann mclk_switch_limit); 28657e252bfSMichael Neumann 28757e252bfSMichael Neumann rv770_write_smc_soft_register(rdev, 28857e252bfSMichael Neumann RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 28957e252bfSMichael Neumann 29057e252bfSMichael Neumann rv770_write_smc_soft_register(rdev, 29157e252bfSMichael Neumann RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 29257e252bfSMichael Neumann 29357e252bfSMichael Neumann rv770_program_response_times(rdev); 29457e252bfSMichael Neumann 29557e252bfSMichael Neumann if (ASIC_IS_LOMBOK(rdev)) 29657e252bfSMichael Neumann rv770_write_smc_soft_register(rdev, 29757e252bfSMichael Neumann RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1); 29857e252bfSMichael Neumann 29957e252bfSMichael Neumann } 30057e252bfSMichael Neumann 30157e252bfSMichael Neumann static int cypress_pcie_performance_request(struct radeon_device *rdev, 30257e252bfSMichael Neumann u8 perf_req, bool advertise) 30357e252bfSMichael Neumann { 304*c6f73aabSFrançois Tigeot #if defined(CONFIG_ACPI) 30557e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 306*c6f73aabSFrançois Tigeot #endif 30757e252bfSMichael Neumann u32 tmp; 30857e252bfSMichael Neumann 309c4ef309bSzrj udelay(10); 31057e252bfSMichael Neumann tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 31157e252bfSMichael Neumann if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE)) 31257e252bfSMichael Neumann return 0; 31357e252bfSMichael Neumann 31457e252bfSMichael Neumann #if defined(CONFIG_ACPI) 31557e252bfSMichael Neumann if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) || 31657e252bfSMichael Neumann (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { 31757e252bfSMichael Neumann eg_pi->pcie_performance_request_registered = true; 31857e252bfSMichael Neumann return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); 31957e252bfSMichael Neumann } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) && 32057e252bfSMichael Neumann eg_pi->pcie_performance_request_registered) { 32157e252bfSMichael Neumann eg_pi->pcie_performance_request_registered = false; 32257e252bfSMichael Neumann return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); 32357e252bfSMichael Neumann } 32457e252bfSMichael Neumann #endif 32557e252bfSMichael Neumann 32657e252bfSMichael Neumann return 0; 32757e252bfSMichael Neumann } 32857e252bfSMichael Neumann 32957e252bfSMichael Neumann void cypress_advertise_gen2_capability(struct radeon_device *rdev) 33057e252bfSMichael Neumann { 33157e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 33257e252bfSMichael Neumann u32 tmp; 33357e252bfSMichael Neumann 33457e252bfSMichael Neumann #if defined(CONFIG_ACPI) 33557e252bfSMichael Neumann radeon_acpi_pcie_notify_device_ready(rdev); 33657e252bfSMichael Neumann #endif 33757e252bfSMichael Neumann 33857e252bfSMichael Neumann tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 33957e252bfSMichael Neumann 34057e252bfSMichael Neumann if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && 34157e252bfSMichael Neumann (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) 34257e252bfSMichael Neumann pi->pcie_gen2 = true; 34357e252bfSMichael Neumann else 34457e252bfSMichael Neumann pi->pcie_gen2 = false; 34557e252bfSMichael Neumann 34657e252bfSMichael Neumann if (!pi->pcie_gen2) 34757e252bfSMichael Neumann cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true); 34857e252bfSMichael Neumann 34957e252bfSMichael Neumann } 35057e252bfSMichael Neumann 35157e252bfSMichael Neumann static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state) 35257e252bfSMichael Neumann { 35357e252bfSMichael Neumann struct rv7xx_ps *state = rv770_get_ps(radeon_state); 35457e252bfSMichael Neumann 35557e252bfSMichael Neumann if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) 35657e252bfSMichael Neumann return 1; 35757e252bfSMichael Neumann return 0; 35857e252bfSMichael Neumann } 35957e252bfSMichael Neumann 36057e252bfSMichael Neumann void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 36157e252bfSMichael Neumann struct radeon_ps *radeon_new_state, 36257e252bfSMichael Neumann struct radeon_ps *radeon_current_state) 36357e252bfSMichael Neumann { 36457e252bfSMichael Neumann enum radeon_pcie_gen pcie_link_speed_target = 36557e252bfSMichael Neumann cypress_get_maximum_link_speed(radeon_new_state); 36657e252bfSMichael Neumann enum radeon_pcie_gen pcie_link_speed_current = 36757e252bfSMichael Neumann cypress_get_maximum_link_speed(radeon_current_state); 36857e252bfSMichael Neumann u8 request; 36957e252bfSMichael Neumann 37057e252bfSMichael Neumann if (pcie_link_speed_target < pcie_link_speed_current) { 37157e252bfSMichael Neumann if (pcie_link_speed_target == RADEON_PCIE_GEN1) 37257e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN1; 37357e252bfSMichael Neumann else if (pcie_link_speed_target == RADEON_PCIE_GEN2) 37457e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN2; 37557e252bfSMichael Neumann else 37657e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN3; 37757e252bfSMichael Neumann 37857e252bfSMichael Neumann cypress_pcie_performance_request(rdev, request, false); 37957e252bfSMichael Neumann } 38057e252bfSMichael Neumann } 38157e252bfSMichael Neumann 38257e252bfSMichael Neumann void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, 38357e252bfSMichael Neumann struct radeon_ps *radeon_new_state, 38457e252bfSMichael Neumann struct radeon_ps *radeon_current_state) 38557e252bfSMichael Neumann { 38657e252bfSMichael Neumann enum radeon_pcie_gen pcie_link_speed_target = 38757e252bfSMichael Neumann cypress_get_maximum_link_speed(radeon_new_state); 38857e252bfSMichael Neumann enum radeon_pcie_gen pcie_link_speed_current = 38957e252bfSMichael Neumann cypress_get_maximum_link_speed(radeon_current_state); 39057e252bfSMichael Neumann u8 request; 39157e252bfSMichael Neumann 39257e252bfSMichael Neumann if (pcie_link_speed_target > pcie_link_speed_current) { 39357e252bfSMichael Neumann if (pcie_link_speed_target == RADEON_PCIE_GEN1) 39457e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN1; 39557e252bfSMichael Neumann else if (pcie_link_speed_target == RADEON_PCIE_GEN2) 39657e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN2; 39757e252bfSMichael Neumann else 39857e252bfSMichael Neumann request = PCIE_PERF_REQ_PECI_GEN3; 39957e252bfSMichael Neumann 40057e252bfSMichael Neumann cypress_pcie_performance_request(rdev, request, false); 40157e252bfSMichael Neumann } 40257e252bfSMichael Neumann } 40357e252bfSMichael Neumann 40457e252bfSMichael Neumann static int cypress_populate_voltage_value(struct radeon_device *rdev, 40557e252bfSMichael Neumann struct atom_voltage_table *table, 40657e252bfSMichael Neumann u16 value, RV770_SMC_VOLTAGE_VALUE *voltage) 40757e252bfSMichael Neumann { 40857e252bfSMichael Neumann unsigned int i; 40957e252bfSMichael Neumann 41057e252bfSMichael Neumann for (i = 0; i < table->count; i++) { 41157e252bfSMichael Neumann if (value <= table->entries[i].value) { 41257e252bfSMichael Neumann voltage->index = (u8)i; 41357e252bfSMichael Neumann voltage->value = cpu_to_be16(table->entries[i].value); 41457e252bfSMichael Neumann break; 41557e252bfSMichael Neumann } 41657e252bfSMichael Neumann } 41757e252bfSMichael Neumann 41857e252bfSMichael Neumann if (i == table->count) 41957e252bfSMichael Neumann return -EINVAL; 42057e252bfSMichael Neumann 42157e252bfSMichael Neumann return 0; 42257e252bfSMichael Neumann } 42357e252bfSMichael Neumann 42457e252bfSMichael Neumann u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 42557e252bfSMichael Neumann { 42657e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 42757e252bfSMichael Neumann u8 result = 0; 42857e252bfSMichael Neumann bool strobe_mode = false; 42957e252bfSMichael Neumann 43057e252bfSMichael Neumann if (pi->mem_gddr5) { 43157e252bfSMichael Neumann if (mclk <= pi->mclk_strobe_mode_threshold) 43257e252bfSMichael Neumann strobe_mode = true; 43357e252bfSMichael Neumann result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); 43457e252bfSMichael Neumann 43557e252bfSMichael Neumann if (strobe_mode) 43657e252bfSMichael Neumann result |= SMC_STROBE_ENABLE; 43757e252bfSMichael Neumann } 43857e252bfSMichael Neumann 43957e252bfSMichael Neumann return result; 44057e252bfSMichael Neumann } 44157e252bfSMichael Neumann 44257e252bfSMichael Neumann u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) 44357e252bfSMichael Neumann { 44457e252bfSMichael Neumann u32 ref_clk = rdev->clock.mpll.reference_freq; 44557e252bfSMichael Neumann u32 vco = clkf * ref_clk; 44657e252bfSMichael Neumann 44757e252bfSMichael Neumann /* 100 Mhz ref clk */ 44857e252bfSMichael Neumann if (ref_clk == 10000) { 44957e252bfSMichael Neumann if (vco > 500000) 45057e252bfSMichael Neumann return 0xC6; 45157e252bfSMichael Neumann if (vco > 400000) 45257e252bfSMichael Neumann return 0x9D; 45357e252bfSMichael Neumann if (vco > 330000) 45457e252bfSMichael Neumann return 0x6C; 45557e252bfSMichael Neumann if (vco > 250000) 45657e252bfSMichael Neumann return 0x2B; 45757e252bfSMichael Neumann if (vco > 160000) 45857e252bfSMichael Neumann return 0x5B; 45957e252bfSMichael Neumann if (vco > 120000) 46057e252bfSMichael Neumann return 0x0A; 46157e252bfSMichael Neumann return 0x4B; 46257e252bfSMichael Neumann } 46357e252bfSMichael Neumann 46457e252bfSMichael Neumann /* 27 Mhz ref clk */ 46557e252bfSMichael Neumann if (vco > 250000) 46657e252bfSMichael Neumann return 0x8B; 46757e252bfSMichael Neumann if (vco > 200000) 46857e252bfSMichael Neumann return 0xCC; 46957e252bfSMichael Neumann if (vco > 150000) 47057e252bfSMichael Neumann return 0x9B; 47157e252bfSMichael Neumann return 0x6B; 47257e252bfSMichael Neumann } 47357e252bfSMichael Neumann 47457e252bfSMichael Neumann static int cypress_populate_mclk_value(struct radeon_device *rdev, 47557e252bfSMichael Neumann u32 engine_clock, u32 memory_clock, 47657e252bfSMichael Neumann RV7XX_SMC_MCLK_VALUE *mclk, 47757e252bfSMichael Neumann bool strobe_mode, bool dll_state_on) 47857e252bfSMichael Neumann { 47957e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 48057e252bfSMichael Neumann 48157e252bfSMichael Neumann u32 mpll_ad_func_cntl = 48257e252bfSMichael Neumann pi->clk_regs.rv770.mpll_ad_func_cntl; 48357e252bfSMichael Neumann u32 mpll_ad_func_cntl_2 = 48457e252bfSMichael Neumann pi->clk_regs.rv770.mpll_ad_func_cntl_2; 48557e252bfSMichael Neumann u32 mpll_dq_func_cntl = 48657e252bfSMichael Neumann pi->clk_regs.rv770.mpll_dq_func_cntl; 48757e252bfSMichael Neumann u32 mpll_dq_func_cntl_2 = 48857e252bfSMichael Neumann pi->clk_regs.rv770.mpll_dq_func_cntl_2; 48957e252bfSMichael Neumann u32 mclk_pwrmgt_cntl = 49057e252bfSMichael Neumann pi->clk_regs.rv770.mclk_pwrmgt_cntl; 49157e252bfSMichael Neumann u32 dll_cntl = 49257e252bfSMichael Neumann pi->clk_regs.rv770.dll_cntl; 49357e252bfSMichael Neumann u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; 49457e252bfSMichael Neumann u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; 49557e252bfSMichael Neumann struct atom_clock_dividers dividers; 49657e252bfSMichael Neumann u32 ibias; 49757e252bfSMichael Neumann u32 dll_speed; 49857e252bfSMichael Neumann int ret; 49957e252bfSMichael Neumann u32 mc_seq_misc7; 50057e252bfSMichael Neumann 50157e252bfSMichael Neumann ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, 50257e252bfSMichael Neumann memory_clock, strobe_mode, ÷rs); 50357e252bfSMichael Neumann if (ret) 50457e252bfSMichael Neumann return ret; 50557e252bfSMichael Neumann 50657e252bfSMichael Neumann if (!strobe_mode) { 50757e252bfSMichael Neumann mc_seq_misc7 = RREG32(MC_SEQ_MISC7); 50857e252bfSMichael Neumann 50957e252bfSMichael Neumann if(mc_seq_misc7 & 0x8000000) 51057e252bfSMichael Neumann dividers.post_div = 1; 51157e252bfSMichael Neumann } 51257e252bfSMichael Neumann 51357e252bfSMichael Neumann ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); 51457e252bfSMichael Neumann 51557e252bfSMichael Neumann mpll_ad_func_cntl &= ~(CLKR_MASK | 51657e252bfSMichael Neumann YCLK_POST_DIV_MASK | 51757e252bfSMichael Neumann CLKF_MASK | 51857e252bfSMichael Neumann CLKFRAC_MASK | 51957e252bfSMichael Neumann IBIAS_MASK); 52057e252bfSMichael Neumann mpll_ad_func_cntl |= CLKR(dividers.ref_div); 52157e252bfSMichael Neumann mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); 52257e252bfSMichael Neumann mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); 52357e252bfSMichael Neumann mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); 52457e252bfSMichael Neumann mpll_ad_func_cntl |= IBIAS(ibias); 52557e252bfSMichael Neumann 52657e252bfSMichael Neumann if (dividers.vco_mode) 52757e252bfSMichael Neumann mpll_ad_func_cntl_2 |= VCO_MODE; 52857e252bfSMichael Neumann else 52957e252bfSMichael Neumann mpll_ad_func_cntl_2 &= ~VCO_MODE; 53057e252bfSMichael Neumann 53157e252bfSMichael Neumann if (pi->mem_gddr5) { 53257e252bfSMichael Neumann mpll_dq_func_cntl &= ~(CLKR_MASK | 53357e252bfSMichael Neumann YCLK_POST_DIV_MASK | 53457e252bfSMichael Neumann CLKF_MASK | 53557e252bfSMichael Neumann CLKFRAC_MASK | 53657e252bfSMichael Neumann IBIAS_MASK); 53757e252bfSMichael Neumann mpll_dq_func_cntl |= CLKR(dividers.ref_div); 53857e252bfSMichael Neumann mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); 53957e252bfSMichael Neumann mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div); 54057e252bfSMichael Neumann mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div); 54157e252bfSMichael Neumann mpll_dq_func_cntl |= IBIAS(ibias); 54257e252bfSMichael Neumann 54357e252bfSMichael Neumann if (strobe_mode) 54457e252bfSMichael Neumann mpll_dq_func_cntl &= ~PDNB; 54557e252bfSMichael Neumann else 54657e252bfSMichael Neumann mpll_dq_func_cntl |= PDNB; 54757e252bfSMichael Neumann 54857e252bfSMichael Neumann if (dividers.vco_mode) 54957e252bfSMichael Neumann mpll_dq_func_cntl_2 |= VCO_MODE; 55057e252bfSMichael Neumann else 55157e252bfSMichael Neumann mpll_dq_func_cntl_2 &= ~VCO_MODE; 55257e252bfSMichael Neumann } 55357e252bfSMichael Neumann 55457e252bfSMichael Neumann if (pi->mclk_ss) { 55557e252bfSMichael Neumann struct radeon_atom_ss ss; 55657e252bfSMichael Neumann u32 vco_freq = memory_clock * dividers.post_div; 55757e252bfSMichael Neumann 55857e252bfSMichael Neumann if (radeon_atombios_get_asic_ss_info(rdev, &ss, 55957e252bfSMichael Neumann ASIC_INTERNAL_MEMORY_SS, vco_freq)) { 56057e252bfSMichael Neumann u32 reference_clock = rdev->clock.mpll.reference_freq; 56157e252bfSMichael Neumann u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); 56257e252bfSMichael Neumann u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); 56357e252bfSMichael Neumann u32 clk_v = ss.percentage * 56457e252bfSMichael Neumann (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); 56557e252bfSMichael Neumann 56657e252bfSMichael Neumann mpll_ss1 &= ~CLKV_MASK; 56757e252bfSMichael Neumann mpll_ss1 |= CLKV(clk_v); 56857e252bfSMichael Neumann 56957e252bfSMichael Neumann mpll_ss2 &= ~CLKS_MASK; 57057e252bfSMichael Neumann mpll_ss2 |= CLKS(clk_s); 57157e252bfSMichael Neumann } 57257e252bfSMichael Neumann } 57357e252bfSMichael Neumann 57457e252bfSMichael Neumann dll_speed = rv740_get_dll_speed(pi->mem_gddr5, 57557e252bfSMichael Neumann memory_clock); 57657e252bfSMichael Neumann 57757e252bfSMichael Neumann mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 57857e252bfSMichael Neumann mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed); 57957e252bfSMichael Neumann if (dll_state_on) 58057e252bfSMichael Neumann mclk_pwrmgt_cntl |= (MRDCKA0_PDNB | 58157e252bfSMichael Neumann MRDCKA1_PDNB | 58257e252bfSMichael Neumann MRDCKB0_PDNB | 58357e252bfSMichael Neumann MRDCKB1_PDNB | 58457e252bfSMichael Neumann MRDCKC0_PDNB | 58557e252bfSMichael Neumann MRDCKC1_PDNB | 58657e252bfSMichael Neumann MRDCKD0_PDNB | 58757e252bfSMichael Neumann MRDCKD1_PDNB); 58857e252bfSMichael Neumann else 58957e252bfSMichael Neumann mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB | 59057e252bfSMichael Neumann MRDCKA1_PDNB | 59157e252bfSMichael Neumann MRDCKB0_PDNB | 59257e252bfSMichael Neumann MRDCKB1_PDNB | 59357e252bfSMichael Neumann MRDCKC0_PDNB | 59457e252bfSMichael Neumann MRDCKC1_PDNB | 59557e252bfSMichael Neumann MRDCKD0_PDNB | 59657e252bfSMichael Neumann MRDCKD1_PDNB); 59757e252bfSMichael Neumann 59857e252bfSMichael Neumann mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); 59957e252bfSMichael Neumann mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 60057e252bfSMichael Neumann mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); 60157e252bfSMichael Neumann mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 60257e252bfSMichael Neumann mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); 60357e252bfSMichael Neumann mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 60457e252bfSMichael Neumann mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); 60557e252bfSMichael Neumann mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); 60657e252bfSMichael Neumann mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); 60757e252bfSMichael Neumann 60857e252bfSMichael Neumann return 0; 60957e252bfSMichael Neumann } 61057e252bfSMichael Neumann 61157e252bfSMichael Neumann u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, 61257e252bfSMichael Neumann u32 memory_clock, bool strobe_mode) 61357e252bfSMichael Neumann { 61457e252bfSMichael Neumann u8 mc_para_index; 61557e252bfSMichael Neumann 61657e252bfSMichael Neumann if (rdev->family >= CHIP_BARTS) { 61757e252bfSMichael Neumann if (strobe_mode) { 61857e252bfSMichael Neumann if (memory_clock < 10000) 61957e252bfSMichael Neumann mc_para_index = 0x00; 62057e252bfSMichael Neumann else if (memory_clock > 47500) 62157e252bfSMichael Neumann mc_para_index = 0x0f; 62257e252bfSMichael Neumann else 62357e252bfSMichael Neumann mc_para_index = (u8)((memory_clock - 10000) / 2500); 62457e252bfSMichael Neumann } else { 62557e252bfSMichael Neumann if (memory_clock < 65000) 62657e252bfSMichael Neumann mc_para_index = 0x00; 62757e252bfSMichael Neumann else if (memory_clock > 135000) 62857e252bfSMichael Neumann mc_para_index = 0x0f; 62957e252bfSMichael Neumann else 63057e252bfSMichael Neumann mc_para_index = (u8)((memory_clock - 60000) / 5000); 63157e252bfSMichael Neumann } 63257e252bfSMichael Neumann } else { 63357e252bfSMichael Neumann if (strobe_mode) { 63457e252bfSMichael Neumann if (memory_clock < 10000) 63557e252bfSMichael Neumann mc_para_index = 0x00; 63657e252bfSMichael Neumann else if (memory_clock > 47500) 63757e252bfSMichael Neumann mc_para_index = 0x0f; 63857e252bfSMichael Neumann else 63957e252bfSMichael Neumann mc_para_index = (u8)((memory_clock - 10000) / 2500); 64057e252bfSMichael Neumann } else { 64157e252bfSMichael Neumann if (memory_clock < 40000) 64257e252bfSMichael Neumann mc_para_index = 0x00; 64357e252bfSMichael Neumann else if (memory_clock > 115000) 64457e252bfSMichael Neumann mc_para_index = 0x0f; 64557e252bfSMichael Neumann else 64657e252bfSMichael Neumann mc_para_index = (u8)((memory_clock - 40000) / 5000); 64757e252bfSMichael Neumann } 64857e252bfSMichael Neumann } 64957e252bfSMichael Neumann return mc_para_index; 65057e252bfSMichael Neumann } 65157e252bfSMichael Neumann 65257e252bfSMichael Neumann static int cypress_populate_mvdd_value(struct radeon_device *rdev, 65357e252bfSMichael Neumann u32 mclk, 65457e252bfSMichael Neumann RV770_SMC_VOLTAGE_VALUE *voltage) 65557e252bfSMichael Neumann { 65657e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 65757e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 65857e252bfSMichael Neumann 65957e252bfSMichael Neumann if (!pi->mvdd_control) { 66057e252bfSMichael Neumann voltage->index = eg_pi->mvdd_high_index; 66157e252bfSMichael Neumann voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 66257e252bfSMichael Neumann return 0; 66357e252bfSMichael Neumann } 66457e252bfSMichael Neumann 66557e252bfSMichael Neumann if (mclk <= pi->mvdd_split_frequency) { 66657e252bfSMichael Neumann voltage->index = eg_pi->mvdd_low_index; 66757e252bfSMichael Neumann voltage->value = cpu_to_be16(MVDD_LOW_VALUE); 66857e252bfSMichael Neumann } else { 66957e252bfSMichael Neumann voltage->index = eg_pi->mvdd_high_index; 67057e252bfSMichael Neumann voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 67157e252bfSMichael Neumann } 67257e252bfSMichael Neumann 67357e252bfSMichael Neumann return 0; 67457e252bfSMichael Neumann } 67557e252bfSMichael Neumann 67657e252bfSMichael Neumann int cypress_convert_power_level_to_smc(struct radeon_device *rdev, 67757e252bfSMichael Neumann struct rv7xx_pl *pl, 67857e252bfSMichael Neumann RV770_SMC_HW_PERFORMANCE_LEVEL *level, 67957e252bfSMichael Neumann u8 watermark_level) 68057e252bfSMichael Neumann { 68157e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 68257e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 68357e252bfSMichael Neumann int ret; 68457e252bfSMichael Neumann bool dll_state_on; 68557e252bfSMichael Neumann 68657e252bfSMichael Neumann level->gen2PCIE = pi->pcie_gen2 ? 68757e252bfSMichael Neumann ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0; 68857e252bfSMichael Neumann level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0; 68957e252bfSMichael Neumann level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0; 69057e252bfSMichael Neumann level->displayWatermark = watermark_level; 69157e252bfSMichael Neumann 69257e252bfSMichael Neumann ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); 69357e252bfSMichael Neumann if (ret) 69457e252bfSMichael Neumann return ret; 69557e252bfSMichael Neumann 69657e252bfSMichael Neumann level->mcFlags = 0; 69757e252bfSMichael Neumann if (pi->mclk_stutter_mode_threshold && 69857e252bfSMichael Neumann (pl->mclk <= pi->mclk_stutter_mode_threshold) && 69957e252bfSMichael Neumann !eg_pi->uvd_enabled) { 70057e252bfSMichael Neumann level->mcFlags |= SMC_MC_STUTTER_EN; 70157e252bfSMichael Neumann if (eg_pi->sclk_deep_sleep) 70257e252bfSMichael Neumann level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP; 70357e252bfSMichael Neumann else 70457e252bfSMichael Neumann level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP; 70557e252bfSMichael Neumann } 70657e252bfSMichael Neumann 70757e252bfSMichael Neumann if (pi->mem_gddr5) { 70857e252bfSMichael Neumann if (pl->mclk > pi->mclk_edc_enable_threshold) 70957e252bfSMichael Neumann level->mcFlags |= SMC_MC_EDC_RD_FLAG; 71057e252bfSMichael Neumann 71157e252bfSMichael Neumann if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 71257e252bfSMichael Neumann level->mcFlags |= SMC_MC_EDC_WR_FLAG; 71357e252bfSMichael Neumann 71457e252bfSMichael Neumann level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk); 71557e252bfSMichael Neumann 71657e252bfSMichael Neumann if (level->strobeMode & SMC_STROBE_ENABLE) { 71757e252bfSMichael Neumann if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >= 71857e252bfSMichael Neumann ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 71957e252bfSMichael Neumann dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 72057e252bfSMichael Neumann else 72157e252bfSMichael Neumann dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 72257e252bfSMichael Neumann } else 72357e252bfSMichael Neumann dll_state_on = eg_pi->dll_default_on; 72457e252bfSMichael Neumann 72557e252bfSMichael Neumann ret = cypress_populate_mclk_value(rdev, 72657e252bfSMichael Neumann pl->sclk, 72757e252bfSMichael Neumann pl->mclk, 72857e252bfSMichael Neumann &level->mclk, 72957e252bfSMichael Neumann (level->strobeMode & SMC_STROBE_ENABLE) != 0, 73057e252bfSMichael Neumann dll_state_on); 73157e252bfSMichael Neumann } else { 73257e252bfSMichael Neumann ret = cypress_populate_mclk_value(rdev, 73357e252bfSMichael Neumann pl->sclk, 73457e252bfSMichael Neumann pl->mclk, 73557e252bfSMichael Neumann &level->mclk, 73657e252bfSMichael Neumann true, 73757e252bfSMichael Neumann true); 73857e252bfSMichael Neumann } 73957e252bfSMichael Neumann if (ret) 74057e252bfSMichael Neumann return ret; 74157e252bfSMichael Neumann 74257e252bfSMichael Neumann ret = cypress_populate_voltage_value(rdev, 74357e252bfSMichael Neumann &eg_pi->vddc_voltage_table, 74457e252bfSMichael Neumann pl->vddc, 74557e252bfSMichael Neumann &level->vddc); 74657e252bfSMichael Neumann if (ret) 74757e252bfSMichael Neumann return ret; 74857e252bfSMichael Neumann 74957e252bfSMichael Neumann if (eg_pi->vddci_control) { 75057e252bfSMichael Neumann ret = cypress_populate_voltage_value(rdev, 75157e252bfSMichael Neumann &eg_pi->vddci_voltage_table, 75257e252bfSMichael Neumann pl->vddci, 75357e252bfSMichael Neumann &level->vddci); 75457e252bfSMichael Neumann if (ret) 75557e252bfSMichael Neumann return ret; 75657e252bfSMichael Neumann } 75757e252bfSMichael Neumann 75857e252bfSMichael Neumann ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 75957e252bfSMichael Neumann 76057e252bfSMichael Neumann return ret; 76157e252bfSMichael Neumann } 76257e252bfSMichael Neumann 76357e252bfSMichael Neumann static int cypress_convert_power_state_to_smc(struct radeon_device *rdev, 76457e252bfSMichael Neumann struct radeon_ps *radeon_state, 76557e252bfSMichael Neumann RV770_SMC_SWSTATE *smc_state) 76657e252bfSMichael Neumann { 76757e252bfSMichael Neumann struct rv7xx_ps *state = rv770_get_ps(radeon_state); 76857e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 76957e252bfSMichael Neumann int ret; 77057e252bfSMichael Neumann 77157e252bfSMichael Neumann if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC)) 77257e252bfSMichael Neumann smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 77357e252bfSMichael Neumann 77457e252bfSMichael Neumann ret = cypress_convert_power_level_to_smc(rdev, 77557e252bfSMichael Neumann &state->low, 77657e252bfSMichael Neumann &smc_state->levels[0], 77757e252bfSMichael Neumann PPSMC_DISPLAY_WATERMARK_LOW); 77857e252bfSMichael Neumann if (ret) 77957e252bfSMichael Neumann return ret; 78057e252bfSMichael Neumann 78157e252bfSMichael Neumann ret = cypress_convert_power_level_to_smc(rdev, 78257e252bfSMichael Neumann &state->medium, 78357e252bfSMichael Neumann &smc_state->levels[1], 78457e252bfSMichael Neumann PPSMC_DISPLAY_WATERMARK_LOW); 78557e252bfSMichael Neumann if (ret) 78657e252bfSMichael Neumann return ret; 78757e252bfSMichael Neumann 78857e252bfSMichael Neumann ret = cypress_convert_power_level_to_smc(rdev, 78957e252bfSMichael Neumann &state->high, 79057e252bfSMichael Neumann &smc_state->levels[2], 79157e252bfSMichael Neumann PPSMC_DISPLAY_WATERMARK_HIGH); 79257e252bfSMichael Neumann if (ret) 79357e252bfSMichael Neumann return ret; 79457e252bfSMichael Neumann 79557e252bfSMichael Neumann smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; 79657e252bfSMichael Neumann smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; 79757e252bfSMichael Neumann smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; 79857e252bfSMichael Neumann 79957e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) { 80057e252bfSMichael Neumann smc_state->levels[0].ACIndex = 2; 80157e252bfSMichael Neumann smc_state->levels[1].ACIndex = 3; 80257e252bfSMichael Neumann smc_state->levels[2].ACIndex = 4; 80357e252bfSMichael Neumann } else { 80457e252bfSMichael Neumann smc_state->levels[0].ACIndex = 0; 80557e252bfSMichael Neumann smc_state->levels[1].ACIndex = 0; 80657e252bfSMichael Neumann smc_state->levels[2].ACIndex = 0; 80757e252bfSMichael Neumann } 80857e252bfSMichael Neumann 80957e252bfSMichael Neumann rv770_populate_smc_sp(rdev, radeon_state, smc_state); 81057e252bfSMichael Neumann 81157e252bfSMichael Neumann return rv770_populate_smc_t(rdev, radeon_state, smc_state); 81257e252bfSMichael Neumann } 81357e252bfSMichael Neumann 81457e252bfSMichael Neumann static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry, 81557e252bfSMichael Neumann SMC_Evergreen_MCRegisterSet *data, 81657e252bfSMichael Neumann u32 num_entries, u32 valid_flag) 81757e252bfSMichael Neumann { 81857e252bfSMichael Neumann u32 i, j; 81957e252bfSMichael Neumann 82057e252bfSMichael Neumann for (i = 0, j = 0; j < num_entries; j++) { 82157e252bfSMichael Neumann if (valid_flag & (1 << j)) { 82257e252bfSMichael Neumann data->value[i] = cpu_to_be32(entry->mc_data[j]); 82357e252bfSMichael Neumann i++; 82457e252bfSMichael Neumann } 82557e252bfSMichael Neumann } 82657e252bfSMichael Neumann } 82757e252bfSMichael Neumann 82857e252bfSMichael Neumann static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 82957e252bfSMichael Neumann struct rv7xx_pl *pl, 83057e252bfSMichael Neumann SMC_Evergreen_MCRegisterSet *mc_reg_table_data) 83157e252bfSMichael Neumann { 83257e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 83357e252bfSMichael Neumann u32 i = 0; 83457e252bfSMichael Neumann 83557e252bfSMichael Neumann for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { 83657e252bfSMichael Neumann if (pl->mclk <= 83757e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 83857e252bfSMichael Neumann break; 83957e252bfSMichael Neumann } 84057e252bfSMichael Neumann 84157e252bfSMichael Neumann if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) 84257e252bfSMichael Neumann --i; 84357e252bfSMichael Neumann 84457e252bfSMichael Neumann cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], 84557e252bfSMichael Neumann mc_reg_table_data, 84657e252bfSMichael Neumann eg_pi->mc_reg_table.last, 84757e252bfSMichael Neumann eg_pi->mc_reg_table.valid_flag); 84857e252bfSMichael Neumann } 84957e252bfSMichael Neumann 85057e252bfSMichael Neumann static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 85157e252bfSMichael Neumann struct radeon_ps *radeon_state, 85257e252bfSMichael Neumann SMC_Evergreen_MCRegisters *mc_reg_table) 85357e252bfSMichael Neumann { 85457e252bfSMichael Neumann struct rv7xx_ps *state = rv770_get_ps(radeon_state); 85557e252bfSMichael Neumann 85657e252bfSMichael Neumann cypress_convert_mc_reg_table_entry_to_smc(rdev, 85757e252bfSMichael Neumann &state->low, 85857e252bfSMichael Neumann &mc_reg_table->data[2]); 85957e252bfSMichael Neumann cypress_convert_mc_reg_table_entry_to_smc(rdev, 86057e252bfSMichael Neumann &state->medium, 86157e252bfSMichael Neumann &mc_reg_table->data[3]); 86257e252bfSMichael Neumann cypress_convert_mc_reg_table_entry_to_smc(rdev, 86357e252bfSMichael Neumann &state->high, 86457e252bfSMichael Neumann &mc_reg_table->data[4]); 86557e252bfSMichael Neumann } 86657e252bfSMichael Neumann 86757e252bfSMichael Neumann int cypress_upload_sw_state(struct radeon_device *rdev, 86857e252bfSMichael Neumann struct radeon_ps *radeon_new_state) 86957e252bfSMichael Neumann { 87057e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 87157e252bfSMichael Neumann u16 address = pi->state_table_start + 87257e252bfSMichael Neumann offsetof(RV770_SMC_STATETABLE, driverState); 87357e252bfSMichael Neumann RV770_SMC_SWSTATE state = { 0 }; 87457e252bfSMichael Neumann int ret; 87557e252bfSMichael Neumann 87657e252bfSMichael Neumann ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state); 87757e252bfSMichael Neumann if (ret) 87857e252bfSMichael Neumann return ret; 87957e252bfSMichael Neumann 88057e252bfSMichael Neumann return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state, 88157e252bfSMichael Neumann sizeof(RV770_SMC_SWSTATE), 88257e252bfSMichael Neumann pi->sram_end); 88357e252bfSMichael Neumann } 88457e252bfSMichael Neumann 88557e252bfSMichael Neumann int cypress_upload_mc_reg_table(struct radeon_device *rdev, 88657e252bfSMichael Neumann struct radeon_ps *radeon_new_state) 88757e252bfSMichael Neumann { 88857e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 88957e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 89057e252bfSMichael Neumann SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; 89157e252bfSMichael Neumann u16 address; 89257e252bfSMichael Neumann 89357e252bfSMichael Neumann cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table); 89457e252bfSMichael Neumann 89557e252bfSMichael Neumann address = eg_pi->mc_reg_table_start + 89657e252bfSMichael Neumann (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]); 89757e252bfSMichael Neumann 89857e252bfSMichael Neumann return rv770_copy_bytes_to_smc(rdev, address, 89957e252bfSMichael Neumann (u8 *)&mc_reg_table.data[2], 90057e252bfSMichael Neumann sizeof(SMC_Evergreen_MCRegisterSet) * 3, 90157e252bfSMichael Neumann pi->sram_end); 90257e252bfSMichael Neumann } 90357e252bfSMichael Neumann 90457e252bfSMichael Neumann u32 cypress_calculate_burst_time(struct radeon_device *rdev, 90557e252bfSMichael Neumann u32 engine_clock, u32 memory_clock) 90657e252bfSMichael Neumann { 90757e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 90857e252bfSMichael Neumann u32 multiplier = pi->mem_gddr5 ? 1 : 2; 90957e252bfSMichael Neumann u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); 91057e252bfSMichael Neumann u32 burst_time; 91157e252bfSMichael Neumann 91257e252bfSMichael Neumann if (result <= 4) 91357e252bfSMichael Neumann burst_time = 0; 91457e252bfSMichael Neumann else if (result < 8) 91557e252bfSMichael Neumann burst_time = result - 4; 91657e252bfSMichael Neumann else { 91757e252bfSMichael Neumann burst_time = result / 2 ; 91857e252bfSMichael Neumann if (burst_time > 18) 91957e252bfSMichael Neumann burst_time = 18; 92057e252bfSMichael Neumann } 92157e252bfSMichael Neumann 92257e252bfSMichael Neumann return burst_time; 92357e252bfSMichael Neumann } 92457e252bfSMichael Neumann 92557e252bfSMichael Neumann void cypress_program_memory_timing_parameters(struct radeon_device *rdev, 92657e252bfSMichael Neumann struct radeon_ps *radeon_new_state) 92757e252bfSMichael Neumann { 92857e252bfSMichael Neumann struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state); 92957e252bfSMichael Neumann u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); 93057e252bfSMichael Neumann 93157e252bfSMichael Neumann mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK); 93257e252bfSMichael Neumann 93357e252bfSMichael Neumann mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev, 93457e252bfSMichael Neumann new_state->low.sclk, 93557e252bfSMichael Neumann new_state->low.mclk)); 93657e252bfSMichael Neumann mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev, 93757e252bfSMichael Neumann new_state->medium.sclk, 93857e252bfSMichael Neumann new_state->medium.mclk)); 93957e252bfSMichael Neumann mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev, 94057e252bfSMichael Neumann new_state->high.sclk, 94157e252bfSMichael Neumann new_state->high.mclk)); 94257e252bfSMichael Neumann 94357e252bfSMichael Neumann rv730_program_memory_timing_parameters(rdev, radeon_new_state); 94457e252bfSMichael Neumann 94557e252bfSMichael Neumann WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time); 94657e252bfSMichael Neumann } 94757e252bfSMichael Neumann 94857e252bfSMichael Neumann static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev, 94957e252bfSMichael Neumann SMC_Evergreen_MCRegisters *mc_reg_table) 95057e252bfSMichael Neumann { 95157e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 95257e252bfSMichael Neumann u32 i, j; 95357e252bfSMichael Neumann 95457e252bfSMichael Neumann for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { 95557e252bfSMichael Neumann if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { 95657e252bfSMichael Neumann mc_reg_table->address[i].s0 = 95757e252bfSMichael Neumann cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); 95857e252bfSMichael Neumann mc_reg_table->address[i].s1 = 95957e252bfSMichael Neumann cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); 96057e252bfSMichael Neumann i++; 96157e252bfSMichael Neumann } 96257e252bfSMichael Neumann } 96357e252bfSMichael Neumann 96457e252bfSMichael Neumann mc_reg_table->last = (u8)i; 96557e252bfSMichael Neumann } 96657e252bfSMichael Neumann 96757e252bfSMichael Neumann static void cypress_set_mc_reg_address_table(struct radeon_device *rdev) 96857e252bfSMichael Neumann { 96957e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 97057e252bfSMichael Neumann u32 i = 0; 97157e252bfSMichael Neumann 97257e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; 97357e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; 97457e252bfSMichael Neumann i++; 97557e252bfSMichael Neumann 97657e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; 97757e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; 97857e252bfSMichael Neumann i++; 97957e252bfSMichael Neumann 98057e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; 98157e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; 98257e252bfSMichael Neumann i++; 98357e252bfSMichael Neumann 98457e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; 98557e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; 98657e252bfSMichael Neumann i++; 98757e252bfSMichael Neumann 98857e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; 98957e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; 99057e252bfSMichael Neumann i++; 99157e252bfSMichael Neumann 99257e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; 99357e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; 99457e252bfSMichael Neumann i++; 99557e252bfSMichael Neumann 99657e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; 99757e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; 99857e252bfSMichael Neumann i++; 99957e252bfSMichael Neumann 100057e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; 100157e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; 100257e252bfSMichael Neumann i++; 100357e252bfSMichael Neumann 100457e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 100557e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; 100657e252bfSMichael Neumann i++; 100757e252bfSMichael Neumann 100857e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 100957e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; 101057e252bfSMichael Neumann i++; 101157e252bfSMichael Neumann 101257e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 101357e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; 101457e252bfSMichael Neumann i++; 101557e252bfSMichael Neumann 101657e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; 101757e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; 101857e252bfSMichael Neumann i++; 101957e252bfSMichael Neumann 102057e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; 102157e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; 102257e252bfSMichael Neumann i++; 102357e252bfSMichael Neumann 102457e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; 102557e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; 102657e252bfSMichael Neumann i++; 102757e252bfSMichael Neumann 102857e252bfSMichael Neumann eg_pi->mc_reg_table.last = (u8)i; 102957e252bfSMichael Neumann } 103057e252bfSMichael Neumann 103157e252bfSMichael Neumann static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev, 103257e252bfSMichael Neumann struct evergreen_mc_reg_entry *entry) 103357e252bfSMichael Neumann { 103457e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 103557e252bfSMichael Neumann u32 i; 103657e252bfSMichael Neumann 103757e252bfSMichael Neumann for (i = 0; i < eg_pi->mc_reg_table.last; i++) 103857e252bfSMichael Neumann entry->mc_data[i] = 103957e252bfSMichael Neumann RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); 104057e252bfSMichael Neumann 104157e252bfSMichael Neumann } 104257e252bfSMichael Neumann 104357e252bfSMichael Neumann static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev, 104457e252bfSMichael Neumann struct atom_memory_clock_range_table *range_table) 104557e252bfSMichael Neumann { 104657e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 104757e252bfSMichael Neumann u32 i, j; 104857e252bfSMichael Neumann 104957e252bfSMichael Neumann for (i = 0; i < range_table->num_entries; i++) { 105057e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = 105157e252bfSMichael Neumann range_table->mclk[i]; 105257e252bfSMichael Neumann radeon_atom_set_ac_timing(rdev, range_table->mclk[i]); 105357e252bfSMichael Neumann cypress_retrieve_ac_timing_for_one_entry(rdev, 105457e252bfSMichael Neumann &eg_pi->mc_reg_table.mc_reg_table_entry[i]); 105557e252bfSMichael Neumann } 105657e252bfSMichael Neumann 105757e252bfSMichael Neumann eg_pi->mc_reg_table.num_entries = range_table->num_entries; 105857e252bfSMichael Neumann eg_pi->mc_reg_table.valid_flag = 0; 105957e252bfSMichael Neumann 106057e252bfSMichael Neumann for (i = 0; i < eg_pi->mc_reg_table.last; i++) { 106157e252bfSMichael Neumann for (j = 1; j < range_table->num_entries; j++) { 106257e252bfSMichael Neumann if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != 106357e252bfSMichael Neumann eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { 106457e252bfSMichael Neumann eg_pi->mc_reg_table.valid_flag |= (1 << i); 106557e252bfSMichael Neumann break; 106657e252bfSMichael Neumann } 106757e252bfSMichael Neumann } 106857e252bfSMichael Neumann } 106957e252bfSMichael Neumann } 107057e252bfSMichael Neumann 107157e252bfSMichael Neumann static int cypress_initialize_mc_reg_table(struct radeon_device *rdev) 107257e252bfSMichael Neumann { 107357e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 107457e252bfSMichael Neumann u8 module_index = rv770_get_memory_module_index(rdev); 107557e252bfSMichael Neumann struct atom_memory_clock_range_table range_table = { 0 }; 107657e252bfSMichael Neumann int ret; 107757e252bfSMichael Neumann 107857e252bfSMichael Neumann ret = radeon_atom_get_mclk_range_table(rdev, 107957e252bfSMichael Neumann pi->mem_gddr5, 108057e252bfSMichael Neumann module_index, &range_table); 108157e252bfSMichael Neumann if (ret) 108257e252bfSMichael Neumann return ret; 108357e252bfSMichael Neumann 108457e252bfSMichael Neumann cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table); 108557e252bfSMichael Neumann 108657e252bfSMichael Neumann return 0; 108757e252bfSMichael Neumann } 108857e252bfSMichael Neumann 108957e252bfSMichael Neumann static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value) 109057e252bfSMichael Neumann { 109157e252bfSMichael Neumann u32 i, j; 109257e252bfSMichael Neumann u32 channels = 2; 109357e252bfSMichael Neumann 109457e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 109557e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK)) 109657e252bfSMichael Neumann channels = 4; 109757e252bfSMichael Neumann else if (rdev->family == CHIP_CEDAR) 109857e252bfSMichael Neumann channels = 1; 109957e252bfSMichael Neumann 110057e252bfSMichael Neumann for (i = 0; i < channels; i++) { 110157e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 110257e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK)) { 110357e252bfSMichael Neumann WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK); 110457e252bfSMichael Neumann WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK); 110557e252bfSMichael Neumann } else { 110657e252bfSMichael Neumann WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK); 110757e252bfSMichael Neumann WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK); 110857e252bfSMichael Neumann } 110957e252bfSMichael Neumann for (j = 0; j < rdev->usec_timeout; j++) { 111057e252bfSMichael Neumann if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value) 111157e252bfSMichael Neumann break; 1112c4ef309bSzrj udelay(1); 111357e252bfSMichael Neumann } 111457e252bfSMichael Neumann } 111557e252bfSMichael Neumann } 111657e252bfSMichael Neumann 111757e252bfSMichael Neumann static void cypress_force_mc_use_s1(struct radeon_device *rdev, 111857e252bfSMichael Neumann struct radeon_ps *radeon_boot_state) 111957e252bfSMichael Neumann { 112057e252bfSMichael Neumann struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state); 112157e252bfSMichael Neumann u32 strobe_mode; 112257e252bfSMichael Neumann u32 mc_seq_cg; 112357e252bfSMichael Neumann int i; 112457e252bfSMichael Neumann 112557e252bfSMichael Neumann if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE) 112657e252bfSMichael Neumann return; 112757e252bfSMichael Neumann 112857e252bfSMichael Neumann radeon_atom_set_ac_timing(rdev, boot_state->low.mclk); 112957e252bfSMichael Neumann radeon_mc_wait_for_idle(rdev); 113057e252bfSMichael Neumann 113157e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 113257e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK)) { 113357e252bfSMichael Neumann WREG32(MC_CONFIG_MCD, 0xf); 113457e252bfSMichael Neumann WREG32(MC_CG_CONFIG_MCD, 0xf); 113557e252bfSMichael Neumann } else { 113657e252bfSMichael Neumann WREG32(MC_CONFIG, 0xf); 113757e252bfSMichael Neumann WREG32(MC_CG_CONFIG, 0xf); 113857e252bfSMichael Neumann } 113957e252bfSMichael Neumann 114057e252bfSMichael Neumann for (i = 0; i < rdev->num_crtc; i++) 114157e252bfSMichael Neumann radeon_wait_for_vblank(rdev, i); 114257e252bfSMichael Neumann 114357e252bfSMichael Neumann WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND); 114457e252bfSMichael Neumann cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND); 114557e252bfSMichael Neumann 114657e252bfSMichael Neumann strobe_mode = cypress_get_strobe_mode_settings(rdev, 114757e252bfSMichael Neumann boot_state->low.mclk); 114857e252bfSMichael Neumann 114957e252bfSMichael Neumann mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1); 115057e252bfSMichael Neumann mc_seq_cg |= SEQ_CG_RESP(strobe_mode); 115157e252bfSMichael Neumann WREG32(MC_SEQ_CG, mc_seq_cg); 115257e252bfSMichael Neumann 115357e252bfSMichael Neumann for (i = 0; i < rdev->usec_timeout; i++) { 115457e252bfSMichael Neumann if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE) 115557e252bfSMichael Neumann break; 1156c4ef309bSzrj udelay(1); 115757e252bfSMichael Neumann } 115857e252bfSMichael Neumann 115957e252bfSMichael Neumann mc_seq_cg &= ~CG_SEQ_REQ_MASK; 116057e252bfSMichael Neumann mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME); 116157e252bfSMichael Neumann WREG32(MC_SEQ_CG, mc_seq_cg); 116257e252bfSMichael Neumann 116357e252bfSMichael Neumann cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME); 116457e252bfSMichael Neumann } 116557e252bfSMichael Neumann 116657e252bfSMichael Neumann static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev) 116757e252bfSMichael Neumann { 116857e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 116957e252bfSMichael Neumann u32 value; 117057e252bfSMichael Neumann u32 i; 117157e252bfSMichael Neumann 117257e252bfSMichael Neumann for (i = 0; i < eg_pi->mc_reg_table.last; i++) { 117357e252bfSMichael Neumann value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); 117457e252bfSMichael Neumann WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); 117557e252bfSMichael Neumann } 117657e252bfSMichael Neumann } 117757e252bfSMichael Neumann 117857e252bfSMichael Neumann static void cypress_force_mc_use_s0(struct radeon_device *rdev, 117957e252bfSMichael Neumann struct radeon_ps *radeon_boot_state) 118057e252bfSMichael Neumann { 118157e252bfSMichael Neumann struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state); 118257e252bfSMichael Neumann u32 strobe_mode; 118357e252bfSMichael Neumann u32 mc_seq_cg; 118457e252bfSMichael Neumann int i; 118557e252bfSMichael Neumann 118657e252bfSMichael Neumann cypress_copy_ac_timing_from_s1_to_s0(rdev); 118757e252bfSMichael Neumann radeon_mc_wait_for_idle(rdev); 118857e252bfSMichael Neumann 118957e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 119057e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK)) { 119157e252bfSMichael Neumann WREG32(MC_CONFIG_MCD, 0xf); 119257e252bfSMichael Neumann WREG32(MC_CG_CONFIG_MCD, 0xf); 119357e252bfSMichael Neumann } else { 119457e252bfSMichael Neumann WREG32(MC_CONFIG, 0xf); 119557e252bfSMichael Neumann WREG32(MC_CG_CONFIG, 0xf); 119657e252bfSMichael Neumann } 119757e252bfSMichael Neumann 119857e252bfSMichael Neumann for (i = 0; i < rdev->num_crtc; i++) 119957e252bfSMichael Neumann radeon_wait_for_vblank(rdev, i); 120057e252bfSMichael Neumann 120157e252bfSMichael Neumann WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND); 120257e252bfSMichael Neumann cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND); 120357e252bfSMichael Neumann 120457e252bfSMichael Neumann strobe_mode = cypress_get_strobe_mode_settings(rdev, 120557e252bfSMichael Neumann boot_state->low.mclk); 120657e252bfSMichael Neumann 120757e252bfSMichael Neumann mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0); 120857e252bfSMichael Neumann mc_seq_cg |= SEQ_CG_RESP(strobe_mode); 120957e252bfSMichael Neumann WREG32(MC_SEQ_CG, mc_seq_cg); 121057e252bfSMichael Neumann 121157e252bfSMichael Neumann for (i = 0; i < rdev->usec_timeout; i++) { 121257e252bfSMichael Neumann if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)) 121357e252bfSMichael Neumann break; 1214c4ef309bSzrj udelay(1); 121557e252bfSMichael Neumann } 121657e252bfSMichael Neumann 121757e252bfSMichael Neumann mc_seq_cg &= ~CG_SEQ_REQ_MASK; 121857e252bfSMichael Neumann mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME); 121957e252bfSMichael Neumann WREG32(MC_SEQ_CG, mc_seq_cg); 122057e252bfSMichael Neumann 122157e252bfSMichael Neumann cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME); 122257e252bfSMichael Neumann } 122357e252bfSMichael Neumann 122457e252bfSMichael Neumann static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev, 122557e252bfSMichael Neumann RV770_SMC_VOLTAGE_VALUE *voltage) 122657e252bfSMichael Neumann { 122757e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 122857e252bfSMichael Neumann 122957e252bfSMichael Neumann voltage->index = eg_pi->mvdd_high_index; 123057e252bfSMichael Neumann voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 123157e252bfSMichael Neumann 123257e252bfSMichael Neumann return 0; 123357e252bfSMichael Neumann } 123457e252bfSMichael Neumann 123557e252bfSMichael Neumann int cypress_populate_smc_initial_state(struct radeon_device *rdev, 123657e252bfSMichael Neumann struct radeon_ps *radeon_initial_state, 123757e252bfSMichael Neumann RV770_SMC_STATETABLE *table) 123857e252bfSMichael Neumann { 123957e252bfSMichael Neumann struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); 124057e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 124157e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 124257e252bfSMichael Neumann u32 a_t; 124357e252bfSMichael Neumann 124457e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = 124557e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); 124657e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = 124757e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); 124857e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = 124957e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl); 125057e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = 125157e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2); 125257e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = 125357e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl); 125457e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vDLL_CNTL = 125557e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.dll_cntl); 125657e252bfSMichael Neumann 125757e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_SS = 125857e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_ss1); 125957e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 = 126057e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.mpll_ss2); 126157e252bfSMichael Neumann 126257e252bfSMichael Neumann table->initialState.levels[0].mclk.mclk770.mclk_value = 126357e252bfSMichael Neumann cpu_to_be32(initial_state->low.mclk); 126457e252bfSMichael Neumann 126557e252bfSMichael Neumann table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 126657e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl); 126757e252bfSMichael Neumann table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 126857e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2); 126957e252bfSMichael Neumann table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 127057e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3); 127157e252bfSMichael Neumann table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 127257e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum); 127357e252bfSMichael Neumann table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 127457e252bfSMichael Neumann cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2); 127557e252bfSMichael Neumann 127657e252bfSMichael Neumann table->initialState.levels[0].sclk.sclk_value = 127757e252bfSMichael Neumann cpu_to_be32(initial_state->low.sclk); 127857e252bfSMichael Neumann 127957e252bfSMichael Neumann table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; 128057e252bfSMichael Neumann 128157e252bfSMichael Neumann table->initialState.levels[0].ACIndex = 0; 128257e252bfSMichael Neumann 128357e252bfSMichael Neumann cypress_populate_voltage_value(rdev, 128457e252bfSMichael Neumann &eg_pi->vddc_voltage_table, 128557e252bfSMichael Neumann initial_state->low.vddc, 128657e252bfSMichael Neumann &table->initialState.levels[0].vddc); 128757e252bfSMichael Neumann 128857e252bfSMichael Neumann if (eg_pi->vddci_control) 128957e252bfSMichael Neumann cypress_populate_voltage_value(rdev, 129057e252bfSMichael Neumann &eg_pi->vddci_voltage_table, 129157e252bfSMichael Neumann initial_state->low.vddci, 129257e252bfSMichael Neumann &table->initialState.levels[0].vddci); 129357e252bfSMichael Neumann 129457e252bfSMichael Neumann cypress_populate_initial_mvdd_value(rdev, 129557e252bfSMichael Neumann &table->initialState.levels[0].mvdd); 129657e252bfSMichael Neumann 129757e252bfSMichael Neumann a_t = CG_R(0xffff) | CG_L(0); 129857e252bfSMichael Neumann table->initialState.levels[0].aT = cpu_to_be32(a_t); 129957e252bfSMichael Neumann 130057e252bfSMichael Neumann table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 130157e252bfSMichael Neumann 130257e252bfSMichael Neumann 130357e252bfSMichael Neumann if (pi->boot_in_gen2) 130457e252bfSMichael Neumann table->initialState.levels[0].gen2PCIE = 1; 130557e252bfSMichael Neumann else 130657e252bfSMichael Neumann table->initialState.levels[0].gen2PCIE = 0; 130757e252bfSMichael Neumann if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) 130857e252bfSMichael Neumann table->initialState.levels[0].gen2XSP = 1; 130957e252bfSMichael Neumann else 131057e252bfSMichael Neumann table->initialState.levels[0].gen2XSP = 0; 131157e252bfSMichael Neumann 131257e252bfSMichael Neumann if (pi->mem_gddr5) { 131357e252bfSMichael Neumann table->initialState.levels[0].strobeMode = 131457e252bfSMichael Neumann cypress_get_strobe_mode_settings(rdev, 131557e252bfSMichael Neumann initial_state->low.mclk); 131657e252bfSMichael Neumann 131757e252bfSMichael Neumann if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) 131857e252bfSMichael Neumann table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG; 131957e252bfSMichael Neumann else 132057e252bfSMichael Neumann table->initialState.levels[0].mcFlags = 0; 132157e252bfSMichael Neumann } 132257e252bfSMichael Neumann 132357e252bfSMichael Neumann table->initialState.levels[1] = table->initialState.levels[0]; 132457e252bfSMichael Neumann table->initialState.levels[2] = table->initialState.levels[0]; 132557e252bfSMichael Neumann 132657e252bfSMichael Neumann table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 132757e252bfSMichael Neumann 132857e252bfSMichael Neumann return 0; 132957e252bfSMichael Neumann } 133057e252bfSMichael Neumann 133157e252bfSMichael Neumann int cypress_populate_smc_acpi_state(struct radeon_device *rdev, 133257e252bfSMichael Neumann RV770_SMC_STATETABLE *table) 133357e252bfSMichael Neumann { 133457e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 133557e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 133657e252bfSMichael Neumann u32 mpll_ad_func_cntl = 133757e252bfSMichael Neumann pi->clk_regs.rv770.mpll_ad_func_cntl; 133857e252bfSMichael Neumann u32 mpll_ad_func_cntl_2 = 133957e252bfSMichael Neumann pi->clk_regs.rv770.mpll_ad_func_cntl_2; 134057e252bfSMichael Neumann u32 mpll_dq_func_cntl = 134157e252bfSMichael Neumann pi->clk_regs.rv770.mpll_dq_func_cntl; 134257e252bfSMichael Neumann u32 mpll_dq_func_cntl_2 = 134357e252bfSMichael Neumann pi->clk_regs.rv770.mpll_dq_func_cntl_2; 134457e252bfSMichael Neumann u32 spll_func_cntl = 134557e252bfSMichael Neumann pi->clk_regs.rv770.cg_spll_func_cntl; 134657e252bfSMichael Neumann u32 spll_func_cntl_2 = 134757e252bfSMichael Neumann pi->clk_regs.rv770.cg_spll_func_cntl_2; 134857e252bfSMichael Neumann u32 spll_func_cntl_3 = 134957e252bfSMichael Neumann pi->clk_regs.rv770.cg_spll_func_cntl_3; 135057e252bfSMichael Neumann u32 mclk_pwrmgt_cntl = 135157e252bfSMichael Neumann pi->clk_regs.rv770.mclk_pwrmgt_cntl; 135257e252bfSMichael Neumann u32 dll_cntl = 135357e252bfSMichael Neumann pi->clk_regs.rv770.dll_cntl; 135457e252bfSMichael Neumann 135557e252bfSMichael Neumann table->ACPIState = table->initialState; 135657e252bfSMichael Neumann 135757e252bfSMichael Neumann table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 135857e252bfSMichael Neumann 135957e252bfSMichael Neumann if (pi->acpi_vddc) { 136057e252bfSMichael Neumann cypress_populate_voltage_value(rdev, 136157e252bfSMichael Neumann &eg_pi->vddc_voltage_table, 136257e252bfSMichael Neumann pi->acpi_vddc, 136357e252bfSMichael Neumann &table->ACPIState.levels[0].vddc); 136457e252bfSMichael Neumann if (pi->pcie_gen2) { 136557e252bfSMichael Neumann if (pi->acpi_pcie_gen2) 136657e252bfSMichael Neumann table->ACPIState.levels[0].gen2PCIE = 1; 136757e252bfSMichael Neumann else 136857e252bfSMichael Neumann table->ACPIState.levels[0].gen2PCIE = 0; 136957e252bfSMichael Neumann } else 137057e252bfSMichael Neumann table->ACPIState.levels[0].gen2PCIE = 0; 137157e252bfSMichael Neumann if (pi->acpi_pcie_gen2) 137257e252bfSMichael Neumann table->ACPIState.levels[0].gen2XSP = 1; 137357e252bfSMichael Neumann else 137457e252bfSMichael Neumann table->ACPIState.levels[0].gen2XSP = 0; 137557e252bfSMichael Neumann } else { 137657e252bfSMichael Neumann cypress_populate_voltage_value(rdev, 137757e252bfSMichael Neumann &eg_pi->vddc_voltage_table, 137857e252bfSMichael Neumann pi->min_vddc_in_table, 137957e252bfSMichael Neumann &table->ACPIState.levels[0].vddc); 138057e252bfSMichael Neumann table->ACPIState.levels[0].gen2PCIE = 0; 138157e252bfSMichael Neumann } 138257e252bfSMichael Neumann 138357e252bfSMichael Neumann if (eg_pi->acpi_vddci) { 138457e252bfSMichael Neumann if (eg_pi->vddci_control) { 138557e252bfSMichael Neumann cypress_populate_voltage_value(rdev, 138657e252bfSMichael Neumann &eg_pi->vddci_voltage_table, 138757e252bfSMichael Neumann eg_pi->acpi_vddci, 138857e252bfSMichael Neumann &table->ACPIState.levels[0].vddci); 138957e252bfSMichael Neumann } 139057e252bfSMichael Neumann } 139157e252bfSMichael Neumann 139257e252bfSMichael Neumann mpll_ad_func_cntl &= ~PDNB; 139357e252bfSMichael Neumann 139457e252bfSMichael Neumann mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; 139557e252bfSMichael Neumann 139657e252bfSMichael Neumann if (pi->mem_gddr5) 139757e252bfSMichael Neumann mpll_dq_func_cntl &= ~PDNB; 139857e252bfSMichael Neumann mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; 139957e252bfSMichael Neumann 140057e252bfSMichael Neumann mclk_pwrmgt_cntl |= (MRDCKA0_RESET | 140157e252bfSMichael Neumann MRDCKA1_RESET | 140257e252bfSMichael Neumann MRDCKB0_RESET | 140357e252bfSMichael Neumann MRDCKB1_RESET | 140457e252bfSMichael Neumann MRDCKC0_RESET | 140557e252bfSMichael Neumann MRDCKC1_RESET | 140657e252bfSMichael Neumann MRDCKD0_RESET | 140757e252bfSMichael Neumann MRDCKD1_RESET); 140857e252bfSMichael Neumann 140957e252bfSMichael Neumann mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB | 141057e252bfSMichael Neumann MRDCKA1_PDNB | 141157e252bfSMichael Neumann MRDCKB0_PDNB | 141257e252bfSMichael Neumann MRDCKB1_PDNB | 141357e252bfSMichael Neumann MRDCKC0_PDNB | 141457e252bfSMichael Neumann MRDCKC1_PDNB | 141557e252bfSMichael Neumann MRDCKD0_PDNB | 141657e252bfSMichael Neumann MRDCKD1_PDNB); 141757e252bfSMichael Neumann 141857e252bfSMichael Neumann dll_cntl |= (MRDCKA0_BYPASS | 141957e252bfSMichael Neumann MRDCKA1_BYPASS | 142057e252bfSMichael Neumann MRDCKB0_BYPASS | 142157e252bfSMichael Neumann MRDCKB1_BYPASS | 142257e252bfSMichael Neumann MRDCKC0_BYPASS | 142357e252bfSMichael Neumann MRDCKC1_BYPASS | 142457e252bfSMichael Neumann MRDCKD0_BYPASS | 142557e252bfSMichael Neumann MRDCKD1_BYPASS); 142657e252bfSMichael Neumann 142757e252bfSMichael Neumann /* evergreen only */ 142857e252bfSMichael Neumann if (rdev->family <= CHIP_HEMLOCK) 142957e252bfSMichael Neumann spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; 143057e252bfSMichael Neumann 143157e252bfSMichael Neumann spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 143257e252bfSMichael Neumann spll_func_cntl_2 |= SCLK_MUX_SEL(4); 143357e252bfSMichael Neumann 143457e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = 143557e252bfSMichael Neumann cpu_to_be32(mpll_ad_func_cntl); 143657e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = 143757e252bfSMichael Neumann cpu_to_be32(mpll_ad_func_cntl_2); 143857e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = 143957e252bfSMichael Neumann cpu_to_be32(mpll_dq_func_cntl); 144057e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = 144157e252bfSMichael Neumann cpu_to_be32(mpll_dq_func_cntl_2); 144257e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = 144357e252bfSMichael Neumann cpu_to_be32(mclk_pwrmgt_cntl); 144457e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); 144557e252bfSMichael Neumann 144657e252bfSMichael Neumann table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; 144757e252bfSMichael Neumann 144857e252bfSMichael Neumann table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 144957e252bfSMichael Neumann cpu_to_be32(spll_func_cntl); 145057e252bfSMichael Neumann table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 145157e252bfSMichael Neumann cpu_to_be32(spll_func_cntl_2); 145257e252bfSMichael Neumann table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 145357e252bfSMichael Neumann cpu_to_be32(spll_func_cntl_3); 145457e252bfSMichael Neumann 145557e252bfSMichael Neumann table->ACPIState.levels[0].sclk.sclk_value = 0; 145657e252bfSMichael Neumann 145757e252bfSMichael Neumann cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 145857e252bfSMichael Neumann 145957e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) 146057e252bfSMichael Neumann table->ACPIState.levels[0].ACIndex = 1; 146157e252bfSMichael Neumann 146257e252bfSMichael Neumann table->ACPIState.levels[1] = table->ACPIState.levels[0]; 146357e252bfSMichael Neumann table->ACPIState.levels[2] = table->ACPIState.levels[0]; 146457e252bfSMichael Neumann 146557e252bfSMichael Neumann return 0; 146657e252bfSMichael Neumann } 146757e252bfSMichael Neumann 146857e252bfSMichael Neumann static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 146957e252bfSMichael Neumann struct atom_voltage_table *voltage_table) 147057e252bfSMichael Neumann { 147157e252bfSMichael Neumann unsigned int i, diff; 147257e252bfSMichael Neumann 147357e252bfSMichael Neumann if (voltage_table->count <= MAX_NO_VREG_STEPS) 147457e252bfSMichael Neumann return; 147557e252bfSMichael Neumann 147657e252bfSMichael Neumann diff = voltage_table->count - MAX_NO_VREG_STEPS; 147757e252bfSMichael Neumann 147857e252bfSMichael Neumann for (i= 0; i < MAX_NO_VREG_STEPS; i++) 147957e252bfSMichael Neumann voltage_table->entries[i] = voltage_table->entries[i + diff]; 148057e252bfSMichael Neumann 148157e252bfSMichael Neumann voltage_table->count = MAX_NO_VREG_STEPS; 148257e252bfSMichael Neumann } 148357e252bfSMichael Neumann 148457e252bfSMichael Neumann int cypress_construct_voltage_tables(struct radeon_device *rdev) 148557e252bfSMichael Neumann { 148657e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 148757e252bfSMichael Neumann int ret; 148857e252bfSMichael Neumann 148957e252bfSMichael Neumann ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0, 149057e252bfSMichael Neumann &eg_pi->vddc_voltage_table); 149157e252bfSMichael Neumann if (ret) 149257e252bfSMichael Neumann return ret; 149357e252bfSMichael Neumann 149457e252bfSMichael Neumann if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS) 149557e252bfSMichael Neumann cypress_trim_voltage_table_to_fit_state_table(rdev, 149657e252bfSMichael Neumann &eg_pi->vddc_voltage_table); 149757e252bfSMichael Neumann 149857e252bfSMichael Neumann if (eg_pi->vddci_control) { 149957e252bfSMichael Neumann ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0, 150057e252bfSMichael Neumann &eg_pi->vddci_voltage_table); 150157e252bfSMichael Neumann if (ret) 150257e252bfSMichael Neumann return ret; 150357e252bfSMichael Neumann 150457e252bfSMichael Neumann if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS) 150557e252bfSMichael Neumann cypress_trim_voltage_table_to_fit_state_table(rdev, 150657e252bfSMichael Neumann &eg_pi->vddci_voltage_table); 150757e252bfSMichael Neumann } 150857e252bfSMichael Neumann 150957e252bfSMichael Neumann return 0; 151057e252bfSMichael Neumann } 151157e252bfSMichael Neumann 151257e252bfSMichael Neumann static void cypress_populate_smc_voltage_table(struct radeon_device *rdev, 151357e252bfSMichael Neumann struct atom_voltage_table *voltage_table, 151457e252bfSMichael Neumann RV770_SMC_STATETABLE *table) 151557e252bfSMichael Neumann { 151657e252bfSMichael Neumann unsigned int i; 151757e252bfSMichael Neumann 151857e252bfSMichael Neumann for (i = 0; i < voltage_table->count; i++) { 151957e252bfSMichael Neumann table->highSMIO[i] = 0; 152057e252bfSMichael Neumann table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 152157e252bfSMichael Neumann } 152257e252bfSMichael Neumann } 152357e252bfSMichael Neumann 152457e252bfSMichael Neumann int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 152557e252bfSMichael Neumann RV770_SMC_STATETABLE *table) 152657e252bfSMichael Neumann { 152757e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 152857e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 152957e252bfSMichael Neumann unsigned char i; 153057e252bfSMichael Neumann 153157e252bfSMichael Neumann if (eg_pi->vddc_voltage_table.count) { 153257e252bfSMichael Neumann cypress_populate_smc_voltage_table(rdev, 153357e252bfSMichael Neumann &eg_pi->vddc_voltage_table, 153457e252bfSMichael Neumann table); 153557e252bfSMichael Neumann 153657e252bfSMichael Neumann table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0; 153757e252bfSMichael Neumann table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] = 153857e252bfSMichael Neumann cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 153957e252bfSMichael Neumann 154057e252bfSMichael Neumann for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 154157e252bfSMichael Neumann if (pi->max_vddc_in_table <= 154257e252bfSMichael Neumann eg_pi->vddc_voltage_table.entries[i].value) { 154357e252bfSMichael Neumann table->maxVDDCIndexInPPTable = i; 154457e252bfSMichael Neumann break; 154557e252bfSMichael Neumann } 154657e252bfSMichael Neumann } 154757e252bfSMichael Neumann } 154857e252bfSMichael Neumann 154957e252bfSMichael Neumann if (eg_pi->vddci_voltage_table.count) { 155057e252bfSMichael Neumann cypress_populate_smc_voltage_table(rdev, 155157e252bfSMichael Neumann &eg_pi->vddci_voltage_table, 155257e252bfSMichael Neumann table); 155357e252bfSMichael Neumann 155457e252bfSMichael Neumann table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0; 155557e252bfSMichael Neumann table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 1556*c6f73aabSFrançois Tigeot cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 155757e252bfSMichael Neumann } 155857e252bfSMichael Neumann 155957e252bfSMichael Neumann return 0; 156057e252bfSMichael Neumann } 156157e252bfSMichael Neumann 156257e252bfSMichael Neumann static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info) 156357e252bfSMichael Neumann { 156457e252bfSMichael Neumann if ((memory_info->mem_type == MEM_TYPE_GDDR3) || 156557e252bfSMichael Neumann (memory_info->mem_type == MEM_TYPE_DDR3)) 156657e252bfSMichael Neumann return 30000; 156757e252bfSMichael Neumann 156857e252bfSMichael Neumann return 0; 156957e252bfSMichael Neumann } 157057e252bfSMichael Neumann 157157e252bfSMichael Neumann int cypress_get_mvdd_configuration(struct radeon_device *rdev) 157257e252bfSMichael Neumann { 157357e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 157457e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 157557e252bfSMichael Neumann u8 module_index; 157657e252bfSMichael Neumann struct atom_memory_info memory_info; 157757e252bfSMichael Neumann u32 tmp = RREG32(GENERAL_PWRMGT); 157857e252bfSMichael Neumann 157957e252bfSMichael Neumann if (!(tmp & BACKBIAS_PAD_EN)) { 158057e252bfSMichael Neumann eg_pi->mvdd_high_index = 0; 158157e252bfSMichael Neumann eg_pi->mvdd_low_index = 1; 158257e252bfSMichael Neumann pi->mvdd_control = false; 158357e252bfSMichael Neumann return 0; 158457e252bfSMichael Neumann } 158557e252bfSMichael Neumann 158657e252bfSMichael Neumann if (tmp & BACKBIAS_VALUE) 158757e252bfSMichael Neumann eg_pi->mvdd_high_index = 1; 158857e252bfSMichael Neumann else 158957e252bfSMichael Neumann eg_pi->mvdd_high_index = 0; 159057e252bfSMichael Neumann 159157e252bfSMichael Neumann eg_pi->mvdd_low_index = 159257e252bfSMichael Neumann (eg_pi->mvdd_high_index == 0) ? 1 : 0; 159357e252bfSMichael Neumann 159457e252bfSMichael Neumann module_index = rv770_get_memory_module_index(rdev); 159557e252bfSMichael Neumann 159657e252bfSMichael Neumann if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) { 159757e252bfSMichael Neumann pi->mvdd_control = false; 159857e252bfSMichael Neumann return 0; 159957e252bfSMichael Neumann } 160057e252bfSMichael Neumann 160157e252bfSMichael Neumann pi->mvdd_split_frequency = 160257e252bfSMichael Neumann cypress_get_mclk_split_point(&memory_info); 160357e252bfSMichael Neumann 160457e252bfSMichael Neumann if (pi->mvdd_split_frequency == 0) { 160557e252bfSMichael Neumann pi->mvdd_control = false; 160657e252bfSMichael Neumann return 0; 160757e252bfSMichael Neumann } 160857e252bfSMichael Neumann 160957e252bfSMichael Neumann return 0; 161057e252bfSMichael Neumann } 161157e252bfSMichael Neumann 161257e252bfSMichael Neumann static int cypress_init_smc_table(struct radeon_device *rdev, 161357e252bfSMichael Neumann struct radeon_ps *radeon_boot_state) 161457e252bfSMichael Neumann { 161557e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 161657e252bfSMichael Neumann RV770_SMC_STATETABLE *table = &pi->smc_statetable; 161757e252bfSMichael Neumann int ret; 161857e252bfSMichael Neumann 161957e252bfSMichael Neumann memset(table, 0, sizeof(RV770_SMC_STATETABLE)); 162057e252bfSMichael Neumann 162157e252bfSMichael Neumann cypress_populate_smc_voltage_tables(rdev, table); 162257e252bfSMichael Neumann 162357e252bfSMichael Neumann switch (rdev->pm.int_thermal_type) { 162457e252bfSMichael Neumann case THERMAL_TYPE_EVERGREEN: 162557e252bfSMichael Neumann case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 162657e252bfSMichael Neumann table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 162757e252bfSMichael Neumann break; 162857e252bfSMichael Neumann case THERMAL_TYPE_NONE: 162957e252bfSMichael Neumann table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 163057e252bfSMichael Neumann break; 163157e252bfSMichael Neumann default: 163257e252bfSMichael Neumann table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 163357e252bfSMichael Neumann break; 163457e252bfSMichael Neumann } 163557e252bfSMichael Neumann 163657e252bfSMichael Neumann if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 163757e252bfSMichael Neumann table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 163857e252bfSMichael Neumann 163957e252bfSMichael Neumann if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 164057e252bfSMichael Neumann table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 164157e252bfSMichael Neumann 164257e252bfSMichael Neumann if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 164357e252bfSMichael Neumann table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 164457e252bfSMichael Neumann 164557e252bfSMichael Neumann if (pi->mem_gddr5) 164657e252bfSMichael Neumann table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 164757e252bfSMichael Neumann 164857e252bfSMichael Neumann ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table); 164957e252bfSMichael Neumann if (ret) 165057e252bfSMichael Neumann return ret; 165157e252bfSMichael Neumann 165257e252bfSMichael Neumann ret = cypress_populate_smc_acpi_state(rdev, table); 165357e252bfSMichael Neumann if (ret) 165457e252bfSMichael Neumann return ret; 165557e252bfSMichael Neumann 165657e252bfSMichael Neumann table->driverState = table->initialState; 165757e252bfSMichael Neumann 165857e252bfSMichael Neumann return rv770_copy_bytes_to_smc(rdev, 165957e252bfSMichael Neumann pi->state_table_start, 166057e252bfSMichael Neumann (u8 *)table, sizeof(RV770_SMC_STATETABLE), 166157e252bfSMichael Neumann pi->sram_end); 166257e252bfSMichael Neumann } 166357e252bfSMichael Neumann 166457e252bfSMichael Neumann int cypress_populate_mc_reg_table(struct radeon_device *rdev, 166557e252bfSMichael Neumann struct radeon_ps *radeon_boot_state) 166657e252bfSMichael Neumann { 166757e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 166857e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 166957e252bfSMichael Neumann struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state); 167057e252bfSMichael Neumann SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; 167157e252bfSMichael Neumann 167257e252bfSMichael Neumann rv770_write_smc_soft_register(rdev, 167357e252bfSMichael Neumann RV770_SMC_SOFT_REGISTER_seq_index, 1); 167457e252bfSMichael Neumann 167557e252bfSMichael Neumann cypress_populate_mc_reg_addresses(rdev, &mc_reg_table); 167657e252bfSMichael Neumann 167757e252bfSMichael Neumann cypress_convert_mc_reg_table_entry_to_smc(rdev, 167857e252bfSMichael Neumann &boot_state->low, 167957e252bfSMichael Neumann &mc_reg_table.data[0]); 168057e252bfSMichael Neumann 168157e252bfSMichael Neumann cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], 168257e252bfSMichael Neumann &mc_reg_table.data[1], eg_pi->mc_reg_table.last, 168357e252bfSMichael Neumann eg_pi->mc_reg_table.valid_flag); 168457e252bfSMichael Neumann 168557e252bfSMichael Neumann cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table); 168657e252bfSMichael Neumann 168757e252bfSMichael Neumann return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start, 168857e252bfSMichael Neumann (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters), 168957e252bfSMichael Neumann pi->sram_end); 169057e252bfSMichael Neumann } 169157e252bfSMichael Neumann 169257e252bfSMichael Neumann int cypress_get_table_locations(struct radeon_device *rdev) 169357e252bfSMichael Neumann { 169457e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 169557e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 169657e252bfSMichael Neumann u32 tmp; 169757e252bfSMichael Neumann int ret; 169857e252bfSMichael Neumann 169957e252bfSMichael Neumann ret = rv770_read_smc_sram_dword(rdev, 170057e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION + 170157e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_stateTable, 170257e252bfSMichael Neumann &tmp, pi->sram_end); 170357e252bfSMichael Neumann if (ret) 170457e252bfSMichael Neumann return ret; 170557e252bfSMichael Neumann 170657e252bfSMichael Neumann pi->state_table_start = (u16)tmp; 170757e252bfSMichael Neumann 170857e252bfSMichael Neumann ret = rv770_read_smc_sram_dword(rdev, 170957e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION + 171057e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters, 171157e252bfSMichael Neumann &tmp, pi->sram_end); 171257e252bfSMichael Neumann if (ret) 171357e252bfSMichael Neumann return ret; 171457e252bfSMichael Neumann 171557e252bfSMichael Neumann pi->soft_regs_start = (u16)tmp; 171657e252bfSMichael Neumann 171757e252bfSMichael Neumann ret = rv770_read_smc_sram_dword(rdev, 171857e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION + 171957e252bfSMichael Neumann EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable, 172057e252bfSMichael Neumann &tmp, pi->sram_end); 172157e252bfSMichael Neumann if (ret) 172257e252bfSMichael Neumann return ret; 172357e252bfSMichael Neumann 172457e252bfSMichael Neumann eg_pi->mc_reg_table_start = (u16)tmp; 172557e252bfSMichael Neumann 172657e252bfSMichael Neumann return 0; 172757e252bfSMichael Neumann } 172857e252bfSMichael Neumann 172957e252bfSMichael Neumann void cypress_enable_display_gap(struct radeon_device *rdev) 173057e252bfSMichael Neumann { 173157e252bfSMichael Neumann u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 173257e252bfSMichael Neumann 173357e252bfSMichael Neumann tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 173457e252bfSMichael Neumann tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 173557e252bfSMichael Neumann DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 173657e252bfSMichael Neumann 173757e252bfSMichael Neumann tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 173857e252bfSMichael Neumann tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 173957e252bfSMichael Neumann DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 174057e252bfSMichael Neumann WREG32(CG_DISPLAY_GAP_CNTL, tmp); 174157e252bfSMichael Neumann } 174257e252bfSMichael Neumann 174357e252bfSMichael Neumann static void cypress_program_display_gap(struct radeon_device *rdev) 174457e252bfSMichael Neumann { 174557e252bfSMichael Neumann u32 tmp, pipe; 174657e252bfSMichael Neumann int i; 174757e252bfSMichael Neumann 174857e252bfSMichael Neumann tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 174957e252bfSMichael Neumann if (rdev->pm.dpm.new_active_crtc_count > 0) 175057e252bfSMichael Neumann tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 175157e252bfSMichael Neumann else 175257e252bfSMichael Neumann tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 175357e252bfSMichael Neumann 175457e252bfSMichael Neumann if (rdev->pm.dpm.new_active_crtc_count > 1) 175557e252bfSMichael Neumann tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 175657e252bfSMichael Neumann else 175757e252bfSMichael Neumann tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 175857e252bfSMichael Neumann 175957e252bfSMichael Neumann WREG32(CG_DISPLAY_GAP_CNTL, tmp); 176057e252bfSMichael Neumann 176157e252bfSMichael Neumann tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 176257e252bfSMichael Neumann pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 176357e252bfSMichael Neumann 176457e252bfSMichael Neumann if ((rdev->pm.dpm.new_active_crtc_count > 0) && 176557e252bfSMichael Neumann (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 176657e252bfSMichael Neumann /* find the first active crtc */ 176757e252bfSMichael Neumann for (i = 0; i < rdev->num_crtc; i++) { 176857e252bfSMichael Neumann if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 176957e252bfSMichael Neumann break; 177057e252bfSMichael Neumann } 177157e252bfSMichael Neumann if (i == rdev->num_crtc) 177257e252bfSMichael Neumann pipe = 0; 177357e252bfSMichael Neumann else 177457e252bfSMichael Neumann pipe = i; 177557e252bfSMichael Neumann 177657e252bfSMichael Neumann tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 177757e252bfSMichael Neumann tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 177857e252bfSMichael Neumann WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 177957e252bfSMichael Neumann } 178057e252bfSMichael Neumann 178157e252bfSMichael Neumann cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 178257e252bfSMichael Neumann } 178357e252bfSMichael Neumann 178457e252bfSMichael Neumann void cypress_dpm_setup_asic(struct radeon_device *rdev) 178557e252bfSMichael Neumann { 178657e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 178757e252bfSMichael Neumann 178857e252bfSMichael Neumann rv740_read_clock_registers(rdev); 178957e252bfSMichael Neumann rv770_read_voltage_smio_registers(rdev); 179057e252bfSMichael Neumann rv770_get_max_vddc(rdev); 179157e252bfSMichael Neumann rv770_get_memory_type(rdev); 179257e252bfSMichael Neumann 179357e252bfSMichael Neumann if (eg_pi->pcie_performance_request) 179457e252bfSMichael Neumann eg_pi->pcie_performance_request_registered = false; 179557e252bfSMichael Neumann 179657e252bfSMichael Neumann if (eg_pi->pcie_performance_request) 179757e252bfSMichael Neumann cypress_advertise_gen2_capability(rdev); 179857e252bfSMichael Neumann 179957e252bfSMichael Neumann rv770_get_pcie_gen2_status(rdev); 180057e252bfSMichael Neumann 180157e252bfSMichael Neumann rv770_enable_acpi_pm(rdev); 180257e252bfSMichael Neumann } 180357e252bfSMichael Neumann 180457e252bfSMichael Neumann int cypress_dpm_enable(struct radeon_device *rdev) 180557e252bfSMichael Neumann { 180657e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 180757e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 180857e252bfSMichael Neumann struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 180957e252bfSMichael Neumann int ret; 181057e252bfSMichael Neumann 181157e252bfSMichael Neumann if (pi->gfx_clock_gating) 181257e252bfSMichael Neumann rv770_restore_cgcg(rdev); 181357e252bfSMichael Neumann 181457e252bfSMichael Neumann if (rv770_dpm_enabled(rdev)) 181557e252bfSMichael Neumann return -EINVAL; 181657e252bfSMichael Neumann 181757e252bfSMichael Neumann if (pi->voltage_control) { 181857e252bfSMichael Neumann rv770_enable_voltage_control(rdev, true); 181957e252bfSMichael Neumann ret = cypress_construct_voltage_tables(rdev); 182057e252bfSMichael Neumann if (ret) { 182157e252bfSMichael Neumann DRM_ERROR("cypress_construct_voltage_tables failed\n"); 182257e252bfSMichael Neumann return ret; 182357e252bfSMichael Neumann } 182457e252bfSMichael Neumann } 182557e252bfSMichael Neumann 182657e252bfSMichael Neumann if (pi->mvdd_control) { 182757e252bfSMichael Neumann ret = cypress_get_mvdd_configuration(rdev); 182857e252bfSMichael Neumann if (ret) { 182957e252bfSMichael Neumann DRM_ERROR("cypress_get_mvdd_configuration failed\n"); 183057e252bfSMichael Neumann return ret; 183157e252bfSMichael Neumann } 183257e252bfSMichael Neumann } 183357e252bfSMichael Neumann 183457e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) { 183557e252bfSMichael Neumann cypress_set_mc_reg_address_table(rdev); 183657e252bfSMichael Neumann cypress_force_mc_use_s0(rdev, boot_ps); 183757e252bfSMichael Neumann ret = cypress_initialize_mc_reg_table(rdev); 183857e252bfSMichael Neumann if (ret) 183957e252bfSMichael Neumann eg_pi->dynamic_ac_timing = false; 184057e252bfSMichael Neumann cypress_force_mc_use_s1(rdev, boot_ps); 184157e252bfSMichael Neumann } 184257e252bfSMichael Neumann 184357e252bfSMichael Neumann if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) 184457e252bfSMichael Neumann rv770_enable_backbias(rdev, true); 184557e252bfSMichael Neumann 184657e252bfSMichael Neumann if (pi->dynamic_ss) 184757e252bfSMichael Neumann cypress_enable_spread_spectrum(rdev, true); 184857e252bfSMichael Neumann 184957e252bfSMichael Neumann if (pi->thermal_protection) 185057e252bfSMichael Neumann rv770_enable_thermal_protection(rdev, true); 185157e252bfSMichael Neumann 185257e252bfSMichael Neumann rv770_setup_bsp(rdev); 185357e252bfSMichael Neumann rv770_program_git(rdev); 185457e252bfSMichael Neumann rv770_program_tp(rdev); 185557e252bfSMichael Neumann rv770_program_tpp(rdev); 185657e252bfSMichael Neumann rv770_program_sstp(rdev); 185757e252bfSMichael Neumann rv770_program_engine_speed_parameters(rdev); 185857e252bfSMichael Neumann cypress_enable_display_gap(rdev); 185957e252bfSMichael Neumann rv770_program_vc(rdev); 186057e252bfSMichael Neumann 186157e252bfSMichael Neumann if (pi->dynamic_pcie_gen2) 186257e252bfSMichael Neumann cypress_enable_dynamic_pcie_gen2(rdev, true); 186357e252bfSMichael Neumann 186457e252bfSMichael Neumann ret = rv770_upload_firmware(rdev); 186557e252bfSMichael Neumann if (ret) { 186657e252bfSMichael Neumann DRM_ERROR("rv770_upload_firmware failed\n"); 186757e252bfSMichael Neumann return ret; 186857e252bfSMichael Neumann } 186957e252bfSMichael Neumann 187057e252bfSMichael Neumann ret = cypress_get_table_locations(rdev); 187157e252bfSMichael Neumann if (ret) { 187257e252bfSMichael Neumann DRM_ERROR("cypress_get_table_locations failed\n"); 187357e252bfSMichael Neumann return ret; 187457e252bfSMichael Neumann } 187557e252bfSMichael Neumann ret = cypress_init_smc_table(rdev, boot_ps); 187657e252bfSMichael Neumann if (ret) { 187757e252bfSMichael Neumann DRM_ERROR("cypress_init_smc_table failed\n"); 187857e252bfSMichael Neumann return ret; 187957e252bfSMichael Neumann } 188057e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) { 188157e252bfSMichael Neumann ret = cypress_populate_mc_reg_table(rdev, boot_ps); 188257e252bfSMichael Neumann if (ret) { 188357e252bfSMichael Neumann DRM_ERROR("cypress_populate_mc_reg_table failed\n"); 188457e252bfSMichael Neumann return ret; 188557e252bfSMichael Neumann } 188657e252bfSMichael Neumann } 188757e252bfSMichael Neumann 188857e252bfSMichael Neumann cypress_program_response_times(rdev); 188957e252bfSMichael Neumann 189057e252bfSMichael Neumann r7xx_start_smc(rdev); 189157e252bfSMichael Neumann 189257e252bfSMichael Neumann ret = cypress_notify_smc_display_change(rdev, false); 189357e252bfSMichael Neumann if (ret) { 189457e252bfSMichael Neumann DRM_ERROR("cypress_notify_smc_display_change failed\n"); 189557e252bfSMichael Neumann return ret; 189657e252bfSMichael Neumann } 189757e252bfSMichael Neumann cypress_enable_sclk_control(rdev, true); 189857e252bfSMichael Neumann 189957e252bfSMichael Neumann if (eg_pi->memory_transition) 190057e252bfSMichael Neumann cypress_enable_mclk_control(rdev, true); 190157e252bfSMichael Neumann 190257e252bfSMichael Neumann cypress_start_dpm(rdev); 190357e252bfSMichael Neumann 190457e252bfSMichael Neumann if (pi->gfx_clock_gating) 190557e252bfSMichael Neumann cypress_gfx_clock_gating_enable(rdev, true); 190657e252bfSMichael Neumann 190757e252bfSMichael Neumann if (pi->mg_clock_gating) 190857e252bfSMichael Neumann cypress_mg_clock_gating_enable(rdev, true); 190957e252bfSMichael Neumann 191057e252bfSMichael Neumann rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 191157e252bfSMichael Neumann 191257e252bfSMichael Neumann return 0; 191357e252bfSMichael Neumann } 191457e252bfSMichael Neumann 191557e252bfSMichael Neumann void cypress_dpm_disable(struct radeon_device *rdev) 191657e252bfSMichael Neumann { 191757e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 191857e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 191957e252bfSMichael Neumann struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 192057e252bfSMichael Neumann 192157e252bfSMichael Neumann if (!rv770_dpm_enabled(rdev)) 192257e252bfSMichael Neumann return; 192357e252bfSMichael Neumann 192457e252bfSMichael Neumann rv770_clear_vc(rdev); 192557e252bfSMichael Neumann 192657e252bfSMichael Neumann if (pi->thermal_protection) 192757e252bfSMichael Neumann rv770_enable_thermal_protection(rdev, false); 192857e252bfSMichael Neumann 192957e252bfSMichael Neumann if (pi->dynamic_pcie_gen2) 193057e252bfSMichael Neumann cypress_enable_dynamic_pcie_gen2(rdev, false); 193157e252bfSMichael Neumann 193257e252bfSMichael Neumann if (rdev->irq.installed && 193357e252bfSMichael Neumann r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 193457e252bfSMichael Neumann rdev->irq.dpm_thermal = false; 193557e252bfSMichael Neumann radeon_irq_set(rdev); 193657e252bfSMichael Neumann } 193757e252bfSMichael Neumann 193857e252bfSMichael Neumann if (pi->gfx_clock_gating) 193957e252bfSMichael Neumann cypress_gfx_clock_gating_enable(rdev, false); 194057e252bfSMichael Neumann 194157e252bfSMichael Neumann if (pi->mg_clock_gating) 194257e252bfSMichael Neumann cypress_mg_clock_gating_enable(rdev, false); 194357e252bfSMichael Neumann 194457e252bfSMichael Neumann rv770_stop_dpm(rdev); 194557e252bfSMichael Neumann r7xx_stop_smc(rdev); 194657e252bfSMichael Neumann 194757e252bfSMichael Neumann cypress_enable_spread_spectrum(rdev, false); 194857e252bfSMichael Neumann 194957e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) 195057e252bfSMichael Neumann cypress_force_mc_use_s1(rdev, boot_ps); 195157e252bfSMichael Neumann 195257e252bfSMichael Neumann rv770_reset_smio_status(rdev); 195357e252bfSMichael Neumann } 195457e252bfSMichael Neumann 195557e252bfSMichael Neumann int cypress_dpm_set_power_state(struct radeon_device *rdev) 195657e252bfSMichael Neumann { 195757e252bfSMichael Neumann struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 195857e252bfSMichael Neumann struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 195957e252bfSMichael Neumann struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; 196057e252bfSMichael Neumann int ret; 196157e252bfSMichael Neumann 196257e252bfSMichael Neumann ret = rv770_restrict_performance_levels_before_switch(rdev); 196357e252bfSMichael Neumann if (ret) { 196457e252bfSMichael Neumann DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); 196557e252bfSMichael Neumann return ret; 196657e252bfSMichael Neumann } 196757e252bfSMichael Neumann if (eg_pi->pcie_performance_request) 196857e252bfSMichael Neumann cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); 196957e252bfSMichael Neumann 197057e252bfSMichael Neumann rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 197157e252bfSMichael Neumann ret = rv770_halt_smc(rdev); 197257e252bfSMichael Neumann if (ret) { 197357e252bfSMichael Neumann DRM_ERROR("rv770_halt_smc failed\n"); 197457e252bfSMichael Neumann return ret; 197557e252bfSMichael Neumann } 197657e252bfSMichael Neumann ret = cypress_upload_sw_state(rdev, new_ps); 197757e252bfSMichael Neumann if (ret) { 197857e252bfSMichael Neumann DRM_ERROR("cypress_upload_sw_state failed\n"); 197957e252bfSMichael Neumann return ret; 198057e252bfSMichael Neumann } 198157e252bfSMichael Neumann if (eg_pi->dynamic_ac_timing) { 198257e252bfSMichael Neumann ret = cypress_upload_mc_reg_table(rdev, new_ps); 198357e252bfSMichael Neumann if (ret) { 198457e252bfSMichael Neumann DRM_ERROR("cypress_upload_mc_reg_table failed\n"); 198557e252bfSMichael Neumann return ret; 198657e252bfSMichael Neumann } 198757e252bfSMichael Neumann } 198857e252bfSMichael Neumann 198957e252bfSMichael Neumann cypress_program_memory_timing_parameters(rdev, new_ps); 199057e252bfSMichael Neumann 199157e252bfSMichael Neumann ret = rv770_resume_smc(rdev); 199257e252bfSMichael Neumann if (ret) { 199357e252bfSMichael Neumann DRM_ERROR("rv770_resume_smc failed\n"); 199457e252bfSMichael Neumann return ret; 199557e252bfSMichael Neumann } 199657e252bfSMichael Neumann ret = rv770_set_sw_state(rdev); 199757e252bfSMichael Neumann if (ret) { 199857e252bfSMichael Neumann DRM_ERROR("rv770_set_sw_state failed\n"); 199957e252bfSMichael Neumann return ret; 200057e252bfSMichael Neumann } 200157e252bfSMichael Neumann rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 200257e252bfSMichael Neumann 200357e252bfSMichael Neumann if (eg_pi->pcie_performance_request) 200457e252bfSMichael Neumann cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 200557e252bfSMichael Neumann 200657e252bfSMichael Neumann return 0; 200757e252bfSMichael Neumann } 200857e252bfSMichael Neumann 200957e252bfSMichael Neumann void cypress_dpm_reset_asic(struct radeon_device *rdev) 201057e252bfSMichael Neumann { 201157e252bfSMichael Neumann rv770_restrict_performance_levels_before_switch(rdev); 201257e252bfSMichael Neumann rv770_set_boot_state(rdev); 201357e252bfSMichael Neumann } 201457e252bfSMichael Neumann 201557e252bfSMichael Neumann void cypress_dpm_display_configuration_changed(struct radeon_device *rdev) 201657e252bfSMichael Neumann { 201757e252bfSMichael Neumann cypress_program_display_gap(rdev); 201857e252bfSMichael Neumann } 201957e252bfSMichael Neumann 202057e252bfSMichael Neumann int cypress_dpm_init(struct radeon_device *rdev) 202157e252bfSMichael Neumann { 202257e252bfSMichael Neumann struct rv7xx_power_info *pi; 202357e252bfSMichael Neumann struct evergreen_power_info *eg_pi; 202457e252bfSMichael Neumann struct atom_clock_dividers dividers; 202557e252bfSMichael Neumann int ret; 202657e252bfSMichael Neumann 202757e252bfSMichael Neumann eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL); 202857e252bfSMichael Neumann if (eg_pi == NULL) 202957e252bfSMichael Neumann return -ENOMEM; 203057e252bfSMichael Neumann rdev->pm.dpm.priv = eg_pi; 203157e252bfSMichael Neumann pi = &eg_pi->rv7xx; 203257e252bfSMichael Neumann 203357e252bfSMichael Neumann rv770_get_max_vddc(rdev); 203457e252bfSMichael Neumann 203557e252bfSMichael Neumann eg_pi->ulv.supported = false; 203657e252bfSMichael Neumann pi->acpi_vddc = 0; 203757e252bfSMichael Neumann eg_pi->acpi_vddci = 0; 203857e252bfSMichael Neumann pi->min_vddc_in_table = 0; 203957e252bfSMichael Neumann pi->max_vddc_in_table = 0; 204057e252bfSMichael Neumann 2041*c6f73aabSFrançois Tigeot ret = r600_get_platform_caps(rdev); 2042*c6f73aabSFrançois Tigeot if (ret) 2043*c6f73aabSFrançois Tigeot return ret; 2044*c6f73aabSFrançois Tigeot 204557e252bfSMichael Neumann ret = rv7xx_parse_power_table(rdev); 204657e252bfSMichael Neumann if (ret) 204757e252bfSMichael Neumann return ret; 204857e252bfSMichael Neumann 204957e252bfSMichael Neumann if (rdev->pm.dpm.voltage_response_time == 0) 205057e252bfSMichael Neumann rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 205157e252bfSMichael Neumann if (rdev->pm.dpm.backbias_response_time == 0) 205257e252bfSMichael Neumann rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 205357e252bfSMichael Neumann 205457e252bfSMichael Neumann ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 205557e252bfSMichael Neumann 0, false, ÷rs); 205657e252bfSMichael Neumann if (ret) 205757e252bfSMichael Neumann pi->ref_div = dividers.ref_div + 1; 205857e252bfSMichael Neumann else 205957e252bfSMichael Neumann pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 206057e252bfSMichael Neumann 206157e252bfSMichael Neumann pi->mclk_strobe_mode_threshold = 40000; 206257e252bfSMichael Neumann pi->mclk_edc_enable_threshold = 40000; 206357e252bfSMichael Neumann eg_pi->mclk_edc_wr_enable_threshold = 40000; 206457e252bfSMichael Neumann 206557e252bfSMichael Neumann pi->rlp = RV770_RLP_DFLT; 206657e252bfSMichael Neumann pi->rmp = RV770_RMP_DFLT; 206757e252bfSMichael Neumann pi->lhp = RV770_LHP_DFLT; 206857e252bfSMichael Neumann pi->lmp = RV770_LMP_DFLT; 206957e252bfSMichael Neumann 207057e252bfSMichael Neumann pi->voltage_control = 207157e252bfSMichael Neumann radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); 207257e252bfSMichael Neumann 207357e252bfSMichael Neumann pi->mvdd_control = 207457e252bfSMichael Neumann radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 207557e252bfSMichael Neumann 207657e252bfSMichael Neumann eg_pi->vddci_control = 207757e252bfSMichael Neumann radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 207857e252bfSMichael Neumann 207957e252bfSMichael Neumann rv770_get_engine_memory_ss(rdev); 208057e252bfSMichael Neumann 208157e252bfSMichael Neumann pi->asi = RV770_ASI_DFLT; 208257e252bfSMichael Neumann pi->pasi = CYPRESS_HASI_DFLT; 208357e252bfSMichael Neumann pi->vrc = CYPRESS_VRC_DFLT; 208457e252bfSMichael Neumann 208557e252bfSMichael Neumann pi->power_gating = false; 208657e252bfSMichael Neumann 208757e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 208857e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK)) 208957e252bfSMichael Neumann pi->gfx_clock_gating = false; 209057e252bfSMichael Neumann else 209157e252bfSMichael Neumann pi->gfx_clock_gating = true; 209257e252bfSMichael Neumann 209357e252bfSMichael Neumann pi->mg_clock_gating = true; 209457e252bfSMichael Neumann pi->mgcgtssm = true; 209557e252bfSMichael Neumann eg_pi->ls_clock_gating = false; 209657e252bfSMichael Neumann eg_pi->sclk_deep_sleep = false; 209757e252bfSMichael Neumann 209857e252bfSMichael Neumann pi->dynamic_pcie_gen2 = true; 209957e252bfSMichael Neumann 210057e252bfSMichael Neumann if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 210157e252bfSMichael Neumann pi->thermal_protection = true; 210257e252bfSMichael Neumann else 210357e252bfSMichael Neumann pi->thermal_protection = false; 210457e252bfSMichael Neumann 210557e252bfSMichael Neumann pi->display_gap = true; 210657e252bfSMichael Neumann 210757e252bfSMichael Neumann if (rdev->flags & RADEON_IS_MOBILITY) 210857e252bfSMichael Neumann pi->dcodt = true; 210957e252bfSMichael Neumann else 211057e252bfSMichael Neumann pi->dcodt = false; 211157e252bfSMichael Neumann 211257e252bfSMichael Neumann pi->ulps = true; 211357e252bfSMichael Neumann 211457e252bfSMichael Neumann eg_pi->dynamic_ac_timing = true; 211557e252bfSMichael Neumann eg_pi->abm = true; 211657e252bfSMichael Neumann eg_pi->mcls = true; 211757e252bfSMichael Neumann eg_pi->light_sleep = true; 211857e252bfSMichael Neumann eg_pi->memory_transition = true; 211957e252bfSMichael Neumann #if defined(CONFIG_ACPI) 212057e252bfSMichael Neumann eg_pi->pcie_performance_request = 212157e252bfSMichael Neumann radeon_acpi_is_pcie_performance_request_supported(rdev); 212257e252bfSMichael Neumann #else 212357e252bfSMichael Neumann eg_pi->pcie_performance_request = false; 212457e252bfSMichael Neumann #endif 212557e252bfSMichael Neumann 212657e252bfSMichael Neumann if ((rdev->family == CHIP_CYPRESS) || 212757e252bfSMichael Neumann (rdev->family == CHIP_HEMLOCK) || 212857e252bfSMichael Neumann (rdev->family == CHIP_JUNIPER)) 212957e252bfSMichael Neumann eg_pi->dll_default_on = true; 213057e252bfSMichael Neumann else 213157e252bfSMichael Neumann eg_pi->dll_default_on = false; 213257e252bfSMichael Neumann 213357e252bfSMichael Neumann eg_pi->sclk_deep_sleep = false; 213457e252bfSMichael Neumann pi->mclk_stutter_mode_threshold = 0; 213557e252bfSMichael Neumann 213657e252bfSMichael Neumann pi->sram_end = SMC_RAM_END; 213757e252bfSMichael Neumann 213857e252bfSMichael Neumann return 0; 213957e252bfSMichael Neumann } 214057e252bfSMichael Neumann 214157e252bfSMichael Neumann void cypress_dpm_fini(struct radeon_device *rdev) 214257e252bfSMichael Neumann { 214357e252bfSMichael Neumann int i; 214457e252bfSMichael Neumann 214557e252bfSMichael Neumann for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 214657e252bfSMichael Neumann kfree(rdev->pm.dpm.ps[i].ps_priv); 214757e252bfSMichael Neumann } 214857e252bfSMichael Neumann kfree(rdev->pm.dpm.ps); 214957e252bfSMichael Neumann kfree(rdev->pm.dpm.priv); 215057e252bfSMichael Neumann } 215157e252bfSMichael Neumann 215257e252bfSMichael Neumann bool cypress_dpm_vblank_too_short(struct radeon_device *rdev) 215357e252bfSMichael Neumann { 215457e252bfSMichael Neumann struct rv7xx_power_info *pi = rv770_get_pi(rdev); 215557e252bfSMichael Neumann u32 vblank_time = r600_dpm_get_vblank_time(rdev); 21564cd92098Szrj /* we never hit the non-gddr5 limit so disable it */ 21574cd92098Szrj u32 switch_limit = pi->mem_gddr5 ? 450 : 0; 215857e252bfSMichael Neumann 215957e252bfSMichael Neumann if (vblank_time < switch_limit) 216057e252bfSMichael Neumann return true; 216157e252bfSMichael Neumann else 216257e252bfSMichael Neumann return false; 216357e252bfSMichael Neumann 216457e252bfSMichael Neumann } 2165