1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * Copyright 2014 Rafał Miłecki 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "radeon_audio.h" 28 #include "r600d.h" 29 30 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 31 u8 *sadb, int sad_count); 32 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 33 u8 *sadb, int sad_count) 34 { 35 struct radeon_device *rdev = encoder->dev->dev_private; 36 u32 tmp; 37 38 /* program the speaker allocation */ 39 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 40 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 41 /* set HDMI mode */ 42 tmp |= HDMI_CONNECTION; 43 if (sad_count) 44 tmp |= SPEAKER_ALLOCATION(sadb[0]); 45 else 46 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 47 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 48 } 49 50 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 51 u8 *sadb, int sad_count); 52 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 53 u8 *sadb, int sad_count) 54 { 55 struct radeon_device *rdev = encoder->dev->dev_private; 56 u32 tmp; 57 58 /* program the speaker allocation */ 59 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 60 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); 61 /* set DP mode */ 62 tmp |= DP_CONNECTION; 63 if (sad_count) 64 tmp |= SPEAKER_ALLOCATION(sadb[0]); 65 else 66 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 67 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 68 } 69 70 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, 71 struct cea_sad *sads, int sad_count); 72 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, 73 struct cea_sad *sads, int sad_count) 74 { 75 int i; 76 struct radeon_device *rdev = encoder->dev->dev_private; 77 static const u16 eld_reg_to_type[][2] = { 78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 84 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 85 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 86 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 87 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 88 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 89 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 90 }; 91 92 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 93 u32 value = 0; 94 u8 stereo_freqs = 0; 95 int max_channels = -1; 96 int j; 97 98 for (j = 0; j < sad_count; j++) { 99 struct cea_sad *sad = &sads[j]; 100 101 if (sad->format == eld_reg_to_type[i][1]) { 102 if (sad->channels > max_channels) { 103 value = MAX_CHANNELS(sad->channels) | 104 DESCRIPTOR_BYTE_2(sad->byte2) | 105 SUPPORTED_FREQUENCIES(sad->freq); 106 max_channels = sad->channels; 107 } 108 109 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 110 stereo_freqs |= sad->freq; 111 else 112 break; 113 } 114 } 115 116 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 117 118 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); 119 } 120 } 121 122 void dce3_2_audio_set_dto(struct radeon_device *rdev, 123 struct radeon_crtc *crtc, unsigned int clock); 124 void dce3_2_audio_set_dto(struct radeon_device *rdev, 125 struct radeon_crtc *crtc, unsigned int clock) 126 { 127 struct radeon_encoder *radeon_encoder; 128 struct radeon_encoder_atom_dig *dig; 129 unsigned int max_ratio = clock / 24000; 130 u32 dto_phase; 131 u32 wallclock_ratio; 132 u32 dto_cntl; 133 134 if (!crtc) 135 return; 136 137 radeon_encoder = to_radeon_encoder(crtc->encoder); 138 dig = radeon_encoder->enc_priv; 139 140 if (!dig) 141 return; 142 143 if (max_ratio >= 8) { 144 dto_phase = 192 * 1000; 145 wallclock_ratio = 3; 146 } else if (max_ratio >= 4) { 147 dto_phase = 96 * 1000; 148 wallclock_ratio = 2; 149 } else if (max_ratio >= 2) { 150 dto_phase = 48 * 1000; 151 wallclock_ratio = 1; 152 } else { 153 dto_phase = 24 * 1000; 154 wallclock_ratio = 0; 155 } 156 157 /* Express [24MHz / target pixel clock] as an exact rational 158 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 159 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 160 */ 161 if (dig->dig_encoder == 0) { 162 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 163 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 164 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 165 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 166 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); 167 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 168 } else { 169 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 170 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 171 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); 172 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); 173 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); 174 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 175 } 176 } 177 178 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, 179 const struct radeon_hdmi_acr *acr); 180 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, 181 const struct radeon_hdmi_acr *acr) 182 { 183 struct drm_device *dev = encoder->dev; 184 struct radeon_device *rdev = dev->dev_private; 185 186 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset, 187 HDMI0_ACR_SOURCE | /* select SW CTS value */ 188 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 189 190 WREG32_P(HDMI0_ACR_32_0 + offset, 191 HDMI0_ACR_CTS_32(acr->cts_32khz), 192 ~HDMI0_ACR_CTS_32_MASK); 193 WREG32_P(HDMI0_ACR_32_1 + offset, 194 HDMI0_ACR_N_32(acr->n_32khz), 195 ~HDMI0_ACR_N_32_MASK); 196 197 WREG32_P(HDMI0_ACR_44_0 + offset, 198 HDMI0_ACR_CTS_44(acr->cts_44_1khz), 199 ~HDMI0_ACR_CTS_44_MASK); 200 WREG32_P(HDMI0_ACR_44_1 + offset, 201 HDMI0_ACR_N_44(acr->n_44_1khz), 202 ~HDMI0_ACR_N_44_MASK); 203 204 WREG32_P(HDMI0_ACR_48_0 + offset, 205 HDMI0_ACR_CTS_48(acr->cts_48khz), 206 ~HDMI0_ACR_CTS_48_MASK); 207 WREG32_P(HDMI0_ACR_48_1 + offset, 208 HDMI0_ACR_N_48(acr->n_48khz), 209 ~HDMI0_ACR_N_48_MASK); 210 } 211 212 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset); 213 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset) 214 { 215 struct drm_device *dev = encoder->dev; 216 struct radeon_device *rdev = dev->dev_private; 217 218 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 219 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 220 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 221 222 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 223 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 224 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 225 226 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 227 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 228 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 229 230 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, 231 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 232 } 233 234 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute); 235 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) 236 { 237 struct drm_device *dev = encoder->dev; 238 struct radeon_device *rdev = dev->dev_private; 239 240 if (mute) 241 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); 242 else 243 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); 244 } 245