1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 29 static u32 dce6_endpoint_rreg(struct radeon_device *rdev, 30 u32 block_offset, u32 reg) 31 { 32 u32 r; 33 34 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 35 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 36 return r; 37 } 38 39 static void dce6_endpoint_wreg(struct radeon_device *rdev, 40 u32 block_offset, u32 reg, u32 v) 41 { 42 if (ASIC_IS_DCE8(rdev)) 43 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 44 else 45 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 46 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 47 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 48 } 49 50 #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) 51 #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) 52 53 54 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 55 { 56 int i; 57 u32 offset, tmp; 58 59 for (i = 0; i < rdev->audio.num_pins; i++) { 60 offset = rdev->audio.pin[i].offset; 61 tmp = RREG32_ENDPOINT(offset, 62 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 63 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 64 rdev->audio.pin[i].connected = false; 65 else 66 rdev->audio.pin[i].connected = true; 67 } 68 } 69 70 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 71 { 72 int i; 73 74 dce6_afmt_get_connected_pins(rdev); 75 76 for (i = 0; i < rdev->audio.num_pins; i++) { 77 if (rdev->audio.pin[i].connected) 78 return &rdev->audio.pin[i]; 79 } 80 DRM_ERROR("No connected audio pins found!\n"); 81 return NULL; 82 } 83 84 void dce6_afmt_select_pin(struct drm_encoder *encoder) 85 { 86 struct radeon_device *rdev = encoder->dev->dev_private; 87 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 88 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 89 u32 offset = dig->afmt->offset; 90 91 if (!dig->afmt->pin) 92 return; 93 94 WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 95 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 96 } 97 98 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) 99 { 100 struct radeon_device *rdev = encoder->dev->dev_private; 101 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 102 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 103 struct drm_connector *connector; 104 struct radeon_connector *radeon_connector = NULL; 105 u32 offset, tmp; 106 u8 *sadb; 107 int sad_count; 108 109 /* XXX: setting this register causes hangs on some asics */ 110 return; 111 112 if (!dig->afmt->pin) 113 return; 114 115 offset = dig->afmt->pin->offset; 116 117 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 118 if (connector->encoder == encoder) 119 radeon_connector = to_radeon_connector(connector); 120 } 121 122 if (!radeon_connector) { 123 DRM_ERROR("Couldn't find encoder's connector\n"); 124 return; 125 } 126 127 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 128 if (sad_count < 0) { 129 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 130 return; 131 } 132 133 /* program the speaker allocation */ 134 tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 135 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 136 /* set HDMI mode */ 137 tmp |= HDMI_CONNECTION; 138 if (sad_count) 139 tmp |= SPEAKER_ALLOCATION(sadb[0]); 140 else 141 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 142 WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 143 144 kfree(sadb); 145 } 146 147 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) 148 { 149 struct radeon_device *rdev = encoder->dev->dev_private; 150 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 151 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 152 u32 offset; 153 struct drm_connector *connector; 154 struct radeon_connector *radeon_connector = NULL; 155 struct cea_sad *sads; 156 int i, sad_count; 157 158 static const u16 eld_reg_to_type[][2] = { 159 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 160 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 161 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 162 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 163 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 164 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 165 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 166 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 167 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 168 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 169 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 170 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 171 }; 172 173 if (!dig->afmt->pin) 174 return; 175 176 offset = dig->afmt->pin->offset; 177 178 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 179 if (connector->encoder == encoder) 180 radeon_connector = to_radeon_connector(connector); 181 } 182 183 if (!radeon_connector) { 184 DRM_ERROR("Couldn't find encoder's connector\n"); 185 return; 186 } 187 188 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 189 if (sad_count < 0) { 190 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 191 return; 192 } 193 BUG_ON(!sads); 194 195 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 196 u32 value = 0; 197 int j; 198 199 for (j = 0; j < sad_count; j++) { 200 struct cea_sad *sad = &sads[j]; 201 202 if (sad->format == eld_reg_to_type[i][1]) { 203 value = MAX_CHANNELS(sad->channels) | 204 DESCRIPTOR_BYTE_2(sad->byte2) | 205 SUPPORTED_FREQUENCIES(sad->freq); 206 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 207 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 208 break; 209 } 210 } 211 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 212 } 213 214 kfree(sads); 215 } 216 217 static int dce6_audio_chipset_supported(struct radeon_device *rdev) 218 { 219 return !ASIC_IS_NODCE(rdev); 220 } 221 222 static void dce6_audio_enable(struct radeon_device *rdev, 223 struct r600_audio_pin *pin, 224 bool enable) 225 { 226 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 227 AUDIO_ENABLED); 228 DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); 229 } 230 231 static const u32 pin_offsets[7] = 232 { 233 (0x5e00 - 0x5e00), 234 (0x5e18 - 0x5e00), 235 (0x5e30 - 0x5e00), 236 (0x5e48 - 0x5e00), 237 (0x5e60 - 0x5e00), 238 (0x5e78 - 0x5e00), 239 (0x5e90 - 0x5e00), 240 }; 241 242 int dce6_audio_init(struct radeon_device *rdev) 243 { 244 int i; 245 246 if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) 247 return 0; 248 249 rdev->audio.enabled = true; 250 251 if (ASIC_IS_DCE8(rdev)) 252 rdev->audio.num_pins = 7; 253 else 254 rdev->audio.num_pins = 6; 255 256 for (i = 0; i < rdev->audio.num_pins; i++) { 257 rdev->audio.pin[i].channels = -1; 258 rdev->audio.pin[i].rate = -1; 259 rdev->audio.pin[i].bits_per_sample = -1; 260 rdev->audio.pin[i].status_bits = 0; 261 rdev->audio.pin[i].category_code = 0; 262 rdev->audio.pin[i].connected = false; 263 rdev->audio.pin[i].offset = pin_offsets[i]; 264 rdev->audio.pin[i].id = i; 265 dce6_audio_enable(rdev, &rdev->audio.pin[i], true); 266 } 267 268 return 0; 269 } 270 271 void dce6_audio_fini(struct radeon_device *rdev) 272 { 273 int i; 274 275 if (!rdev->audio.enabled) 276 return; 277 278 for (i = 0; i < rdev->audio.num_pins; i++) 279 dce6_audio_enable(rdev, &rdev->audio.pin[i], false); 280 281 rdev->audio.enabled = false; 282 } 283