1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 */ 27 #include <linux/hdmi.h> 28 #include <drm/drmP.h> 29 #include <uapi_drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "evergreend.h" 33 #include "atom.h" 34 35 /* 36 * update the N and CTS parameters for a given pixel clock rate 37 */ 38 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 45 uint32_t offset = dig->afmt->offset; 46 47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 49 50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 52 53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 55 } 56 57 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) 58 { 59 struct radeon_device *rdev = encoder->dev->dev_private; 60 struct drm_connector *connector; 61 struct radeon_connector *radeon_connector = NULL; 62 struct cea_sad *sads; 63 int i, sad_count; 64 65 static const u16 eld_reg_to_type[][2] = { 66 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 67 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 68 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 69 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 70 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 71 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 78 }; 79 80 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 81 if (connector->encoder == encoder) 82 radeon_connector = to_radeon_connector(connector); 83 } 84 85 if (!radeon_connector) { 86 DRM_ERROR("Couldn't find encoder's connector\n"); 87 return; 88 } 89 90 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 91 if (sad_count < 0) { 92 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 93 return; 94 } 95 BUG_ON(!sads); 96 97 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 98 u32 value = 0; 99 int j; 100 101 for (j = 0; j < sad_count; j++) { 102 struct cea_sad *sad = &sads[j]; 103 104 if (sad->format == eld_reg_to_type[i][1]) { 105 value = MAX_CHANNELS(sad->channels) | 106 DESCRIPTOR_BYTE_2(sad->byte2) | 107 SUPPORTED_FREQUENCIES(sad->freq); 108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 109 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 110 break; 111 } 112 } 113 WREG32(eld_reg_to_type[i][0], value); 114 } 115 116 kfree(sads); 117 } 118 119 /* 120 * build a HDMI Video Info Frame 121 */ 122 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 123 void *buffer, size_t size) 124 { 125 struct drm_device *dev = encoder->dev; 126 struct radeon_device *rdev = dev->dev_private; 127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 128 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 129 uint32_t offset = dig->afmt->offset; 130 uint8_t *frame = (uint8_t*)buffer + 3; 131 uint8_t *header = buffer; 132 133 WREG32(AFMT_AVI_INFO0 + offset, 134 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 135 WREG32(AFMT_AVI_INFO1 + offset, 136 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 137 WREG32(AFMT_AVI_INFO2 + offset, 138 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 139 WREG32(AFMT_AVI_INFO3 + offset, 140 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 141 } 142 143 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 144 { 145 struct drm_device *dev = encoder->dev; 146 struct radeon_device *rdev = dev->dev_private; 147 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 148 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 149 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 150 u32 base_rate = 24000; 151 u32 max_ratio = clock / base_rate; 152 u32 dto_phase; 153 u32 dto_modulo = clock; 154 u32 wallclock_ratio; 155 u32 dto_cntl; 156 157 if (!dig || !dig->afmt) 158 return; 159 160 if (max_ratio >= 8) { 161 dto_phase = 192 * 1000; 162 wallclock_ratio = 3; 163 } else if (max_ratio >= 4) { 164 dto_phase = 96 * 1000; 165 wallclock_ratio = 2; 166 } else if (max_ratio >= 2) { 167 dto_phase = 48 * 1000; 168 wallclock_ratio = 1; 169 } else { 170 dto_phase = 24 * 1000; 171 wallclock_ratio = 0; 172 } 173 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 174 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 175 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 176 177 /* XXX two dtos; generally use dto0 for hdmi */ 178 /* Express [24MHz / target pixel clock] as an exact rational 179 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 180 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 181 */ 182 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 183 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 184 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 185 } 186 187 188 /* 189 * update the info frames with the data from the current display mode 190 */ 191 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 192 { 193 struct drm_device *dev = encoder->dev; 194 struct radeon_device *rdev = dev->dev_private; 195 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 196 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 197 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 198 struct hdmi_avi_infoframe frame; 199 uint32_t offset; 200 ssize_t err; 201 202 if (!dig || !dig->afmt) 203 return; 204 205 /* Silent, r600_hdmi_enable will raise WARN for us */ 206 if (!dig->afmt->enabled) 207 return; 208 offset = dig->afmt->offset; 209 210 evergreen_audio_set_dto(encoder, mode->clock); 211 212 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 213 HDMI_NULL_SEND); /* send null packets when required */ 214 215 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 216 217 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 218 HDMI_NULL_SEND | /* send null packets when required */ 219 HDMI_GC_SEND | /* send general control packets */ 220 HDMI_GC_CONT); /* send general control packets every frame */ 221 222 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 223 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 224 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 225 226 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 227 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 228 229 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 230 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 231 232 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 233 234 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 235 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 236 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 237 238 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 239 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 240 241 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 242 243 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 244 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 245 HDMI_ACR_SOURCE); /* select SW CTS value */ 246 247 evergreen_hdmi_update_ACR(encoder, mode->clock); 248 249 WREG32(AFMT_60958_0 + offset, 250 AFMT_60958_CS_CHANNEL_NUMBER_L(1)); 251 252 WREG32(AFMT_60958_1 + offset, 253 AFMT_60958_CS_CHANNEL_NUMBER_R(2)); 254 255 WREG32(AFMT_60958_2 + offset, 256 AFMT_60958_CS_CHANNEL_NUMBER_2(3) | 257 AFMT_60958_CS_CHANNEL_NUMBER_3(4) | 258 AFMT_60958_CS_CHANNEL_NUMBER_4(5) | 259 AFMT_60958_CS_CHANNEL_NUMBER_5(6) | 260 AFMT_60958_CS_CHANNEL_NUMBER_6(7) | 261 AFMT_60958_CS_CHANNEL_NUMBER_7(8)); 262 263 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */ 264 265 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, 266 AFMT_AUDIO_CHANNEL_ENABLE(0xff)); 267 268 /* fglrx sets 0x40 in 0x5f80 here */ 269 evergreen_hdmi_write_sad_regs(encoder); 270 271 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 272 if (err < 0) { 273 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 274 return; 275 } 276 277 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 278 if (err < 0) { 279 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 280 return; 281 } 282 283 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 284 285 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, 286 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 287 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ 288 289 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, 290 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ 291 ~HDMI_AVI_INFO_LINE_MASK); 292 293 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, 294 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ 295 296 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 297 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 298 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 299 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 300 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 301 } 302 303 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 304 { 305 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 306 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 307 308 if (!dig || !dig->afmt) 309 return; 310 311 /* Silent, r600_hdmi_enable will raise WARN for us */ 312 if (enable && dig->afmt->enabled) 313 return; 314 if (!enable && !dig->afmt->enabled) 315 return; 316 317 dig->afmt->enabled = enable; 318 319 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 320 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 321 } 322