1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 */ 27 #include <linux/hdmi.h> 28 #include <drm/drmP.h> 29 #include <uapi_drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "evergreend.h" 33 #include "atom.h" 34 35 /* 36 * update the N and CTS parameters for a given pixel clock rate 37 */ 38 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 45 uint32_t offset = dig->afmt->offset; 46 47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 49 50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 52 53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 55 } 56 57 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) 58 { 59 struct radeon_device *rdev = encoder->dev->dev_private; 60 struct drm_connector *connector; 61 struct radeon_connector *radeon_connector = NULL; 62 u32 tmp; 63 u8 *sadb; 64 int sad_count; 65 66 /* XXX: setting this register causes hangs on some asics */ 67 return; 68 69 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 70 if (connector->encoder == encoder) 71 radeon_connector = to_radeon_connector(connector); 72 } 73 74 if (!radeon_connector) { 75 DRM_ERROR("Couldn't find encoder's connector\n"); 76 return; 77 } 78 79 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 80 if (sad_count < 0) { 81 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 82 return; 83 } 84 85 /* program the speaker allocation */ 86 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 87 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 88 /* set HDMI mode */ 89 tmp |= HDMI_CONNECTION; 90 if (sad_count) 91 tmp |= SPEAKER_ALLOCATION(sadb[0]); 92 else 93 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 94 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 95 96 kfree(sadb); 97 } 98 99 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) 100 { 101 struct radeon_device *rdev = encoder->dev->dev_private; 102 struct drm_connector *connector; 103 struct radeon_connector *radeon_connector = NULL; 104 struct cea_sad *sads; 105 int i, sad_count; 106 107 static const u16 eld_reg_to_type[][2] = { 108 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 109 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 110 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 111 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 112 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 113 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 114 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 115 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 116 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 117 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 118 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 119 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 120 }; 121 122 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 123 if (connector->encoder == encoder) 124 radeon_connector = to_radeon_connector(connector); 125 } 126 127 if (!radeon_connector) { 128 DRM_ERROR("Couldn't find encoder's connector\n"); 129 return; 130 } 131 132 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 133 if (sad_count < 0) { 134 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 135 return; 136 } 137 BUG_ON(!sads); 138 139 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 140 u32 value = 0; 141 int j; 142 143 for (j = 0; j < sad_count; j++) { 144 struct cea_sad *sad = &sads[j]; 145 146 if (sad->format == eld_reg_to_type[i][1]) { 147 value = MAX_CHANNELS(sad->channels) | 148 DESCRIPTOR_BYTE_2(sad->byte2) | 149 SUPPORTED_FREQUENCIES(sad->freq); 150 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 151 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 152 break; 153 } 154 } 155 WREG32(eld_reg_to_type[i][0], value); 156 } 157 158 kfree(sads); 159 } 160 161 /* 162 * build a HDMI Video Info Frame 163 */ 164 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 165 void *buffer, size_t size) 166 { 167 struct drm_device *dev = encoder->dev; 168 struct radeon_device *rdev = dev->dev_private; 169 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 170 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 171 uint32_t offset = dig->afmt->offset; 172 uint8_t *frame = (uint8_t*)buffer + 3; 173 uint8_t *header = buffer; 174 175 WREG32(AFMT_AVI_INFO0 + offset, 176 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 177 WREG32(AFMT_AVI_INFO1 + offset, 178 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 179 WREG32(AFMT_AVI_INFO2 + offset, 180 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 181 WREG32(AFMT_AVI_INFO3 + offset, 182 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 183 } 184 185 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 186 { 187 struct drm_device *dev = encoder->dev; 188 struct radeon_device *rdev = dev->dev_private; 189 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 190 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 191 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 192 u32 base_rate = 24000; 193 u32 max_ratio = clock / base_rate; 194 u32 dto_phase; 195 u32 dto_modulo = clock; 196 u32 wallclock_ratio; 197 u32 dto_cntl; 198 199 if (!dig || !dig->afmt) 200 return; 201 202 if (ASIC_IS_DCE6(rdev)) { 203 dto_phase = 24 * 1000; 204 } else { 205 if (max_ratio >= 8) { 206 dto_phase = 192 * 1000; 207 wallclock_ratio = 3; 208 } else if (max_ratio >= 4) { 209 dto_phase = 96 * 1000; 210 wallclock_ratio = 2; 211 } else if (max_ratio >= 2) { 212 dto_phase = 48 * 1000; 213 wallclock_ratio = 1; 214 } else { 215 dto_phase = 24 * 1000; 216 wallclock_ratio = 0; 217 } 218 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 219 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 220 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 221 } 222 223 /* XXX two dtos; generally use dto0 for hdmi */ 224 /* Express [24MHz / target pixel clock] as an exact rational 225 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 226 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 227 */ 228 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 229 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 230 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 231 } 232 233 234 /* 235 * update the info frames with the data from the current display mode 236 */ 237 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 238 { 239 struct drm_device *dev = encoder->dev; 240 struct radeon_device *rdev = dev->dev_private; 241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 242 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 243 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 244 struct hdmi_avi_infoframe frame; 245 uint32_t offset; 246 ssize_t err; 247 248 if (!dig || !dig->afmt) 249 return; 250 251 /* Silent, r600_hdmi_enable will raise WARN for us */ 252 if (!dig->afmt->enabled) 253 return; 254 offset = dig->afmt->offset; 255 256 evergreen_audio_set_dto(encoder, mode->clock); 257 258 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 259 HDMI_NULL_SEND); /* send null packets when required */ 260 261 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 262 263 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 264 HDMI_NULL_SEND | /* send null packets when required */ 265 HDMI_GC_SEND | /* send general control packets */ 266 HDMI_GC_CONT); /* send general control packets every frame */ 267 268 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 269 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 270 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 271 272 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 273 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 274 275 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 276 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 277 278 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 279 280 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 281 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 282 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 283 284 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 285 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 286 287 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 288 289 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 290 HDMI_ACR_SOURCE | /* select SW CTS value */ 291 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 292 293 evergreen_hdmi_update_ACR(encoder, mode->clock); 294 295 WREG32(AFMT_60958_0 + offset, 296 AFMT_60958_CS_CHANNEL_NUMBER_L(1)); 297 298 WREG32(AFMT_60958_1 + offset, 299 AFMT_60958_CS_CHANNEL_NUMBER_R(2)); 300 301 WREG32(AFMT_60958_2 + offset, 302 AFMT_60958_CS_CHANNEL_NUMBER_2(3) | 303 AFMT_60958_CS_CHANNEL_NUMBER_3(4) | 304 AFMT_60958_CS_CHANNEL_NUMBER_4(5) | 305 AFMT_60958_CS_CHANNEL_NUMBER_5(6) | 306 AFMT_60958_CS_CHANNEL_NUMBER_6(7) | 307 AFMT_60958_CS_CHANNEL_NUMBER_7(8)); 308 309 if (ASIC_IS_DCE6(rdev)) { 310 dce6_afmt_write_speaker_allocation(encoder); 311 } else { 312 dce4_afmt_write_speaker_allocation(encoder); 313 } 314 315 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, 316 AFMT_AUDIO_CHANNEL_ENABLE(0xff)); 317 318 /* fglrx sets 0x40 in 0x5f80 here */ 319 320 if (ASIC_IS_DCE6(rdev)) { 321 dce6_afmt_select_pin(encoder); 322 dce6_afmt_write_sad_regs(encoder); 323 } else { 324 evergreen_hdmi_write_sad_regs(encoder); 325 } 326 327 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 328 if (err < 0) { 329 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 330 return; 331 } 332 333 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 334 if (err < 0) { 335 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 336 return; 337 } 338 339 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 340 341 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, 342 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 343 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ 344 345 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, 346 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ 347 ~HDMI_AVI_INFO_LINE_MASK); 348 349 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, 350 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ 351 352 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 353 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 354 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 355 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 356 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 357 } 358 359 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 360 { 361 struct drm_device *dev = encoder->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 364 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 365 366 if (!dig || !dig->afmt) 367 return; 368 369 /* Silent, r600_hdmi_enable will raise WARN for us */ 370 if (enable && dig->afmt->enabled) 371 return; 372 if (!enable && !dig->afmt->enabled) 373 return; 374 375 if (enable) { 376 if (ASIC_IS_DCE6(rdev)) 377 dig->afmt->pin = dce6_audio_get_pin(rdev); 378 else 379 dig->afmt->pin = r600_audio_get_pin(rdev); 380 } else { 381 dig->afmt->pin = NULL; 382 } 383 384 dig->afmt->enabled = enable; 385 386 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 387 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 388 } 389