1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/evergreen_hdmi.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "evergreend.h" 35 #include "atom.h" 36 37 /* 38 * update the N and CTS parameters for a given pixel clock rate 39 */ 40 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 41 { 42 struct drm_device *dev = encoder->dev; 43 struct radeon_device *rdev = dev->dev_private; 44 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 45 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 46 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 47 uint32_t offset = dig->afmt->offset; 48 49 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 50 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 51 52 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 53 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 54 55 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 56 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 57 } 58 59 /* 60 * calculate the crc for a given info frame 61 */ 62 static void evergreen_hdmi_infoframe_checksum(uint8_t packetType, 63 uint8_t versionNumber, 64 uint8_t length, 65 uint8_t *frame) 66 { 67 int i; 68 frame[0] = packetType + versionNumber + length; 69 for (i = 1; i <= length; i++) 70 frame[0] += frame[i]; 71 frame[0] = 0x100 - frame[0]; 72 } 73 74 /* 75 * build a HDMI Video Info Frame 76 */ 77 static void evergreen_hdmi_videoinfoframe( 78 struct drm_encoder *encoder, 79 uint8_t color_format, 80 int active_information_present, 81 uint8_t active_format_aspect_ratio, 82 uint8_t scan_information, 83 uint8_t colorimetry, 84 uint8_t ex_colorimetry, 85 uint8_t quantization, 86 int ITC, 87 uint8_t picture_aspect_ratio, 88 uint8_t video_format_identification, 89 uint8_t pixel_repetition, 90 uint8_t non_uniform_picture_scaling, 91 uint8_t bar_info_data_valid, 92 uint16_t top_bar, 93 uint16_t bottom_bar, 94 uint16_t left_bar, 95 uint16_t right_bar 96 ) 97 { 98 struct drm_device *dev = encoder->dev; 99 struct radeon_device *rdev = dev->dev_private; 100 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 101 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 102 uint32_t offset = dig->afmt->offset; 103 104 uint8_t frame[14]; 105 106 frame[0x0] = 0; 107 frame[0x1] = 108 (scan_information & 0x3) | 109 ((bar_info_data_valid & 0x3) << 2) | 110 ((active_information_present & 0x1) << 4) | 111 ((color_format & 0x3) << 5); 112 frame[0x2] = 113 (active_format_aspect_ratio & 0xF) | 114 ((picture_aspect_ratio & 0x3) << 4) | 115 ((colorimetry & 0x3) << 6); 116 frame[0x3] = 117 (non_uniform_picture_scaling & 0x3) | 118 ((quantization & 0x3) << 2) | 119 ((ex_colorimetry & 0x7) << 4) | 120 ((ITC & 0x1) << 7); 121 frame[0x4] = (video_format_identification & 0x7F); 122 frame[0x5] = (pixel_repetition & 0xF); 123 frame[0x6] = (top_bar & 0xFF); 124 frame[0x7] = (top_bar >> 8); 125 frame[0x8] = (bottom_bar & 0xFF); 126 frame[0x9] = (bottom_bar >> 8); 127 frame[0xA] = (left_bar & 0xFF); 128 frame[0xB] = (left_bar >> 8); 129 frame[0xC] = (right_bar & 0xFF); 130 frame[0xD] = (right_bar >> 8); 131 132 evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 133 /* Our header values (type, version, length) should be alright, Intel 134 * is using the same. Checksum function also seems to be OK, it works 135 * fine for audio infoframe. However calculated value is always lower 136 * by 2 in comparison to fglrx. It breaks displaying anything in case 137 * of TVs that strictly check the checksum. Hack it manually here to 138 * workaround this issue. */ 139 frame[0x0] += 2; 140 141 WREG32(AFMT_AVI_INFO0 + offset, 142 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 143 WREG32(AFMT_AVI_INFO1 + offset, 144 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 145 WREG32(AFMT_AVI_INFO2 + offset, 146 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 147 WREG32(AFMT_AVI_INFO3 + offset, 148 frame[0xC] | (frame[0xD] << 8)); 149 } 150 151 /* 152 * update the info frames with the data from the current display mode 153 */ 154 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 155 { 156 struct drm_device *dev = encoder->dev; 157 struct radeon_device *rdev = dev->dev_private; 158 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 159 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 160 uint32_t offset; 161 162 /* Silent, r600_hdmi_enable will raise WARN for us */ 163 if (!dig->afmt->enabled) 164 return; 165 offset = dig->afmt->offset; 166 167 r600_audio_set_clock(encoder, mode->clock); 168 169 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 170 HDMI_NULL_SEND); /* send null packets when required */ 171 172 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 173 174 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 175 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 176 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 177 178 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 179 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 180 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 181 182 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 183 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 184 HDMI_ACR_SOURCE); /* select SW CTS value */ 185 186 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 187 HDMI_NULL_SEND | /* send null packets when required */ 188 HDMI_GC_SEND | /* send general control packets */ 189 HDMI_GC_CONT); /* send general control packets every frame */ 190 191 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 192 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 193 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 194 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 195 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 196 197 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 198 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 199 200 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 201 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ 202 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 203 204 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 205 206 evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 207 0, 0, 0, 0, 0, 0); 208 209 evergreen_hdmi_update_ACR(encoder, mode->clock); 210 211 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 212 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 213 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 214 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 215 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 216 } 217