1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/evergreen_hdmi.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <linux/hdmi.h> 31 #include <drm/drmP.h> 32 #include <uapi_drm/radeon_drm.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "evergreend.h" 36 #include "atom.h" 37 38 /* 39 * update the N and CTS parameters for a given pixel clock rate 40 */ 41 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 42 { 43 struct drm_device *dev = encoder->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 47 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 48 uint32_t offset = dig->afmt->offset; 49 50 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 51 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 52 53 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 54 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 55 56 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 57 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 58 } 59 60 /* 61 * build a HDMI Video Info Frame 62 */ 63 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 64 void *buffer, size_t size) 65 { 66 struct drm_device *dev = encoder->dev; 67 struct radeon_device *rdev = dev->dev_private; 68 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 69 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 70 uint32_t offset = dig->afmt->offset; 71 uint8_t *frame = (uint8_t*)buffer + 3; 72 73 /* Our header values (type, version, length) should be alright, Intel 74 * is using the same. Checksum function also seems to be OK, it works 75 * fine for audio infoframe. However calculated value is always lower 76 * by 2 in comparison to fglrx. It breaks displaying anything in case 77 * of TVs that strictly check the checksum. Hack it manually here to 78 * workaround this issue. */ 79 frame[0x0] += 2; 80 81 WREG32(AFMT_AVI_INFO0 + offset, 82 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 83 WREG32(AFMT_AVI_INFO1 + offset, 84 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 85 WREG32(AFMT_AVI_INFO2 + offset, 86 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 87 WREG32(AFMT_AVI_INFO3 + offset, 88 frame[0xC] | (frame[0xD] << 8)); 89 } 90 91 /* 92 * update the info frames with the data from the current display mode 93 */ 94 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 95 { 96 struct drm_device *dev = encoder->dev; 97 struct radeon_device *rdev = dev->dev_private; 98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 99 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 100 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 101 struct hdmi_avi_infoframe frame; 102 uint32_t offset; 103 ssize_t err; 104 105 /* Silent, r600_hdmi_enable will raise WARN for us */ 106 if (!dig->afmt->enabled) 107 return; 108 offset = dig->afmt->offset; 109 110 r600_audio_set_clock(encoder, mode->clock); 111 112 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 113 HDMI_NULL_SEND); /* send null packets when required */ 114 115 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 116 117 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 118 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 119 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 120 121 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 122 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 123 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 124 125 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 126 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 127 HDMI_ACR_SOURCE); /* select SW CTS value */ 128 129 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 130 HDMI_NULL_SEND | /* send null packets when required */ 131 HDMI_GC_SEND | /* send general control packets */ 132 HDMI_GC_CONT); /* send general control packets every frame */ 133 134 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 135 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 136 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 137 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 138 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 139 140 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 141 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 142 143 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 144 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ 145 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 146 147 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 148 149 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 150 if (err < 0) { 151 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 152 return; 153 } 154 155 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 156 if (err < 0) { 157 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 158 return; 159 } 160 161 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 162 evergreen_hdmi_update_ACR(encoder, mode->clock); 163 164 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 165 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 166 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 167 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 168 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 169 } 170