1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 */ 27 #include <linux/hdmi.h> 28 #include <drm/drmP.h> 29 #include <uapi_drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "evergreend.h" 33 #include "atom.h" 34 35 /* 36 * update the N and CTS parameters for a given pixel clock rate 37 */ 38 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 45 uint32_t offset = dig->afmt->offset; 46 47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 49 50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 52 53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 55 } 56 57 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, 58 struct drm_display_mode *mode) 59 { 60 struct radeon_device *rdev = encoder->dev->dev_private; 61 struct drm_connector *connector; 62 struct radeon_connector *radeon_connector = NULL; 63 u32 tmp = 0; 64 65 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 66 if (connector->encoder == encoder) { 67 radeon_connector = to_radeon_connector(connector); 68 break; 69 } 70 } 71 72 if (!radeon_connector) { 73 DRM_ERROR("Couldn't find encoder's connector\n"); 74 return; 75 } 76 77 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 78 if (connector->latency_present[1]) 79 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 80 AUDIO_LIPSYNC(connector->audio_latency[1]); 81 else 82 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 83 } else { 84 if (connector->latency_present[0]) 85 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 86 AUDIO_LIPSYNC(connector->audio_latency[0]); 87 else 88 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 89 } 90 WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); 91 } 92 93 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) 94 { 95 struct radeon_device *rdev = encoder->dev->dev_private; 96 struct drm_connector *connector; 97 struct radeon_connector *radeon_connector = NULL; 98 u32 tmp; 99 u8 *sadb; 100 int sad_count; 101 102 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 103 if (connector->encoder == encoder) { 104 radeon_connector = to_radeon_connector(connector); 105 break; 106 } 107 } 108 109 if (!radeon_connector) { 110 DRM_ERROR("Couldn't find encoder's connector\n"); 111 return; 112 } 113 114 sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); 115 if (sad_count <= 0) { 116 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 117 return; 118 } 119 120 /* program the speaker allocation */ 121 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 122 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 123 /* set HDMI mode */ 124 tmp |= HDMI_CONNECTION; 125 if (sad_count) 126 tmp |= SPEAKER_ALLOCATION(sadb[0]); 127 else 128 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 129 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 130 131 kfree(sadb); 132 } 133 134 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) 135 { 136 struct radeon_device *rdev = encoder->dev->dev_private; 137 struct drm_connector *connector; 138 struct radeon_connector *radeon_connector = NULL; 139 struct cea_sad *sads; 140 int i, sad_count; 141 142 static const u16 eld_reg_to_type[][2] = { 143 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 144 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 145 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 146 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 147 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 148 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 149 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 150 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 151 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 152 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 153 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 154 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 155 }; 156 157 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 158 if (connector->encoder == encoder) { 159 radeon_connector = to_radeon_connector(connector); 160 break; 161 } 162 } 163 164 if (!radeon_connector) { 165 DRM_ERROR("Couldn't find encoder's connector\n"); 166 return; 167 } 168 169 sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); 170 if (sad_count <= 0) { 171 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 172 return; 173 } 174 BUG_ON(!sads); 175 176 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 177 u32 value = 0; 178 u8 stereo_freqs = 0; 179 int max_channels = -1; 180 int j; 181 182 for (j = 0; j < sad_count; j++) { 183 struct cea_sad *sad = &sads[j]; 184 185 if (sad->format == eld_reg_to_type[i][1]) { 186 if (sad->channels > max_channels) { 187 value = MAX_CHANNELS(sad->channels) | 188 DESCRIPTOR_BYTE_2(sad->byte2) | 189 SUPPORTED_FREQUENCIES(sad->freq); 190 max_channels = sad->channels; 191 } 192 193 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 194 stereo_freqs |= sad->freq; 195 else 196 break; 197 } 198 } 199 200 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 201 202 WREG32(eld_reg_to_type[i][0], value); 203 } 204 205 kfree(sads); 206 } 207 208 /* 209 * build a HDMI Video Info Frame 210 */ 211 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 212 void *buffer, size_t size) 213 { 214 struct drm_device *dev = encoder->dev; 215 struct radeon_device *rdev = dev->dev_private; 216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 217 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 218 uint32_t offset = dig->afmt->offset; 219 uint8_t *frame = (uint8_t*)buffer + 3; 220 uint8_t *header = buffer; 221 222 WREG32(AFMT_AVI_INFO0 + offset, 223 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 224 WREG32(AFMT_AVI_INFO1 + offset, 225 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 226 WREG32(AFMT_AVI_INFO2 + offset, 227 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 228 WREG32(AFMT_AVI_INFO3 + offset, 229 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 230 } 231 232 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 233 { 234 struct drm_device *dev = encoder->dev; 235 struct radeon_device *rdev = dev->dev_private; 236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 237 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 239 u32 base_rate = 24000; 240 u32 max_ratio = clock / base_rate; 241 u32 dto_phase; 242 u32 dto_modulo = clock; 243 u32 wallclock_ratio; 244 u32 dto_cntl; 245 246 if (!dig || !dig->afmt) 247 return; 248 249 if (ASIC_IS_DCE6(rdev)) { 250 dto_phase = 24 * 1000; 251 } else { 252 if (max_ratio >= 8) { 253 dto_phase = 192 * 1000; 254 wallclock_ratio = 3; 255 } else if (max_ratio >= 4) { 256 dto_phase = 96 * 1000; 257 wallclock_ratio = 2; 258 } else if (max_ratio >= 2) { 259 dto_phase = 48 * 1000; 260 wallclock_ratio = 1; 261 } else { 262 dto_phase = 24 * 1000; 263 wallclock_ratio = 0; 264 } 265 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 266 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 267 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 268 } 269 270 /* XXX two dtos; generally use dto0 for hdmi */ 271 /* Express [24MHz / target pixel clock] as an exact rational 272 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 273 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 274 */ 275 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 276 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 277 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 278 } 279 280 281 /* 282 * update the info frames with the data from the current display mode 283 */ 284 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 285 { 286 struct drm_device *dev = encoder->dev; 287 struct radeon_device *rdev = dev->dev_private; 288 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 289 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 290 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 291 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 292 struct hdmi_avi_infoframe frame; 293 uint32_t offset; 294 ssize_t err; 295 uint32_t val; 296 int bpc = 8; 297 298 if (!dig || !dig->afmt) 299 return; 300 301 /* Silent, r600_hdmi_enable will raise WARN for us */ 302 if (!dig->afmt->enabled) 303 return; 304 offset = dig->afmt->offset; 305 306 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 307 if (encoder->crtc) { 308 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 309 bpc = radeon_crtc->bpc; 310 } 311 312 /* disable audio prior to setting up hw */ 313 if (ASIC_IS_DCE6(rdev)) { 314 dig->afmt->pin = dce6_audio_get_pin(rdev); 315 dce6_audio_enable(rdev, dig->afmt->pin, false); 316 } else { 317 dig->afmt->pin = r600_audio_get_pin(rdev); 318 r600_audio_enable(rdev, dig->afmt->pin, false); 319 } 320 321 evergreen_audio_set_dto(encoder, mode->clock); 322 323 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 324 HDMI_NULL_SEND); /* send null packets when required */ 325 326 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 327 328 val = RREG32(HDMI_CONTROL + offset); 329 val &= ~HDMI_DEEP_COLOR_ENABLE; 330 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; 331 332 switch (bpc) { 333 case 0: 334 case 6: 335 case 8: 336 case 16: 337 default: 338 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 339 connector->name, bpc); 340 break; 341 case 10: 342 val |= HDMI_DEEP_COLOR_ENABLE; 343 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); 344 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 345 connector->name); 346 break; 347 case 12: 348 val |= HDMI_DEEP_COLOR_ENABLE; 349 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); 350 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 351 connector->name); 352 break; 353 } 354 355 WREG32(HDMI_CONTROL + offset, val); 356 357 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 358 HDMI_NULL_SEND | /* send null packets when required */ 359 HDMI_GC_SEND | /* send general control packets */ 360 HDMI_GC_CONT); /* send general control packets every frame */ 361 362 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 363 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 364 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 365 366 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 367 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 368 369 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 370 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 371 372 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 373 374 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 375 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 376 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 377 378 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 379 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 380 381 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 382 383 if (bpc > 8) 384 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 385 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 386 else 387 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 388 HDMI_ACR_SOURCE | /* select SW CTS value */ 389 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 390 391 evergreen_hdmi_update_ACR(encoder, mode->clock); 392 393 WREG32(AFMT_60958_0 + offset, 394 AFMT_60958_CS_CHANNEL_NUMBER_L(1)); 395 396 WREG32(AFMT_60958_1 + offset, 397 AFMT_60958_CS_CHANNEL_NUMBER_R(2)); 398 399 WREG32(AFMT_60958_2 + offset, 400 AFMT_60958_CS_CHANNEL_NUMBER_2(3) | 401 AFMT_60958_CS_CHANNEL_NUMBER_3(4) | 402 AFMT_60958_CS_CHANNEL_NUMBER_4(5) | 403 AFMT_60958_CS_CHANNEL_NUMBER_5(6) | 404 AFMT_60958_CS_CHANNEL_NUMBER_6(7) | 405 AFMT_60958_CS_CHANNEL_NUMBER_7(8)); 406 407 if (ASIC_IS_DCE6(rdev)) { 408 dce6_afmt_write_speaker_allocation(encoder); 409 } else { 410 dce4_afmt_write_speaker_allocation(encoder); 411 } 412 413 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, 414 AFMT_AUDIO_CHANNEL_ENABLE(0xff)); 415 416 /* fglrx sets 0x40 in 0x5f80 here */ 417 418 if (ASIC_IS_DCE6(rdev)) { 419 dce6_afmt_select_pin(encoder); 420 dce6_afmt_write_sad_regs(encoder); 421 dce6_afmt_write_latency_fields(encoder, mode); 422 } else { 423 evergreen_hdmi_write_sad_regs(encoder); 424 dce4_afmt_write_latency_fields(encoder, mode); 425 } 426 427 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 428 if (err < 0) { 429 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 430 return; 431 } 432 433 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 434 if (err < 0) { 435 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 436 return; 437 } 438 439 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 440 441 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, 442 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 443 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ 444 445 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, 446 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ 447 ~HDMI_AVI_INFO_LINE_MASK); 448 449 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, 450 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ 451 452 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 453 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 454 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 455 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 456 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 457 458 /* enable audio after to setting up hw */ 459 if (ASIC_IS_DCE6(rdev)) 460 dce6_audio_enable(rdev, dig->afmt->pin, true); 461 else 462 r600_audio_enable(rdev, dig->afmt->pin, true); 463 } 464 465 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 466 { 467 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 468 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 469 470 if (!dig || !dig->afmt) 471 return; 472 473 /* Silent, r600_hdmi_enable will raise WARN for us */ 474 if (enable && dig->afmt->enabled) 475 return; 476 if (!enable && !dig->afmt->enabled) 477 return; 478 479 dig->afmt->enabled = enable; 480 481 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 482 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 483 } 484