1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * Rafał Miłecki 26 */ 27 #include <linux/hdmi.h> 28 #include <drm/drmP.h> 29 #include <uapi_drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "evergreend.h" 33 #include "atom.h" 34 35 /* enable the audio stream */ 36 static void dce4_audio_enable(struct radeon_device *rdev, 37 struct r600_audio_pin *pin, 38 u8 enable_mask) 39 { 40 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); 41 42 if (!pin) 43 return; 44 45 if (enable_mask) { 46 tmp |= AUDIO_ENABLED; 47 if (enable_mask & 1) 48 tmp |= PIN0_AUDIO_ENABLED; 49 if (enable_mask & 2) 50 tmp |= PIN1_AUDIO_ENABLED; 51 if (enable_mask & 4) 52 tmp |= PIN2_AUDIO_ENABLED; 53 if (enable_mask & 8) 54 tmp |= PIN3_AUDIO_ENABLED; 55 } else { 56 tmp &= ~(AUDIO_ENABLED | 57 PIN0_AUDIO_ENABLED | 58 PIN1_AUDIO_ENABLED | 59 PIN2_AUDIO_ENABLED | 60 PIN3_AUDIO_ENABLED); 61 } 62 63 WREG32(AZ_HOT_PLUG_CONTROL, tmp); 64 } 65 66 /* 67 * update the N and CTS parameters for a given pixel clock rate 68 */ 69 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 70 { 71 struct drm_device *dev = encoder->dev; 72 struct radeon_device *rdev = dev->dev_private; 73 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 74 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 75 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 76 uint32_t offset = dig->afmt->offset; 77 78 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 79 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 80 81 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 82 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 83 84 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 85 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 86 } 87 88 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, 89 struct drm_display_mode *mode) 90 { 91 struct radeon_device *rdev = encoder->dev->dev_private; 92 struct drm_connector *connector; 93 struct radeon_connector *radeon_connector = NULL; 94 u32 tmp = 0; 95 96 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 97 if (connector->encoder == encoder) { 98 radeon_connector = to_radeon_connector(connector); 99 break; 100 } 101 } 102 103 if (!radeon_connector) { 104 DRM_ERROR("Couldn't find encoder's connector\n"); 105 return; 106 } 107 108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 109 if (connector->latency_present[1]) 110 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 111 AUDIO_LIPSYNC(connector->audio_latency[1]); 112 else 113 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 114 } else { 115 if (connector->latency_present[0]) 116 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 117 AUDIO_LIPSYNC(connector->audio_latency[0]); 118 else 119 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 120 } 121 WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); 122 } 123 124 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) 125 { 126 struct radeon_device *rdev = encoder->dev->dev_private; 127 struct drm_connector *connector; 128 struct radeon_connector *radeon_connector = NULL; 129 u32 tmp; 130 u8 *sadb = NULL; 131 int sad_count; 132 133 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 134 if (connector->encoder == encoder) { 135 radeon_connector = to_radeon_connector(connector); 136 break; 137 } 138 } 139 140 if (!radeon_connector) { 141 DRM_ERROR("Couldn't find encoder's connector\n"); 142 return; 143 } 144 145 sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); 146 if (sad_count < 0) { 147 DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 148 sad_count = 0; 149 } 150 151 /* program the speaker allocation */ 152 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 153 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 154 /* set HDMI mode */ 155 tmp |= HDMI_CONNECTION; 156 if (sad_count) 157 tmp |= SPEAKER_ALLOCATION(sadb[0]); 158 else 159 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 160 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 161 162 kfree(sadb); 163 } 164 165 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) 166 { 167 struct radeon_device *rdev = encoder->dev->dev_private; 168 struct drm_connector *connector; 169 struct radeon_connector *radeon_connector = NULL; 170 struct cea_sad *sads; 171 int i, sad_count; 172 173 static const u16 eld_reg_to_type[][2] = { 174 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 175 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 176 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 177 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 178 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 179 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 180 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 181 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 182 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 183 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 184 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 185 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 186 }; 187 188 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 189 if (connector->encoder == encoder) { 190 radeon_connector = to_radeon_connector(connector); 191 break; 192 } 193 } 194 195 if (!radeon_connector) { 196 DRM_ERROR("Couldn't find encoder's connector\n"); 197 return; 198 } 199 200 sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); 201 if (sad_count <= 0) { 202 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 203 return; 204 } 205 BUG_ON(!sads); 206 207 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 208 u32 value = 0; 209 u8 stereo_freqs = 0; 210 int max_channels = -1; 211 int j; 212 213 for (j = 0; j < sad_count; j++) { 214 struct cea_sad *sad = &sads[j]; 215 216 if (sad->format == eld_reg_to_type[i][1]) { 217 if (sad->channels > max_channels) { 218 value = MAX_CHANNELS(sad->channels) | 219 DESCRIPTOR_BYTE_2(sad->byte2) | 220 SUPPORTED_FREQUENCIES(sad->freq); 221 max_channels = sad->channels; 222 } 223 224 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 225 stereo_freqs |= sad->freq; 226 else 227 break; 228 } 229 } 230 231 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 232 233 WREG32(eld_reg_to_type[i][0], value); 234 } 235 236 kfree(sads); 237 } 238 239 /* 240 * build a HDMI Video Info Frame 241 */ 242 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 243 void *buffer, size_t size) 244 { 245 struct drm_device *dev = encoder->dev; 246 struct radeon_device *rdev = dev->dev_private; 247 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 248 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 249 uint32_t offset = dig->afmt->offset; 250 uint8_t *frame = (uint8_t*)buffer + 3; 251 uint8_t *header = buffer; 252 253 WREG32(AFMT_AVI_INFO0 + offset, 254 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 255 WREG32(AFMT_AVI_INFO1 + offset, 256 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 257 WREG32(AFMT_AVI_INFO2 + offset, 258 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 259 WREG32(AFMT_AVI_INFO3 + offset, 260 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 261 } 262 263 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 264 { 265 struct drm_device *dev = encoder->dev; 266 struct radeon_device *rdev = dev->dev_private; 267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 268 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 270 u32 base_rate = 24000; 271 u32 max_ratio = clock / base_rate; 272 u32 dto_phase; 273 u32 dto_modulo = clock; 274 u32 wallclock_ratio; 275 u32 dto_cntl; 276 277 if (!dig || !dig->afmt) 278 return; 279 280 if (ASIC_IS_DCE6(rdev)) { 281 dto_phase = 24 * 1000; 282 } else { 283 if (max_ratio >= 8) { 284 dto_phase = 192 * 1000; 285 wallclock_ratio = 3; 286 } else if (max_ratio >= 4) { 287 dto_phase = 96 * 1000; 288 wallclock_ratio = 2; 289 } else if (max_ratio >= 2) { 290 dto_phase = 48 * 1000; 291 wallclock_ratio = 1; 292 } else { 293 dto_phase = 24 * 1000; 294 wallclock_ratio = 0; 295 } 296 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 297 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 298 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 299 } 300 301 /* XXX two dtos; generally use dto0 for hdmi */ 302 /* Express [24MHz / target pixel clock] as an exact rational 303 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 304 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 305 */ 306 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 307 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 308 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 309 } 310 311 312 /* 313 * update the info frames with the data from the current display mode 314 */ 315 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 316 { 317 struct drm_device *dev = encoder->dev; 318 struct radeon_device *rdev = dev->dev_private; 319 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 320 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 321 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 322 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 323 struct hdmi_avi_infoframe frame; 324 uint32_t offset; 325 ssize_t err; 326 uint32_t val; 327 int bpc = 8; 328 329 if (!dig || !dig->afmt) 330 return; 331 332 /* Silent, r600_hdmi_enable will raise WARN for us */ 333 if (!dig->afmt->enabled) 334 return; 335 offset = dig->afmt->offset; 336 337 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 338 if (encoder->crtc) { 339 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 340 bpc = radeon_crtc->bpc; 341 } 342 343 /* disable audio prior to setting up hw */ 344 if (ASIC_IS_DCE6(rdev)) { 345 dig->afmt->pin = dce6_audio_get_pin(rdev); 346 dce6_audio_enable(rdev, dig->afmt->pin, 0); 347 } else { 348 dig->afmt->pin = r600_audio_get_pin(rdev); 349 dce4_audio_enable(rdev, dig->afmt->pin, 0); 350 } 351 352 evergreen_audio_set_dto(encoder, mode->clock); 353 354 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 355 HDMI_NULL_SEND); /* send null packets when required */ 356 357 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 358 359 val = RREG32(HDMI_CONTROL + offset); 360 val &= ~HDMI_DEEP_COLOR_ENABLE; 361 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; 362 363 switch (bpc) { 364 case 0: 365 case 6: 366 case 8: 367 case 16: 368 default: 369 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 370 connector->name, bpc); 371 break; 372 case 10: 373 val |= HDMI_DEEP_COLOR_ENABLE; 374 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); 375 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 376 connector->name); 377 break; 378 case 12: 379 val |= HDMI_DEEP_COLOR_ENABLE; 380 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); 381 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 382 connector->name); 383 break; 384 } 385 386 WREG32(HDMI_CONTROL + offset, val); 387 388 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 389 HDMI_NULL_SEND | /* send null packets when required */ 390 HDMI_GC_SEND | /* send general control packets */ 391 HDMI_GC_CONT); /* send general control packets every frame */ 392 393 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 394 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 395 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 396 397 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 398 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 399 400 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 401 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 402 403 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 404 405 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 406 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 407 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 408 409 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 410 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 411 412 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 413 414 if (bpc > 8) 415 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 416 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 417 else 418 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 419 HDMI_ACR_SOURCE | /* select SW CTS value */ 420 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 421 422 evergreen_hdmi_update_ACR(encoder, mode->clock); 423 424 WREG32(AFMT_60958_0 + offset, 425 AFMT_60958_CS_CHANNEL_NUMBER_L(1)); 426 427 WREG32(AFMT_60958_1 + offset, 428 AFMT_60958_CS_CHANNEL_NUMBER_R(2)); 429 430 WREG32(AFMT_60958_2 + offset, 431 AFMT_60958_CS_CHANNEL_NUMBER_2(3) | 432 AFMT_60958_CS_CHANNEL_NUMBER_3(4) | 433 AFMT_60958_CS_CHANNEL_NUMBER_4(5) | 434 AFMT_60958_CS_CHANNEL_NUMBER_5(6) | 435 AFMT_60958_CS_CHANNEL_NUMBER_6(7) | 436 AFMT_60958_CS_CHANNEL_NUMBER_7(8)); 437 438 if (ASIC_IS_DCE6(rdev)) { 439 dce6_afmt_write_speaker_allocation(encoder); 440 } else { 441 dce4_afmt_write_speaker_allocation(encoder); 442 } 443 444 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, 445 AFMT_AUDIO_CHANNEL_ENABLE(0xff)); 446 447 /* fglrx sets 0x40 in 0x5f80 here */ 448 449 if (ASIC_IS_DCE6(rdev)) { 450 dce6_afmt_select_pin(encoder); 451 dce6_afmt_write_sad_regs(encoder); 452 dce6_afmt_write_latency_fields(encoder, mode); 453 } else { 454 evergreen_hdmi_write_sad_regs(encoder); 455 dce4_afmt_write_latency_fields(encoder, mode); 456 } 457 458 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 459 if (err < 0) { 460 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 461 return; 462 } 463 464 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 465 if (err < 0) { 466 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 467 return; 468 } 469 470 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 471 472 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, 473 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 474 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ 475 476 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, 477 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ 478 ~HDMI_AVI_INFO_LINE_MASK); 479 480 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, 481 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ 482 483 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 484 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 485 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 486 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 487 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 488 489 /* enable audio after to setting up hw */ 490 if (ASIC_IS_DCE6(rdev)) 491 dce6_audio_enable(rdev, dig->afmt->pin, 1); 492 else 493 dce4_audio_enable(rdev, dig->afmt->pin, 0xf); 494 } 495 496 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 497 { 498 struct drm_device *dev = encoder->dev; 499 struct radeon_device *rdev = dev->dev_private; 500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 501 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 502 503 if (!dig || !dig->afmt) 504 return; 505 506 /* Silent, r600_hdmi_enable will raise WARN for us */ 507 if (enable && dig->afmt->enabled) 508 return; 509 if (!enable && !dig->afmt->enabled) 510 return; 511 512 if (!enable && dig->afmt->pin) { 513 if (ASIC_IS_DCE6(rdev)) 514 dce6_audio_enable(rdev, dig->afmt->pin, 0); 515 else 516 dce4_audio_enable(rdev, dig->afmt->pin, 0); 517 dig->afmt->pin = NULL; 518 } 519 520 dig->afmt->enabled = enable; 521 522 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 523 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 524 } 525