1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 * 24 * $FreeBSD: head/sys/dev/drm2/radeon/evergreend.h 254885 2013-08-25 19:37:15Z dumbbell $ 25 */ 26 27 #ifndef EVERGREEND_H 28 #define EVERGREEND_H 29 30 #define EVERGREEN_MAX_SH_GPRS 256 31 #define EVERGREEN_MAX_TEMP_GPRS 16 32 #define EVERGREEN_MAX_SH_THREADS 256 33 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 34 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 35 #define EVERGREEN_MAX_BACKENDS 8 36 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 37 #define EVERGREEN_MAX_SIMDS 16 38 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 39 #define EVERGREEN_MAX_PIPES 8 40 #define EVERGREEN_MAX_PIPES_MASK 0xFF 41 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 42 43 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 44 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 45 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 46 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 47 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 48 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 49 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 50 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 51 #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 52 #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 53 54 /* Registers */ 55 56 #define RCU_IND_INDEX 0x100 57 #define RCU_IND_DATA 0x104 58 59 #define GRBM_GFX_INDEX 0x802C 60 #define INSTANCE_INDEX(x) ((x) << 0) 61 #define SE_INDEX(x) ((x) << 16) 62 #define INSTANCE_BROADCAST_WRITES (1 << 30) 63 #define SE_BROADCAST_WRITES (1 << 31) 64 #define RLC_GFX_INDEX 0x3fC4 65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 66 #define WRITE_DIS (1 << 0) 67 #define CC_RB_BACKEND_DISABLE 0x98F4 68 #define BACKEND_DISABLE(x) ((x) << 16) 69 #define GB_ADDR_CONFIG 0x98F8 70 #define NUM_PIPES(x) ((x) << 0) 71 #define NUM_PIPES_MASK 0x0000000f 72 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 73 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 74 #define NUM_SHADER_ENGINES(x) ((x) << 12) 75 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 76 #define NUM_GPUS(x) ((x) << 20) 77 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 78 #define ROW_SIZE(x) ((x) << 28) 79 #define GB_BACKEND_MAP 0x98FC 80 #define DMIF_ADDR_CONFIG 0xBD4 81 #define HDP_ADDR_CONFIG 0x2F48 82 #define HDP_MISC_CNTL 0x2F4C 83 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 84 85 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 86 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 87 88 #define CGTS_SYS_TCC_DISABLE 0x3F90 89 #define CGTS_TCC_DISABLE 0x9148 90 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 91 #define CGTS_USER_TCC_DISABLE 0x914C 92 93 #define CONFIG_MEMSIZE 0x5428 94 95 #define BIF_FB_EN 0x5490 96 #define FB_READ_EN (1 << 0) 97 #define FB_WRITE_EN (1 << 1) 98 99 #define CP_STRMOUT_CNTL 0x84FC 100 101 #define CP_COHER_CNTL 0x85F0 102 #define CP_COHER_SIZE 0x85F4 103 #define CP_COHER_BASE 0x85F8 104 #define CP_STALLED_STAT1 0x8674 105 #define CP_STALLED_STAT2 0x8678 106 #define CP_BUSY_STAT 0x867C 107 #define CP_STAT 0x8680 108 #define CP_ME_CNTL 0x86D8 109 #define CP_ME_HALT (1 << 28) 110 #define CP_PFP_HALT (1 << 26) 111 #define CP_ME_RAM_DATA 0xC160 112 #define CP_ME_RAM_RADDR 0xC158 113 #define CP_ME_RAM_WADDR 0xC15C 114 #define CP_MEQ_THRESHOLDS 0x8764 115 #define STQ_SPLIT(x) ((x) << 0) 116 #define CP_PERFMON_CNTL 0x87FC 117 #define CP_PFP_UCODE_ADDR 0xC150 118 #define CP_PFP_UCODE_DATA 0xC154 119 #define CP_QUEUE_THRESHOLDS 0x8760 120 #define ROQ_IB1_START(x) ((x) << 0) 121 #define ROQ_IB2_START(x) ((x) << 8) 122 #define CP_RB_BASE 0xC100 123 #define CP_RB_CNTL 0xC104 124 #define RB_BUFSZ(x) ((x) << 0) 125 #define RB_BLKSZ(x) ((x) << 8) 126 #define RB_NO_UPDATE (1 << 27) 127 #define RB_RPTR_WR_ENA (1 << 31) 128 #define BUF_SWAP_32BIT (2 << 16) 129 #define CP_RB_RPTR 0x8700 130 #define CP_RB_RPTR_ADDR 0xC10C 131 #define RB_RPTR_SWAP(x) ((x) << 0) 132 #define CP_RB_RPTR_ADDR_HI 0xC110 133 #define CP_RB_RPTR_WR 0xC108 134 #define CP_RB_WPTR 0xC114 135 #define CP_RB_WPTR_ADDR 0xC118 136 #define CP_RB_WPTR_ADDR_HI 0xC11C 137 #define CP_RB_WPTR_DELAY 0x8704 138 #define CP_SEM_WAIT_TIMER 0x85BC 139 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 140 #define CP_DEBUG 0xC1FC 141 142 /* Audio clocks */ 143 #define DCCG_AUDIO_DTO_SOURCE 0x05ac 144 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 145 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 146 147 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 148 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 149 #define DCCG_AUDIO_DTO0_LOAD 0x05b8 150 #define DCCG_AUDIO_DTO0_CNTL 0x05bc 151 152 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 153 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 154 #define DCCG_AUDIO_DTO1_LOAD 0x05c8 155 #define DCCG_AUDIO_DTO1_CNTL 0x05cc 156 157 /* DCE 4.0 AFMT */ 158 #define HDMI_CONTROL 0x7030 159 # define HDMI_KEEPOUT_MODE (1 << 0) 160 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 161 # define HDMI_ERROR_ACK (1 << 8) 162 # define HDMI_ERROR_MASK (1 << 9) 163 # define HDMI_DEEP_COLOR_ENABLE (1 << 24) 164 # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 165 # define HDMI_24BIT_DEEP_COLOR 0 166 # define HDMI_30BIT_DEEP_COLOR 1 167 # define HDMI_36BIT_DEEP_COLOR 2 168 #define HDMI_STATUS 0x7034 169 # define HDMI_ACTIVE_AVMUTE (1 << 0) 170 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 171 # define HDMI_VBI_PACKET_ERROR (1 << 20) 172 #define HDMI_AUDIO_PACKET_CONTROL 0x7038 173 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 174 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 175 #define HDMI_ACR_PACKET_CONTROL 0x703c 176 # define HDMI_ACR_SEND (1 << 0) 177 # define HDMI_ACR_CONT (1 << 1) 178 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 179 # define HDMI_ACR_HW 0 180 # define HDMI_ACR_32 1 181 # define HDMI_ACR_44 2 182 # define HDMI_ACR_48 3 183 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 184 # define HDMI_ACR_AUTO_SEND (1 << 12) 185 # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 186 # define HDMI_ACR_X1 1 187 # define HDMI_ACR_X2 2 188 # define HDMI_ACR_X4 4 189 # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) 190 #define HDMI_VBI_PACKET_CONTROL 0x7040 191 # define HDMI_NULL_SEND (1 << 0) 192 # define HDMI_GC_SEND (1 << 4) 193 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 194 #define HDMI_INFOFRAME_CONTROL0 0x7044 195 # define HDMI_AVI_INFO_SEND (1 << 0) 196 # define HDMI_AVI_INFO_CONT (1 << 1) 197 # define HDMI_AUDIO_INFO_SEND (1 << 4) 198 # define HDMI_AUDIO_INFO_CONT (1 << 5) 199 # define HDMI_MPEG_INFO_SEND (1 << 8) 200 # define HDMI_MPEG_INFO_CONT (1 << 9) 201 #define HDMI_INFOFRAME_CONTROL1 0x7048 202 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 203 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 204 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 205 #define HDMI_GENERIC_PACKET_CONTROL 0x704c 206 # define HDMI_GENERIC0_SEND (1 << 0) 207 # define HDMI_GENERIC0_CONT (1 << 1) 208 # define HDMI_GENERIC1_SEND (1 << 4) 209 # define HDMI_GENERIC1_CONT (1 << 5) 210 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 211 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 212 #define HDMI_GC 0x7058 213 # define HDMI_GC_AVMUTE (1 << 0) 214 # define HDMI_GC_AVMUTE_CONT (1 << 2) 215 #define AFMT_AUDIO_PACKET_CONTROL2 0x705c 216 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 217 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 218 # define AFMT_60958_CS_SOURCE (1 << 4) 219 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 220 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 221 #define AFMT_AVI_INFO0 0x7084 222 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 223 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 224 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 225 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 226 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 227 # define AFMT_AVI_INFO_Y_RGB 0 228 # define AFMT_AVI_INFO_Y_YCBCR422 1 229 # define AFMT_AVI_INFO_Y_YCBCR444 2 230 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 231 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 232 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 233 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 234 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 235 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 236 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 237 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 238 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 239 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 240 #define AFMT_AVI_INFO1 0x7088 241 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 242 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 243 # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 244 # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 245 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 246 #define AFMT_AVI_INFO2 0x708c 247 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 248 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 249 #define AFMT_AVI_INFO3 0x7090 250 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 251 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 252 #define AFMT_MPEG_INFO0 0x7094 253 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 254 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 255 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 256 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 257 #define AFMT_MPEG_INFO1 0x7098 258 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 259 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 260 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 261 #define AFMT_GENERIC0_HDR 0x709c 262 #define AFMT_GENERIC0_0 0x70a0 263 #define AFMT_GENERIC0_1 0x70a4 264 #define AFMT_GENERIC0_2 0x70a8 265 #define AFMT_GENERIC0_3 0x70ac 266 #define AFMT_GENERIC0_4 0x70b0 267 #define AFMT_GENERIC0_5 0x70b4 268 #define AFMT_GENERIC0_6 0x70b8 269 #define AFMT_GENERIC1_HDR 0x70bc 270 #define AFMT_GENERIC1_0 0x70c0 271 #define AFMT_GENERIC1_1 0x70c4 272 #define AFMT_GENERIC1_2 0x70c8 273 #define AFMT_GENERIC1_3 0x70cc 274 #define AFMT_GENERIC1_4 0x70d0 275 #define AFMT_GENERIC1_5 0x70d4 276 #define AFMT_GENERIC1_6 0x70d8 277 #define HDMI_ACR_32_0 0x70dc 278 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 279 #define HDMI_ACR_32_1 0x70e0 280 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 281 #define HDMI_ACR_44_0 0x70e4 282 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 283 #define HDMI_ACR_44_1 0x70e8 284 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 285 #define HDMI_ACR_48_0 0x70ec 286 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 287 #define HDMI_ACR_48_1 0x70f0 288 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 289 #define HDMI_ACR_STATUS_0 0x70f4 290 #define HDMI_ACR_STATUS_1 0x70f8 291 #define AFMT_AUDIO_INFO0 0x70fc 292 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 293 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 294 # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 295 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 296 # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 297 #define AFMT_AUDIO_INFO1 0x7100 298 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 299 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 300 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 301 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 302 # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 303 #define AFMT_60958_0 0x7104 304 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 305 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 306 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 307 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 308 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 309 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 310 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 311 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 312 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 313 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 314 #define AFMT_60958_1 0x7108 315 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 316 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 317 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 318 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 319 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 320 #define AFMT_AUDIO_CRC_CONTROL 0x710c 321 # define AFMT_AUDIO_CRC_EN (1 << 0) 322 #define AFMT_RAMP_CONTROL0 0x7110 323 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 324 # define AFMT_RAMP_DATA_SIGN (1 << 31) 325 #define AFMT_RAMP_CONTROL1 0x7114 326 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 327 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 328 #define AFMT_RAMP_CONTROL2 0x7118 329 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 330 #define AFMT_RAMP_CONTROL3 0x711c 331 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 332 #define AFMT_60958_2 0x7120 333 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 334 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 335 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 336 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 337 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 338 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 339 #define AFMT_STATUS 0x7128 340 # define AFMT_AUDIO_ENABLE (1 << 4) 341 # define AFMT_AUDIO_HBR_ENABLE (1 << 8) 342 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 343 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 344 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 345 #define AFMT_AUDIO_PACKET_CONTROL 0x712c 346 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 347 # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 348 # define AFMT_AUDIO_TEST_EN (1 << 12) 349 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 350 # define AFMT_60958_CS_UPDATE (1 << 26) 351 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 352 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 353 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 354 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 355 #define AFMT_VBI_PACKET_CONTROL 0x7130 356 # define AFMT_GENERIC0_UPDATE (1 << 2) 357 #define AFMT_INFOFRAME_CONTROL0 0x7134 358 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 359 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 360 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 361 #define AFMT_GENERIC0_7 0x7138 362 363 /* DCE4/5 ELD audio interface */ 364 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ 365 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ 366 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ 367 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ 368 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ 369 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ 370 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ 371 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ 372 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ 373 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ 374 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ 375 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ 376 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ 377 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ 378 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 379 /* max channels minus one. 7 = 8 channels */ 380 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 381 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 382 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 383 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 384 * bit0 = 32 kHz 385 * bit1 = 44.1 kHz 386 * bit2 = 48 kHz 387 * bit3 = 88.2 kHz 388 * bit4 = 96 kHz 389 * bit5 = 176.4 kHz 390 * bit6 = 192 kHz 391 */ 392 393 #define AZ_HOT_PLUG_CONTROL 0x5e78 394 # define AZ_FORCE_CODEC_WAKE (1 << 0) 395 # define PIN0_JACK_DETECTION_ENABLE (1 << 4) 396 # define PIN1_JACK_DETECTION_ENABLE (1 << 5) 397 # define PIN2_JACK_DETECTION_ENABLE (1 << 6) 398 # define PIN3_JACK_DETECTION_ENABLE (1 << 7) 399 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 400 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 401 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 402 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 403 # define CODEC_HOT_PLUG_ENABLE (1 << 12) 404 # define PIN0_AUDIO_ENABLED (1 << 24) 405 # define PIN1_AUDIO_ENABLED (1 << 25) 406 # define PIN2_AUDIO_ENABLED (1 << 26) 407 # define PIN3_AUDIO_ENABLED (1 << 27) 408 # define AUDIO_ENABLED (1 << 31) 409 410 411 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 412 #define INACTIVE_QD_PIPES(x) ((x) << 8) 413 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 414 #define INACTIVE_SIMDS(x) ((x) << 16) 415 #define INACTIVE_SIMDS_MASK 0x00FF0000 416 417 #define GRBM_CNTL 0x8000 418 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 419 #define GRBM_SOFT_RESET 0x8020 420 #define SOFT_RESET_CP (1 << 0) 421 #define SOFT_RESET_CB (1 << 1) 422 #define SOFT_RESET_DB (1 << 3) 423 #define SOFT_RESET_PA (1 << 5) 424 #define SOFT_RESET_SC (1 << 6) 425 #define SOFT_RESET_SPI (1 << 8) 426 #define SOFT_RESET_SH (1 << 9) 427 #define SOFT_RESET_SX (1 << 10) 428 #define SOFT_RESET_TC (1 << 11) 429 #define SOFT_RESET_TA (1 << 12) 430 #define SOFT_RESET_VC (1 << 13) 431 #define SOFT_RESET_VGT (1 << 14) 432 433 #define GRBM_STATUS 0x8010 434 #define CMDFIFO_AVAIL_MASK 0x0000000F 435 #define SRBM_RQ_PENDING (1 << 5) 436 #define CF_RQ_PENDING (1 << 7) 437 #define PF_RQ_PENDING (1 << 8) 438 #define GRBM_EE_BUSY (1 << 10) 439 #define SX_CLEAN (1 << 11) 440 #define DB_CLEAN (1 << 12) 441 #define CB_CLEAN (1 << 13) 442 #define TA_BUSY (1 << 14) 443 #define VGT_BUSY_NO_DMA (1 << 16) 444 #define VGT_BUSY (1 << 17) 445 #define SX_BUSY (1 << 20) 446 #define SH_BUSY (1 << 21) 447 #define SPI_BUSY (1 << 22) 448 #define SC_BUSY (1 << 24) 449 #define PA_BUSY (1 << 25) 450 #define DB_BUSY (1 << 26) 451 #define CP_COHERENCY_BUSY (1 << 28) 452 #define CP_BUSY (1 << 29) 453 #define CB_BUSY (1 << 30) 454 #define GUI_ACTIVE (1 << 31) 455 #define GRBM_STATUS_SE0 0x8014 456 #define GRBM_STATUS_SE1 0x8018 457 #define SE_SX_CLEAN (1 << 0) 458 #define SE_DB_CLEAN (1 << 1) 459 #define SE_CB_CLEAN (1 << 2) 460 #define SE_TA_BUSY (1 << 25) 461 #define SE_SX_BUSY (1 << 26) 462 #define SE_SPI_BUSY (1 << 27) 463 #define SE_SH_BUSY (1 << 28) 464 #define SE_SC_BUSY (1 << 29) 465 #define SE_DB_BUSY (1 << 30) 466 #define SE_CB_BUSY (1 << 31) 467 /* evergreen */ 468 #define CG_THERMAL_CTRL 0x72c 469 #define TOFFSET_MASK 0x00003FE0 470 #define TOFFSET_SHIFT 5 471 #define CG_MULT_THERMAL_STATUS 0x740 472 #define ASIC_T(x) ((x) << 16) 473 #define ASIC_T_MASK 0x07FF0000 474 #define ASIC_T_SHIFT 16 475 #define CG_TS0_STATUS 0x760 476 #define TS0_ADC_DOUT_MASK 0x000003FF 477 #define TS0_ADC_DOUT_SHIFT 0 478 /* APU */ 479 #define CG_THERMAL_STATUS 0x678 480 481 #define HDP_HOST_PATH_CNTL 0x2C00 482 #define HDP_NONSURFACE_BASE 0x2C04 483 #define HDP_NONSURFACE_INFO 0x2C08 484 #define HDP_NONSURFACE_SIZE 0x2C0C 485 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 486 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 487 #define HDP_TILING_CONFIG 0x2F3C 488 489 #define MC_SHARED_CHMAP 0x2004 490 #define NOOFCHAN_SHIFT 12 491 #define NOOFCHAN_MASK 0x00003000 492 #define MC_SHARED_CHREMAP 0x2008 493 494 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 495 #define BLACKOUT_MODE_MASK 0x00000007 496 497 #define MC_ARB_RAMCFG 0x2760 498 #define NOOFBANK_SHIFT 0 499 #define NOOFBANK_MASK 0x00000003 500 #define NOOFRANK_SHIFT 2 501 #define NOOFRANK_MASK 0x00000004 502 #define NOOFROWS_SHIFT 3 503 #define NOOFROWS_MASK 0x00000038 504 #define NOOFCOLS_SHIFT 6 505 #define NOOFCOLS_MASK 0x000000C0 506 #define CHANSIZE_SHIFT 8 507 #define CHANSIZE_MASK 0x00000100 508 #define BURSTLENGTH_SHIFT 9 509 #define BURSTLENGTH_MASK 0x00000200 510 #define CHANSIZE_OVERRIDE (1 << 11) 511 #define FUS_MC_ARB_RAMCFG 0x2768 512 #define MC_VM_AGP_TOP 0x2028 513 #define MC_VM_AGP_BOT 0x202C 514 #define MC_VM_AGP_BASE 0x2030 515 #define MC_VM_FB_LOCATION 0x2024 516 #define MC_FUS_VM_FB_OFFSET 0x2898 517 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 518 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 519 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 520 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 521 #define ENABLE_L1_TLB (1 << 0) 522 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 523 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 524 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 525 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 526 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 527 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 528 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 529 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 530 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 531 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 532 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 533 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 534 535 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 536 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 537 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 538 539 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 540 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 541 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 542 543 #define PA_CL_ENHANCE 0x8A14 544 #define CLIP_VTX_REORDER_ENA (1 << 0) 545 #define NUM_CLIP_SEQ(x) ((x) << 1) 546 #define PA_SC_ENHANCE 0x8BF0 547 #define PA_SC_AA_CONFIG 0x28C04 548 #define MSAA_NUM_SAMPLES_SHIFT 0 549 #define MSAA_NUM_SAMPLES_MASK 0x3 550 #define PA_SC_CLIPRECT_RULE 0x2820C 551 #define PA_SC_EDGERULE 0x28230 552 #define PA_SC_FIFO_SIZE 0x8BCC 553 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 554 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 555 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 556 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 557 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 558 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 559 #define PA_SC_LINE_STIPPLE 0x28A0C 560 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 561 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 562 563 #define SCRATCH_REG0 0x8500 564 #define SCRATCH_REG1 0x8504 565 #define SCRATCH_REG2 0x8508 566 #define SCRATCH_REG3 0x850C 567 #define SCRATCH_REG4 0x8510 568 #define SCRATCH_REG5 0x8514 569 #define SCRATCH_REG6 0x8518 570 #define SCRATCH_REG7 0x851C 571 #define SCRATCH_UMSK 0x8540 572 #define SCRATCH_ADDR 0x8544 573 574 #define SMX_SAR_CTL0 0xA008 575 #define SMX_DC_CTL0 0xA020 576 #define USE_HASH_FUNCTION (1 << 0) 577 #define NUMBER_OF_SETS(x) ((x) << 1) 578 #define FLUSH_ALL_ON_EVENT (1 << 10) 579 #define STALL_ON_EVENT (1 << 11) 580 #define SMX_EVENT_CTL 0xA02C 581 #define ES_FLUSH_CTL(x) ((x) << 0) 582 #define GS_FLUSH_CTL(x) ((x) << 3) 583 #define ACK_FLUSH_CTL(x) ((x) << 6) 584 #define SYNC_FLUSH_CTL (1 << 8) 585 586 #define SPI_CONFIG_CNTL 0x9100 587 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 588 #define SPI_CONFIG_CNTL_1 0x913C 589 #define VTX_DONE_DELAY(x) ((x) << 0) 590 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 591 #define SPI_INPUT_Z 0x286D8 592 #define SPI_PS_IN_CONTROL_0 0x286CC 593 #define NUM_INTERP(x) ((x)<<0) 594 #define POSITION_ENA (1<<8) 595 #define POSITION_CENTROID (1<<9) 596 #define POSITION_ADDR(x) ((x)<<10) 597 #define PARAM_GEN(x) ((x)<<15) 598 #define PARAM_GEN_ADDR(x) ((x)<<19) 599 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 600 #define PERSP_GRADIENT_ENA (1<<28) 601 #define LINEAR_GRADIENT_ENA (1<<29) 602 #define POSITION_SAMPLE (1<<30) 603 #define BARYC_AT_SAMPLE_ENA (1<<31) 604 605 #define SQ_CONFIG 0x8C00 606 #define VC_ENABLE (1 << 0) 607 #define EXPORT_SRC_C (1 << 1) 608 #define CS_PRIO(x) ((x) << 18) 609 #define LS_PRIO(x) ((x) << 20) 610 #define HS_PRIO(x) ((x) << 22) 611 #define PS_PRIO(x) ((x) << 24) 612 #define VS_PRIO(x) ((x) << 26) 613 #define GS_PRIO(x) ((x) << 28) 614 #define ES_PRIO(x) ((x) << 30) 615 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 616 #define NUM_PS_GPRS(x) ((x) << 0) 617 #define NUM_VS_GPRS(x) ((x) << 16) 618 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 619 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 620 #define NUM_GS_GPRS(x) ((x) << 0) 621 #define NUM_ES_GPRS(x) ((x) << 16) 622 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 623 #define NUM_HS_GPRS(x) ((x) << 0) 624 #define NUM_LS_GPRS(x) ((x) << 16) 625 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 626 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 627 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 628 #define NUM_PS_THREADS(x) ((x) << 0) 629 #define NUM_VS_THREADS(x) ((x) << 8) 630 #define NUM_GS_THREADS(x) ((x) << 16) 631 #define NUM_ES_THREADS(x) ((x) << 24) 632 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 633 #define NUM_HS_THREADS(x) ((x) << 0) 634 #define NUM_LS_THREADS(x) ((x) << 8) 635 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 636 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 637 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 638 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 639 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 640 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 641 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 642 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 643 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 644 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 645 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 646 #define SQ_STATIC_THREAD_MGMT_1 0x8E20 647 #define SQ_STATIC_THREAD_MGMT_2 0x8E24 648 #define SQ_STATIC_THREAD_MGMT_3 0x8E28 649 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 650 651 #define SQ_MS_FIFO_SIZES 0x8CF0 652 #define CACHE_FIFO_SIZE(x) ((x) << 0) 653 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 654 #define DONE_FIFO_HIWATER(x) ((x) << 16) 655 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 656 657 #define SX_DEBUG_1 0x9058 658 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 659 #define SX_EXPORT_BUFFER_SIZES 0x900C 660 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 661 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 662 #define SMX_BUFFER_SIZE(x) ((x) << 16) 663 #define SX_MEMORY_EXPORT_BASE 0x9010 664 #define SX_MISC 0x28350 665 666 #define CB_PERF_CTR0_SEL_0 0x9A20 667 #define CB_PERF_CTR0_SEL_1 0x9A24 668 #define CB_PERF_CTR1_SEL_0 0x9A28 669 #define CB_PERF_CTR1_SEL_1 0x9A2C 670 #define CB_PERF_CTR2_SEL_0 0x9A30 671 #define CB_PERF_CTR2_SEL_1 0x9A34 672 #define CB_PERF_CTR3_SEL_0 0x9A38 673 #define CB_PERF_CTR3_SEL_1 0x9A3C 674 675 #define TA_CNTL_AUX 0x9508 676 #define DISABLE_CUBE_WRAP (1 << 0) 677 #define DISABLE_CUBE_ANISO (1 << 1) 678 #define SYNC_GRADIENT (1 << 24) 679 #define SYNC_WALKER (1 << 25) 680 #define SYNC_ALIGNER (1 << 26) 681 682 #define TCP_CHAN_STEER_LO 0x960c 683 #define TCP_CHAN_STEER_HI 0x9610 684 685 #define VGT_CACHE_INVALIDATION 0x88C4 686 #define CACHE_INVALIDATION(x) ((x) << 0) 687 #define VC_ONLY 0 688 #define TC_ONLY 1 689 #define VC_AND_TC 2 690 #define AUTO_INVLD_EN(x) ((x) << 6) 691 #define NO_AUTO 0 692 #define ES_AUTO 1 693 #define GS_AUTO 2 694 #define ES_AND_GS_AUTO 3 695 #define VGT_GS_VERTEX_REUSE 0x88D4 696 #define VGT_NUM_INSTANCES 0x8974 697 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 698 #define DEALLOC_DIST_MASK 0x0000007F 699 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 700 #define VTX_REUSE_DEPTH_MASK 0x000000FF 701 702 #define VM_CONTEXT0_CNTL 0x1410 703 #define ENABLE_CONTEXT (1 << 0) 704 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 705 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 706 #define VM_CONTEXT1_CNTL 0x1414 707 #define VM_CONTEXT1_CNTL2 0x1434 708 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 709 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 710 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 711 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 712 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 713 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 714 #define RESPONSE_TYPE_MASK 0x000000F0 715 #define RESPONSE_TYPE_SHIFT 4 716 #define VM_L2_CNTL 0x1400 717 #define ENABLE_L2_CACHE (1 << 0) 718 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 719 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 720 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 721 #define VM_L2_CNTL2 0x1404 722 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 723 #define INVALIDATE_L2_CACHE (1 << 1) 724 #define VM_L2_CNTL3 0x1408 725 #define BANK_SELECT(x) ((x) << 0) 726 #define CACHE_UPDATE_MODE(x) ((x) << 6) 727 #define VM_L2_STATUS 0x140C 728 #define L2_BUSY (1 << 0) 729 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 730 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 731 732 #define WAIT_UNTIL 0x8040 733 734 #define SRBM_STATUS 0x0E50 735 #define RLC_RQ_PENDING (1 << 3) 736 #define GRBM_RQ_PENDING (1 << 5) 737 #define VMC_BUSY (1 << 8) 738 #define MCB_BUSY (1 << 9) 739 #define MCB_NON_DISPLAY_BUSY (1 << 10) 740 #define MCC_BUSY (1 << 11) 741 #define MCD_BUSY (1 << 12) 742 #define SEM_BUSY (1 << 14) 743 #define RLC_BUSY (1 << 15) 744 #define IH_BUSY (1 << 17) 745 #define SRBM_STATUS2 0x0EC4 746 #define DMA_BUSY (1 << 5) 747 #define SRBM_SOFT_RESET 0x0E60 748 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 749 #define SOFT_RESET_BIF (1 << 1) 750 #define SOFT_RESET_CG (1 << 2) 751 #define SOFT_RESET_DC (1 << 5) 752 #define SOFT_RESET_GRBM (1 << 8) 753 #define SOFT_RESET_HDP (1 << 9) 754 #define SOFT_RESET_IH (1 << 10) 755 #define SOFT_RESET_MC (1 << 11) 756 #define SOFT_RESET_RLC (1 << 13) 757 #define SOFT_RESET_ROM (1 << 14) 758 #define SOFT_RESET_SEM (1 << 15) 759 #define SOFT_RESET_VMC (1 << 17) 760 #define SOFT_RESET_DMA (1 << 20) 761 #define SOFT_RESET_TST (1 << 21) 762 #define SOFT_RESET_REGBB (1 << 22) 763 #define SOFT_RESET_ORB (1 << 23) 764 765 /* display watermarks */ 766 #define DC_LB_MEMORY_SPLIT 0x6b0c 767 #define PRIORITY_A_CNT 0x6b18 768 #define PRIORITY_MARK_MASK 0x7fff 769 #define PRIORITY_OFF (1 << 16) 770 #define PRIORITY_ALWAYS_ON (1 << 20) 771 #define PRIORITY_B_CNT 0x6b1c 772 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 773 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 774 #define PIPE0_LATENCY_CONTROL 0x0bf4 775 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 776 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 777 778 #define IH_RB_CNTL 0x3e00 779 # define IH_RB_ENABLE (1 << 0) 780 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 781 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 782 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 783 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 784 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 785 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 786 #define IH_RB_BASE 0x3e04 787 #define IH_RB_RPTR 0x3e08 788 #define IH_RB_WPTR 0x3e0c 789 # define RB_OVERFLOW (1 << 0) 790 # define WPTR_OFFSET_MASK 0x3fffc 791 #define IH_RB_WPTR_ADDR_HI 0x3e10 792 #define IH_RB_WPTR_ADDR_LO 0x3e14 793 #define IH_CNTL 0x3e18 794 # define ENABLE_INTR (1 << 0) 795 # define IH_MC_SWAP(x) ((x) << 1) 796 # define IH_MC_SWAP_NONE 0 797 # define IH_MC_SWAP_16BIT 1 798 # define IH_MC_SWAP_32BIT 2 799 # define IH_MC_SWAP_64BIT 3 800 # define RPTR_REARM (1 << 4) 801 # define MC_WRREQ_CREDIT(x) ((x) << 15) 802 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 803 804 #define CP_INT_CNTL 0xc124 805 # define CNTX_BUSY_INT_ENABLE (1 << 19) 806 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 807 # define SCRATCH_INT_ENABLE (1 << 25) 808 # define TIME_STAMP_INT_ENABLE (1 << 26) 809 # define IB2_INT_ENABLE (1 << 29) 810 # define IB1_INT_ENABLE (1 << 30) 811 # define RB_INT_ENABLE (1 << 31) 812 #define CP_INT_STATUS 0xc128 813 # define SCRATCH_INT_STAT (1 << 25) 814 # define TIME_STAMP_INT_STAT (1 << 26) 815 # define IB2_INT_STAT (1 << 29) 816 # define IB1_INT_STAT (1 << 30) 817 # define RB_INT_STAT (1 << 31) 818 819 #define GRBM_INT_CNTL 0x8060 820 # define RDERR_INT_ENABLE (1 << 0) 821 # define GUI_IDLE_INT_ENABLE (1 << 19) 822 823 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 824 #define CRTC_STATUS_FRAME_COUNT 0x6e98 825 826 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 827 #define VLINE_STATUS 0x6bb8 828 # define VLINE_OCCURRED (1 << 0) 829 # define VLINE_ACK (1 << 4) 830 # define VLINE_STAT (1 << 12) 831 # define VLINE_INTERRUPT (1 << 16) 832 # define VLINE_INTERRUPT_TYPE (1 << 17) 833 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 834 #define VBLANK_STATUS 0x6bbc 835 # define VBLANK_OCCURRED (1 << 0) 836 # define VBLANK_ACK (1 << 4) 837 # define VBLANK_STAT (1 << 12) 838 # define VBLANK_INTERRUPT (1 << 16) 839 # define VBLANK_INTERRUPT_TYPE (1 << 17) 840 841 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 842 #define INT_MASK 0x6b40 843 # define VBLANK_INT_MASK (1 << 0) 844 # define VLINE_INT_MASK (1 << 4) 845 846 #define DISP_INTERRUPT_STATUS 0x60f4 847 # define LB_D1_VLINE_INTERRUPT (1 << 2) 848 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 849 # define DC_HPD1_INTERRUPT (1 << 17) 850 # define DC_HPD1_RX_INTERRUPT (1 << 18) 851 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 852 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 853 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 854 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 855 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 856 # define LB_D2_VLINE_INTERRUPT (1 << 2) 857 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 858 # define DC_HPD2_INTERRUPT (1 << 17) 859 # define DC_HPD2_RX_INTERRUPT (1 << 18) 860 # define DISP_TIMER_INTERRUPT (1 << 24) 861 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 862 # define LB_D3_VLINE_INTERRUPT (1 << 2) 863 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 864 # define DC_HPD3_INTERRUPT (1 << 17) 865 # define DC_HPD3_RX_INTERRUPT (1 << 18) 866 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 867 # define LB_D4_VLINE_INTERRUPT (1 << 2) 868 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 869 # define DC_HPD4_INTERRUPT (1 << 17) 870 # define DC_HPD4_RX_INTERRUPT (1 << 18) 871 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 872 # define LB_D5_VLINE_INTERRUPT (1 << 2) 873 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 874 # define DC_HPD5_INTERRUPT (1 << 17) 875 # define DC_HPD5_RX_INTERRUPT (1 << 18) 876 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 877 # define LB_D6_VLINE_INTERRUPT (1 << 2) 878 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 879 # define DC_HPD6_INTERRUPT (1 << 17) 880 # define DC_HPD6_RX_INTERRUPT (1 << 18) 881 882 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 883 #define GRPH_INT_STATUS 0x6858 884 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 885 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 886 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 887 #define GRPH_INT_CONTROL 0x685c 888 # define GRPH_PFLIP_INT_MASK (1 << 0) 889 # define GRPH_PFLIP_INT_TYPE (1 << 8) 890 891 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 892 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 893 894 #define DC_HPD1_INT_STATUS 0x601c 895 #define DC_HPD2_INT_STATUS 0x6028 896 #define DC_HPD3_INT_STATUS 0x6034 897 #define DC_HPD4_INT_STATUS 0x6040 898 #define DC_HPD5_INT_STATUS 0x604c 899 #define DC_HPD6_INT_STATUS 0x6058 900 # define DC_HPDx_INT_STATUS (1 << 0) 901 # define DC_HPDx_SENSE (1 << 1) 902 # define DC_HPDx_RX_INT_STATUS (1 << 8) 903 904 #define DC_HPD1_INT_CONTROL 0x6020 905 #define DC_HPD2_INT_CONTROL 0x602c 906 #define DC_HPD3_INT_CONTROL 0x6038 907 #define DC_HPD4_INT_CONTROL 0x6044 908 #define DC_HPD5_INT_CONTROL 0x6050 909 #define DC_HPD6_INT_CONTROL 0x605c 910 # define DC_HPDx_INT_ACK (1 << 0) 911 # define DC_HPDx_INT_POLARITY (1 << 8) 912 # define DC_HPDx_INT_EN (1 << 16) 913 # define DC_HPDx_RX_INT_ACK (1 << 20) 914 # define DC_HPDx_RX_INT_EN (1 << 24) 915 916 #define DC_HPD1_CONTROL 0x6024 917 #define DC_HPD2_CONTROL 0x6030 918 #define DC_HPD3_CONTROL 0x603c 919 #define DC_HPD4_CONTROL 0x6048 920 #define DC_HPD5_CONTROL 0x6054 921 #define DC_HPD6_CONTROL 0x6060 922 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 923 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 924 # define DC_HPDx_EN (1 << 28) 925 926 /* ASYNC DMA */ 927 #define DMA_RB_RPTR 0xd008 928 #define DMA_RB_WPTR 0xd00c 929 930 #define DMA_CNTL 0xd02c 931 # define TRAP_ENABLE (1 << 0) 932 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 933 # define SEM_WAIT_INT_ENABLE (1 << 2) 934 # define DATA_SWAP_ENABLE (1 << 3) 935 # define FENCE_SWAP_ENABLE (1 << 4) 936 # define CTXEMPTY_INT_ENABLE (1 << 28) 937 #define DMA_TILING_CONFIG 0xD0B8 938 939 #define CAYMAN_DMA1_CNTL 0xd82c 940 941 /* async DMA packets */ 942 #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ 943 (((sub_cmd) & 0xFF) << 20) |\ 944 (((n) & 0xFFFFF) << 0)) 945 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 946 #define GET_DMA_COUNT(h) ((h) & 0x000fffff) 947 #define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20) 948 949 /* async DMA Packet types */ 950 #define DMA_PACKET_WRITE 0x2 951 #define DMA_PACKET_COPY 0x3 952 #define DMA_PACKET_INDIRECT_BUFFER 0x4 953 #define DMA_PACKET_SEMAPHORE 0x5 954 #define DMA_PACKET_FENCE 0x6 955 #define DMA_PACKET_TRAP 0x7 956 #define DMA_PACKET_SRBM_WRITE 0x9 957 #define DMA_PACKET_CONSTANT_FILL 0xd 958 #define DMA_PACKET_NOP 0xf 959 960 /* PCIE link stuff */ 961 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 962 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 963 # define LC_LINK_WIDTH_SHIFT 0 964 # define LC_LINK_WIDTH_MASK 0x7 965 # define LC_LINK_WIDTH_X0 0 966 # define LC_LINK_WIDTH_X1 1 967 # define LC_LINK_WIDTH_X2 2 968 # define LC_LINK_WIDTH_X4 3 969 # define LC_LINK_WIDTH_X8 4 970 # define LC_LINK_WIDTH_X16 6 971 # define LC_LINK_WIDTH_RD_SHIFT 4 972 # define LC_LINK_WIDTH_RD_MASK 0x70 973 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 974 # define LC_RECONFIG_NOW (1 << 8) 975 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 976 # define LC_RENEGOTIATE_EN (1 << 10) 977 # define LC_SHORT_RECONFIG_EN (1 << 11) 978 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 979 # define LC_UPCONFIGURE_DIS (1 << 13) 980 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 981 # define LC_GEN2_EN_STRAP (1 << 0) 982 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 983 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 984 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 985 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 986 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 987 # define LC_CURRENT_DATA_RATE (1 << 11) 988 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 989 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 990 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 991 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 992 #define MM_CFGREGS_CNTL 0x544c 993 # define MM_WR_TO_CFG_EN (1 << 3) 994 #define LINK_CNTL2 0x88 /* F0 */ 995 # define TARGET_LINK_SPEED_MASK (0xf << 0) 996 # define SELECTABLE_DEEMPHASIS (1 << 6) 997 998 /* 999 * PM4 1000 */ 1001 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1002 (((reg) >> 2) & 0xFFFF) | \ 1003 ((n) & 0x3FFF) << 16) 1004 #define CP_PACKET2 0x80000000 1005 #define PACKET2_PAD_SHIFT 0 1006 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1007 1008 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1009 1010 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1011 (((op) & 0xFF) << 8) | \ 1012 ((n) & 0x3FFF) << 16) 1013 1014 /* Packet 3 types */ 1015 #define PACKET3_NOP 0x10 1016 #define PACKET3_SET_BASE 0x11 1017 #define PACKET3_CLEAR_STATE 0x12 1018 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1019 #define PACKET3_DISPATCH_DIRECT 0x15 1020 #define PACKET3_DISPATCH_INDIRECT 0x16 1021 #define PACKET3_INDIRECT_BUFFER_END 0x17 1022 #define PACKET3_MODE_CONTROL 0x18 1023 #define PACKET3_SET_PREDICATION 0x20 1024 #define PACKET3_REG_RMW 0x21 1025 #define PACKET3_COND_EXEC 0x22 1026 #define PACKET3_PRED_EXEC 0x23 1027 #define PACKET3_DRAW_INDIRECT 0x24 1028 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1029 #define PACKET3_INDEX_BASE 0x26 1030 #define PACKET3_DRAW_INDEX_2 0x27 1031 #define PACKET3_CONTEXT_CONTROL 0x28 1032 #define PACKET3_DRAW_INDEX_OFFSET 0x29 1033 #define PACKET3_INDEX_TYPE 0x2A 1034 #define PACKET3_DRAW_INDEX 0x2B 1035 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1036 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1037 #define PACKET3_NUM_INSTANCES 0x2F 1038 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1039 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1040 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1041 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1042 #define PACKET3_MEM_SEMAPHORE 0x39 1043 #define PACKET3_MPEG_INDEX 0x3A 1044 #define PACKET3_COPY_DW 0x3B 1045 #define PACKET3_WAIT_REG_MEM 0x3C 1046 #define PACKET3_MEM_WRITE 0x3D 1047 #define PACKET3_INDIRECT_BUFFER 0x32 1048 #define PACKET3_CP_DMA 0x41 1049 /* 1. header 1050 * 2. SRC_ADDR_LO or DATA [31:0] 1051 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1052 * SRC_ADDR_HI [7:0] 1053 * 4. DST_ADDR_LO [31:0] 1054 * 5. DST_ADDR_HI [7:0] 1055 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1056 */ 1057 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1058 /* 0 - SRC_ADDR 1059 * 1 - GDS 1060 */ 1061 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1062 /* 0 - ME 1063 * 1 - PFP 1064 */ 1065 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1066 /* 0 - SRC_ADDR 1067 * 1 - GDS 1068 * 2 - DATA 1069 */ 1070 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1071 /* COMMAND */ 1072 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1073 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1074 /* 0 - none 1075 * 1 - 8 in 16 1076 * 2 - 8 in 32 1077 * 3 - 8 in 64 1078 */ 1079 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1080 /* 0 - none 1081 * 1 - 8 in 16 1082 * 2 - 8 in 32 1083 * 3 - 8 in 64 1084 */ 1085 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1086 /* 0 - memory 1087 * 1 - register 1088 */ 1089 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1090 /* 0 - memory 1091 * 1 - register 1092 */ 1093 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1094 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1095 #define PACKET3_SURFACE_SYNC 0x43 1096 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1097 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1098 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1099 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1100 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1101 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1102 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1103 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1104 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1105 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1106 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1107 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1108 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1109 # define PACKET3_FULL_CACHE_ENA (1 << 20) 1110 # define PACKET3_TC_ACTION_ENA (1 << 23) 1111 # define PACKET3_VC_ACTION_ENA (1 << 24) 1112 # define PACKET3_CB_ACTION_ENA (1 << 25) 1113 # define PACKET3_DB_ACTION_ENA (1 << 26) 1114 # define PACKET3_SH_ACTION_ENA (1 << 27) 1115 # define PACKET3_SX_ACTION_ENA (1 << 28) 1116 #define PACKET3_ME_INITIALIZE 0x44 1117 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1118 #define PACKET3_COND_WRITE 0x45 1119 #define PACKET3_EVENT_WRITE 0x46 1120 #define PACKET3_EVENT_WRITE_EOP 0x47 1121 #define PACKET3_EVENT_WRITE_EOS 0x48 1122 #define PACKET3_PREAMBLE_CNTL 0x4A 1123 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1124 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1125 #define PACKET3_RB_OFFSET 0x4B 1126 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1127 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1128 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1129 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1130 #define PACKET3_ONE_REG_WRITE 0x57 1131 #define PACKET3_SET_CONFIG_REG 0x68 1132 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1133 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1134 #define PACKET3_SET_CONTEXT_REG 0x69 1135 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1136 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1137 #define PACKET3_SET_ALU_CONST 0x6A 1138 /* alu const buffers only; no reg file */ 1139 #define PACKET3_SET_BOOL_CONST 0x6B 1140 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1141 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1142 #define PACKET3_SET_LOOP_CONST 0x6C 1143 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1144 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1145 #define PACKET3_SET_RESOURCE 0x6D 1146 #define PACKET3_SET_RESOURCE_START 0x00030000 1147 #define PACKET3_SET_RESOURCE_END 0x00038000 1148 #define PACKET3_SET_SAMPLER 0x6E 1149 #define PACKET3_SET_SAMPLER_START 0x0003c000 1150 #define PACKET3_SET_SAMPLER_END 0x0003c600 1151 #define PACKET3_SET_CTL_CONST 0x6F 1152 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1153 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1154 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1155 #define PACKET3_SET_ALU_CONST_VS 0x71 1156 #define PACKET3_SET_ALU_CONST_DI 0x72 1157 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1158 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1159 #define PACKET3_SET_APPEND_CNT 0x75 1160 1161 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1162 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1163 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1164 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1165 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 1166 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 1167 #define SQ_TEX_VTX_VALID_BUFFER 0x3 1168 1169 #define VGT_VTX_VECT_EJECT_REG 0x88b0 1170 1171 #define SQ_CONST_MEM_BASE 0x8df8 1172 1173 #define SQ_ESGS_RING_BASE 0x8c40 1174 #define SQ_ESGS_RING_SIZE 0x8c44 1175 #define SQ_GSVS_RING_BASE 0x8c48 1176 #define SQ_GSVS_RING_SIZE 0x8c4c 1177 #define SQ_ESTMP_RING_BASE 0x8c50 1178 #define SQ_ESTMP_RING_SIZE 0x8c54 1179 #define SQ_GSTMP_RING_BASE 0x8c58 1180 #define SQ_GSTMP_RING_SIZE 0x8c5c 1181 #define SQ_VSTMP_RING_BASE 0x8c60 1182 #define SQ_VSTMP_RING_SIZE 0x8c64 1183 #define SQ_PSTMP_RING_BASE 0x8c68 1184 #define SQ_PSTMP_RING_SIZE 0x8c6c 1185 #define SQ_LSTMP_RING_BASE 0x8e10 1186 #define SQ_LSTMP_RING_SIZE 0x8e14 1187 #define SQ_HSTMP_RING_BASE 0x8e18 1188 #define SQ_HSTMP_RING_SIZE 0x8e1c 1189 #define VGT_TF_RING_SIZE 0x8988 1190 1191 #define SQ_ESGS_RING_ITEMSIZE 0x28900 1192 #define SQ_GSVS_RING_ITEMSIZE 0x28904 1193 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 1194 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1195 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 1196 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 1197 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 1198 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 1199 1200 #define SQ_GS_VERT_ITEMSIZE 0x2891c 1201 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 1202 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 1203 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 1204 #define SQ_GSVS_RING_OFFSET_1 0x2892c 1205 #define SQ_GSVS_RING_OFFSET_2 0x28930 1206 #define SQ_GSVS_RING_OFFSET_3 0x28934 1207 1208 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1209 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1210 1211 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 1212 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 1213 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 1214 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1215 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 1216 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 1217 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 1218 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1219 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 1220 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 1221 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 1222 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1223 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 1224 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 1225 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 1226 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1227 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 1228 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 1229 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 1230 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1231 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 1232 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 1233 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 1234 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1235 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1236 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1237 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1238 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1239 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1240 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1241 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1242 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1243 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1244 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1245 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1246 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1247 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1248 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1249 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1250 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1251 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1252 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1253 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1254 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1255 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1256 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1257 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1258 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1259 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1260 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1261 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1262 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1263 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1264 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1265 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1266 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1267 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1268 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1269 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1270 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1271 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1272 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1273 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1274 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1275 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1276 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1277 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1278 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1279 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1280 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1281 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1282 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1283 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1284 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1285 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1286 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1287 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1288 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1289 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1290 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1291 1292 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 1293 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 1294 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 1295 1296 #define VGT_PRIMITIVE_TYPE 0x8958 1297 #define VGT_INDEX_TYPE 0x895C 1298 1299 #define VGT_NUM_INDICES 0x8970 1300 1301 #define VGT_COMPUTE_DIM_X 0x8990 1302 #define VGT_COMPUTE_DIM_Y 0x8994 1303 #define VGT_COMPUTE_DIM_Z 0x8998 1304 #define VGT_COMPUTE_START_X 0x899C 1305 #define VGT_COMPUTE_START_Y 0x89A0 1306 #define VGT_COMPUTE_START_Z 0x89A4 1307 #define VGT_COMPUTE_INDEX 0x89A8 1308 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1309 #define VGT_HS_OFFCHIP_PARAM 0x89B0 1310 1311 #define DB_DEBUG 0x9830 1312 #define DB_DEBUG2 0x9834 1313 #define DB_DEBUG3 0x9838 1314 #define DB_DEBUG4 0x983C 1315 #define DB_WATERMARKS 0x9854 1316 #define DB_DEPTH_CONTROL 0x28800 1317 #define R_028800_DB_DEPTH_CONTROL 0x028800 1318 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1319 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1320 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1321 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1322 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1323 #define C_028800_Z_ENABLE 0xFFFFFFFD 1324 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1325 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1326 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1327 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1328 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1329 #define C_028800_ZFUNC 0xFFFFFF8F 1330 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1331 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1332 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1333 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1334 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1335 #define C_028800_STENCILFUNC 0xFFFFF8FF 1336 #define V_028800_STENCILFUNC_NEVER 0x00000000 1337 #define V_028800_STENCILFUNC_LESS 0x00000001 1338 #define V_028800_STENCILFUNC_EQUAL 0x00000002 1339 #define V_028800_STENCILFUNC_LEQUAL 0x00000003 1340 #define V_028800_STENCILFUNC_GREATER 0x00000004 1341 #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1342 #define V_028800_STENCILFUNC_GEQUAL 0x00000006 1343 #define V_028800_STENCILFUNC_ALWAYS 0x00000007 1344 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1345 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1346 #define C_028800_STENCILFAIL 0xFFFFC7FF 1347 #define V_028800_STENCIL_KEEP 0x00000000 1348 #define V_028800_STENCIL_ZERO 0x00000001 1349 #define V_028800_STENCIL_REPLACE 0x00000002 1350 #define V_028800_STENCIL_INCR 0x00000003 1351 #define V_028800_STENCIL_DECR 0x00000004 1352 #define V_028800_STENCIL_INVERT 0x00000005 1353 #define V_028800_STENCIL_INCR_WRAP 0x00000006 1354 #define V_028800_STENCIL_DECR_WRAP 0x00000007 1355 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1356 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1357 #define C_028800_STENCILZPASS 0xFFFE3FFF 1358 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1359 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1360 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1361 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1362 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1363 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1364 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1365 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1366 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1367 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1368 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1369 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1370 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1371 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1372 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1373 #define DB_DEPTH_VIEW 0x28008 1374 #define R_028008_DB_DEPTH_VIEW 0x00028008 1375 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1376 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1377 #define C_028008_SLICE_START 0xFFFFF800 1378 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1379 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1380 #define C_028008_SLICE_MAX 0xFF001FFF 1381 #define DB_HTILE_DATA_BASE 0x28014 1382 #define DB_HTILE_SURFACE 0x28abc 1383 #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1384 #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1385 #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1386 #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1387 #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1388 #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1389 #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1390 #define DB_Z_INFO 0x28040 1391 # define Z_ARRAY_MODE(x) ((x) << 4) 1392 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1393 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1394 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1395 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1396 # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1397 #define R_028040_DB_Z_INFO 0x028040 1398 #define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1399 #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1400 #define C_028040_FORMAT 0xFFFFFFFC 1401 #define V_028040_Z_INVALID 0x00000000 1402 #define V_028040_Z_16 0x00000001 1403 #define V_028040_Z_24 0x00000002 1404 #define V_028040_Z_32_FLOAT 0x00000003 1405 #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1406 #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1407 #define C_028040_ARRAY_MODE 0xFFFFFF0F 1408 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1409 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1410 #define C_028040_READ_SIZE 0xEFFFFFFF 1411 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1412 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1413 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1414 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1415 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1416 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1417 #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1418 #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1419 #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1420 #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1421 #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1422 #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1423 #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1424 #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1425 #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1426 #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1427 #define DB_STENCIL_INFO 0x28044 1428 #define R_028044_DB_STENCIL_INFO 0x028044 1429 #define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1430 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1431 #define C_028044_FORMAT 0xFFFFFFFE 1432 #define V_028044_STENCIL_INVALID 0 1433 #define V_028044_STENCIL_8 1 1434 #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1435 #define DB_Z_READ_BASE 0x28048 1436 #define DB_STENCIL_READ_BASE 0x2804c 1437 #define DB_Z_WRITE_BASE 0x28050 1438 #define DB_STENCIL_WRITE_BASE 0x28054 1439 #define DB_DEPTH_SIZE 0x28058 1440 #define R_028058_DB_DEPTH_SIZE 0x028058 1441 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1442 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1443 #define C_028058_PITCH_TILE_MAX 0xFFFFF800 1444 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1445 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1446 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1447 #define R_02805C_DB_DEPTH_SLICE 0x02805C 1448 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1449 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1450 #define C_02805C_SLICE_TILE_MAX 0xFFC00000 1451 1452 #define SQ_PGM_START_PS 0x28840 1453 #define SQ_PGM_START_VS 0x2885c 1454 #define SQ_PGM_START_GS 0x28874 1455 #define SQ_PGM_START_ES 0x2888c 1456 #define SQ_PGM_START_FS 0x288a4 1457 #define SQ_PGM_START_HS 0x288b8 1458 #define SQ_PGM_START_LS 0x288d0 1459 1460 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1461 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1462 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1463 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1464 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1465 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1466 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1467 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1468 #define VGT_STRMOUT_CONFIG 0x28b94 1469 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1470 1471 #define CB_TARGET_MASK 0x28238 1472 #define CB_SHADER_MASK 0x2823c 1473 1474 #define GDS_ADDR_BASE 0x28720 1475 1476 #define CB_IMMED0_BASE 0x28b9c 1477 #define CB_IMMED1_BASE 0x28ba0 1478 #define CB_IMMED2_BASE 0x28ba4 1479 #define CB_IMMED3_BASE 0x28ba8 1480 #define CB_IMMED4_BASE 0x28bac 1481 #define CB_IMMED5_BASE 0x28bb0 1482 #define CB_IMMED6_BASE 0x28bb4 1483 #define CB_IMMED7_BASE 0x28bb8 1484 #define CB_IMMED8_BASE 0x28bbc 1485 #define CB_IMMED9_BASE 0x28bc0 1486 #define CB_IMMED10_BASE 0x28bc4 1487 #define CB_IMMED11_BASE 0x28bc8 1488 1489 /* all 12 CB blocks have these regs */ 1490 #define CB_COLOR0_BASE 0x28c60 1491 #define CB_COLOR0_PITCH 0x28c64 1492 #define CB_COLOR0_SLICE 0x28c68 1493 #define CB_COLOR0_VIEW 0x28c6c 1494 #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1495 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1496 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1497 #define C_028C6C_SLICE_START 0xFFFFF800 1498 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1499 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1500 #define C_028C6C_SLICE_MAX 0xFF001FFF 1501 #define R_028C70_CB_COLOR0_INFO 0x028C70 1502 #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1503 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1504 #define C_028C70_ENDIAN 0xFFFFFFFC 1505 #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1506 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1507 #define C_028C70_FORMAT 0xFFFFFF03 1508 #define V_028C70_COLOR_INVALID 0x00000000 1509 #define V_028C70_COLOR_8 0x00000001 1510 #define V_028C70_COLOR_4_4 0x00000002 1511 #define V_028C70_COLOR_3_3_2 0x00000003 1512 #define V_028C70_COLOR_16 0x00000005 1513 #define V_028C70_COLOR_16_FLOAT 0x00000006 1514 #define V_028C70_COLOR_8_8 0x00000007 1515 #define V_028C70_COLOR_5_6_5 0x00000008 1516 #define V_028C70_COLOR_6_5_5 0x00000009 1517 #define V_028C70_COLOR_1_5_5_5 0x0000000A 1518 #define V_028C70_COLOR_4_4_4_4 0x0000000B 1519 #define V_028C70_COLOR_5_5_5_1 0x0000000C 1520 #define V_028C70_COLOR_32 0x0000000D 1521 #define V_028C70_COLOR_32_FLOAT 0x0000000E 1522 #define V_028C70_COLOR_16_16 0x0000000F 1523 #define V_028C70_COLOR_16_16_FLOAT 0x00000010 1524 #define V_028C70_COLOR_8_24 0x00000011 1525 #define V_028C70_COLOR_8_24_FLOAT 0x00000012 1526 #define V_028C70_COLOR_24_8 0x00000013 1527 #define V_028C70_COLOR_24_8_FLOAT 0x00000014 1528 #define V_028C70_COLOR_10_11_11 0x00000015 1529 #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1530 #define V_028C70_COLOR_11_11_10 0x00000017 1531 #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1532 #define V_028C70_COLOR_2_10_10_10 0x00000019 1533 #define V_028C70_COLOR_8_8_8_8 0x0000001A 1534 #define V_028C70_COLOR_10_10_10_2 0x0000001B 1535 #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1536 #define V_028C70_COLOR_32_32 0x0000001D 1537 #define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1538 #define V_028C70_COLOR_16_16_16_16 0x0000001F 1539 #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1540 #define V_028C70_COLOR_32_32_32_32 0x00000022 1541 #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1542 #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1543 #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1544 #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1545 #define C_028C70_ARRAY_MODE 0xFFFFF0FF 1546 #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1547 #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1548 #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1549 #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1550 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1551 #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1552 #define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1553 #define V_028C70_NUMBER_UNORM 0x00000000 1554 #define V_028C70_NUMBER_SNORM 0x00000001 1555 #define V_028C70_NUMBER_USCALED 0x00000002 1556 #define V_028C70_NUMBER_SSCALED 0x00000003 1557 #define V_028C70_NUMBER_UINT 0x00000004 1558 #define V_028C70_NUMBER_SINT 0x00000005 1559 #define V_028C70_NUMBER_SRGB 0x00000006 1560 #define V_028C70_NUMBER_FLOAT 0x00000007 1561 #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1562 #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1563 #define C_028C70_COMP_SWAP 0xFFFE7FFF 1564 #define V_028C70_SWAP_STD 0x00000000 1565 #define V_028C70_SWAP_ALT 0x00000001 1566 #define V_028C70_SWAP_STD_REV 0x00000002 1567 #define V_028C70_SWAP_ALT_REV 0x00000003 1568 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1569 #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1570 #define C_028C70_FAST_CLEAR 0xFFFDFFFF 1571 #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1572 #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1573 #define C_028C70_COMPRESSION 0xFFF3FFFF 1574 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1575 #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1576 #define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1577 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1578 #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1579 #define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1580 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1581 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1582 #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1583 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1584 #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1585 #define C_028C70_ROUND_MODE 0xFFBFFFFF 1586 #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1587 #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1588 #define C_028C70_TILE_COMPACT 0xFF7FFFFF 1589 #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1590 #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1591 #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1592 #define V_028C70_EXPORT_4C_32BPC 0x0 1593 #define V_028C70_EXPORT_4C_16BPC 0x1 1594 #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1595 #define S_028C70_RAT(x) (((x) & 0x1) << 26) 1596 #define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1597 #define C_028C70_RAT 0xFBFFFFFF 1598 #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1599 #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1600 #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1601 1602 #define CB_COLOR0_INFO 0x28c70 1603 # define CB_FORMAT(x) ((x) << 2) 1604 # define CB_ARRAY_MODE(x) ((x) << 8) 1605 # define ARRAY_LINEAR_GENERAL 0 1606 # define ARRAY_LINEAR_ALIGNED 1 1607 # define ARRAY_1D_TILED_THIN1 2 1608 # define ARRAY_2D_TILED_THIN1 4 1609 # define CB_SOURCE_FORMAT(x) ((x) << 24) 1610 # define CB_SF_EXPORT_FULL 0 1611 # define CB_SF_EXPORT_NORM 1 1612 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1613 #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1614 #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1615 #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1616 #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1617 #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1618 #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1619 #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1620 #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1621 #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1622 #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1623 #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1624 #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1625 #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1626 #define CB_COLOR0_ATTRIB 0x28c74 1627 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1628 # define ADDR_SURF_TILE_SPLIT_64B 0 1629 # define ADDR_SURF_TILE_SPLIT_128B 1 1630 # define ADDR_SURF_TILE_SPLIT_256B 2 1631 # define ADDR_SURF_TILE_SPLIT_512B 3 1632 # define ADDR_SURF_TILE_SPLIT_1KB 4 1633 # define ADDR_SURF_TILE_SPLIT_2KB 5 1634 # define ADDR_SURF_TILE_SPLIT_4KB 6 1635 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1636 # define ADDR_SURF_2_BANK 0 1637 # define ADDR_SURF_4_BANK 1 1638 # define ADDR_SURF_8_BANK 2 1639 # define ADDR_SURF_16_BANK 3 1640 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1641 # define ADDR_SURF_BANK_WIDTH_1 0 1642 # define ADDR_SURF_BANK_WIDTH_2 1 1643 # define ADDR_SURF_BANK_WIDTH_4 2 1644 # define ADDR_SURF_BANK_WIDTH_8 3 1645 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1646 # define ADDR_SURF_BANK_HEIGHT_1 0 1647 # define ADDR_SURF_BANK_HEIGHT_2 1 1648 # define ADDR_SURF_BANK_HEIGHT_4 2 1649 # define ADDR_SURF_BANK_HEIGHT_8 3 1650 # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1651 #define CB_COLOR0_DIM 0x28c78 1652 /* only CB0-7 blocks have these regs */ 1653 #define CB_COLOR0_CMASK 0x28c7c 1654 #define CB_COLOR0_CMASK_SLICE 0x28c80 1655 #define CB_COLOR0_FMASK 0x28c84 1656 #define CB_COLOR0_FMASK_SLICE 0x28c88 1657 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 1658 #define CB_COLOR0_CLEAR_WORD1 0x28c90 1659 #define CB_COLOR0_CLEAR_WORD2 0x28c94 1660 #define CB_COLOR0_CLEAR_WORD3 0x28c98 1661 1662 #define CB_COLOR1_BASE 0x28c9c 1663 #define CB_COLOR2_BASE 0x28cd8 1664 #define CB_COLOR3_BASE 0x28d14 1665 #define CB_COLOR4_BASE 0x28d50 1666 #define CB_COLOR5_BASE 0x28d8c 1667 #define CB_COLOR6_BASE 0x28dc8 1668 #define CB_COLOR7_BASE 0x28e04 1669 #define CB_COLOR8_BASE 0x28e40 1670 #define CB_COLOR9_BASE 0x28e5c 1671 #define CB_COLOR10_BASE 0x28e78 1672 #define CB_COLOR11_BASE 0x28e94 1673 1674 #define CB_COLOR1_PITCH 0x28ca0 1675 #define CB_COLOR2_PITCH 0x28cdc 1676 #define CB_COLOR3_PITCH 0x28d18 1677 #define CB_COLOR4_PITCH 0x28d54 1678 #define CB_COLOR5_PITCH 0x28d90 1679 #define CB_COLOR6_PITCH 0x28dcc 1680 #define CB_COLOR7_PITCH 0x28e08 1681 #define CB_COLOR8_PITCH 0x28e44 1682 #define CB_COLOR9_PITCH 0x28e60 1683 #define CB_COLOR10_PITCH 0x28e7c 1684 #define CB_COLOR11_PITCH 0x28e98 1685 1686 #define CB_COLOR1_SLICE 0x28ca4 1687 #define CB_COLOR2_SLICE 0x28ce0 1688 #define CB_COLOR3_SLICE 0x28d1c 1689 #define CB_COLOR4_SLICE 0x28d58 1690 #define CB_COLOR5_SLICE 0x28d94 1691 #define CB_COLOR6_SLICE 0x28dd0 1692 #define CB_COLOR7_SLICE 0x28e0c 1693 #define CB_COLOR8_SLICE 0x28e48 1694 #define CB_COLOR9_SLICE 0x28e64 1695 #define CB_COLOR10_SLICE 0x28e80 1696 #define CB_COLOR11_SLICE 0x28e9c 1697 1698 #define CB_COLOR1_VIEW 0x28ca8 1699 #define CB_COLOR2_VIEW 0x28ce4 1700 #define CB_COLOR3_VIEW 0x28d20 1701 #define CB_COLOR4_VIEW 0x28d5c 1702 #define CB_COLOR5_VIEW 0x28d98 1703 #define CB_COLOR6_VIEW 0x28dd4 1704 #define CB_COLOR7_VIEW 0x28e10 1705 #define CB_COLOR8_VIEW 0x28e4c 1706 #define CB_COLOR9_VIEW 0x28e68 1707 #define CB_COLOR10_VIEW 0x28e84 1708 #define CB_COLOR11_VIEW 0x28ea0 1709 1710 #define CB_COLOR1_INFO 0x28cac 1711 #define CB_COLOR2_INFO 0x28ce8 1712 #define CB_COLOR3_INFO 0x28d24 1713 #define CB_COLOR4_INFO 0x28d60 1714 #define CB_COLOR5_INFO 0x28d9c 1715 #define CB_COLOR6_INFO 0x28dd8 1716 #define CB_COLOR7_INFO 0x28e14 1717 #define CB_COLOR8_INFO 0x28e50 1718 #define CB_COLOR9_INFO 0x28e6c 1719 #define CB_COLOR10_INFO 0x28e88 1720 #define CB_COLOR11_INFO 0x28ea4 1721 1722 #define CB_COLOR1_ATTRIB 0x28cb0 1723 #define CB_COLOR2_ATTRIB 0x28cec 1724 #define CB_COLOR3_ATTRIB 0x28d28 1725 #define CB_COLOR4_ATTRIB 0x28d64 1726 #define CB_COLOR5_ATTRIB 0x28da0 1727 #define CB_COLOR6_ATTRIB 0x28ddc 1728 #define CB_COLOR7_ATTRIB 0x28e18 1729 #define CB_COLOR8_ATTRIB 0x28e54 1730 #define CB_COLOR9_ATTRIB 0x28e70 1731 #define CB_COLOR10_ATTRIB 0x28e8c 1732 #define CB_COLOR11_ATTRIB 0x28ea8 1733 1734 #define CB_COLOR1_DIM 0x28cb4 1735 #define CB_COLOR2_DIM 0x28cf0 1736 #define CB_COLOR3_DIM 0x28d2c 1737 #define CB_COLOR4_DIM 0x28d68 1738 #define CB_COLOR5_DIM 0x28da4 1739 #define CB_COLOR6_DIM 0x28de0 1740 #define CB_COLOR7_DIM 0x28e1c 1741 #define CB_COLOR8_DIM 0x28e58 1742 #define CB_COLOR9_DIM 0x28e74 1743 #define CB_COLOR10_DIM 0x28e90 1744 #define CB_COLOR11_DIM 0x28eac 1745 1746 #define CB_COLOR1_CMASK 0x28cb8 1747 #define CB_COLOR2_CMASK 0x28cf4 1748 #define CB_COLOR3_CMASK 0x28d30 1749 #define CB_COLOR4_CMASK 0x28d6c 1750 #define CB_COLOR5_CMASK 0x28da8 1751 #define CB_COLOR6_CMASK 0x28de4 1752 #define CB_COLOR7_CMASK 0x28e20 1753 1754 #define CB_COLOR1_CMASK_SLICE 0x28cbc 1755 #define CB_COLOR2_CMASK_SLICE 0x28cf8 1756 #define CB_COLOR3_CMASK_SLICE 0x28d34 1757 #define CB_COLOR4_CMASK_SLICE 0x28d70 1758 #define CB_COLOR5_CMASK_SLICE 0x28dac 1759 #define CB_COLOR6_CMASK_SLICE 0x28de8 1760 #define CB_COLOR7_CMASK_SLICE 0x28e24 1761 1762 #define CB_COLOR1_FMASK 0x28cc0 1763 #define CB_COLOR2_FMASK 0x28cfc 1764 #define CB_COLOR3_FMASK 0x28d38 1765 #define CB_COLOR4_FMASK 0x28d74 1766 #define CB_COLOR5_FMASK 0x28db0 1767 #define CB_COLOR6_FMASK 0x28dec 1768 #define CB_COLOR7_FMASK 0x28e28 1769 1770 #define CB_COLOR1_FMASK_SLICE 0x28cc4 1771 #define CB_COLOR2_FMASK_SLICE 0x28d00 1772 #define CB_COLOR3_FMASK_SLICE 0x28d3c 1773 #define CB_COLOR4_FMASK_SLICE 0x28d78 1774 #define CB_COLOR5_FMASK_SLICE 0x28db4 1775 #define CB_COLOR6_FMASK_SLICE 0x28df0 1776 #define CB_COLOR7_FMASK_SLICE 0x28e2c 1777 1778 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 1779 #define CB_COLOR2_CLEAR_WORD0 0x28d04 1780 #define CB_COLOR3_CLEAR_WORD0 0x28d40 1781 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 1782 #define CB_COLOR5_CLEAR_WORD0 0x28db8 1783 #define CB_COLOR6_CLEAR_WORD0 0x28df4 1784 #define CB_COLOR7_CLEAR_WORD0 0x28e30 1785 1786 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 1787 #define CB_COLOR2_CLEAR_WORD1 0x28d08 1788 #define CB_COLOR3_CLEAR_WORD1 0x28d44 1789 #define CB_COLOR4_CLEAR_WORD1 0x28d80 1790 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 1791 #define CB_COLOR6_CLEAR_WORD1 0x28df8 1792 #define CB_COLOR7_CLEAR_WORD1 0x28e34 1793 1794 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 1795 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 1796 #define CB_COLOR3_CLEAR_WORD2 0x28d48 1797 #define CB_COLOR4_CLEAR_WORD2 0x28d84 1798 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 1799 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 1800 #define CB_COLOR7_CLEAR_WORD2 0x28e38 1801 1802 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 1803 #define CB_COLOR2_CLEAR_WORD3 0x28d10 1804 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 1805 #define CB_COLOR4_CLEAR_WORD3 0x28d88 1806 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 1807 #define CB_COLOR6_CLEAR_WORD3 0x28e00 1808 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 1809 1810 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 1811 # define TEX_DIM(x) ((x) << 0) 1812 # define SQ_TEX_DIM_1D 0 1813 # define SQ_TEX_DIM_2D 1 1814 # define SQ_TEX_DIM_3D 2 1815 # define SQ_TEX_DIM_CUBEMAP 3 1816 # define SQ_TEX_DIM_1D_ARRAY 4 1817 # define SQ_TEX_DIM_2D_ARRAY 5 1818 # define SQ_TEX_DIM_2D_MSAA 6 1819 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1820 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 1821 # define TEX_ARRAY_MODE(x) ((x) << 28) 1822 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 1823 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1824 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 1825 # define TEX_DST_SEL_X(x) ((x) << 16) 1826 # define TEX_DST_SEL_Y(x) ((x) << 19) 1827 # define TEX_DST_SEL_Z(x) ((x) << 22) 1828 # define TEX_DST_SEL_W(x) ((x) << 25) 1829 # define SQ_SEL_X 0 1830 # define SQ_SEL_Y 1 1831 # define SQ_SEL_Z 2 1832 # define SQ_SEL_W 3 1833 # define SQ_SEL_0 4 1834 # define SQ_SEL_1 5 1835 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 1836 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 1837 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1838 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1839 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1840 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1841 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1842 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1843 #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1844 #define S_030000_DIM(x) (((x) & 0x7) << 0) 1845 #define G_030000_DIM(x) (((x) >> 0) & 0x7) 1846 #define C_030000_DIM 0xFFFFFFF8 1847 #define V_030000_SQ_TEX_DIM_1D 0x00000000 1848 #define V_030000_SQ_TEX_DIM_2D 0x00000001 1849 #define V_030000_SQ_TEX_DIM_3D 0x00000002 1850 #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1851 #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1852 #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1853 #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1854 #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1855 #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1856 #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1857 #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1858 #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1859 #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1860 #define C_030000_PITCH 0xFFFC003F 1861 #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1862 #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1863 #define C_030000_TEX_WIDTH 0x0003FFFF 1864 #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1865 #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1866 #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1867 #define C_030004_TEX_HEIGHT 0xFFFFC000 1868 #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1869 #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1870 #define C_030004_TEX_DEPTH 0xF8003FFF 1871 #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1872 #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1873 #define C_030004_ARRAY_MODE 0x0FFFFFFF 1874 #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1875 #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1876 #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1877 #define C_030008_BASE_ADDRESS 0x00000000 1878 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1879 #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1880 #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1881 #define C_03000C_MIP_ADDRESS 0x00000000 1882 #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1883 #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1884 #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1885 #define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1886 #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1887 #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1888 #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1889 #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1890 #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1891 #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1892 #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1893 #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1894 #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1895 #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1896 #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1897 #define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1898 #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1899 #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1900 #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1901 #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1902 #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1903 #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1904 #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1905 #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1906 #define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1907 #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1908 #define V_030010_SRF_MODE_NO_ZERO 0x00000001 1909 #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1910 #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1911 #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1912 #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1913 #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1914 #define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1915 #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1916 #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1917 #define C_030010_DST_SEL_X 0xFFF8FFFF 1918 #define V_030010_SQ_SEL_X 0x00000000 1919 #define V_030010_SQ_SEL_Y 0x00000001 1920 #define V_030010_SQ_SEL_Z 0x00000002 1921 #define V_030010_SQ_SEL_W 0x00000003 1922 #define V_030010_SQ_SEL_0 0x00000004 1923 #define V_030010_SQ_SEL_1 0x00000005 1924 #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1925 #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1926 #define C_030010_DST_SEL_Y 0xFFC7FFFF 1927 #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1928 #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1929 #define C_030010_DST_SEL_Z 0xFE3FFFFF 1930 #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1931 #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1932 #define C_030010_DST_SEL_W 0xF1FFFFFF 1933 #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1934 #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1935 #define C_030010_BASE_LEVEL 0x0FFFFFFF 1936 #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1937 #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1938 #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1939 #define C_030014_LAST_LEVEL 0xFFFFFFF0 1940 #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1941 #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1942 #define C_030014_BASE_ARRAY 0xFFFE000F 1943 #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1944 #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1945 #define C_030014_LAST_ARRAY 0xC001FFFF 1946 #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1947 #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1948 #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1949 #define C_030018_MAX_ANISO 0xFFFFFFF8 1950 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1951 #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1952 #define C_030018_PERF_MODULATION 0xFFFFFFC7 1953 #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1954 #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1955 #define C_030018_INTERLACED 0xFFFFFFBF 1956 #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1957 #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1958 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1959 #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1960 #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1961 #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1962 #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1963 #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1964 #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1965 #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1966 #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1967 #define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1968 #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1969 #define C_03001C_TYPE 0x3FFFFFFF 1970 #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1971 #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1972 #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1973 #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1974 #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1975 #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1976 #define C_03001C_DATA_FORMAT 0xFFFFFFC0 1977 1978 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 1979 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 1980 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 1981 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1982 # define SQ_VTXC_STRIDE(x) ((x) << 8) 1983 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1984 # define SQ_ENDIAN_NONE 0 1985 # define SQ_ENDIAN_8IN16 1 1986 # define SQ_ENDIAN_8IN32 2 1987 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1988 # define SQ_VTCX_SEL_X(x) ((x) << 3) 1989 # define SQ_VTCX_SEL_Y(x) ((x) << 6) 1990 # define SQ_VTCX_SEL_Z(x) ((x) << 9) 1991 # define SQ_VTCX_SEL_W(x) ((x) << 12) 1992 #define SQ_VTX_CONSTANT_WORD4_0 0x30010 1993 #define SQ_VTX_CONSTANT_WORD5_0 0x30014 1994 #define SQ_VTX_CONSTANT_WORD6_0 0x30018 1995 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1996 1997 #define TD_PS_BORDER_COLOR_INDEX 0xA400 1998 #define TD_PS_BORDER_COLOR_RED 0xA404 1999 #define TD_PS_BORDER_COLOR_GREEN 0xA408 2000 #define TD_PS_BORDER_COLOR_BLUE 0xA40C 2001 #define TD_PS_BORDER_COLOR_ALPHA 0xA410 2002 #define TD_VS_BORDER_COLOR_INDEX 0xA414 2003 #define TD_VS_BORDER_COLOR_RED 0xA418 2004 #define TD_VS_BORDER_COLOR_GREEN 0xA41C 2005 #define TD_VS_BORDER_COLOR_BLUE 0xA420 2006 #define TD_VS_BORDER_COLOR_ALPHA 0xA424 2007 #define TD_GS_BORDER_COLOR_INDEX 0xA428 2008 #define TD_GS_BORDER_COLOR_RED 0xA42C 2009 #define TD_GS_BORDER_COLOR_GREEN 0xA430 2010 #define TD_GS_BORDER_COLOR_BLUE 0xA434 2011 #define TD_GS_BORDER_COLOR_ALPHA 0xA438 2012 #define TD_HS_BORDER_COLOR_INDEX 0xA43C 2013 #define TD_HS_BORDER_COLOR_RED 0xA440 2014 #define TD_HS_BORDER_COLOR_GREEN 0xA444 2015 #define TD_HS_BORDER_COLOR_BLUE 0xA448 2016 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C 2017 #define TD_LS_BORDER_COLOR_INDEX 0xA450 2018 #define TD_LS_BORDER_COLOR_RED 0xA454 2019 #define TD_LS_BORDER_COLOR_GREEN 0xA458 2020 #define TD_LS_BORDER_COLOR_BLUE 0xA45C 2021 #define TD_LS_BORDER_COLOR_ALPHA 0xA460 2022 #define TD_CS_BORDER_COLOR_INDEX 0xA464 2023 #define TD_CS_BORDER_COLOR_RED 0xA468 2024 #define TD_CS_BORDER_COLOR_GREEN 0xA46C 2025 #define TD_CS_BORDER_COLOR_BLUE 0xA470 2026 #define TD_CS_BORDER_COLOR_ALPHA 0xA474 2027 2028 /* cayman 3D regs */ 2029 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 2030 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 2031 #define CAYMAN_DB_EQAA 0x28804 2032 #define CAYMAN_DB_DEPTH_INFO 0x2803C 2033 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 2034 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 2035 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 2036 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 2037 /* cayman packet3 addition */ 2038 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2039 2040 /* DMA regs common on r6xx/r7xx/evergreen/ni */ 2041 #define DMA_RB_CNTL 0xd000 2042 # define DMA_RB_ENABLE (1 << 0) 2043 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 2044 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 2045 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 2046 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 2047 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 2048 #define DMA_STATUS_REG 0xd034 2049 # define DMA_IDLE (1 << 0) 2050 2051 #endif 2052