1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "cikd.h" 28 #include "r600_dpm.h" 29 #include "kv_dpm.h" 30 #include "radeon_asic.h" 31 #include <linux/seq_file.h> 32 33 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 34 #define KV_MINIMUM_ENGINE_CLOCK 800 35 #define SMC_RAM_END 0x40000 36 37 static int kv_enable_nb_dpm(struct radeon_device *rdev, 38 bool enable); 39 static void kv_init_graphics_levels(struct radeon_device *rdev); 40 static int kv_calculate_ds_divider(struct radeon_device *rdev); 41 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev); 42 static int kv_calculate_dpm_settings(struct radeon_device *rdev); 43 static void kv_enable_new_levels(struct radeon_device *rdev); 44 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 45 struct radeon_ps *new_rps); 46 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level); 47 static int kv_set_enabled_levels(struct radeon_device *rdev); 48 static int kv_force_dpm_highest(struct radeon_device *rdev); 49 static int kv_force_dpm_lowest(struct radeon_device *rdev); 50 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 51 struct radeon_ps *new_rps, 52 struct radeon_ps *old_rps); 53 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 54 int min_temp, int max_temp); 55 static int kv_init_fps_limits(struct radeon_device *rdev); 56 57 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate); 58 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate); 59 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate); 60 61 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 62 { 63 { 0, 4, 1 }, 64 { 1, 4, 1 }, 65 { 2, 5, 1 }, 66 { 3, 4, 2 }, 67 { 4, 1, 1 }, 68 { 5, 5, 2 }, 69 { 6, 6, 1 }, 70 { 7, 9, 2 }, 71 { 0xffffffff } 72 }; 73 74 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = 75 { 76 { 0, 4, 1 }, 77 { 0xffffffff } 78 }; 79 80 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = 81 { 82 { 0, 4, 1 }, 83 { 0xffffffff } 84 }; 85 86 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = 87 { 88 { 0, 4, 1 }, 89 { 0xffffffff } 90 }; 91 92 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = 93 { 94 { 0, 4, 1 }, 95 { 0xffffffff } 96 }; 97 98 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = 99 { 100 { 0, 4, 1 }, 101 { 1, 4, 1 }, 102 { 2, 5, 1 }, 103 { 3, 4, 1 }, 104 { 4, 1, 1 }, 105 { 5, 5, 1 }, 106 { 6, 6, 1 }, 107 { 7, 9, 1 }, 108 { 8, 4, 1 }, 109 { 9, 2, 1 }, 110 { 10, 3, 1 }, 111 { 11, 6, 1 }, 112 { 12, 8, 2 }, 113 { 13, 1, 1 }, 114 { 14, 2, 1 }, 115 { 15, 3, 1 }, 116 { 16, 1, 1 }, 117 { 17, 4, 1 }, 118 { 18, 3, 1 }, 119 { 19, 1, 1 }, 120 { 20, 8, 1 }, 121 { 21, 5, 1 }, 122 { 22, 1, 1 }, 123 { 23, 1, 1 }, 124 { 24, 4, 1 }, 125 { 27, 6, 1 }, 126 { 28, 1, 1 }, 127 { 0xffffffff } 128 }; 129 130 static const struct kv_lcac_config_reg sx0_cac_config_reg[] = 131 { 132 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 133 }; 134 135 static const struct kv_lcac_config_reg mc0_cac_config_reg[] = 136 { 137 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 138 }; 139 140 static const struct kv_lcac_config_reg mc1_cac_config_reg[] = 141 { 142 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 143 }; 144 145 static const struct kv_lcac_config_reg mc2_cac_config_reg[] = 146 { 147 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 148 }; 149 150 static const struct kv_lcac_config_reg mc3_cac_config_reg[] = 151 { 152 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 153 }; 154 155 static const struct kv_lcac_config_reg cpl_cac_config_reg[] = 156 { 157 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 158 }; 159 160 static const struct kv_pt_config_reg didt_config_kv[] = 161 { 162 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 163 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 164 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 165 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 166 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 167 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 168 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 169 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 170 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 171 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 172 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 173 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 174 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 175 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 176 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 177 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 178 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 179 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 180 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 181 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 182 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 183 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 184 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 185 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 186 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 187 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 188 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 189 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 190 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 191 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 192 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 193 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 194 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 195 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 196 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 197 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 198 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 199 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 200 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 201 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 202 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 203 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 204 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 205 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 206 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 207 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 208 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 209 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 210 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 211 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 212 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 213 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 214 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 215 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 216 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 217 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 218 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 219 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 220 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 221 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 222 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 223 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 224 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 225 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 226 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 227 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 228 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 229 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 230 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 231 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 232 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 233 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 234 { 0xFFFFFFFF } 235 }; 236 237 static struct kv_ps *kv_get_ps(struct radeon_ps *rps) 238 { 239 struct kv_ps *ps = rps->ps_priv; 240 241 return ps; 242 } 243 244 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev) 245 { 246 struct kv_power_info *pi = rdev->pm.dpm.priv; 247 248 return pi; 249 } 250 251 #if 0 252 static void kv_program_local_cac_table(struct radeon_device *rdev, 253 const struct kv_lcac_config_values *local_cac_table, 254 const struct kv_lcac_config_reg *local_cac_reg) 255 { 256 u32 i, count, data; 257 const struct kv_lcac_config_values *values = local_cac_table; 258 259 while (values->block_id != 0xffffffff) { 260 count = values->signal_id; 261 for (i = 0; i < count; i++) { 262 data = ((values->block_id << local_cac_reg->block_shift) & 263 local_cac_reg->block_mask); 264 data |= ((i << local_cac_reg->signal_shift) & 265 local_cac_reg->signal_mask); 266 data |= ((values->t << local_cac_reg->t_shift) & 267 local_cac_reg->t_mask); 268 data |= ((1 << local_cac_reg->enable_shift) & 269 local_cac_reg->enable_mask); 270 WREG32_SMC(local_cac_reg->cntl, data); 271 } 272 values++; 273 } 274 } 275 #endif 276 277 static int kv_program_pt_config_registers(struct radeon_device *rdev, 278 const struct kv_pt_config_reg *cac_config_regs) 279 { 280 const struct kv_pt_config_reg *config_regs = cac_config_regs; 281 u32 data; 282 u32 cache = 0; 283 284 if (config_regs == NULL) 285 return -EINVAL; 286 287 while (config_regs->offset != 0xFFFFFFFF) { 288 if (config_regs->type == KV_CONFIGREG_CACHE) { 289 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 290 } else { 291 switch (config_regs->type) { 292 case KV_CONFIGREG_SMC_IND: 293 data = RREG32_SMC(config_regs->offset); 294 break; 295 case KV_CONFIGREG_DIDT_IND: 296 data = RREG32_DIDT(config_regs->offset); 297 break; 298 default: 299 data = RREG32(config_regs->offset << 2); 300 break; 301 } 302 303 data &= ~config_regs->mask; 304 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 305 data |= cache; 306 cache = 0; 307 308 switch (config_regs->type) { 309 case KV_CONFIGREG_SMC_IND: 310 WREG32_SMC(config_regs->offset, data); 311 break; 312 case KV_CONFIGREG_DIDT_IND: 313 WREG32_DIDT(config_regs->offset, data); 314 break; 315 default: 316 WREG32(config_regs->offset << 2, data); 317 break; 318 } 319 } 320 config_regs++; 321 } 322 323 return 0; 324 } 325 326 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable) 327 { 328 struct kv_power_info *pi = kv_get_pi(rdev); 329 u32 data; 330 331 if (pi->caps_sq_ramping) { 332 data = RREG32_DIDT(DIDT_SQ_CTRL0); 333 if (enable) 334 data |= DIDT_CTRL_EN; 335 else 336 data &= ~DIDT_CTRL_EN; 337 WREG32_DIDT(DIDT_SQ_CTRL0, data); 338 } 339 340 if (pi->caps_db_ramping) { 341 data = RREG32_DIDT(DIDT_DB_CTRL0); 342 if (enable) 343 data |= DIDT_CTRL_EN; 344 else 345 data &= ~DIDT_CTRL_EN; 346 WREG32_DIDT(DIDT_DB_CTRL0, data); 347 } 348 349 if (pi->caps_td_ramping) { 350 data = RREG32_DIDT(DIDT_TD_CTRL0); 351 if (enable) 352 data |= DIDT_CTRL_EN; 353 else 354 data &= ~DIDT_CTRL_EN; 355 WREG32_DIDT(DIDT_TD_CTRL0, data); 356 } 357 358 if (pi->caps_tcp_ramping) { 359 data = RREG32_DIDT(DIDT_TCP_CTRL0); 360 if (enable) 361 data |= DIDT_CTRL_EN; 362 else 363 data &= ~DIDT_CTRL_EN; 364 WREG32_DIDT(DIDT_TCP_CTRL0, data); 365 } 366 } 367 368 static int kv_enable_didt(struct radeon_device *rdev, bool enable) 369 { 370 struct kv_power_info *pi = kv_get_pi(rdev); 371 int ret; 372 373 if (pi->caps_sq_ramping || 374 pi->caps_db_ramping || 375 pi->caps_td_ramping || 376 pi->caps_tcp_ramping) { 377 cik_enter_rlc_safe_mode(rdev); 378 379 if (enable) { 380 ret = kv_program_pt_config_registers(rdev, didt_config_kv); 381 if (ret) { 382 cik_exit_rlc_safe_mode(rdev); 383 return ret; 384 } 385 } 386 387 kv_do_enable_didt(rdev, enable); 388 389 cik_exit_rlc_safe_mode(rdev); 390 } 391 392 return 0; 393 } 394 395 #if 0 396 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev) 397 { 398 struct kv_power_info *pi = kv_get_pi(rdev); 399 400 if (pi->caps_cac) { 401 WREG32_SMC(LCAC_SX0_OVR_SEL, 0); 402 WREG32_SMC(LCAC_SX0_OVR_VAL, 0); 403 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg); 404 405 WREG32_SMC(LCAC_MC0_OVR_SEL, 0); 406 WREG32_SMC(LCAC_MC0_OVR_VAL, 0); 407 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); 408 409 WREG32_SMC(LCAC_MC1_OVR_SEL, 0); 410 WREG32_SMC(LCAC_MC1_OVR_VAL, 0); 411 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); 412 413 WREG32_SMC(LCAC_MC2_OVR_SEL, 0); 414 WREG32_SMC(LCAC_MC2_OVR_VAL, 0); 415 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); 416 417 WREG32_SMC(LCAC_MC3_OVR_SEL, 0); 418 WREG32_SMC(LCAC_MC3_OVR_VAL, 0); 419 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); 420 421 WREG32_SMC(LCAC_CPL_OVR_SEL, 0); 422 WREG32_SMC(LCAC_CPL_OVR_VAL, 0); 423 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); 424 } 425 } 426 #endif 427 428 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable) 429 { 430 struct kv_power_info *pi = kv_get_pi(rdev); 431 int ret = 0; 432 433 if (pi->caps_cac) { 434 if (enable) { 435 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac); 436 if (ret) 437 pi->cac_enabled = false; 438 else 439 pi->cac_enabled = true; 440 } else if (pi->cac_enabled) { 441 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac); 442 pi->cac_enabled = false; 443 } 444 } 445 446 return ret; 447 } 448 449 static int kv_process_firmware_header(struct radeon_device *rdev) 450 { 451 struct kv_power_info *pi = kv_get_pi(rdev); 452 u32 tmp; 453 int ret; 454 455 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 456 offsetof(SMU7_Firmware_Header, DpmTable), 457 &tmp, pi->sram_end); 458 459 if (ret == 0) 460 pi->dpm_table_start = tmp; 461 462 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 463 offsetof(SMU7_Firmware_Header, SoftRegisters), 464 &tmp, pi->sram_end); 465 466 if (ret == 0) 467 pi->soft_regs_start = tmp; 468 469 return ret; 470 } 471 472 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev) 473 { 474 struct kv_power_info *pi = kv_get_pi(rdev); 475 int ret; 476 477 pi->graphics_voltage_change_enable = 1; 478 479 ret = kv_copy_bytes_to_smc(rdev, 480 pi->dpm_table_start + 481 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), 482 &pi->graphics_voltage_change_enable, 483 sizeof(u8), pi->sram_end); 484 485 return ret; 486 } 487 488 static int kv_set_dpm_interval(struct radeon_device *rdev) 489 { 490 struct kv_power_info *pi = kv_get_pi(rdev); 491 int ret; 492 493 pi->graphics_interval = 1; 494 495 ret = kv_copy_bytes_to_smc(rdev, 496 pi->dpm_table_start + 497 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), 498 &pi->graphics_interval, 499 sizeof(u8), pi->sram_end); 500 501 return ret; 502 } 503 504 static int kv_set_dpm_boot_state(struct radeon_device *rdev) 505 { 506 struct kv_power_info *pi = kv_get_pi(rdev); 507 int ret; 508 509 ret = kv_copy_bytes_to_smc(rdev, 510 pi->dpm_table_start + 511 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), 512 &pi->graphics_boot_level, 513 sizeof(u8), pi->sram_end); 514 515 return ret; 516 } 517 518 static void kv_program_vc(struct radeon_device *rdev) 519 { 520 WREG32_SMC(CG_FTV_0, 0x3FFFC100); 521 } 522 523 static void kv_clear_vc(struct radeon_device *rdev) 524 { 525 WREG32_SMC(CG_FTV_0, 0); 526 } 527 528 static int kv_set_divider_value(struct radeon_device *rdev, 529 u32 index, u32 sclk) 530 { 531 struct kv_power_info *pi = kv_get_pi(rdev); 532 struct atom_clock_dividers dividers; 533 int ret; 534 535 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 536 sclk, false, ÷rs); 537 if (ret) 538 return ret; 539 540 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; 541 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); 542 543 return 0; 544 } 545 546 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev, 547 struct sumo_vid_mapping_table *vid_mapping_table, 548 u32 vid_2bit) 549 { 550 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 551 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 552 u32 i; 553 554 if (vddc_sclk_table && vddc_sclk_table->count) { 555 if (vid_2bit < vddc_sclk_table->count) 556 return vddc_sclk_table->entries[vid_2bit].v; 557 else 558 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; 559 } else { 560 for (i = 0; i < vid_mapping_table->num_entries; i++) { 561 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 562 return vid_mapping_table->entries[i].vid_7bit; 563 } 564 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 565 } 566 } 567 568 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev, 569 struct sumo_vid_mapping_table *vid_mapping_table, 570 u32 vid_7bit) 571 { 572 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 573 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 574 u32 i; 575 576 if (vddc_sclk_table && vddc_sclk_table->count) { 577 for (i = 0; i < vddc_sclk_table->count; i++) { 578 if (vddc_sclk_table->entries[i].v == vid_7bit) 579 return i; 580 } 581 return vddc_sclk_table->count - 1; 582 } else { 583 for (i = 0; i < vid_mapping_table->num_entries; i++) { 584 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 585 return vid_mapping_table->entries[i].vid_2bit; 586 } 587 588 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 589 } 590 } 591 592 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev, 593 u16 voltage) 594 { 595 return 6200 - (voltage * 25); 596 } 597 598 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev, 599 u32 vid_2bit) 600 { 601 struct kv_power_info *pi = kv_get_pi(rdev); 602 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev, 603 &pi->sys_info.vid_mapping_table, 604 vid_2bit); 605 606 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit); 607 } 608 609 610 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid) 611 { 612 struct kv_power_info *pi = kv_get_pi(rdev); 613 614 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; 615 pi->graphics_level[index].MinVddNb = 616 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid)); 617 618 return 0; 619 } 620 621 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at) 622 { 623 struct kv_power_info *pi = kv_get_pi(rdev); 624 625 pi->graphics_level[index].AT = cpu_to_be16((u16)at); 626 627 return 0; 628 } 629 630 static void kv_dpm_power_level_enable(struct radeon_device *rdev, 631 u32 index, bool enable) 632 { 633 struct kv_power_info *pi = kv_get_pi(rdev); 634 635 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; 636 } 637 638 static void kv_start_dpm(struct radeon_device *rdev) 639 { 640 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 641 642 tmp |= GLOBAL_PWRMGT_EN; 643 WREG32_SMC(GENERAL_PWRMGT, tmp); 644 645 kv_smc_dpm_enable(rdev, true); 646 } 647 648 static void kv_stop_dpm(struct radeon_device *rdev) 649 { 650 kv_smc_dpm_enable(rdev, false); 651 } 652 653 static void kv_start_am(struct radeon_device *rdev) 654 { 655 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 656 657 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 658 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN; 659 660 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 661 } 662 663 static void kv_reset_am(struct radeon_device *rdev) 664 { 665 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 666 667 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 668 669 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 670 } 671 672 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze) 673 { 674 return kv_notify_message_to_smu(rdev, freeze ? 675 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); 676 } 677 678 static int kv_force_lowest_valid(struct radeon_device *rdev) 679 { 680 return kv_force_dpm_lowest(rdev); 681 } 682 683 static int kv_unforce_levels(struct radeon_device *rdev) 684 { 685 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 686 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); 687 else 688 return kv_set_enabled_levels(rdev); 689 } 690 691 static int kv_update_sclk_t(struct radeon_device *rdev) 692 { 693 struct kv_power_info *pi = kv_get_pi(rdev); 694 u32 low_sclk_interrupt_t = 0; 695 int ret = 0; 696 697 if (pi->caps_sclk_throttle_low_notification) { 698 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 699 700 ret = kv_copy_bytes_to_smc(rdev, 701 pi->dpm_table_start + 702 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), 703 (u8 *)&low_sclk_interrupt_t, 704 sizeof(u32), pi->sram_end); 705 } 706 return ret; 707 } 708 709 static int kv_program_bootup_state(struct radeon_device *rdev) 710 { 711 struct kv_power_info *pi = kv_get_pi(rdev); 712 u32 i; 713 struct radeon_clock_voltage_dependency_table *table = 714 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 715 716 if (table && table->count) { 717 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 718 if (table->entries[i].clk == pi->boot_pl.sclk) 719 break; 720 } 721 722 pi->graphics_boot_level = (u8)i; 723 kv_dpm_power_level_enable(rdev, i, true); 724 } else { 725 struct sumo_sclk_voltage_mapping_table *table = 726 &pi->sys_info.sclk_voltage_mapping_table; 727 728 if (table->num_max_dpm_entries == 0) 729 return -EINVAL; 730 731 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 732 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) 733 break; 734 } 735 736 pi->graphics_boot_level = (u8)i; 737 kv_dpm_power_level_enable(rdev, i, true); 738 } 739 return 0; 740 } 741 742 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev) 743 { 744 struct kv_power_info *pi = kv_get_pi(rdev); 745 int ret; 746 747 pi->graphics_therm_throttle_enable = 1; 748 749 ret = kv_copy_bytes_to_smc(rdev, 750 pi->dpm_table_start + 751 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), 752 &pi->graphics_therm_throttle_enable, 753 sizeof(u8), pi->sram_end); 754 755 return ret; 756 } 757 758 static int kv_upload_dpm_settings(struct radeon_device *rdev) 759 { 760 struct kv_power_info *pi = kv_get_pi(rdev); 761 int ret; 762 763 ret = kv_copy_bytes_to_smc(rdev, 764 pi->dpm_table_start + 765 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), 766 (u8 *)&pi->graphics_level, 767 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, 768 pi->sram_end); 769 770 if (ret) 771 return ret; 772 773 ret = kv_copy_bytes_to_smc(rdev, 774 pi->dpm_table_start + 775 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), 776 &pi->graphics_dpm_level_count, 777 sizeof(u8), pi->sram_end); 778 779 return ret; 780 } 781 782 static u32 kv_get_clock_difference(u32 a, u32 b) 783 { 784 return (a >= b) ? a - b : b - a; 785 } 786 787 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk) 788 { 789 struct kv_power_info *pi = kv_get_pi(rdev); 790 u32 value; 791 792 if (pi->caps_enable_dfs_bypass) { 793 if (kv_get_clock_difference(clk, 40000) < 200) 794 value = 3; 795 else if (kv_get_clock_difference(clk, 30000) < 200) 796 value = 2; 797 else if (kv_get_clock_difference(clk, 20000) < 200) 798 value = 7; 799 else if (kv_get_clock_difference(clk, 15000) < 200) 800 value = 6; 801 else if (kv_get_clock_difference(clk, 10000) < 200) 802 value = 8; 803 else 804 value = 0; 805 } else { 806 value = 0; 807 } 808 809 return value; 810 } 811 812 static int kv_populate_uvd_table(struct radeon_device *rdev) 813 { 814 struct kv_power_info *pi = kv_get_pi(rdev); 815 struct radeon_uvd_clock_voltage_dependency_table *table = 816 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 817 struct atom_clock_dividers dividers; 818 int ret; 819 u32 i; 820 821 if (table == NULL || table->count == 0) 822 return 0; 823 824 pi->uvd_level_count = 0; 825 for (i = 0; i < table->count; i++) { 826 if (pi->high_voltage_t && 827 (pi->high_voltage_t < table->entries[i].v)) 828 break; 829 830 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); 831 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); 832 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); 833 834 pi->uvd_level[i].VClkBypassCntl = 835 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); 836 pi->uvd_level[i].DClkBypassCntl = 837 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); 838 839 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 840 table->entries[i].vclk, false, ÷rs); 841 if (ret) 842 return ret; 843 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; 844 845 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 846 table->entries[i].dclk, false, ÷rs); 847 if (ret) 848 return ret; 849 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; 850 851 pi->uvd_level_count++; 852 } 853 854 ret = kv_copy_bytes_to_smc(rdev, 855 pi->dpm_table_start + 856 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), 857 (u8 *)&pi->uvd_level_count, 858 sizeof(u8), pi->sram_end); 859 if (ret) 860 return ret; 861 862 pi->uvd_interval = 1; 863 864 ret = kv_copy_bytes_to_smc(rdev, 865 pi->dpm_table_start + 866 offsetof(SMU7_Fusion_DpmTable, UVDInterval), 867 &pi->uvd_interval, 868 sizeof(u8), pi->sram_end); 869 if (ret) 870 return ret; 871 872 ret = kv_copy_bytes_to_smc(rdev, 873 pi->dpm_table_start + 874 offsetof(SMU7_Fusion_DpmTable, UvdLevel), 875 (u8 *)&pi->uvd_level, 876 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, 877 pi->sram_end); 878 879 return ret; 880 881 } 882 883 static int kv_populate_vce_table(struct radeon_device *rdev) 884 { 885 struct kv_power_info *pi = kv_get_pi(rdev); 886 int ret; 887 u32 i; 888 struct radeon_vce_clock_voltage_dependency_table *table = 889 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 890 struct atom_clock_dividers dividers; 891 892 if (table == NULL || table->count == 0) 893 return 0; 894 895 pi->vce_level_count = 0; 896 for (i = 0; i < table->count; i++) { 897 if (pi->high_voltage_t && 898 pi->high_voltage_t < table->entries[i].v) 899 break; 900 901 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); 902 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 903 904 pi->vce_level[i].ClkBypassCntl = 905 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); 906 907 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 908 table->entries[i].evclk, false, ÷rs); 909 if (ret) 910 return ret; 911 pi->vce_level[i].Divider = (u8)dividers.post_div; 912 913 pi->vce_level_count++; 914 } 915 916 ret = kv_copy_bytes_to_smc(rdev, 917 pi->dpm_table_start + 918 offsetof(SMU7_Fusion_DpmTable, VceLevelCount), 919 (u8 *)&pi->vce_level_count, 920 sizeof(u8), 921 pi->sram_end); 922 if (ret) 923 return ret; 924 925 pi->vce_interval = 1; 926 927 ret = kv_copy_bytes_to_smc(rdev, 928 pi->dpm_table_start + 929 offsetof(SMU7_Fusion_DpmTable, VCEInterval), 930 (u8 *)&pi->vce_interval, 931 sizeof(u8), 932 pi->sram_end); 933 if (ret) 934 return ret; 935 936 ret = kv_copy_bytes_to_smc(rdev, 937 pi->dpm_table_start + 938 offsetof(SMU7_Fusion_DpmTable, VceLevel), 939 (u8 *)&pi->vce_level, 940 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, 941 pi->sram_end); 942 943 return ret; 944 } 945 946 static int kv_populate_samu_table(struct radeon_device *rdev) 947 { 948 struct kv_power_info *pi = kv_get_pi(rdev); 949 struct radeon_clock_voltage_dependency_table *table = 950 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 951 struct atom_clock_dividers dividers; 952 int ret; 953 u32 i; 954 955 if (table == NULL || table->count == 0) 956 return 0; 957 958 pi->samu_level_count = 0; 959 for (i = 0; i < table->count; i++) { 960 if (pi->high_voltage_t && 961 pi->high_voltage_t < table->entries[i].v) 962 break; 963 964 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 965 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 966 967 pi->samu_level[i].ClkBypassCntl = 968 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk); 969 970 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 971 table->entries[i].clk, false, ÷rs); 972 if (ret) 973 return ret; 974 pi->samu_level[i].Divider = (u8)dividers.post_div; 975 976 pi->samu_level_count++; 977 } 978 979 ret = kv_copy_bytes_to_smc(rdev, 980 pi->dpm_table_start + 981 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), 982 (u8 *)&pi->samu_level_count, 983 sizeof(u8), 984 pi->sram_end); 985 if (ret) 986 return ret; 987 988 pi->samu_interval = 1; 989 990 ret = kv_copy_bytes_to_smc(rdev, 991 pi->dpm_table_start + 992 offsetof(SMU7_Fusion_DpmTable, SAMUInterval), 993 (u8 *)&pi->samu_interval, 994 sizeof(u8), 995 pi->sram_end); 996 if (ret) 997 return ret; 998 999 ret = kv_copy_bytes_to_smc(rdev, 1000 pi->dpm_table_start + 1001 offsetof(SMU7_Fusion_DpmTable, SamuLevel), 1002 (u8 *)&pi->samu_level, 1003 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, 1004 pi->sram_end); 1005 if (ret) 1006 return ret; 1007 1008 return ret; 1009 } 1010 1011 1012 static int kv_populate_acp_table(struct radeon_device *rdev) 1013 { 1014 struct kv_power_info *pi = kv_get_pi(rdev); 1015 struct radeon_clock_voltage_dependency_table *table = 1016 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1017 struct atom_clock_dividers dividers; 1018 int ret; 1019 u32 i; 1020 1021 if (table == NULL || table->count == 0) 1022 return 0; 1023 1024 pi->acp_level_count = 0; 1025 for (i = 0; i < table->count; i++) { 1026 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1027 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1028 1029 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1030 table->entries[i].clk, false, ÷rs); 1031 if (ret) 1032 return ret; 1033 pi->acp_level[i].Divider = (u8)dividers.post_div; 1034 1035 pi->acp_level_count++; 1036 } 1037 1038 ret = kv_copy_bytes_to_smc(rdev, 1039 pi->dpm_table_start + 1040 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), 1041 (u8 *)&pi->acp_level_count, 1042 sizeof(u8), 1043 pi->sram_end); 1044 if (ret) 1045 return ret; 1046 1047 pi->acp_interval = 1; 1048 1049 ret = kv_copy_bytes_to_smc(rdev, 1050 pi->dpm_table_start + 1051 offsetof(SMU7_Fusion_DpmTable, ACPInterval), 1052 (u8 *)&pi->acp_interval, 1053 sizeof(u8), 1054 pi->sram_end); 1055 if (ret) 1056 return ret; 1057 1058 ret = kv_copy_bytes_to_smc(rdev, 1059 pi->dpm_table_start + 1060 offsetof(SMU7_Fusion_DpmTable, AcpLevel), 1061 (u8 *)&pi->acp_level, 1062 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, 1063 pi->sram_end); 1064 if (ret) 1065 return ret; 1066 1067 return ret; 1068 } 1069 1070 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev) 1071 { 1072 struct kv_power_info *pi = kv_get_pi(rdev); 1073 u32 i; 1074 struct radeon_clock_voltage_dependency_table *table = 1075 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1076 1077 if (table && table->count) { 1078 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1079 if (pi->caps_enable_dfs_bypass) { 1080 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) 1081 pi->graphics_level[i].ClkBypassCntl = 3; 1082 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) 1083 pi->graphics_level[i].ClkBypassCntl = 2; 1084 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) 1085 pi->graphics_level[i].ClkBypassCntl = 7; 1086 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) 1087 pi->graphics_level[i].ClkBypassCntl = 6; 1088 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) 1089 pi->graphics_level[i].ClkBypassCntl = 8; 1090 else 1091 pi->graphics_level[i].ClkBypassCntl = 0; 1092 } else { 1093 pi->graphics_level[i].ClkBypassCntl = 0; 1094 } 1095 } 1096 } else { 1097 struct sumo_sclk_voltage_mapping_table *table = 1098 &pi->sys_info.sclk_voltage_mapping_table; 1099 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1100 if (pi->caps_enable_dfs_bypass) { 1101 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) 1102 pi->graphics_level[i].ClkBypassCntl = 3; 1103 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) 1104 pi->graphics_level[i].ClkBypassCntl = 2; 1105 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) 1106 pi->graphics_level[i].ClkBypassCntl = 7; 1107 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) 1108 pi->graphics_level[i].ClkBypassCntl = 6; 1109 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) 1110 pi->graphics_level[i].ClkBypassCntl = 8; 1111 else 1112 pi->graphics_level[i].ClkBypassCntl = 0; 1113 } else { 1114 pi->graphics_level[i].ClkBypassCntl = 0; 1115 } 1116 } 1117 } 1118 } 1119 1120 static int kv_enable_ulv(struct radeon_device *rdev, bool enable) 1121 { 1122 return kv_notify_message_to_smu(rdev, enable ? 1123 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); 1124 } 1125 1126 static void kv_reset_acp_boot_level(struct radeon_device *rdev) 1127 { 1128 struct kv_power_info *pi = kv_get_pi(rdev); 1129 1130 pi->acp_boot_level = 0xff; 1131 } 1132 1133 static void kv_update_current_ps(struct radeon_device *rdev, 1134 struct radeon_ps *rps) 1135 { 1136 struct kv_ps *new_ps = kv_get_ps(rps); 1137 struct kv_power_info *pi = kv_get_pi(rdev); 1138 1139 pi->current_rps = *rps; 1140 pi->current_ps = *new_ps; 1141 pi->current_rps.ps_priv = &pi->current_ps; 1142 } 1143 1144 static void kv_update_requested_ps(struct radeon_device *rdev, 1145 struct radeon_ps *rps) 1146 { 1147 struct kv_ps *new_ps = kv_get_ps(rps); 1148 struct kv_power_info *pi = kv_get_pi(rdev); 1149 1150 pi->requested_rps = *rps; 1151 pi->requested_ps = *new_ps; 1152 pi->requested_rps.ps_priv = &pi->requested_ps; 1153 } 1154 1155 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable) 1156 { 1157 struct kv_power_info *pi = kv_get_pi(rdev); 1158 int ret; 1159 1160 if (pi->bapm_enable) { 1161 ret = kv_smc_bapm_enable(rdev, enable); 1162 if (ret) 1163 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1164 } 1165 } 1166 1167 static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable) 1168 { 1169 u32 thermal_int; 1170 1171 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); 1172 if (enable) 1173 thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; 1174 else 1175 thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK); 1176 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); 1177 1178 } 1179 1180 int kv_dpm_enable(struct radeon_device *rdev) 1181 { 1182 struct kv_power_info *pi = kv_get_pi(rdev); 1183 int ret; 1184 1185 ret = kv_process_firmware_header(rdev); 1186 if (ret) { 1187 DRM_ERROR("kv_process_firmware_header failed\n"); 1188 return ret; 1189 } 1190 kv_init_fps_limits(rdev); 1191 kv_init_graphics_levels(rdev); 1192 ret = kv_program_bootup_state(rdev); 1193 if (ret) { 1194 DRM_ERROR("kv_program_bootup_state failed\n"); 1195 return ret; 1196 } 1197 kv_calculate_dfs_bypass_settings(rdev); 1198 ret = kv_upload_dpm_settings(rdev); 1199 if (ret) { 1200 DRM_ERROR("kv_upload_dpm_settings failed\n"); 1201 return ret; 1202 } 1203 ret = kv_populate_uvd_table(rdev); 1204 if (ret) { 1205 DRM_ERROR("kv_populate_uvd_table failed\n"); 1206 return ret; 1207 } 1208 ret = kv_populate_vce_table(rdev); 1209 if (ret) { 1210 DRM_ERROR("kv_populate_vce_table failed\n"); 1211 return ret; 1212 } 1213 ret = kv_populate_samu_table(rdev); 1214 if (ret) { 1215 DRM_ERROR("kv_populate_samu_table failed\n"); 1216 return ret; 1217 } 1218 ret = kv_populate_acp_table(rdev); 1219 if (ret) { 1220 DRM_ERROR("kv_populate_acp_table failed\n"); 1221 return ret; 1222 } 1223 kv_program_vc(rdev); 1224 #if 0 1225 kv_initialize_hardware_cac_manager(rdev); 1226 #endif 1227 kv_start_am(rdev); 1228 if (pi->enable_auto_thermal_throttling) { 1229 ret = kv_enable_auto_thermal_throttling(rdev); 1230 if (ret) { 1231 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); 1232 return ret; 1233 } 1234 } 1235 ret = kv_enable_dpm_voltage_scaling(rdev); 1236 if (ret) { 1237 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); 1238 return ret; 1239 } 1240 ret = kv_set_dpm_interval(rdev); 1241 if (ret) { 1242 DRM_ERROR("kv_set_dpm_interval failed\n"); 1243 return ret; 1244 } 1245 ret = kv_set_dpm_boot_state(rdev); 1246 if (ret) { 1247 DRM_ERROR("kv_set_dpm_boot_state failed\n"); 1248 return ret; 1249 } 1250 ret = kv_enable_ulv(rdev, true); 1251 if (ret) { 1252 DRM_ERROR("kv_enable_ulv failed\n"); 1253 return ret; 1254 } 1255 kv_start_dpm(rdev); 1256 ret = kv_enable_didt(rdev, true); 1257 if (ret) { 1258 DRM_ERROR("kv_enable_didt failed\n"); 1259 return ret; 1260 } 1261 ret = kv_enable_smc_cac(rdev, true); 1262 if (ret) { 1263 DRM_ERROR("kv_enable_smc_cac failed\n"); 1264 return ret; 1265 } 1266 1267 kv_reset_acp_boot_level(rdev); 1268 1269 ret = kv_smc_bapm_enable(rdev, false); 1270 if (ret) { 1271 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1272 return ret; 1273 } 1274 1275 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1276 1277 return ret; 1278 } 1279 1280 int kv_dpm_late_enable(struct radeon_device *rdev) 1281 { 1282 int ret = 0; 1283 1284 if (rdev->irq.installed && 1285 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1286 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1287 if (ret) { 1288 DRM_ERROR("kv_set_thermal_temperature_range failed\n"); 1289 return ret; 1290 } 1291 kv_enable_thermal_int(rdev, true); 1292 } 1293 1294 /* powerdown unused blocks for now */ 1295 kv_dpm_powergate_acp(rdev, true); 1296 kv_dpm_powergate_samu(rdev, true); 1297 kv_dpm_powergate_vce(rdev, true); 1298 kv_dpm_powergate_uvd(rdev, true); 1299 1300 return ret; 1301 } 1302 1303 void kv_dpm_disable(struct radeon_device *rdev) 1304 { 1305 kv_smc_bapm_enable(rdev, false); 1306 1307 if (rdev->family == CHIP_MULLINS) 1308 kv_enable_nb_dpm(rdev, false); 1309 1310 /* powerup blocks */ 1311 kv_dpm_powergate_acp(rdev, false); 1312 kv_dpm_powergate_samu(rdev, false); 1313 kv_dpm_powergate_vce(rdev, false); 1314 kv_dpm_powergate_uvd(rdev, false); 1315 1316 kv_enable_smc_cac(rdev, false); 1317 kv_enable_didt(rdev, false); 1318 kv_clear_vc(rdev); 1319 kv_stop_dpm(rdev); 1320 kv_enable_ulv(rdev, false); 1321 kv_reset_am(rdev); 1322 kv_enable_thermal_int(rdev, false); 1323 1324 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1325 } 1326 1327 #if 0 1328 static int kv_write_smc_soft_register(struct radeon_device *rdev, 1329 u16 reg_offset, u32 value) 1330 { 1331 struct kv_power_info *pi = kv_get_pi(rdev); 1332 1333 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, 1334 (u8 *)&value, sizeof(u16), pi->sram_end); 1335 } 1336 1337 static int kv_read_smc_soft_register(struct radeon_device *rdev, 1338 u16 reg_offset, u32 *value) 1339 { 1340 struct kv_power_info *pi = kv_get_pi(rdev); 1341 1342 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, 1343 value, pi->sram_end); 1344 } 1345 #endif 1346 1347 static void kv_init_sclk_t(struct radeon_device *rdev) 1348 { 1349 struct kv_power_info *pi = kv_get_pi(rdev); 1350 1351 pi->low_sclk_interrupt_t = 0; 1352 } 1353 1354 static int kv_init_fps_limits(struct radeon_device *rdev) 1355 { 1356 struct kv_power_info *pi = kv_get_pi(rdev); 1357 int ret = 0; 1358 1359 if (pi->caps_fps) { 1360 u16 tmp; 1361 1362 tmp = 45; 1363 pi->fps_high_t = cpu_to_be16(tmp); 1364 ret = kv_copy_bytes_to_smc(rdev, 1365 pi->dpm_table_start + 1366 offsetof(SMU7_Fusion_DpmTable, FpsHighT), 1367 (u8 *)&pi->fps_high_t, 1368 sizeof(u16), pi->sram_end); 1369 1370 tmp = 30; 1371 pi->fps_low_t = cpu_to_be16(tmp); 1372 1373 ret = kv_copy_bytes_to_smc(rdev, 1374 pi->dpm_table_start + 1375 offsetof(SMU7_Fusion_DpmTable, FpsLowT), 1376 (u8 *)&pi->fps_low_t, 1377 sizeof(u16), pi->sram_end); 1378 1379 } 1380 return ret; 1381 } 1382 1383 static void kv_init_powergate_state(struct radeon_device *rdev) 1384 { 1385 struct kv_power_info *pi = kv_get_pi(rdev); 1386 1387 pi->uvd_power_gated = false; 1388 pi->vce_power_gated = false; 1389 pi->samu_power_gated = false; 1390 pi->acp_power_gated = false; 1391 1392 } 1393 1394 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 1395 { 1396 return kv_notify_message_to_smu(rdev, enable ? 1397 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); 1398 } 1399 1400 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable) 1401 { 1402 return kv_notify_message_to_smu(rdev, enable ? 1403 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); 1404 } 1405 1406 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable) 1407 { 1408 return kv_notify_message_to_smu(rdev, enable ? 1409 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); 1410 } 1411 1412 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable) 1413 { 1414 return kv_notify_message_to_smu(rdev, enable ? 1415 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); 1416 } 1417 1418 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) 1419 { 1420 struct kv_power_info *pi = kv_get_pi(rdev); 1421 struct radeon_uvd_clock_voltage_dependency_table *table = 1422 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1423 int ret; 1424 u32 mask; 1425 1426 if (!gate) { 1427 if (table->count) 1428 pi->uvd_boot_level = table->count - 1; 1429 else 1430 pi->uvd_boot_level = 0; 1431 1432 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { 1433 mask = 1 << pi->uvd_boot_level; 1434 } else { 1435 mask = 0x1f; 1436 } 1437 1438 ret = kv_copy_bytes_to_smc(rdev, 1439 pi->dpm_table_start + 1440 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1441 (uint8_t *)&pi->uvd_boot_level, 1442 sizeof(u8), pi->sram_end); 1443 if (ret) 1444 return ret; 1445 1446 kv_send_msg_to_smc_with_parameter(rdev, 1447 PPSMC_MSG_UVDDPM_SetEnabledMask, 1448 mask); 1449 } 1450 1451 return kv_enable_uvd_dpm(rdev, !gate); 1452 } 1453 1454 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) 1455 { 1456 u8 i; 1457 struct radeon_vce_clock_voltage_dependency_table *table = 1458 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1459 1460 for (i = 0; i < table->count; i++) { 1461 if (table->entries[i].evclk >= evclk) 1462 break; 1463 } 1464 1465 return i; 1466 } 1467 1468 static int kv_update_vce_dpm(struct radeon_device *rdev, 1469 struct radeon_ps *radeon_new_state, 1470 struct radeon_ps *radeon_current_state) 1471 { 1472 struct kv_power_info *pi = kv_get_pi(rdev); 1473 struct radeon_vce_clock_voltage_dependency_table *table = 1474 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1475 int ret; 1476 1477 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { 1478 kv_dpm_powergate_vce(rdev, false); 1479 /* turn the clocks on when encoding */ 1480 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 1481 if (pi->caps_stable_p_state) 1482 pi->vce_boot_level = table->count - 1; 1483 else 1484 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); 1485 1486 ret = kv_copy_bytes_to_smc(rdev, 1487 pi->dpm_table_start + 1488 offsetof(SMU7_Fusion_DpmTable, VceBootLevel), 1489 (u8 *)&pi->vce_boot_level, 1490 sizeof(u8), 1491 pi->sram_end); 1492 if (ret) 1493 return ret; 1494 1495 if (pi->caps_stable_p_state) 1496 kv_send_msg_to_smc_with_parameter(rdev, 1497 PPSMC_MSG_VCEDPM_SetEnabledMask, 1498 (1 << pi->vce_boot_level)); 1499 1500 kv_enable_vce_dpm(rdev, true); 1501 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { 1502 kv_enable_vce_dpm(rdev, false); 1503 /* turn the clocks off when not encoding */ 1504 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 1505 kv_dpm_powergate_vce(rdev, true); 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) 1512 { 1513 struct kv_power_info *pi = kv_get_pi(rdev); 1514 struct radeon_clock_voltage_dependency_table *table = 1515 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1516 int ret; 1517 1518 if (!gate) { 1519 if (pi->caps_stable_p_state) 1520 pi->samu_boot_level = table->count - 1; 1521 else 1522 pi->samu_boot_level = 0; 1523 1524 ret = kv_copy_bytes_to_smc(rdev, 1525 pi->dpm_table_start + 1526 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), 1527 (u8 *)&pi->samu_boot_level, 1528 sizeof(u8), 1529 pi->sram_end); 1530 if (ret) 1531 return ret; 1532 1533 if (pi->caps_stable_p_state) 1534 kv_send_msg_to_smc_with_parameter(rdev, 1535 PPSMC_MSG_SAMUDPM_SetEnabledMask, 1536 (1 << pi->samu_boot_level)); 1537 } 1538 1539 return kv_enable_samu_dpm(rdev, !gate); 1540 } 1541 1542 static u8 kv_get_acp_boot_level(struct radeon_device *rdev) 1543 { 1544 u8 i; 1545 struct radeon_clock_voltage_dependency_table *table = 1546 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1547 1548 for (i = 0; i < table->count; i++) { 1549 if (table->entries[i].clk >= 0) /* XXX */ 1550 break; 1551 } 1552 1553 if (i >= table->count) 1554 i = table->count - 1; 1555 1556 return i; 1557 } 1558 1559 static void kv_update_acp_boot_level(struct radeon_device *rdev) 1560 { 1561 struct kv_power_info *pi = kv_get_pi(rdev); 1562 u8 acp_boot_level; 1563 1564 if (!pi->caps_stable_p_state) { 1565 acp_boot_level = kv_get_acp_boot_level(rdev); 1566 if (acp_boot_level != pi->acp_boot_level) { 1567 pi->acp_boot_level = acp_boot_level; 1568 kv_send_msg_to_smc_with_parameter(rdev, 1569 PPSMC_MSG_ACPDPM_SetEnabledMask, 1570 (1 << pi->acp_boot_level)); 1571 } 1572 } 1573 } 1574 1575 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate) 1576 { 1577 struct kv_power_info *pi = kv_get_pi(rdev); 1578 struct radeon_clock_voltage_dependency_table *table = 1579 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1580 int ret; 1581 1582 if (!gate) { 1583 if (pi->caps_stable_p_state) 1584 pi->acp_boot_level = table->count - 1; 1585 else 1586 pi->acp_boot_level = kv_get_acp_boot_level(rdev); 1587 1588 ret = kv_copy_bytes_to_smc(rdev, 1589 pi->dpm_table_start + 1590 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), 1591 (u8 *)&pi->acp_boot_level, 1592 sizeof(u8), 1593 pi->sram_end); 1594 if (ret) 1595 return ret; 1596 1597 if (pi->caps_stable_p_state) 1598 kv_send_msg_to_smc_with_parameter(rdev, 1599 PPSMC_MSG_ACPDPM_SetEnabledMask, 1600 (1 << pi->acp_boot_level)); 1601 } 1602 1603 return kv_enable_acp_dpm(rdev, !gate); 1604 } 1605 1606 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 1607 { 1608 struct kv_power_info *pi = kv_get_pi(rdev); 1609 1610 if (pi->uvd_power_gated == gate) 1611 return; 1612 1613 pi->uvd_power_gated = gate; 1614 1615 if (gate) { 1616 if (pi->caps_uvd_pg) { 1617 uvd_v1_0_stop(rdev); 1618 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false); 1619 } 1620 kv_update_uvd_dpm(rdev, gate); 1621 if (pi->caps_uvd_pg) 1622 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF); 1623 } else { 1624 if (pi->caps_uvd_pg) { 1625 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON); 1626 uvd_v4_2_resume(rdev); 1627 uvd_v1_0_start(rdev); 1628 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true); 1629 } 1630 kv_update_uvd_dpm(rdev, gate); 1631 } 1632 } 1633 1634 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate) 1635 { 1636 struct kv_power_info *pi = kv_get_pi(rdev); 1637 1638 if (pi->vce_power_gated == gate) 1639 return; 1640 1641 pi->vce_power_gated = gate; 1642 1643 if (gate) { 1644 if (pi->caps_vce_pg) { 1645 /* XXX do we need a vce_v1_0_stop() ? */ 1646 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF); 1647 } 1648 } else { 1649 if (pi->caps_vce_pg) { 1650 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON); 1651 vce_v2_0_resume(rdev); 1652 vce_v1_0_start(rdev); 1653 } 1654 } 1655 } 1656 1657 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate) 1658 { 1659 struct kv_power_info *pi = kv_get_pi(rdev); 1660 1661 if (pi->samu_power_gated == gate) 1662 return; 1663 1664 pi->samu_power_gated = gate; 1665 1666 if (gate) { 1667 kv_update_samu_dpm(rdev, true); 1668 if (pi->caps_samu_pg) 1669 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF); 1670 } else { 1671 if (pi->caps_samu_pg) 1672 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON); 1673 kv_update_samu_dpm(rdev, false); 1674 } 1675 } 1676 1677 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate) 1678 { 1679 struct kv_power_info *pi = kv_get_pi(rdev); 1680 1681 if (pi->acp_power_gated == gate) 1682 return; 1683 1684 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 1685 return; 1686 1687 pi->acp_power_gated = gate; 1688 1689 if (gate) { 1690 kv_update_acp_dpm(rdev, true); 1691 if (pi->caps_acp_pg) 1692 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF); 1693 } else { 1694 if (pi->caps_acp_pg) 1695 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON); 1696 kv_update_acp_dpm(rdev, false); 1697 } 1698 } 1699 1700 static void kv_set_valid_clock_range(struct radeon_device *rdev, 1701 struct radeon_ps *new_rps) 1702 { 1703 struct kv_ps *new_ps = kv_get_ps(new_rps); 1704 struct kv_power_info *pi = kv_get_pi(rdev); 1705 u32 i; 1706 struct radeon_clock_voltage_dependency_table *table = 1707 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1708 1709 if (table && table->count) { 1710 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1711 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || 1712 (i == (pi->graphics_dpm_level_count - 1))) { 1713 pi->lowest_valid = i; 1714 break; 1715 } 1716 } 1717 1718 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1719 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) 1720 break; 1721 } 1722 pi->highest_valid = i; 1723 1724 if (pi->lowest_valid > pi->highest_valid) { 1725 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > 1726 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) 1727 pi->highest_valid = pi->lowest_valid; 1728 else 1729 pi->lowest_valid = pi->highest_valid; 1730 } 1731 } else { 1732 struct sumo_sclk_voltage_mapping_table *table = 1733 &pi->sys_info.sclk_voltage_mapping_table; 1734 1735 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { 1736 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || 1737 i == (int)(pi->graphics_dpm_level_count - 1)) { 1738 pi->lowest_valid = i; 1739 break; 1740 } 1741 } 1742 1743 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1744 if (table->entries[i].sclk_frequency <= 1745 new_ps->levels[new_ps->num_levels - 1].sclk) 1746 break; 1747 } 1748 pi->highest_valid = i; 1749 1750 if (pi->lowest_valid > pi->highest_valid) { 1751 if ((new_ps->levels[0].sclk - 1752 table->entries[pi->highest_valid].sclk_frequency) > 1753 (table->entries[pi->lowest_valid].sclk_frequency - 1754 new_ps->levels[new_ps->num_levels -1].sclk)) 1755 pi->highest_valid = pi->lowest_valid; 1756 else 1757 pi->lowest_valid = pi->highest_valid; 1758 } 1759 } 1760 } 1761 1762 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev, 1763 struct radeon_ps *new_rps) 1764 { 1765 struct kv_ps *new_ps = kv_get_ps(new_rps); 1766 struct kv_power_info *pi = kv_get_pi(rdev); 1767 int ret = 0; 1768 u8 clk_bypass_cntl; 1769 1770 if (pi->caps_enable_dfs_bypass) { 1771 clk_bypass_cntl = new_ps->need_dfs_bypass ? 1772 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; 1773 ret = kv_copy_bytes_to_smc(rdev, 1774 (pi->dpm_table_start + 1775 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + 1776 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + 1777 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), 1778 &clk_bypass_cntl, 1779 sizeof(u8), pi->sram_end); 1780 } 1781 1782 return ret; 1783 } 1784 1785 static int kv_enable_nb_dpm(struct radeon_device *rdev, 1786 bool enable) 1787 { 1788 struct kv_power_info *pi = kv_get_pi(rdev); 1789 int ret = 0; 1790 1791 if (enable) { 1792 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { 1793 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable); 1794 if (ret == 0) 1795 pi->nb_dpm_enabled = true; 1796 } 1797 } else { 1798 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { 1799 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable); 1800 if (ret == 0) 1801 pi->nb_dpm_enabled = false; 1802 } 1803 } 1804 1805 return ret; 1806 } 1807 1808 int kv_dpm_force_performance_level(struct radeon_device *rdev, 1809 enum radeon_dpm_forced_level level) 1810 { 1811 int ret; 1812 1813 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1814 ret = kv_force_dpm_highest(rdev); 1815 if (ret) 1816 return ret; 1817 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1818 ret = kv_force_dpm_lowest(rdev); 1819 if (ret) 1820 return ret; 1821 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1822 ret = kv_unforce_levels(rdev); 1823 if (ret) 1824 return ret; 1825 } 1826 1827 rdev->pm.dpm.forced_level = level; 1828 1829 return 0; 1830 } 1831 1832 int kv_dpm_pre_set_power_state(struct radeon_device *rdev) 1833 { 1834 struct kv_power_info *pi = kv_get_pi(rdev); 1835 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 1836 struct radeon_ps *new_ps = &requested_ps; 1837 1838 kv_update_requested_ps(rdev, new_ps); 1839 1840 kv_apply_state_adjust_rules(rdev, 1841 &pi->requested_rps, 1842 &pi->current_rps); 1843 1844 return 0; 1845 } 1846 1847 int kv_dpm_set_power_state(struct radeon_device *rdev) 1848 { 1849 struct kv_power_info *pi = kv_get_pi(rdev); 1850 struct radeon_ps *new_ps = &pi->requested_rps; 1851 struct radeon_ps *old_ps = &pi->current_rps; 1852 int ret; 1853 1854 if (pi->bapm_enable) { 1855 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power); 1856 if (ret) { 1857 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1858 return ret; 1859 } 1860 } 1861 1862 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1863 if (pi->enable_dpm) { 1864 kv_set_valid_clock_range(rdev, new_ps); 1865 kv_update_dfs_bypass_settings(rdev, new_ps); 1866 ret = kv_calculate_ds_divider(rdev); 1867 if (ret) { 1868 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1869 return ret; 1870 } 1871 kv_calculate_nbps_level_settings(rdev); 1872 kv_calculate_dpm_settings(rdev); 1873 kv_force_lowest_valid(rdev); 1874 kv_enable_new_levels(rdev); 1875 kv_upload_dpm_settings(rdev); 1876 kv_program_nbps_index_settings(rdev, new_ps); 1877 kv_unforce_levels(rdev); 1878 kv_set_enabled_levels(rdev); 1879 kv_force_lowest_valid(rdev); 1880 kv_unforce_levels(rdev); 1881 1882 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1883 if (ret) { 1884 DRM_ERROR("kv_update_vce_dpm failed\n"); 1885 return ret; 1886 } 1887 kv_update_sclk_t(rdev); 1888 if (rdev->family == CHIP_MULLINS) 1889 kv_enable_nb_dpm(rdev, true); 1890 } 1891 } else { 1892 if (pi->enable_dpm) { 1893 kv_set_valid_clock_range(rdev, new_ps); 1894 kv_update_dfs_bypass_settings(rdev, new_ps); 1895 ret = kv_calculate_ds_divider(rdev); 1896 if (ret) { 1897 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1898 return ret; 1899 } 1900 kv_calculate_nbps_level_settings(rdev); 1901 kv_calculate_dpm_settings(rdev); 1902 kv_freeze_sclk_dpm(rdev, true); 1903 kv_upload_dpm_settings(rdev); 1904 kv_program_nbps_index_settings(rdev, new_ps); 1905 kv_freeze_sclk_dpm(rdev, false); 1906 kv_set_enabled_levels(rdev); 1907 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1908 if (ret) { 1909 DRM_ERROR("kv_update_vce_dpm failed\n"); 1910 return ret; 1911 } 1912 kv_update_acp_boot_level(rdev); 1913 kv_update_sclk_t(rdev); 1914 kv_enable_nb_dpm(rdev, true); 1915 } 1916 } 1917 1918 return 0; 1919 } 1920 1921 void kv_dpm_post_set_power_state(struct radeon_device *rdev) 1922 { 1923 struct kv_power_info *pi = kv_get_pi(rdev); 1924 struct radeon_ps *new_ps = &pi->requested_rps; 1925 1926 kv_update_current_ps(rdev, new_ps); 1927 } 1928 1929 void kv_dpm_setup_asic(struct radeon_device *rdev) 1930 { 1931 sumo_take_smu_control(rdev, true); 1932 kv_init_powergate_state(rdev); 1933 kv_init_sclk_t(rdev); 1934 } 1935 1936 #if 0 1937 void kv_dpm_reset_asic(struct radeon_device *rdev) 1938 { 1939 struct kv_power_info *pi = kv_get_pi(rdev); 1940 1941 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1942 kv_force_lowest_valid(rdev); 1943 kv_init_graphics_levels(rdev); 1944 kv_program_bootup_state(rdev); 1945 kv_upload_dpm_settings(rdev); 1946 kv_force_lowest_valid(rdev); 1947 kv_unforce_levels(rdev); 1948 } else { 1949 kv_init_graphics_levels(rdev); 1950 kv_program_bootup_state(rdev); 1951 kv_freeze_sclk_dpm(rdev, true); 1952 kv_upload_dpm_settings(rdev); 1953 kv_freeze_sclk_dpm(rdev, false); 1954 kv_set_enabled_level(rdev, pi->graphics_boot_level); 1955 } 1956 } 1957 #endif 1958 1959 //XXX use sumo_dpm_display_configuration_changed 1960 1961 static void kv_construct_max_power_limits_table(struct radeon_device *rdev, 1962 struct radeon_clock_and_voltage_limits *table) 1963 { 1964 struct kv_power_info *pi = kv_get_pi(rdev); 1965 1966 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { 1967 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; 1968 table->sclk = 1969 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; 1970 table->vddc = 1971 kv_convert_2bit_index_to_voltage(rdev, 1972 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); 1973 } 1974 1975 table->mclk = pi->sys_info.nbp_memory_clock[0]; 1976 } 1977 1978 static void kv_patch_voltage_values(struct radeon_device *rdev) 1979 { 1980 int i; 1981 struct radeon_uvd_clock_voltage_dependency_table *uvd_table = 1982 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1983 struct radeon_vce_clock_voltage_dependency_table *vce_table = 1984 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1985 struct radeon_clock_voltage_dependency_table *samu_table = 1986 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1987 struct radeon_clock_voltage_dependency_table *acp_table = 1988 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1989 1990 if (uvd_table->count) { 1991 for (i = 0; i < uvd_table->count; i++) 1992 uvd_table->entries[i].v = 1993 kv_convert_8bit_index_to_voltage(rdev, 1994 uvd_table->entries[i].v); 1995 } 1996 1997 if (vce_table->count) { 1998 for (i = 0; i < vce_table->count; i++) 1999 vce_table->entries[i].v = 2000 kv_convert_8bit_index_to_voltage(rdev, 2001 vce_table->entries[i].v); 2002 } 2003 2004 if (samu_table->count) { 2005 for (i = 0; i < samu_table->count; i++) 2006 samu_table->entries[i].v = 2007 kv_convert_8bit_index_to_voltage(rdev, 2008 samu_table->entries[i].v); 2009 } 2010 2011 if (acp_table->count) { 2012 for (i = 0; i < acp_table->count; i++) 2013 acp_table->entries[i].v = 2014 kv_convert_8bit_index_to_voltage(rdev, 2015 acp_table->entries[i].v); 2016 } 2017 2018 } 2019 2020 static void kv_construct_boot_state(struct radeon_device *rdev) 2021 { 2022 struct kv_power_info *pi = kv_get_pi(rdev); 2023 2024 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 2025 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 2026 pi->boot_pl.ds_divider_index = 0; 2027 pi->boot_pl.ss_divider_index = 0; 2028 pi->boot_pl.allow_gnb_slow = 1; 2029 pi->boot_pl.force_nbp_state = 0; 2030 pi->boot_pl.display_wm = 0; 2031 pi->boot_pl.vce_wm = 0; 2032 } 2033 2034 static int kv_force_dpm_highest(struct radeon_device *rdev) 2035 { 2036 int ret; 2037 u32 enable_mask, i; 2038 2039 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2040 if (ret) 2041 return ret; 2042 2043 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { 2044 if (enable_mask & (1 << i)) 2045 break; 2046 } 2047 2048 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2049 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2050 else 2051 return kv_set_enabled_level(rdev, i); 2052 } 2053 2054 static int kv_force_dpm_lowest(struct radeon_device *rdev) 2055 { 2056 int ret; 2057 u32 enable_mask, i; 2058 2059 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2060 if (ret) 2061 return ret; 2062 2063 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2064 if (enable_mask & (1 << i)) 2065 break; 2066 } 2067 2068 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2069 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2070 else 2071 return kv_set_enabled_level(rdev, i); 2072 } 2073 2074 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2075 u32 sclk, u32 min_sclk_in_sr) 2076 { 2077 struct kv_power_info *pi = kv_get_pi(rdev); 2078 u32 i; 2079 u32 temp; 2080 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? 2081 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; 2082 2083 if (sclk < min) 2084 return 0; 2085 2086 if (!pi->caps_sclk_ds) 2087 return 0; 2088 2089 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { 2090 temp = sclk / sumo_get_sleep_divider_from_id(i); 2091 if (temp >= min) 2092 break; 2093 } 2094 2095 return (u8)i; 2096 } 2097 2098 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit) 2099 { 2100 struct kv_power_info *pi = kv_get_pi(rdev); 2101 struct radeon_clock_voltage_dependency_table *table = 2102 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2103 int i; 2104 2105 if (table && table->count) { 2106 for (i = table->count - 1; i >= 0; i--) { 2107 if (pi->high_voltage_t && 2108 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <= 2109 pi->high_voltage_t)) { 2110 *limit = i; 2111 return 0; 2112 } 2113 } 2114 } else { 2115 struct sumo_sclk_voltage_mapping_table *table = 2116 &pi->sys_info.sclk_voltage_mapping_table; 2117 2118 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { 2119 if (pi->high_voltage_t && 2120 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <= 2121 pi->high_voltage_t)) { 2122 *limit = i; 2123 return 0; 2124 } 2125 } 2126 } 2127 2128 *limit = 0; 2129 return 0; 2130 } 2131 2132 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 2133 struct radeon_ps *new_rps, 2134 struct radeon_ps *old_rps) 2135 { 2136 struct kv_ps *ps = kv_get_ps(new_rps); 2137 struct kv_power_info *pi = kv_get_pi(rdev); 2138 u32 min_sclk = 10000; /* ??? */ 2139 u32 sclk, mclk = 0; 2140 int i, limit; 2141 bool force_high; 2142 struct radeon_clock_voltage_dependency_table *table = 2143 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2144 u32 stable_p_state_sclk = 0; 2145 struct radeon_clock_and_voltage_limits *max_limits = 2146 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2147 2148 if (new_rps->vce_active) { 2149 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2150 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2151 } else { 2152 new_rps->evclk = 0; 2153 new_rps->ecclk = 0; 2154 } 2155 2156 mclk = max_limits->mclk; 2157 sclk = min_sclk; 2158 2159 if (pi->caps_stable_p_state) { 2160 stable_p_state_sclk = (max_limits->sclk * 75) / 100; 2161 2162 for (i = table->count - 1; i >= 0; i--) { 2163 if (stable_p_state_sclk >= table->entries[i].clk) { 2164 stable_p_state_sclk = table->entries[i].clk; 2165 break; 2166 } 2167 } 2168 2169 if (i > 0) 2170 stable_p_state_sclk = table->entries[0].clk; 2171 2172 sclk = stable_p_state_sclk; 2173 } 2174 2175 if (new_rps->vce_active) { 2176 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 2177 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 2178 } 2179 2180 ps->need_dfs_bypass = true; 2181 2182 for (i = 0; i < ps->num_levels; i++) { 2183 if (ps->levels[i].sclk < sclk) 2184 ps->levels[i].sclk = sclk; 2185 } 2186 2187 if (table && table->count) { 2188 for (i = 0; i < ps->num_levels; i++) { 2189 if (pi->high_voltage_t && 2190 (pi->high_voltage_t < 2191 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2192 kv_get_high_voltage_limit(rdev, &limit); 2193 ps->levels[i].sclk = table->entries[limit].clk; 2194 } 2195 } 2196 } else { 2197 struct sumo_sclk_voltage_mapping_table *table = 2198 &pi->sys_info.sclk_voltage_mapping_table; 2199 2200 for (i = 0; i < ps->num_levels; i++) { 2201 if (pi->high_voltage_t && 2202 (pi->high_voltage_t < 2203 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2204 kv_get_high_voltage_limit(rdev, &limit); 2205 ps->levels[i].sclk = table->entries[limit].sclk_frequency; 2206 } 2207 } 2208 } 2209 2210 if (pi->caps_stable_p_state) { 2211 for (i = 0; i < ps->num_levels; i++) { 2212 ps->levels[i].sclk = stable_p_state_sclk; 2213 } 2214 } 2215 2216 pi->video_start = new_rps->dclk || new_rps->vclk || 2217 new_rps->evclk || new_rps->ecclk; 2218 2219 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2220 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 2221 pi->battery_state = true; 2222 else 2223 pi->battery_state = false; 2224 2225 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2226 ps->dpm0_pg_nb_ps_lo = 0x1; 2227 ps->dpm0_pg_nb_ps_hi = 0x0; 2228 ps->dpmx_nb_ps_lo = 0x1; 2229 ps->dpmx_nb_ps_hi = 0x0; 2230 } else { 2231 ps->dpm0_pg_nb_ps_lo = 0x3; 2232 ps->dpm0_pg_nb_ps_hi = 0x0; 2233 ps->dpmx_nb_ps_lo = 0x3; 2234 ps->dpmx_nb_ps_hi = 0x0; 2235 2236 if (pi->sys_info.nb_dpm_enable) { 2237 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || 2238 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || 2239 pi->disable_nb_ps3_in_battery; 2240 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; 2241 ps->dpm0_pg_nb_ps_hi = 0x2; 2242 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; 2243 ps->dpmx_nb_ps_hi = 0x2; 2244 } 2245 } 2246 } 2247 2248 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev, 2249 u32 index, bool enable) 2250 { 2251 struct kv_power_info *pi = kv_get_pi(rdev); 2252 2253 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; 2254 } 2255 2256 static int kv_calculate_ds_divider(struct radeon_device *rdev) 2257 { 2258 struct kv_power_info *pi = kv_get_pi(rdev); 2259 u32 sclk_in_sr = 10000; /* ??? */ 2260 u32 i; 2261 2262 if (pi->lowest_valid > pi->highest_valid) 2263 return -EINVAL; 2264 2265 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2266 pi->graphics_level[i].DeepSleepDivId = 2267 kv_get_sleep_divider_id_from_clock(rdev, 2268 be32_to_cpu(pi->graphics_level[i].SclkFrequency), 2269 sclk_in_sr); 2270 } 2271 return 0; 2272 } 2273 2274 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev) 2275 { 2276 struct kv_power_info *pi = kv_get_pi(rdev); 2277 u32 i; 2278 bool force_high; 2279 struct radeon_clock_and_voltage_limits *max_limits = 2280 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2281 u32 mclk = max_limits->mclk; 2282 2283 if (pi->lowest_valid > pi->highest_valid) 2284 return -EINVAL; 2285 2286 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2287 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2288 pi->graphics_level[i].GnbSlow = 1; 2289 pi->graphics_level[i].ForceNbPs1 = 0; 2290 pi->graphics_level[i].UpH = 0; 2291 } 2292 2293 if (!pi->sys_info.nb_dpm_enable) 2294 return 0; 2295 2296 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || 2297 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); 2298 2299 if (force_high) { 2300 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2301 pi->graphics_level[i].GnbSlow = 0; 2302 } else { 2303 if (pi->battery_state) 2304 pi->graphics_level[0].ForceNbPs1 = 1; 2305 2306 pi->graphics_level[1].GnbSlow = 0; 2307 pi->graphics_level[2].GnbSlow = 0; 2308 pi->graphics_level[3].GnbSlow = 0; 2309 pi->graphics_level[4].GnbSlow = 0; 2310 } 2311 } else { 2312 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2313 pi->graphics_level[i].GnbSlow = 1; 2314 pi->graphics_level[i].ForceNbPs1 = 0; 2315 pi->graphics_level[i].UpH = 0; 2316 } 2317 2318 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { 2319 pi->graphics_level[pi->lowest_valid].UpH = 0x28; 2320 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; 2321 if (pi->lowest_valid != pi->highest_valid) 2322 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; 2323 } 2324 } 2325 return 0; 2326 } 2327 2328 static int kv_calculate_dpm_settings(struct radeon_device *rdev) 2329 { 2330 struct kv_power_info *pi = kv_get_pi(rdev); 2331 u32 i; 2332 2333 if (pi->lowest_valid > pi->highest_valid) 2334 return -EINVAL; 2335 2336 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2337 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; 2338 2339 return 0; 2340 } 2341 2342 static void kv_init_graphics_levels(struct radeon_device *rdev) 2343 { 2344 struct kv_power_info *pi = kv_get_pi(rdev); 2345 u32 i; 2346 struct radeon_clock_voltage_dependency_table *table = 2347 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2348 2349 if (table && table->count) { 2350 u32 vid_2bit; 2351 2352 pi->graphics_dpm_level_count = 0; 2353 for (i = 0; i < table->count; i++) { 2354 if (pi->high_voltage_t && 2355 (pi->high_voltage_t < 2356 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v))) 2357 break; 2358 2359 kv_set_divider_value(rdev, i, table->entries[i].clk); 2360 vid_2bit = kv_convert_vid7_to_vid2(rdev, 2361 &pi->sys_info.vid_mapping_table, 2362 table->entries[i].v); 2363 kv_set_vid(rdev, i, vid_2bit); 2364 kv_set_at(rdev, i, pi->at[i]); 2365 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2366 pi->graphics_dpm_level_count++; 2367 } 2368 } else { 2369 struct sumo_sclk_voltage_mapping_table *table = 2370 &pi->sys_info.sclk_voltage_mapping_table; 2371 2372 pi->graphics_dpm_level_count = 0; 2373 for (i = 0; i < table->num_max_dpm_entries; i++) { 2374 if (pi->high_voltage_t && 2375 pi->high_voltage_t < 2376 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit)) 2377 break; 2378 2379 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency); 2380 kv_set_vid(rdev, i, table->entries[i].vid_2bit); 2381 kv_set_at(rdev, i, pi->at[i]); 2382 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2383 pi->graphics_dpm_level_count++; 2384 } 2385 } 2386 2387 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 2388 kv_dpm_power_level_enable(rdev, i, false); 2389 } 2390 2391 static void kv_enable_new_levels(struct radeon_device *rdev) 2392 { 2393 struct kv_power_info *pi = kv_get_pi(rdev); 2394 u32 i; 2395 2396 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2397 if (i >= pi->lowest_valid && i <= pi->highest_valid) 2398 kv_dpm_power_level_enable(rdev, i, true); 2399 } 2400 } 2401 2402 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level) 2403 { 2404 u32 new_mask = (1 << level); 2405 2406 return kv_send_msg_to_smc_with_parameter(rdev, 2407 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2408 new_mask); 2409 } 2410 2411 static int kv_set_enabled_levels(struct radeon_device *rdev) 2412 { 2413 struct kv_power_info *pi = kv_get_pi(rdev); 2414 u32 i, new_mask = 0; 2415 2416 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2417 new_mask |= (1 << i); 2418 2419 return kv_send_msg_to_smc_with_parameter(rdev, 2420 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2421 new_mask); 2422 } 2423 2424 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 2425 struct radeon_ps *new_rps) 2426 { 2427 struct kv_ps *new_ps = kv_get_ps(new_rps); 2428 struct kv_power_info *pi = kv_get_pi(rdev); 2429 u32 nbdpmconfig1; 2430 2431 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2432 return; 2433 2434 if (pi->sys_info.nb_dpm_enable) { 2435 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); 2436 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | 2437 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK); 2438 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) | 2439 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) | 2440 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) | 2441 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi)); 2442 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); 2443 } 2444 } 2445 2446 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 2447 int min_temp, int max_temp) 2448 { 2449 int low_temp = 0 * 1000; 2450 int high_temp = 255 * 1000; 2451 u32 tmp; 2452 2453 if (low_temp < min_temp) 2454 low_temp = min_temp; 2455 if (high_temp > max_temp) 2456 high_temp = max_temp; 2457 if (high_temp < low_temp) { 2458 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 2459 return -EINVAL; 2460 } 2461 2462 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); 2463 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK); 2464 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) | 2465 DIG_THERM_INTL(49 + (low_temp / 1000))); 2466 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); 2467 2468 rdev->pm.dpm.thermal.min_temp = low_temp; 2469 rdev->pm.dpm.thermal.max_temp = high_temp; 2470 2471 return 0; 2472 } 2473 2474 union igp_info { 2475 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 2476 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 2477 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 2478 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 2479 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 2480 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 2481 }; 2482 2483 static int kv_parse_sys_info_table(struct radeon_device *rdev) 2484 { 2485 struct kv_power_info *pi = kv_get_pi(rdev); 2486 struct radeon_mode_info *mode_info = &rdev->mode_info; 2487 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 2488 union igp_info *igp_info; 2489 u8 frev, crev; 2490 u16 data_offset; 2491 int i; 2492 2493 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2494 &frev, &crev, &data_offset)) { 2495 igp_info = (union igp_info *)(mode_info->atom_context->bios + 2496 data_offset); 2497 2498 if (crev != 8) { 2499 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 2500 return -EINVAL; 2501 } 2502 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); 2503 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); 2504 pi->sys_info.bootup_nb_voltage_index = 2505 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); 2506 if (igp_info->info_8.ucHtcTmpLmt == 0) 2507 pi->sys_info.htc_tmp_lmt = 203; 2508 else 2509 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; 2510 if (igp_info->info_8.ucHtcHystLmt == 0) 2511 pi->sys_info.htc_hyst_lmt = 5; 2512 else 2513 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; 2514 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 2515 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 2516 } 2517 2518 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) 2519 pi->sys_info.nb_dpm_enable = true; 2520 else 2521 pi->sys_info.nb_dpm_enable = false; 2522 2523 for (i = 0; i < KV_NUM_NBPSTATES; i++) { 2524 pi->sys_info.nbp_memory_clock[i] = 2525 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); 2526 pi->sys_info.nbp_n_clock[i] = 2527 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); 2528 } 2529 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & 2530 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) 2531 pi->caps_enable_dfs_bypass = true; 2532 2533 sumo_construct_sclk_voltage_mapping_table(rdev, 2534 &pi->sys_info.sclk_voltage_mapping_table, 2535 igp_info->info_8.sAvail_SCLK); 2536 2537 sumo_construct_vid_mapping_table(rdev, 2538 &pi->sys_info.vid_mapping_table, 2539 igp_info->info_8.sAvail_SCLK); 2540 2541 kv_construct_max_power_limits_table(rdev, 2542 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 2543 } 2544 return 0; 2545 } 2546 2547 union power_info { 2548 struct _ATOM_POWERPLAY_INFO info; 2549 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2550 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2551 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2552 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2553 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2554 }; 2555 2556 union pplib_clock_info { 2557 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2558 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2559 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2560 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2561 }; 2562 2563 union pplib_power_state { 2564 struct _ATOM_PPLIB_STATE v1; 2565 struct _ATOM_PPLIB_STATE_V2 v2; 2566 }; 2567 2568 static void kv_patch_boot_state(struct radeon_device *rdev, 2569 struct kv_ps *ps) 2570 { 2571 struct kv_power_info *pi = kv_get_pi(rdev); 2572 2573 ps->num_levels = 1; 2574 ps->levels[0] = pi->boot_pl; 2575 } 2576 2577 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev, 2578 struct radeon_ps *rps, 2579 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 2580 u8 table_rev) 2581 { 2582 struct kv_ps *ps = kv_get_ps(rps); 2583 2584 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2585 rps->class = le16_to_cpu(non_clock_info->usClassification); 2586 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 2587 2588 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 2589 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 2590 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 2591 } else { 2592 rps->vclk = 0; 2593 rps->dclk = 0; 2594 } 2595 2596 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2597 rdev->pm.dpm.boot_ps = rps; 2598 kv_patch_boot_state(rdev, ps); 2599 } 2600 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 2601 rdev->pm.dpm.uvd_ps = rps; 2602 } 2603 2604 static void kv_parse_pplib_clock_info(struct radeon_device *rdev, 2605 struct radeon_ps *rps, int index, 2606 union pplib_clock_info *clock_info) 2607 { 2608 struct kv_power_info *pi = kv_get_pi(rdev); 2609 struct kv_ps *ps = kv_get_ps(rps); 2610 struct kv_pl *pl = &ps->levels[index]; 2611 u32 sclk; 2612 2613 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2614 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2615 pl->sclk = sclk; 2616 pl->vddc_index = clock_info->sumo.vddcIndex; 2617 2618 ps->num_levels = index + 1; 2619 2620 if (pi->caps_sclk_ds) { 2621 pl->ds_divider_index = 5; 2622 pl->ss_divider_index = 5; 2623 } 2624 } 2625 2626 static int kv_parse_power_table(struct radeon_device *rdev) 2627 { 2628 struct radeon_mode_info *mode_info = &rdev->mode_info; 2629 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2630 union pplib_power_state *power_state; 2631 int i, j, k, non_clock_array_index, clock_array_index; 2632 union pplib_clock_info *clock_info; 2633 struct _StateArray *state_array; 2634 struct _ClockInfoArray *clock_info_array; 2635 struct _NonClockInfoArray *non_clock_info_array; 2636 union power_info *power_info; 2637 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2638 u16 data_offset; 2639 u8 frev, crev; 2640 u8 *power_state_offset; 2641 struct kv_ps *ps; 2642 2643 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2644 &frev, &crev, &data_offset)) 2645 return -EINVAL; 2646 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2647 2648 state_array = (struct _StateArray *) 2649 (mode_info->atom_context->bios + data_offset + 2650 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2651 clock_info_array = (struct _ClockInfoArray *) 2652 (mode_info->atom_context->bios + data_offset + 2653 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2654 non_clock_info_array = (struct _NonClockInfoArray *) 2655 (mode_info->atom_context->bios + data_offset + 2656 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2657 2658 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 2659 state_array->ucNumEntries, GFP_KERNEL); 2660 if (!rdev->pm.dpm.ps) 2661 return -ENOMEM; 2662 power_state_offset = (u8 *)state_array->states; 2663 for (i = 0; i < state_array->ucNumEntries; i++) { 2664 u8 *idx; 2665 power_state = (union pplib_power_state *)power_state_offset; 2666 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2667 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2668 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2669 if (!rdev->pm.power_state[i].clock_info) 2670 return -EINVAL; 2671 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); 2672 if (ps == NULL) { 2673 kfree(rdev->pm.dpm.ps); 2674 return -ENOMEM; 2675 } 2676 rdev->pm.dpm.ps[i].ps_priv = ps; 2677 k = 0; 2678 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2679 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2680 clock_array_index = idx[j]; 2681 if (clock_array_index >= clock_info_array->ucNumEntries) 2682 continue; 2683 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 2684 break; 2685 clock_info = (union pplib_clock_info *) 2686 ((u8 *)&clock_info_array->clockInfo[0] + 2687 (clock_array_index * clock_info_array->ucEntrySize)); 2688 kv_parse_pplib_clock_info(rdev, 2689 &rdev->pm.dpm.ps[i], k, 2690 clock_info); 2691 k++; 2692 } 2693 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 2694 non_clock_info, 2695 non_clock_info_array->ucEntrySize); 2696 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2697 } 2698 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 2699 2700 /* fill in the vce power states */ 2701 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 2702 u32 sclk; 2703 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 2704 clock_info = (union pplib_clock_info *) 2705 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2706 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2707 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2708 rdev->pm.dpm.vce_states[i].sclk = sclk; 2709 rdev->pm.dpm.vce_states[i].mclk = 0; 2710 } 2711 2712 return 0; 2713 } 2714 2715 int kv_dpm_init(struct radeon_device *rdev) 2716 { 2717 struct kv_power_info *pi; 2718 int ret, i; 2719 2720 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); 2721 if (pi == NULL) 2722 return -ENOMEM; 2723 rdev->pm.dpm.priv = pi; 2724 2725 ret = r600_get_platform_caps(rdev); 2726 if (ret) 2727 return ret; 2728 2729 ret = r600_parse_extended_power_table(rdev); 2730 if (ret) 2731 return ret; 2732 2733 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 2734 pi->at[i] = TRINITY_AT_DFLT; 2735 2736 pi->sram_end = SMC_RAM_END; 2737 2738 /* Enabling nb dpm on an asrock system prevents dpm from working */ 2739 if (rdev->pdev->subsystem_vendor == 0x1849) 2740 pi->enable_nb_dpm = false; 2741 else 2742 pi->enable_nb_dpm = true; 2743 2744 pi->caps_power_containment = true; 2745 pi->caps_cac = true; 2746 pi->enable_didt = false; 2747 if (pi->enable_didt) { 2748 pi->caps_sq_ramping = true; 2749 pi->caps_db_ramping = true; 2750 pi->caps_td_ramping = true; 2751 pi->caps_tcp_ramping = true; 2752 } 2753 2754 pi->caps_sclk_ds = true; 2755 pi->enable_auto_thermal_throttling = true; 2756 pi->disable_nb_ps3_in_battery = false; 2757 if (radeon_bapm == -1) { 2758 /* only enable bapm on KB, ML by default */ 2759 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2760 pi->bapm_enable = true; 2761 else 2762 pi->bapm_enable = false; 2763 } else if (radeon_bapm == 0) { 2764 pi->bapm_enable = false; 2765 } else { 2766 pi->bapm_enable = true; 2767 } 2768 pi->voltage_drop_t = 0; 2769 pi->caps_sclk_throttle_low_notification = false; 2770 pi->caps_fps = false; /* true? */ 2771 pi->caps_uvd_pg = true; 2772 pi->caps_uvd_dpm = true; 2773 pi->caps_vce_pg = false; /* XXX true */ 2774 pi->caps_samu_pg = false; 2775 pi->caps_acp_pg = false; 2776 pi->caps_stable_p_state = false; 2777 2778 ret = kv_parse_sys_info_table(rdev); 2779 if (ret) 2780 return ret; 2781 2782 kv_patch_voltage_values(rdev); 2783 kv_construct_boot_state(rdev); 2784 2785 ret = kv_parse_power_table(rdev); 2786 if (ret) 2787 return ret; 2788 2789 pi->enable_dpm = true; 2790 2791 return 0; 2792 } 2793 2794 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 2795 struct seq_file *m) 2796 { 2797 struct kv_power_info *pi = kv_get_pi(rdev); 2798 u32 current_index = 2799 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> 2800 CURR_SCLK_INDEX_SHIFT; 2801 u32 sclk, tmp; 2802 u16 vddc; 2803 2804 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2805 seq_printf(m, "invalid dpm profile %d\n", current_index); 2806 } else { 2807 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2808 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2809 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT; 2810 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp); 2811 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); 2812 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); 2813 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2814 current_index, sclk, vddc); 2815 } 2816 } 2817 2818 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev) 2819 { 2820 struct kv_power_info *pi = kv_get_pi(rdev); 2821 u32 current_index = 2822 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> 2823 CURR_SCLK_INDEX_SHIFT; 2824 u32 sclk; 2825 2826 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2827 return 0; 2828 } else { 2829 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2830 return sclk; 2831 } 2832 } 2833 2834 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev) 2835 { 2836 struct kv_power_info *pi = kv_get_pi(rdev); 2837 2838 return pi->sys_info.bootup_uma_clk; 2839 } 2840 2841 void kv_dpm_print_power_state(struct radeon_device *rdev, 2842 struct radeon_ps *rps) 2843 { 2844 int i; 2845 struct kv_ps *ps = kv_get_ps(rps); 2846 2847 r600_dpm_print_class_info(rps->class, rps->class2); 2848 r600_dpm_print_cap_info(rps->caps); 2849 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2850 for (i = 0; i < ps->num_levels; i++) { 2851 struct kv_pl *pl = &ps->levels[i]; 2852 printk("\t\tpower level %d sclk: %u vddc: %u\n", 2853 i, pl->sclk, 2854 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index)); 2855 } 2856 r600_dpm_print_ps_status(rdev, rps); 2857 } 2858 2859 void kv_dpm_fini(struct radeon_device *rdev) 2860 { 2861 int i; 2862 2863 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 2864 kfree(rdev->pm.dpm.ps[i].ps_priv); 2865 } 2866 kfree(rdev->pm.dpm.ps); 2867 kfree(rdev->pm.dpm.priv); 2868 r600_free_extended_power_table(rdev); 2869 } 2870 2871 void kv_dpm_display_configuration_changed(struct radeon_device *rdev) 2872 { 2873 2874 } 2875 2876 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low) 2877 { 2878 struct kv_power_info *pi = kv_get_pi(rdev); 2879 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2880 2881 if (low) 2882 return requested_state->levels[0].sclk; 2883 else 2884 return requested_state->levels[requested_state->num_levels - 1].sclk; 2885 } 2886 2887 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low) 2888 { 2889 struct kv_power_info *pi = kv_get_pi(rdev); 2890 2891 return pi->sys_info.bootup_uma_clk; 2892 } 2893 2894