1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "cikd.h" 28 #include "r600_dpm.h" 29 #include "kv_dpm.h" 30 #include "radeon_asic.h" 31 #include <linux/seq_file.h> 32 33 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 34 #define KV_MINIMUM_ENGINE_CLOCK 800 35 #define SMC_RAM_END 0x40000 36 37 static int kv_enable_nb_dpm(struct radeon_device *rdev, 38 bool enable); 39 static void kv_init_graphics_levels(struct radeon_device *rdev); 40 static int kv_calculate_ds_divider(struct radeon_device *rdev); 41 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev); 42 static int kv_calculate_dpm_settings(struct radeon_device *rdev); 43 static void kv_enable_new_levels(struct radeon_device *rdev); 44 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 45 struct radeon_ps *new_rps); 46 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level); 47 static int kv_set_enabled_levels(struct radeon_device *rdev); 48 static int kv_force_dpm_highest(struct radeon_device *rdev); 49 static int kv_force_dpm_lowest(struct radeon_device *rdev); 50 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 51 struct radeon_ps *new_rps, 52 struct radeon_ps *old_rps); 53 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 54 int min_temp, int max_temp); 55 static int kv_init_fps_limits(struct radeon_device *rdev); 56 57 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate); 58 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate); 59 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate); 60 61 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 62 { 63 { 0, 4, 1 }, 64 { 1, 4, 1 }, 65 { 2, 5, 1 }, 66 { 3, 4, 2 }, 67 { 4, 1, 1 }, 68 { 5, 5, 2 }, 69 { 6, 6, 1 }, 70 { 7, 9, 2 }, 71 { 0xffffffff } 72 }; 73 74 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = 75 { 76 { 0, 4, 1 }, 77 { 0xffffffff } 78 }; 79 80 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = 81 { 82 { 0, 4, 1 }, 83 { 0xffffffff } 84 }; 85 86 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = 87 { 88 { 0, 4, 1 }, 89 { 0xffffffff } 90 }; 91 92 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = 93 { 94 { 0, 4, 1 }, 95 { 0xffffffff } 96 }; 97 98 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = 99 { 100 { 0, 4, 1 }, 101 { 1, 4, 1 }, 102 { 2, 5, 1 }, 103 { 3, 4, 1 }, 104 { 4, 1, 1 }, 105 { 5, 5, 1 }, 106 { 6, 6, 1 }, 107 { 7, 9, 1 }, 108 { 8, 4, 1 }, 109 { 9, 2, 1 }, 110 { 10, 3, 1 }, 111 { 11, 6, 1 }, 112 { 12, 8, 2 }, 113 { 13, 1, 1 }, 114 { 14, 2, 1 }, 115 { 15, 3, 1 }, 116 { 16, 1, 1 }, 117 { 17, 4, 1 }, 118 { 18, 3, 1 }, 119 { 19, 1, 1 }, 120 { 20, 8, 1 }, 121 { 21, 5, 1 }, 122 { 22, 1, 1 }, 123 { 23, 1, 1 }, 124 { 24, 4, 1 }, 125 { 27, 6, 1 }, 126 { 28, 1, 1 }, 127 { 0xffffffff } 128 }; 129 130 static const struct kv_lcac_config_reg sx0_cac_config_reg[] = 131 { 132 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 133 }; 134 135 static const struct kv_lcac_config_reg mc0_cac_config_reg[] = 136 { 137 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 138 }; 139 140 static const struct kv_lcac_config_reg mc1_cac_config_reg[] = 141 { 142 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 143 }; 144 145 static const struct kv_lcac_config_reg mc2_cac_config_reg[] = 146 { 147 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 148 }; 149 150 static const struct kv_lcac_config_reg mc3_cac_config_reg[] = 151 { 152 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 153 }; 154 155 static const struct kv_lcac_config_reg cpl_cac_config_reg[] = 156 { 157 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 158 }; 159 160 static const struct kv_pt_config_reg didt_config_kv[] = 161 { 162 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 163 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 164 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 165 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 166 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 167 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 168 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 169 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 170 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 171 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 172 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 173 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 174 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 175 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 176 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 177 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 178 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 179 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 180 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 181 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 182 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 183 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 184 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 185 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 186 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 187 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 188 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 189 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 190 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 191 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 192 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 193 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 194 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 195 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 196 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 197 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 198 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 199 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 200 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 201 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 202 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 203 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 204 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 205 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 206 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 207 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 208 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 209 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 210 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 211 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 212 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 213 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 214 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 215 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 216 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 217 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 218 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 219 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 220 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 221 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 222 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 223 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 224 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 225 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 226 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 227 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 228 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 229 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 230 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 231 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 232 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 233 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 234 { 0xFFFFFFFF } 235 }; 236 237 static struct kv_ps *kv_get_ps(struct radeon_ps *rps) 238 { 239 struct kv_ps *ps = rps->ps_priv; 240 241 return ps; 242 } 243 244 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev) 245 { 246 struct kv_power_info *pi = rdev->pm.dpm.priv; 247 248 return pi; 249 } 250 251 #if 0 252 static void kv_program_local_cac_table(struct radeon_device *rdev, 253 const struct kv_lcac_config_values *local_cac_table, 254 const struct kv_lcac_config_reg *local_cac_reg) 255 { 256 u32 i, count, data; 257 const struct kv_lcac_config_values *values = local_cac_table; 258 259 while (values->block_id != 0xffffffff) { 260 count = values->signal_id; 261 for (i = 0; i < count; i++) { 262 data = ((values->block_id << local_cac_reg->block_shift) & 263 local_cac_reg->block_mask); 264 data |= ((i << local_cac_reg->signal_shift) & 265 local_cac_reg->signal_mask); 266 data |= ((values->t << local_cac_reg->t_shift) & 267 local_cac_reg->t_mask); 268 data |= ((1 << local_cac_reg->enable_shift) & 269 local_cac_reg->enable_mask); 270 WREG32_SMC(local_cac_reg->cntl, data); 271 } 272 values++; 273 } 274 } 275 #endif 276 277 static int kv_program_pt_config_registers(struct radeon_device *rdev, 278 const struct kv_pt_config_reg *cac_config_regs) 279 { 280 const struct kv_pt_config_reg *config_regs = cac_config_regs; 281 u32 data; 282 u32 cache = 0; 283 284 if (config_regs == NULL) 285 return -EINVAL; 286 287 while (config_regs->offset != 0xFFFFFFFF) { 288 if (config_regs->type == KV_CONFIGREG_CACHE) { 289 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 290 } else { 291 switch (config_regs->type) { 292 case KV_CONFIGREG_SMC_IND: 293 data = RREG32_SMC(config_regs->offset); 294 break; 295 case KV_CONFIGREG_DIDT_IND: 296 data = RREG32_DIDT(config_regs->offset); 297 break; 298 default: 299 data = RREG32(config_regs->offset << 2); 300 break; 301 } 302 303 data &= ~config_regs->mask; 304 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 305 data |= cache; 306 cache = 0; 307 308 switch (config_regs->type) { 309 case KV_CONFIGREG_SMC_IND: 310 WREG32_SMC(config_regs->offset, data); 311 break; 312 case KV_CONFIGREG_DIDT_IND: 313 WREG32_DIDT(config_regs->offset, data); 314 break; 315 default: 316 WREG32(config_regs->offset << 2, data); 317 break; 318 } 319 } 320 config_regs++; 321 } 322 323 return 0; 324 } 325 326 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable) 327 { 328 struct kv_power_info *pi = kv_get_pi(rdev); 329 u32 data; 330 331 if (pi->caps_sq_ramping) { 332 data = RREG32_DIDT(DIDT_SQ_CTRL0); 333 if (enable) 334 data |= DIDT_CTRL_EN; 335 else 336 data &= ~DIDT_CTRL_EN; 337 WREG32_DIDT(DIDT_SQ_CTRL0, data); 338 } 339 340 if (pi->caps_db_ramping) { 341 data = RREG32_DIDT(DIDT_DB_CTRL0); 342 if (enable) 343 data |= DIDT_CTRL_EN; 344 else 345 data &= ~DIDT_CTRL_EN; 346 WREG32_DIDT(DIDT_DB_CTRL0, data); 347 } 348 349 if (pi->caps_td_ramping) { 350 data = RREG32_DIDT(DIDT_TD_CTRL0); 351 if (enable) 352 data |= DIDT_CTRL_EN; 353 else 354 data &= ~DIDT_CTRL_EN; 355 WREG32_DIDT(DIDT_TD_CTRL0, data); 356 } 357 358 if (pi->caps_tcp_ramping) { 359 data = RREG32_DIDT(DIDT_TCP_CTRL0); 360 if (enable) 361 data |= DIDT_CTRL_EN; 362 else 363 data &= ~DIDT_CTRL_EN; 364 WREG32_DIDT(DIDT_TCP_CTRL0, data); 365 } 366 } 367 368 static int kv_enable_didt(struct radeon_device *rdev, bool enable) 369 { 370 struct kv_power_info *pi = kv_get_pi(rdev); 371 int ret; 372 373 if (pi->caps_sq_ramping || 374 pi->caps_db_ramping || 375 pi->caps_td_ramping || 376 pi->caps_tcp_ramping) { 377 cik_enter_rlc_safe_mode(rdev); 378 379 if (enable) { 380 ret = kv_program_pt_config_registers(rdev, didt_config_kv); 381 if (ret) { 382 cik_exit_rlc_safe_mode(rdev); 383 return ret; 384 } 385 } 386 387 kv_do_enable_didt(rdev, enable); 388 389 cik_exit_rlc_safe_mode(rdev); 390 } 391 392 return 0; 393 } 394 395 #if 0 396 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev) 397 { 398 struct kv_power_info *pi = kv_get_pi(rdev); 399 400 if (pi->caps_cac) { 401 WREG32_SMC(LCAC_SX0_OVR_SEL, 0); 402 WREG32_SMC(LCAC_SX0_OVR_VAL, 0); 403 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg); 404 405 WREG32_SMC(LCAC_MC0_OVR_SEL, 0); 406 WREG32_SMC(LCAC_MC0_OVR_VAL, 0); 407 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); 408 409 WREG32_SMC(LCAC_MC1_OVR_SEL, 0); 410 WREG32_SMC(LCAC_MC1_OVR_VAL, 0); 411 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); 412 413 WREG32_SMC(LCAC_MC2_OVR_SEL, 0); 414 WREG32_SMC(LCAC_MC2_OVR_VAL, 0); 415 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); 416 417 WREG32_SMC(LCAC_MC3_OVR_SEL, 0); 418 WREG32_SMC(LCAC_MC3_OVR_VAL, 0); 419 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); 420 421 WREG32_SMC(LCAC_CPL_OVR_SEL, 0); 422 WREG32_SMC(LCAC_CPL_OVR_VAL, 0); 423 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); 424 } 425 } 426 #endif 427 428 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable) 429 { 430 struct kv_power_info *pi = kv_get_pi(rdev); 431 int ret = 0; 432 433 if (pi->caps_cac) { 434 if (enable) { 435 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac); 436 if (ret) 437 pi->cac_enabled = false; 438 else 439 pi->cac_enabled = true; 440 } else if (pi->cac_enabled) { 441 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac); 442 pi->cac_enabled = false; 443 } 444 } 445 446 return ret; 447 } 448 449 static int kv_process_firmware_header(struct radeon_device *rdev) 450 { 451 struct kv_power_info *pi = kv_get_pi(rdev); 452 u32 tmp; 453 int ret; 454 455 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 456 offsetof(SMU7_Firmware_Header, DpmTable), 457 &tmp, pi->sram_end); 458 459 if (ret == 0) 460 pi->dpm_table_start = tmp; 461 462 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 463 offsetof(SMU7_Firmware_Header, SoftRegisters), 464 &tmp, pi->sram_end); 465 466 if (ret == 0) 467 pi->soft_regs_start = tmp; 468 469 return ret; 470 } 471 472 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev) 473 { 474 struct kv_power_info *pi = kv_get_pi(rdev); 475 int ret; 476 477 pi->graphics_voltage_change_enable = 1; 478 479 ret = kv_copy_bytes_to_smc(rdev, 480 pi->dpm_table_start + 481 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), 482 &pi->graphics_voltage_change_enable, 483 sizeof(u8), pi->sram_end); 484 485 return ret; 486 } 487 488 static int kv_set_dpm_interval(struct radeon_device *rdev) 489 { 490 struct kv_power_info *pi = kv_get_pi(rdev); 491 int ret; 492 493 pi->graphics_interval = 1; 494 495 ret = kv_copy_bytes_to_smc(rdev, 496 pi->dpm_table_start + 497 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), 498 &pi->graphics_interval, 499 sizeof(u8), pi->sram_end); 500 501 return ret; 502 } 503 504 static int kv_set_dpm_boot_state(struct radeon_device *rdev) 505 { 506 struct kv_power_info *pi = kv_get_pi(rdev); 507 int ret; 508 509 ret = kv_copy_bytes_to_smc(rdev, 510 pi->dpm_table_start + 511 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), 512 &pi->graphics_boot_level, 513 sizeof(u8), pi->sram_end); 514 515 return ret; 516 } 517 518 static void kv_program_vc(struct radeon_device *rdev) 519 { 520 WREG32_SMC(CG_FTV_0, 0x3FFFC100); 521 } 522 523 static void kv_clear_vc(struct radeon_device *rdev) 524 { 525 WREG32_SMC(CG_FTV_0, 0); 526 } 527 528 static int kv_set_divider_value(struct radeon_device *rdev, 529 u32 index, u32 sclk) 530 { 531 struct kv_power_info *pi = kv_get_pi(rdev); 532 struct atom_clock_dividers dividers; 533 int ret; 534 535 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 536 sclk, false, ÷rs); 537 if (ret) 538 return ret; 539 540 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; 541 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); 542 543 return 0; 544 } 545 546 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev, 547 struct sumo_vid_mapping_table *vid_mapping_table, 548 u32 vid_2bit) 549 { 550 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 551 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 552 u32 i; 553 554 if (vddc_sclk_table && vddc_sclk_table->count) { 555 if (vid_2bit < vddc_sclk_table->count) 556 return vddc_sclk_table->entries[vid_2bit].v; 557 else 558 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; 559 } else { 560 for (i = 0; i < vid_mapping_table->num_entries; i++) { 561 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 562 return vid_mapping_table->entries[i].vid_7bit; 563 } 564 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 565 } 566 } 567 568 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev, 569 struct sumo_vid_mapping_table *vid_mapping_table, 570 u32 vid_7bit) 571 { 572 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 573 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 574 u32 i; 575 576 if (vddc_sclk_table && vddc_sclk_table->count) { 577 for (i = 0; i < vddc_sclk_table->count; i++) { 578 if (vddc_sclk_table->entries[i].v == vid_7bit) 579 return i; 580 } 581 return vddc_sclk_table->count - 1; 582 } else { 583 for (i = 0; i < vid_mapping_table->num_entries; i++) { 584 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 585 return vid_mapping_table->entries[i].vid_2bit; 586 } 587 588 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 589 } 590 } 591 592 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev, 593 u16 voltage) 594 { 595 return 6200 - (voltage * 25); 596 } 597 598 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev, 599 u32 vid_2bit) 600 { 601 struct kv_power_info *pi = kv_get_pi(rdev); 602 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev, 603 &pi->sys_info.vid_mapping_table, 604 vid_2bit); 605 606 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit); 607 } 608 609 610 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid) 611 { 612 struct kv_power_info *pi = kv_get_pi(rdev); 613 614 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; 615 pi->graphics_level[index].MinVddNb = 616 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid)); 617 618 return 0; 619 } 620 621 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at) 622 { 623 struct kv_power_info *pi = kv_get_pi(rdev); 624 625 pi->graphics_level[index].AT = cpu_to_be16((u16)at); 626 627 return 0; 628 } 629 630 static void kv_dpm_power_level_enable(struct radeon_device *rdev, 631 u32 index, bool enable) 632 { 633 struct kv_power_info *pi = kv_get_pi(rdev); 634 635 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; 636 } 637 638 static void kv_start_dpm(struct radeon_device *rdev) 639 { 640 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 641 642 tmp |= GLOBAL_PWRMGT_EN; 643 WREG32_SMC(GENERAL_PWRMGT, tmp); 644 645 kv_smc_dpm_enable(rdev, true); 646 } 647 648 static void kv_stop_dpm(struct radeon_device *rdev) 649 { 650 kv_smc_dpm_enable(rdev, false); 651 } 652 653 static void kv_start_am(struct radeon_device *rdev) 654 { 655 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 656 657 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 658 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN; 659 660 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 661 } 662 663 static void kv_reset_am(struct radeon_device *rdev) 664 { 665 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 666 667 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 668 669 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 670 } 671 672 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze) 673 { 674 return kv_notify_message_to_smu(rdev, freeze ? 675 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); 676 } 677 678 static int kv_force_lowest_valid(struct radeon_device *rdev) 679 { 680 return kv_force_dpm_lowest(rdev); 681 } 682 683 static int kv_unforce_levels(struct radeon_device *rdev) 684 { 685 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 686 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); 687 else 688 return kv_set_enabled_levels(rdev); 689 } 690 691 static int kv_update_sclk_t(struct radeon_device *rdev) 692 { 693 struct kv_power_info *pi = kv_get_pi(rdev); 694 u32 low_sclk_interrupt_t = 0; 695 int ret = 0; 696 697 if (pi->caps_sclk_throttle_low_notification) { 698 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 699 700 ret = kv_copy_bytes_to_smc(rdev, 701 pi->dpm_table_start + 702 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), 703 (u8 *)&low_sclk_interrupt_t, 704 sizeof(u32), pi->sram_end); 705 } 706 return ret; 707 } 708 709 static int kv_program_bootup_state(struct radeon_device *rdev) 710 { 711 struct kv_power_info *pi = kv_get_pi(rdev); 712 u32 i; 713 struct radeon_clock_voltage_dependency_table *table = 714 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 715 716 if (table && table->count) { 717 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 718 if (table->entries[i].clk == pi->boot_pl.sclk) 719 break; 720 } 721 722 pi->graphics_boot_level = (u8)i; 723 kv_dpm_power_level_enable(rdev, i, true); 724 } else { 725 struct sumo_sclk_voltage_mapping_table *table = 726 &pi->sys_info.sclk_voltage_mapping_table; 727 728 if (table->num_max_dpm_entries == 0) 729 return -EINVAL; 730 731 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 732 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) 733 break; 734 } 735 736 pi->graphics_boot_level = (u8)i; 737 kv_dpm_power_level_enable(rdev, i, true); 738 } 739 return 0; 740 } 741 742 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev) 743 { 744 struct kv_power_info *pi = kv_get_pi(rdev); 745 int ret; 746 747 pi->graphics_therm_throttle_enable = 1; 748 749 ret = kv_copy_bytes_to_smc(rdev, 750 pi->dpm_table_start + 751 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), 752 &pi->graphics_therm_throttle_enable, 753 sizeof(u8), pi->sram_end); 754 755 return ret; 756 } 757 758 static int kv_upload_dpm_settings(struct radeon_device *rdev) 759 { 760 struct kv_power_info *pi = kv_get_pi(rdev); 761 int ret; 762 763 ret = kv_copy_bytes_to_smc(rdev, 764 pi->dpm_table_start + 765 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), 766 (u8 *)&pi->graphics_level, 767 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, 768 pi->sram_end); 769 770 if (ret) 771 return ret; 772 773 ret = kv_copy_bytes_to_smc(rdev, 774 pi->dpm_table_start + 775 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), 776 &pi->graphics_dpm_level_count, 777 sizeof(u8), pi->sram_end); 778 779 return ret; 780 } 781 782 static u32 kv_get_clock_difference(u32 a, u32 b) 783 { 784 return (a >= b) ? a - b : b - a; 785 } 786 787 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk) 788 { 789 struct kv_power_info *pi = kv_get_pi(rdev); 790 u32 value; 791 792 if (pi->caps_enable_dfs_bypass) { 793 if (kv_get_clock_difference(clk, 40000) < 200) 794 value = 3; 795 else if (kv_get_clock_difference(clk, 30000) < 200) 796 value = 2; 797 else if (kv_get_clock_difference(clk, 20000) < 200) 798 value = 7; 799 else if (kv_get_clock_difference(clk, 15000) < 200) 800 value = 6; 801 else if (kv_get_clock_difference(clk, 10000) < 200) 802 value = 8; 803 else 804 value = 0; 805 } else { 806 value = 0; 807 } 808 809 return value; 810 } 811 812 static int kv_populate_uvd_table(struct radeon_device *rdev) 813 { 814 struct kv_power_info *pi = kv_get_pi(rdev); 815 struct radeon_uvd_clock_voltage_dependency_table *table = 816 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 817 struct atom_clock_dividers dividers; 818 int ret; 819 u32 i; 820 821 if (table == NULL || table->count == 0) 822 return 0; 823 824 pi->uvd_level_count = 0; 825 for (i = 0; i < table->count; i++) { 826 if (pi->high_voltage_t && 827 (pi->high_voltage_t < table->entries[i].v)) 828 break; 829 830 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); 831 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); 832 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); 833 834 pi->uvd_level[i].VClkBypassCntl = 835 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); 836 pi->uvd_level[i].DClkBypassCntl = 837 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); 838 839 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 840 table->entries[i].vclk, false, ÷rs); 841 if (ret) 842 return ret; 843 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; 844 845 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 846 table->entries[i].dclk, false, ÷rs); 847 if (ret) 848 return ret; 849 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; 850 851 pi->uvd_level_count++; 852 } 853 854 ret = kv_copy_bytes_to_smc(rdev, 855 pi->dpm_table_start + 856 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), 857 (u8 *)&pi->uvd_level_count, 858 sizeof(u8), pi->sram_end); 859 if (ret) 860 return ret; 861 862 pi->uvd_interval = 1; 863 864 ret = kv_copy_bytes_to_smc(rdev, 865 pi->dpm_table_start + 866 offsetof(SMU7_Fusion_DpmTable, UVDInterval), 867 &pi->uvd_interval, 868 sizeof(u8), pi->sram_end); 869 if (ret) 870 return ret; 871 872 ret = kv_copy_bytes_to_smc(rdev, 873 pi->dpm_table_start + 874 offsetof(SMU7_Fusion_DpmTable, UvdLevel), 875 (u8 *)&pi->uvd_level, 876 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, 877 pi->sram_end); 878 879 return ret; 880 881 } 882 883 static int kv_populate_vce_table(struct radeon_device *rdev) 884 { 885 struct kv_power_info *pi = kv_get_pi(rdev); 886 int ret; 887 u32 i; 888 struct radeon_vce_clock_voltage_dependency_table *table = 889 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 890 struct atom_clock_dividers dividers; 891 892 if (table == NULL || table->count == 0) 893 return 0; 894 895 pi->vce_level_count = 0; 896 for (i = 0; i < table->count; i++) { 897 if (pi->high_voltage_t && 898 pi->high_voltage_t < table->entries[i].v) 899 break; 900 901 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); 902 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 903 904 pi->vce_level[i].ClkBypassCntl = 905 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); 906 907 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 908 table->entries[i].evclk, false, ÷rs); 909 if (ret) 910 return ret; 911 pi->vce_level[i].Divider = (u8)dividers.post_div; 912 913 pi->vce_level_count++; 914 } 915 916 ret = kv_copy_bytes_to_smc(rdev, 917 pi->dpm_table_start + 918 offsetof(SMU7_Fusion_DpmTable, VceLevelCount), 919 (u8 *)&pi->vce_level_count, 920 sizeof(u8), 921 pi->sram_end); 922 if (ret) 923 return ret; 924 925 pi->vce_interval = 1; 926 927 ret = kv_copy_bytes_to_smc(rdev, 928 pi->dpm_table_start + 929 offsetof(SMU7_Fusion_DpmTable, VCEInterval), 930 (u8 *)&pi->vce_interval, 931 sizeof(u8), 932 pi->sram_end); 933 if (ret) 934 return ret; 935 936 ret = kv_copy_bytes_to_smc(rdev, 937 pi->dpm_table_start + 938 offsetof(SMU7_Fusion_DpmTable, VceLevel), 939 (u8 *)&pi->vce_level, 940 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, 941 pi->sram_end); 942 943 return ret; 944 } 945 946 static int kv_populate_samu_table(struct radeon_device *rdev) 947 { 948 struct kv_power_info *pi = kv_get_pi(rdev); 949 struct radeon_clock_voltage_dependency_table *table = 950 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 951 struct atom_clock_dividers dividers; 952 int ret; 953 u32 i; 954 955 if (table == NULL || table->count == 0) 956 return 0; 957 958 pi->samu_level_count = 0; 959 for (i = 0; i < table->count; i++) { 960 if (pi->high_voltage_t && 961 pi->high_voltage_t < table->entries[i].v) 962 break; 963 964 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 965 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 966 967 pi->samu_level[i].ClkBypassCntl = 968 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk); 969 970 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 971 table->entries[i].clk, false, ÷rs); 972 if (ret) 973 return ret; 974 pi->samu_level[i].Divider = (u8)dividers.post_div; 975 976 pi->samu_level_count++; 977 } 978 979 ret = kv_copy_bytes_to_smc(rdev, 980 pi->dpm_table_start + 981 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), 982 (u8 *)&pi->samu_level_count, 983 sizeof(u8), 984 pi->sram_end); 985 if (ret) 986 return ret; 987 988 pi->samu_interval = 1; 989 990 ret = kv_copy_bytes_to_smc(rdev, 991 pi->dpm_table_start + 992 offsetof(SMU7_Fusion_DpmTable, SAMUInterval), 993 (u8 *)&pi->samu_interval, 994 sizeof(u8), 995 pi->sram_end); 996 if (ret) 997 return ret; 998 999 ret = kv_copy_bytes_to_smc(rdev, 1000 pi->dpm_table_start + 1001 offsetof(SMU7_Fusion_DpmTable, SamuLevel), 1002 (u8 *)&pi->samu_level, 1003 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, 1004 pi->sram_end); 1005 if (ret) 1006 return ret; 1007 1008 return ret; 1009 } 1010 1011 1012 static int kv_populate_acp_table(struct radeon_device *rdev) 1013 { 1014 struct kv_power_info *pi = kv_get_pi(rdev); 1015 struct radeon_clock_voltage_dependency_table *table = 1016 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1017 struct atom_clock_dividers dividers; 1018 int ret; 1019 u32 i; 1020 1021 if (table == NULL || table->count == 0) 1022 return 0; 1023 1024 pi->acp_level_count = 0; 1025 for (i = 0; i < table->count; i++) { 1026 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1027 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1028 1029 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1030 table->entries[i].clk, false, ÷rs); 1031 if (ret) 1032 return ret; 1033 pi->acp_level[i].Divider = (u8)dividers.post_div; 1034 1035 pi->acp_level_count++; 1036 } 1037 1038 ret = kv_copy_bytes_to_smc(rdev, 1039 pi->dpm_table_start + 1040 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), 1041 (u8 *)&pi->acp_level_count, 1042 sizeof(u8), 1043 pi->sram_end); 1044 if (ret) 1045 return ret; 1046 1047 pi->acp_interval = 1; 1048 1049 ret = kv_copy_bytes_to_smc(rdev, 1050 pi->dpm_table_start + 1051 offsetof(SMU7_Fusion_DpmTable, ACPInterval), 1052 (u8 *)&pi->acp_interval, 1053 sizeof(u8), 1054 pi->sram_end); 1055 if (ret) 1056 return ret; 1057 1058 ret = kv_copy_bytes_to_smc(rdev, 1059 pi->dpm_table_start + 1060 offsetof(SMU7_Fusion_DpmTable, AcpLevel), 1061 (u8 *)&pi->acp_level, 1062 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, 1063 pi->sram_end); 1064 if (ret) 1065 return ret; 1066 1067 return ret; 1068 } 1069 1070 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev) 1071 { 1072 struct kv_power_info *pi = kv_get_pi(rdev); 1073 u32 i; 1074 struct radeon_clock_voltage_dependency_table *table = 1075 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1076 1077 if (table && table->count) { 1078 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1079 if (pi->caps_enable_dfs_bypass) { 1080 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) 1081 pi->graphics_level[i].ClkBypassCntl = 3; 1082 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) 1083 pi->graphics_level[i].ClkBypassCntl = 2; 1084 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) 1085 pi->graphics_level[i].ClkBypassCntl = 7; 1086 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) 1087 pi->graphics_level[i].ClkBypassCntl = 6; 1088 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) 1089 pi->graphics_level[i].ClkBypassCntl = 8; 1090 else 1091 pi->graphics_level[i].ClkBypassCntl = 0; 1092 } else { 1093 pi->graphics_level[i].ClkBypassCntl = 0; 1094 } 1095 } 1096 } else { 1097 struct sumo_sclk_voltage_mapping_table *table = 1098 &pi->sys_info.sclk_voltage_mapping_table; 1099 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1100 if (pi->caps_enable_dfs_bypass) { 1101 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) 1102 pi->graphics_level[i].ClkBypassCntl = 3; 1103 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) 1104 pi->graphics_level[i].ClkBypassCntl = 2; 1105 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) 1106 pi->graphics_level[i].ClkBypassCntl = 7; 1107 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) 1108 pi->graphics_level[i].ClkBypassCntl = 6; 1109 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) 1110 pi->graphics_level[i].ClkBypassCntl = 8; 1111 else 1112 pi->graphics_level[i].ClkBypassCntl = 0; 1113 } else { 1114 pi->graphics_level[i].ClkBypassCntl = 0; 1115 } 1116 } 1117 } 1118 } 1119 1120 static int kv_enable_ulv(struct radeon_device *rdev, bool enable) 1121 { 1122 return kv_notify_message_to_smu(rdev, enable ? 1123 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); 1124 } 1125 1126 static void kv_reset_acp_boot_level(struct radeon_device *rdev) 1127 { 1128 struct kv_power_info *pi = kv_get_pi(rdev); 1129 1130 pi->acp_boot_level = 0xff; 1131 } 1132 1133 static void kv_update_current_ps(struct radeon_device *rdev, 1134 struct radeon_ps *rps) 1135 { 1136 struct kv_ps *new_ps = kv_get_ps(rps); 1137 struct kv_power_info *pi = kv_get_pi(rdev); 1138 1139 pi->current_rps = *rps; 1140 pi->current_ps = *new_ps; 1141 pi->current_rps.ps_priv = &pi->current_ps; 1142 } 1143 1144 static void kv_update_requested_ps(struct radeon_device *rdev, 1145 struct radeon_ps *rps) 1146 { 1147 struct kv_ps *new_ps = kv_get_ps(rps); 1148 struct kv_power_info *pi = kv_get_pi(rdev); 1149 1150 pi->requested_rps = *rps; 1151 pi->requested_ps = *new_ps; 1152 pi->requested_rps.ps_priv = &pi->requested_ps; 1153 } 1154 1155 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable) 1156 { 1157 struct kv_power_info *pi = kv_get_pi(rdev); 1158 int ret; 1159 1160 if (pi->bapm_enable) { 1161 ret = kv_smc_bapm_enable(rdev, enable); 1162 if (ret) 1163 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1164 } 1165 } 1166 1167 int kv_dpm_enable(struct radeon_device *rdev) 1168 { 1169 struct kv_power_info *pi = kv_get_pi(rdev); 1170 int ret; 1171 1172 ret = kv_process_firmware_header(rdev); 1173 if (ret) { 1174 DRM_ERROR("kv_process_firmware_header failed\n"); 1175 return ret; 1176 } 1177 kv_init_fps_limits(rdev); 1178 kv_init_graphics_levels(rdev); 1179 ret = kv_program_bootup_state(rdev); 1180 if (ret) { 1181 DRM_ERROR("kv_program_bootup_state failed\n"); 1182 return ret; 1183 } 1184 kv_calculate_dfs_bypass_settings(rdev); 1185 ret = kv_upload_dpm_settings(rdev); 1186 if (ret) { 1187 DRM_ERROR("kv_upload_dpm_settings failed\n"); 1188 return ret; 1189 } 1190 ret = kv_populate_uvd_table(rdev); 1191 if (ret) { 1192 DRM_ERROR("kv_populate_uvd_table failed\n"); 1193 return ret; 1194 } 1195 ret = kv_populate_vce_table(rdev); 1196 if (ret) { 1197 DRM_ERROR("kv_populate_vce_table failed\n"); 1198 return ret; 1199 } 1200 ret = kv_populate_samu_table(rdev); 1201 if (ret) { 1202 DRM_ERROR("kv_populate_samu_table failed\n"); 1203 return ret; 1204 } 1205 ret = kv_populate_acp_table(rdev); 1206 if (ret) { 1207 DRM_ERROR("kv_populate_acp_table failed\n"); 1208 return ret; 1209 } 1210 kv_program_vc(rdev); 1211 #if 0 1212 kv_initialize_hardware_cac_manager(rdev); 1213 #endif 1214 kv_start_am(rdev); 1215 if (pi->enable_auto_thermal_throttling) { 1216 ret = kv_enable_auto_thermal_throttling(rdev); 1217 if (ret) { 1218 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); 1219 return ret; 1220 } 1221 } 1222 ret = kv_enable_dpm_voltage_scaling(rdev); 1223 if (ret) { 1224 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); 1225 return ret; 1226 } 1227 ret = kv_set_dpm_interval(rdev); 1228 if (ret) { 1229 DRM_ERROR("kv_set_dpm_interval failed\n"); 1230 return ret; 1231 } 1232 ret = kv_set_dpm_boot_state(rdev); 1233 if (ret) { 1234 DRM_ERROR("kv_set_dpm_boot_state failed\n"); 1235 return ret; 1236 } 1237 ret = kv_enable_ulv(rdev, true); 1238 if (ret) { 1239 DRM_ERROR("kv_enable_ulv failed\n"); 1240 return ret; 1241 } 1242 kv_start_dpm(rdev); 1243 ret = kv_enable_didt(rdev, true); 1244 if (ret) { 1245 DRM_ERROR("kv_enable_didt failed\n"); 1246 return ret; 1247 } 1248 ret = kv_enable_smc_cac(rdev, true); 1249 if (ret) { 1250 DRM_ERROR("kv_enable_smc_cac failed\n"); 1251 return ret; 1252 } 1253 1254 kv_reset_acp_boot_level(rdev); 1255 1256 ret = kv_smc_bapm_enable(rdev, false); 1257 if (ret) { 1258 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1259 return ret; 1260 } 1261 1262 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1263 1264 return ret; 1265 } 1266 1267 int kv_dpm_late_enable(struct radeon_device *rdev) 1268 { 1269 int ret = 0; 1270 1271 if (rdev->irq.installed && 1272 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1273 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1274 if (ret) { 1275 DRM_ERROR("kv_set_thermal_temperature_range failed\n"); 1276 return ret; 1277 } 1278 rdev->irq.dpm_thermal = true; 1279 radeon_irq_set(rdev); 1280 } 1281 1282 /* powerdown unused blocks for now */ 1283 kv_dpm_powergate_acp(rdev, true); 1284 kv_dpm_powergate_samu(rdev, true); 1285 kv_dpm_powergate_vce(rdev, true); 1286 kv_dpm_powergate_uvd(rdev, true); 1287 1288 return ret; 1289 } 1290 1291 void kv_dpm_disable(struct radeon_device *rdev) 1292 { 1293 kv_smc_bapm_enable(rdev, false); 1294 1295 if (rdev->family == CHIP_MULLINS) 1296 kv_enable_nb_dpm(rdev, false); 1297 1298 /* powerup blocks */ 1299 kv_dpm_powergate_acp(rdev, false); 1300 kv_dpm_powergate_samu(rdev, false); 1301 kv_dpm_powergate_vce(rdev, false); 1302 kv_dpm_powergate_uvd(rdev, false); 1303 1304 kv_enable_smc_cac(rdev, false); 1305 kv_enable_didt(rdev, false); 1306 kv_clear_vc(rdev); 1307 kv_stop_dpm(rdev); 1308 kv_enable_ulv(rdev, false); 1309 kv_reset_am(rdev); 1310 1311 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1312 } 1313 1314 #if 0 1315 static int kv_write_smc_soft_register(struct radeon_device *rdev, 1316 u16 reg_offset, u32 value) 1317 { 1318 struct kv_power_info *pi = kv_get_pi(rdev); 1319 1320 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, 1321 (u8 *)&value, sizeof(u16), pi->sram_end); 1322 } 1323 1324 static int kv_read_smc_soft_register(struct radeon_device *rdev, 1325 u16 reg_offset, u32 *value) 1326 { 1327 struct kv_power_info *pi = kv_get_pi(rdev); 1328 1329 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, 1330 value, pi->sram_end); 1331 } 1332 #endif 1333 1334 static void kv_init_sclk_t(struct radeon_device *rdev) 1335 { 1336 struct kv_power_info *pi = kv_get_pi(rdev); 1337 1338 pi->low_sclk_interrupt_t = 0; 1339 } 1340 1341 static int kv_init_fps_limits(struct radeon_device *rdev) 1342 { 1343 struct kv_power_info *pi = kv_get_pi(rdev); 1344 int ret = 0; 1345 1346 if (pi->caps_fps) { 1347 u16 tmp; 1348 1349 tmp = 45; 1350 pi->fps_high_t = cpu_to_be16(tmp); 1351 ret = kv_copy_bytes_to_smc(rdev, 1352 pi->dpm_table_start + 1353 offsetof(SMU7_Fusion_DpmTable, FpsHighT), 1354 (u8 *)&pi->fps_high_t, 1355 sizeof(u16), pi->sram_end); 1356 1357 tmp = 30; 1358 pi->fps_low_t = cpu_to_be16(tmp); 1359 1360 ret = kv_copy_bytes_to_smc(rdev, 1361 pi->dpm_table_start + 1362 offsetof(SMU7_Fusion_DpmTable, FpsLowT), 1363 (u8 *)&pi->fps_low_t, 1364 sizeof(u16), pi->sram_end); 1365 1366 } 1367 return ret; 1368 } 1369 1370 static void kv_init_powergate_state(struct radeon_device *rdev) 1371 { 1372 struct kv_power_info *pi = kv_get_pi(rdev); 1373 1374 pi->uvd_power_gated = false; 1375 pi->vce_power_gated = false; 1376 pi->samu_power_gated = false; 1377 pi->acp_power_gated = false; 1378 1379 } 1380 1381 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 1382 { 1383 return kv_notify_message_to_smu(rdev, enable ? 1384 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); 1385 } 1386 1387 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable) 1388 { 1389 return kv_notify_message_to_smu(rdev, enable ? 1390 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); 1391 } 1392 1393 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable) 1394 { 1395 return kv_notify_message_to_smu(rdev, enable ? 1396 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); 1397 } 1398 1399 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable) 1400 { 1401 return kv_notify_message_to_smu(rdev, enable ? 1402 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); 1403 } 1404 1405 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) 1406 { 1407 struct kv_power_info *pi = kv_get_pi(rdev); 1408 struct radeon_uvd_clock_voltage_dependency_table *table = 1409 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1410 int ret; 1411 u32 mask; 1412 1413 if (!gate) { 1414 if (table->count) 1415 pi->uvd_boot_level = table->count - 1; 1416 else 1417 pi->uvd_boot_level = 0; 1418 1419 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { 1420 mask = 1 << pi->uvd_boot_level; 1421 } else { 1422 mask = 0x1f; 1423 } 1424 1425 ret = kv_copy_bytes_to_smc(rdev, 1426 pi->dpm_table_start + 1427 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1428 (uint8_t *)&pi->uvd_boot_level, 1429 sizeof(u8), pi->sram_end); 1430 if (ret) 1431 return ret; 1432 1433 kv_send_msg_to_smc_with_parameter(rdev, 1434 PPSMC_MSG_UVDDPM_SetEnabledMask, 1435 mask); 1436 } 1437 1438 return kv_enable_uvd_dpm(rdev, !gate); 1439 } 1440 1441 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) 1442 { 1443 u8 i; 1444 struct radeon_vce_clock_voltage_dependency_table *table = 1445 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1446 1447 for (i = 0; i < table->count; i++) { 1448 if (table->entries[i].evclk >= evclk) 1449 break; 1450 } 1451 1452 return i; 1453 } 1454 1455 static int kv_update_vce_dpm(struct radeon_device *rdev, 1456 struct radeon_ps *radeon_new_state, 1457 struct radeon_ps *radeon_current_state) 1458 { 1459 struct kv_power_info *pi = kv_get_pi(rdev); 1460 struct radeon_vce_clock_voltage_dependency_table *table = 1461 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1462 int ret; 1463 1464 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { 1465 kv_dpm_powergate_vce(rdev, false); 1466 /* turn the clocks on when encoding */ 1467 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 1468 if (pi->caps_stable_p_state) 1469 pi->vce_boot_level = table->count - 1; 1470 else 1471 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); 1472 1473 ret = kv_copy_bytes_to_smc(rdev, 1474 pi->dpm_table_start + 1475 offsetof(SMU7_Fusion_DpmTable, VceBootLevel), 1476 (u8 *)&pi->vce_boot_level, 1477 sizeof(u8), 1478 pi->sram_end); 1479 if (ret) 1480 return ret; 1481 1482 if (pi->caps_stable_p_state) 1483 kv_send_msg_to_smc_with_parameter(rdev, 1484 PPSMC_MSG_VCEDPM_SetEnabledMask, 1485 (1 << pi->vce_boot_level)); 1486 1487 kv_enable_vce_dpm(rdev, true); 1488 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { 1489 kv_enable_vce_dpm(rdev, false); 1490 /* turn the clocks off when not encoding */ 1491 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 1492 kv_dpm_powergate_vce(rdev, true); 1493 } 1494 1495 return 0; 1496 } 1497 1498 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) 1499 { 1500 struct kv_power_info *pi = kv_get_pi(rdev); 1501 struct radeon_clock_voltage_dependency_table *table = 1502 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1503 int ret; 1504 1505 if (!gate) { 1506 if (pi->caps_stable_p_state) 1507 pi->samu_boot_level = table->count - 1; 1508 else 1509 pi->samu_boot_level = 0; 1510 1511 ret = kv_copy_bytes_to_smc(rdev, 1512 pi->dpm_table_start + 1513 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), 1514 (u8 *)&pi->samu_boot_level, 1515 sizeof(u8), 1516 pi->sram_end); 1517 if (ret) 1518 return ret; 1519 1520 if (pi->caps_stable_p_state) 1521 kv_send_msg_to_smc_with_parameter(rdev, 1522 PPSMC_MSG_SAMUDPM_SetEnabledMask, 1523 (1 << pi->samu_boot_level)); 1524 } 1525 1526 return kv_enable_samu_dpm(rdev, !gate); 1527 } 1528 1529 static u8 kv_get_acp_boot_level(struct radeon_device *rdev) 1530 { 1531 u8 i; 1532 struct radeon_clock_voltage_dependency_table *table = 1533 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1534 1535 for (i = 0; i < table->count; i++) { 1536 if (table->entries[i].clk >= 0) /* XXX */ 1537 break; 1538 } 1539 1540 if (i >= table->count) 1541 i = table->count - 1; 1542 1543 return i; 1544 } 1545 1546 static void kv_update_acp_boot_level(struct radeon_device *rdev) 1547 { 1548 struct kv_power_info *pi = kv_get_pi(rdev); 1549 u8 acp_boot_level; 1550 1551 if (!pi->caps_stable_p_state) { 1552 acp_boot_level = kv_get_acp_boot_level(rdev); 1553 if (acp_boot_level != pi->acp_boot_level) { 1554 pi->acp_boot_level = acp_boot_level; 1555 kv_send_msg_to_smc_with_parameter(rdev, 1556 PPSMC_MSG_ACPDPM_SetEnabledMask, 1557 (1 << pi->acp_boot_level)); 1558 } 1559 } 1560 } 1561 1562 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate) 1563 { 1564 struct kv_power_info *pi = kv_get_pi(rdev); 1565 struct radeon_clock_voltage_dependency_table *table = 1566 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1567 int ret; 1568 1569 if (!gate) { 1570 if (pi->caps_stable_p_state) 1571 pi->acp_boot_level = table->count - 1; 1572 else 1573 pi->acp_boot_level = kv_get_acp_boot_level(rdev); 1574 1575 ret = kv_copy_bytes_to_smc(rdev, 1576 pi->dpm_table_start + 1577 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), 1578 (u8 *)&pi->acp_boot_level, 1579 sizeof(u8), 1580 pi->sram_end); 1581 if (ret) 1582 return ret; 1583 1584 if (pi->caps_stable_p_state) 1585 kv_send_msg_to_smc_with_parameter(rdev, 1586 PPSMC_MSG_ACPDPM_SetEnabledMask, 1587 (1 << pi->acp_boot_level)); 1588 } 1589 1590 return kv_enable_acp_dpm(rdev, !gate); 1591 } 1592 1593 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 1594 { 1595 struct kv_power_info *pi = kv_get_pi(rdev); 1596 1597 if (pi->uvd_power_gated == gate) 1598 return; 1599 1600 pi->uvd_power_gated = gate; 1601 1602 if (gate) { 1603 if (pi->caps_uvd_pg) { 1604 uvd_v1_0_stop(rdev); 1605 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false); 1606 } 1607 kv_update_uvd_dpm(rdev, gate); 1608 if (pi->caps_uvd_pg) 1609 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF); 1610 } else { 1611 if (pi->caps_uvd_pg) { 1612 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON); 1613 uvd_v4_2_resume(rdev); 1614 uvd_v1_0_start(rdev); 1615 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true); 1616 } 1617 kv_update_uvd_dpm(rdev, gate); 1618 } 1619 } 1620 1621 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate) 1622 { 1623 struct kv_power_info *pi = kv_get_pi(rdev); 1624 1625 if (pi->vce_power_gated == gate) 1626 return; 1627 1628 pi->vce_power_gated = gate; 1629 1630 if (gate) { 1631 if (pi->caps_vce_pg) { 1632 /* XXX do we need a vce_v1_0_stop() ? */ 1633 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF); 1634 } 1635 } else { 1636 if (pi->caps_vce_pg) { 1637 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON); 1638 vce_v2_0_resume(rdev); 1639 vce_v1_0_start(rdev); 1640 } 1641 } 1642 } 1643 1644 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate) 1645 { 1646 struct kv_power_info *pi = kv_get_pi(rdev); 1647 1648 if (pi->samu_power_gated == gate) 1649 return; 1650 1651 pi->samu_power_gated = gate; 1652 1653 if (gate) { 1654 kv_update_samu_dpm(rdev, true); 1655 if (pi->caps_samu_pg) 1656 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF); 1657 } else { 1658 if (pi->caps_samu_pg) 1659 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON); 1660 kv_update_samu_dpm(rdev, false); 1661 } 1662 } 1663 1664 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate) 1665 { 1666 struct kv_power_info *pi = kv_get_pi(rdev); 1667 1668 if (pi->acp_power_gated == gate) 1669 return; 1670 1671 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 1672 return; 1673 1674 pi->acp_power_gated = gate; 1675 1676 if (gate) { 1677 kv_update_acp_dpm(rdev, true); 1678 if (pi->caps_acp_pg) 1679 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF); 1680 } else { 1681 if (pi->caps_acp_pg) 1682 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON); 1683 kv_update_acp_dpm(rdev, false); 1684 } 1685 } 1686 1687 static void kv_set_valid_clock_range(struct radeon_device *rdev, 1688 struct radeon_ps *new_rps) 1689 { 1690 struct kv_ps *new_ps = kv_get_ps(new_rps); 1691 struct kv_power_info *pi = kv_get_pi(rdev); 1692 u32 i; 1693 struct radeon_clock_voltage_dependency_table *table = 1694 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1695 1696 if (table && table->count) { 1697 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1698 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || 1699 (i == (pi->graphics_dpm_level_count - 1))) { 1700 pi->lowest_valid = i; 1701 break; 1702 } 1703 } 1704 1705 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1706 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) 1707 break; 1708 } 1709 pi->highest_valid = i; 1710 1711 if (pi->lowest_valid > pi->highest_valid) { 1712 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > 1713 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) 1714 pi->highest_valid = pi->lowest_valid; 1715 else 1716 pi->lowest_valid = pi->highest_valid; 1717 } 1718 } else { 1719 struct sumo_sclk_voltage_mapping_table *table = 1720 &pi->sys_info.sclk_voltage_mapping_table; 1721 1722 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { 1723 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || 1724 i == (int)(pi->graphics_dpm_level_count - 1)) { 1725 pi->lowest_valid = i; 1726 break; 1727 } 1728 } 1729 1730 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1731 if (table->entries[i].sclk_frequency <= 1732 new_ps->levels[new_ps->num_levels - 1].sclk) 1733 break; 1734 } 1735 pi->highest_valid = i; 1736 1737 if (pi->lowest_valid > pi->highest_valid) { 1738 if ((new_ps->levels[0].sclk - 1739 table->entries[pi->highest_valid].sclk_frequency) > 1740 (table->entries[pi->lowest_valid].sclk_frequency - 1741 new_ps->levels[new_ps->num_levels -1].sclk)) 1742 pi->highest_valid = pi->lowest_valid; 1743 else 1744 pi->lowest_valid = pi->highest_valid; 1745 } 1746 } 1747 } 1748 1749 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev, 1750 struct radeon_ps *new_rps) 1751 { 1752 struct kv_ps *new_ps = kv_get_ps(new_rps); 1753 struct kv_power_info *pi = kv_get_pi(rdev); 1754 int ret = 0; 1755 u8 clk_bypass_cntl; 1756 1757 if (pi->caps_enable_dfs_bypass) { 1758 clk_bypass_cntl = new_ps->need_dfs_bypass ? 1759 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; 1760 ret = kv_copy_bytes_to_smc(rdev, 1761 (pi->dpm_table_start + 1762 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + 1763 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + 1764 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), 1765 &clk_bypass_cntl, 1766 sizeof(u8), pi->sram_end); 1767 } 1768 1769 return ret; 1770 } 1771 1772 static int kv_enable_nb_dpm(struct radeon_device *rdev, 1773 bool enable) 1774 { 1775 struct kv_power_info *pi = kv_get_pi(rdev); 1776 int ret = 0; 1777 1778 if (enable) { 1779 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { 1780 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable); 1781 if (ret == 0) 1782 pi->nb_dpm_enabled = true; 1783 } 1784 } else { 1785 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { 1786 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable); 1787 if (ret == 0) 1788 pi->nb_dpm_enabled = false; 1789 } 1790 } 1791 1792 return ret; 1793 } 1794 1795 int kv_dpm_force_performance_level(struct radeon_device *rdev, 1796 enum radeon_dpm_forced_level level) 1797 { 1798 int ret; 1799 1800 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1801 ret = kv_force_dpm_highest(rdev); 1802 if (ret) 1803 return ret; 1804 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1805 ret = kv_force_dpm_lowest(rdev); 1806 if (ret) 1807 return ret; 1808 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1809 ret = kv_unforce_levels(rdev); 1810 if (ret) 1811 return ret; 1812 } 1813 1814 rdev->pm.dpm.forced_level = level; 1815 1816 return 0; 1817 } 1818 1819 int kv_dpm_pre_set_power_state(struct radeon_device *rdev) 1820 { 1821 struct kv_power_info *pi = kv_get_pi(rdev); 1822 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 1823 struct radeon_ps *new_ps = &requested_ps; 1824 1825 kv_update_requested_ps(rdev, new_ps); 1826 1827 kv_apply_state_adjust_rules(rdev, 1828 &pi->requested_rps, 1829 &pi->current_rps); 1830 1831 return 0; 1832 } 1833 1834 int kv_dpm_set_power_state(struct radeon_device *rdev) 1835 { 1836 struct kv_power_info *pi = kv_get_pi(rdev); 1837 struct radeon_ps *new_ps = &pi->requested_rps; 1838 struct radeon_ps *old_ps = &pi->current_rps; 1839 int ret; 1840 1841 if (pi->bapm_enable) { 1842 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power); 1843 if (ret) { 1844 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1845 return ret; 1846 } 1847 } 1848 1849 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1850 if (pi->enable_dpm) { 1851 kv_set_valid_clock_range(rdev, new_ps); 1852 kv_update_dfs_bypass_settings(rdev, new_ps); 1853 ret = kv_calculate_ds_divider(rdev); 1854 if (ret) { 1855 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1856 return ret; 1857 } 1858 kv_calculate_nbps_level_settings(rdev); 1859 kv_calculate_dpm_settings(rdev); 1860 kv_force_lowest_valid(rdev); 1861 kv_enable_new_levels(rdev); 1862 kv_upload_dpm_settings(rdev); 1863 kv_program_nbps_index_settings(rdev, new_ps); 1864 kv_unforce_levels(rdev); 1865 kv_set_enabled_levels(rdev); 1866 kv_force_lowest_valid(rdev); 1867 kv_unforce_levels(rdev); 1868 1869 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1870 if (ret) { 1871 DRM_ERROR("kv_update_vce_dpm failed\n"); 1872 return ret; 1873 } 1874 kv_update_sclk_t(rdev); 1875 if (rdev->family == CHIP_MULLINS) 1876 kv_enable_nb_dpm(rdev, true); 1877 } 1878 } else { 1879 if (pi->enable_dpm) { 1880 kv_set_valid_clock_range(rdev, new_ps); 1881 kv_update_dfs_bypass_settings(rdev, new_ps); 1882 ret = kv_calculate_ds_divider(rdev); 1883 if (ret) { 1884 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1885 return ret; 1886 } 1887 kv_calculate_nbps_level_settings(rdev); 1888 kv_calculate_dpm_settings(rdev); 1889 kv_freeze_sclk_dpm(rdev, true); 1890 kv_upload_dpm_settings(rdev); 1891 kv_program_nbps_index_settings(rdev, new_ps); 1892 kv_freeze_sclk_dpm(rdev, false); 1893 kv_set_enabled_levels(rdev); 1894 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1895 if (ret) { 1896 DRM_ERROR("kv_update_vce_dpm failed\n"); 1897 return ret; 1898 } 1899 kv_update_acp_boot_level(rdev); 1900 kv_update_sclk_t(rdev); 1901 kv_enable_nb_dpm(rdev, true); 1902 } 1903 } 1904 1905 return 0; 1906 } 1907 1908 void kv_dpm_post_set_power_state(struct radeon_device *rdev) 1909 { 1910 struct kv_power_info *pi = kv_get_pi(rdev); 1911 struct radeon_ps *new_ps = &pi->requested_rps; 1912 1913 kv_update_current_ps(rdev, new_ps); 1914 } 1915 1916 void kv_dpm_setup_asic(struct radeon_device *rdev) 1917 { 1918 sumo_take_smu_control(rdev, true); 1919 kv_init_powergate_state(rdev); 1920 kv_init_sclk_t(rdev); 1921 } 1922 1923 void kv_dpm_reset_asic(struct radeon_device *rdev) 1924 { 1925 struct kv_power_info *pi = kv_get_pi(rdev); 1926 1927 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1928 kv_force_lowest_valid(rdev); 1929 kv_init_graphics_levels(rdev); 1930 kv_program_bootup_state(rdev); 1931 kv_upload_dpm_settings(rdev); 1932 kv_force_lowest_valid(rdev); 1933 kv_unforce_levels(rdev); 1934 } else { 1935 kv_init_graphics_levels(rdev); 1936 kv_program_bootup_state(rdev); 1937 kv_freeze_sclk_dpm(rdev, true); 1938 kv_upload_dpm_settings(rdev); 1939 kv_freeze_sclk_dpm(rdev, false); 1940 kv_set_enabled_level(rdev, pi->graphics_boot_level); 1941 } 1942 } 1943 1944 //XXX use sumo_dpm_display_configuration_changed 1945 1946 static void kv_construct_max_power_limits_table(struct radeon_device *rdev, 1947 struct radeon_clock_and_voltage_limits *table) 1948 { 1949 struct kv_power_info *pi = kv_get_pi(rdev); 1950 1951 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { 1952 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; 1953 table->sclk = 1954 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; 1955 table->vddc = 1956 kv_convert_2bit_index_to_voltage(rdev, 1957 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); 1958 } 1959 1960 table->mclk = pi->sys_info.nbp_memory_clock[0]; 1961 } 1962 1963 static void kv_patch_voltage_values(struct radeon_device *rdev) 1964 { 1965 int i; 1966 struct radeon_uvd_clock_voltage_dependency_table *uvd_table = 1967 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1968 struct radeon_vce_clock_voltage_dependency_table *vce_table = 1969 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1970 struct radeon_clock_voltage_dependency_table *samu_table = 1971 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1972 struct radeon_clock_voltage_dependency_table *acp_table = 1973 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1974 1975 if (uvd_table->count) { 1976 for (i = 0; i < uvd_table->count; i++) 1977 uvd_table->entries[i].v = 1978 kv_convert_8bit_index_to_voltage(rdev, 1979 uvd_table->entries[i].v); 1980 } 1981 1982 if (vce_table->count) { 1983 for (i = 0; i < vce_table->count; i++) 1984 vce_table->entries[i].v = 1985 kv_convert_8bit_index_to_voltage(rdev, 1986 vce_table->entries[i].v); 1987 } 1988 1989 if (samu_table->count) { 1990 for (i = 0; i < samu_table->count; i++) 1991 samu_table->entries[i].v = 1992 kv_convert_8bit_index_to_voltage(rdev, 1993 samu_table->entries[i].v); 1994 } 1995 1996 if (acp_table->count) { 1997 for (i = 0; i < acp_table->count; i++) 1998 acp_table->entries[i].v = 1999 kv_convert_8bit_index_to_voltage(rdev, 2000 acp_table->entries[i].v); 2001 } 2002 2003 } 2004 2005 static void kv_construct_boot_state(struct radeon_device *rdev) 2006 { 2007 struct kv_power_info *pi = kv_get_pi(rdev); 2008 2009 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 2010 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 2011 pi->boot_pl.ds_divider_index = 0; 2012 pi->boot_pl.ss_divider_index = 0; 2013 pi->boot_pl.allow_gnb_slow = 1; 2014 pi->boot_pl.force_nbp_state = 0; 2015 pi->boot_pl.display_wm = 0; 2016 pi->boot_pl.vce_wm = 0; 2017 } 2018 2019 static int kv_force_dpm_highest(struct radeon_device *rdev) 2020 { 2021 int ret; 2022 u32 enable_mask, i; 2023 2024 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2025 if (ret) 2026 return ret; 2027 2028 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { 2029 if (enable_mask & (1 << i)) 2030 break; 2031 } 2032 2033 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2034 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2035 else 2036 return kv_set_enabled_level(rdev, i); 2037 } 2038 2039 static int kv_force_dpm_lowest(struct radeon_device *rdev) 2040 { 2041 int ret; 2042 u32 enable_mask, i; 2043 2044 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2045 if (ret) 2046 return ret; 2047 2048 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2049 if (enable_mask & (1 << i)) 2050 break; 2051 } 2052 2053 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2054 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2055 else 2056 return kv_set_enabled_level(rdev, i); 2057 } 2058 2059 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2060 u32 sclk, u32 min_sclk_in_sr) 2061 { 2062 struct kv_power_info *pi = kv_get_pi(rdev); 2063 u32 i; 2064 u32 temp; 2065 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? 2066 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; 2067 2068 if (sclk < min) 2069 return 0; 2070 2071 if (!pi->caps_sclk_ds) 2072 return 0; 2073 2074 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { 2075 temp = sclk / sumo_get_sleep_divider_from_id(i); 2076 if (temp >= min) 2077 break; 2078 } 2079 2080 return (u8)i; 2081 } 2082 2083 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit) 2084 { 2085 struct kv_power_info *pi = kv_get_pi(rdev); 2086 struct radeon_clock_voltage_dependency_table *table = 2087 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2088 int i; 2089 2090 if (table && table->count) { 2091 for (i = table->count - 1; i >= 0; i--) { 2092 if (pi->high_voltage_t && 2093 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <= 2094 pi->high_voltage_t)) { 2095 *limit = i; 2096 return 0; 2097 } 2098 } 2099 } else { 2100 struct sumo_sclk_voltage_mapping_table *table = 2101 &pi->sys_info.sclk_voltage_mapping_table; 2102 2103 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { 2104 if (pi->high_voltage_t && 2105 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <= 2106 pi->high_voltage_t)) { 2107 *limit = i; 2108 return 0; 2109 } 2110 } 2111 } 2112 2113 *limit = 0; 2114 return 0; 2115 } 2116 2117 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 2118 struct radeon_ps *new_rps, 2119 struct radeon_ps *old_rps) 2120 { 2121 struct kv_ps *ps = kv_get_ps(new_rps); 2122 struct kv_power_info *pi = kv_get_pi(rdev); 2123 u32 min_sclk = 10000; /* ??? */ 2124 u32 sclk, mclk = 0; 2125 int i, limit; 2126 bool force_high; 2127 struct radeon_clock_voltage_dependency_table *table = 2128 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2129 u32 stable_p_state_sclk = 0; 2130 struct radeon_clock_and_voltage_limits *max_limits = 2131 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2132 2133 if (new_rps->vce_active) { 2134 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2135 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2136 } else { 2137 new_rps->evclk = 0; 2138 new_rps->ecclk = 0; 2139 } 2140 2141 mclk = max_limits->mclk; 2142 sclk = min_sclk; 2143 2144 if (pi->caps_stable_p_state) { 2145 stable_p_state_sclk = (max_limits->sclk * 75) / 100; 2146 2147 for (i = table->count - 1; i >= 0; i++) { 2148 if (stable_p_state_sclk >= table->entries[i].clk) { 2149 stable_p_state_sclk = table->entries[i].clk; 2150 break; 2151 } 2152 } 2153 2154 if (i > 0) 2155 stable_p_state_sclk = table->entries[0].clk; 2156 2157 sclk = stable_p_state_sclk; 2158 } 2159 2160 if (new_rps->vce_active) { 2161 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 2162 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 2163 } 2164 2165 ps->need_dfs_bypass = true; 2166 2167 for (i = 0; i < ps->num_levels; i++) { 2168 if (ps->levels[i].sclk < sclk) 2169 ps->levels[i].sclk = sclk; 2170 } 2171 2172 if (table && table->count) { 2173 for (i = 0; i < ps->num_levels; i++) { 2174 if (pi->high_voltage_t && 2175 (pi->high_voltage_t < 2176 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2177 kv_get_high_voltage_limit(rdev, &limit); 2178 ps->levels[i].sclk = table->entries[limit].clk; 2179 } 2180 } 2181 } else { 2182 struct sumo_sclk_voltage_mapping_table *table = 2183 &pi->sys_info.sclk_voltage_mapping_table; 2184 2185 for (i = 0; i < ps->num_levels; i++) { 2186 if (pi->high_voltage_t && 2187 (pi->high_voltage_t < 2188 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2189 kv_get_high_voltage_limit(rdev, &limit); 2190 ps->levels[i].sclk = table->entries[limit].sclk_frequency; 2191 } 2192 } 2193 } 2194 2195 if (pi->caps_stable_p_state) { 2196 for (i = 0; i < ps->num_levels; i++) { 2197 ps->levels[i].sclk = stable_p_state_sclk; 2198 } 2199 } 2200 2201 pi->video_start = new_rps->dclk || new_rps->vclk || 2202 new_rps->evclk || new_rps->ecclk; 2203 2204 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2205 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 2206 pi->battery_state = true; 2207 else 2208 pi->battery_state = false; 2209 2210 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2211 ps->dpm0_pg_nb_ps_lo = 0x1; 2212 ps->dpm0_pg_nb_ps_hi = 0x0; 2213 ps->dpmx_nb_ps_lo = 0x1; 2214 ps->dpmx_nb_ps_hi = 0x0; 2215 } else { 2216 ps->dpm0_pg_nb_ps_lo = 0x3; 2217 ps->dpm0_pg_nb_ps_hi = 0x0; 2218 ps->dpmx_nb_ps_lo = 0x3; 2219 ps->dpmx_nb_ps_hi = 0x0; 2220 2221 if (pi->sys_info.nb_dpm_enable) { 2222 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || 2223 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || 2224 pi->disable_nb_ps3_in_battery; 2225 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; 2226 ps->dpm0_pg_nb_ps_hi = 0x2; 2227 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; 2228 ps->dpmx_nb_ps_hi = 0x2; 2229 } 2230 } 2231 } 2232 2233 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev, 2234 u32 index, bool enable) 2235 { 2236 struct kv_power_info *pi = kv_get_pi(rdev); 2237 2238 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; 2239 } 2240 2241 static int kv_calculate_ds_divider(struct radeon_device *rdev) 2242 { 2243 struct kv_power_info *pi = kv_get_pi(rdev); 2244 u32 sclk_in_sr = 10000; /* ??? */ 2245 u32 i; 2246 2247 if (pi->lowest_valid > pi->highest_valid) 2248 return -EINVAL; 2249 2250 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2251 pi->graphics_level[i].DeepSleepDivId = 2252 kv_get_sleep_divider_id_from_clock(rdev, 2253 be32_to_cpu(pi->graphics_level[i].SclkFrequency), 2254 sclk_in_sr); 2255 } 2256 return 0; 2257 } 2258 2259 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev) 2260 { 2261 struct kv_power_info *pi = kv_get_pi(rdev); 2262 u32 i; 2263 bool force_high; 2264 struct radeon_clock_and_voltage_limits *max_limits = 2265 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2266 u32 mclk = max_limits->mclk; 2267 2268 if (pi->lowest_valid > pi->highest_valid) 2269 return -EINVAL; 2270 2271 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2272 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2273 pi->graphics_level[i].GnbSlow = 1; 2274 pi->graphics_level[i].ForceNbPs1 = 0; 2275 pi->graphics_level[i].UpH = 0; 2276 } 2277 2278 if (!pi->sys_info.nb_dpm_enable) 2279 return 0; 2280 2281 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || 2282 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); 2283 2284 if (force_high) { 2285 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2286 pi->graphics_level[i].GnbSlow = 0; 2287 } else { 2288 if (pi->battery_state) 2289 pi->graphics_level[0].ForceNbPs1 = 1; 2290 2291 pi->graphics_level[1].GnbSlow = 0; 2292 pi->graphics_level[2].GnbSlow = 0; 2293 pi->graphics_level[3].GnbSlow = 0; 2294 pi->graphics_level[4].GnbSlow = 0; 2295 } 2296 } else { 2297 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2298 pi->graphics_level[i].GnbSlow = 1; 2299 pi->graphics_level[i].ForceNbPs1 = 0; 2300 pi->graphics_level[i].UpH = 0; 2301 } 2302 2303 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { 2304 pi->graphics_level[pi->lowest_valid].UpH = 0x28; 2305 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; 2306 if (pi->lowest_valid != pi->highest_valid) 2307 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; 2308 } 2309 } 2310 return 0; 2311 } 2312 2313 static int kv_calculate_dpm_settings(struct radeon_device *rdev) 2314 { 2315 struct kv_power_info *pi = kv_get_pi(rdev); 2316 u32 i; 2317 2318 if (pi->lowest_valid > pi->highest_valid) 2319 return -EINVAL; 2320 2321 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2322 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; 2323 2324 return 0; 2325 } 2326 2327 static void kv_init_graphics_levels(struct radeon_device *rdev) 2328 { 2329 struct kv_power_info *pi = kv_get_pi(rdev); 2330 u32 i; 2331 struct radeon_clock_voltage_dependency_table *table = 2332 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2333 2334 if (table && table->count) { 2335 u32 vid_2bit; 2336 2337 pi->graphics_dpm_level_count = 0; 2338 for (i = 0; i < table->count; i++) { 2339 if (pi->high_voltage_t && 2340 (pi->high_voltage_t < 2341 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v))) 2342 break; 2343 2344 kv_set_divider_value(rdev, i, table->entries[i].clk); 2345 vid_2bit = kv_convert_vid7_to_vid2(rdev, 2346 &pi->sys_info.vid_mapping_table, 2347 table->entries[i].v); 2348 kv_set_vid(rdev, i, vid_2bit); 2349 kv_set_at(rdev, i, pi->at[i]); 2350 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2351 pi->graphics_dpm_level_count++; 2352 } 2353 } else { 2354 struct sumo_sclk_voltage_mapping_table *table = 2355 &pi->sys_info.sclk_voltage_mapping_table; 2356 2357 pi->graphics_dpm_level_count = 0; 2358 for (i = 0; i < table->num_max_dpm_entries; i++) { 2359 if (pi->high_voltage_t && 2360 pi->high_voltage_t < 2361 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit)) 2362 break; 2363 2364 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency); 2365 kv_set_vid(rdev, i, table->entries[i].vid_2bit); 2366 kv_set_at(rdev, i, pi->at[i]); 2367 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2368 pi->graphics_dpm_level_count++; 2369 } 2370 } 2371 2372 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 2373 kv_dpm_power_level_enable(rdev, i, false); 2374 } 2375 2376 static void kv_enable_new_levels(struct radeon_device *rdev) 2377 { 2378 struct kv_power_info *pi = kv_get_pi(rdev); 2379 u32 i; 2380 2381 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2382 if (i >= pi->lowest_valid && i <= pi->highest_valid) 2383 kv_dpm_power_level_enable(rdev, i, true); 2384 } 2385 } 2386 2387 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level) 2388 { 2389 u32 new_mask = (1 << level); 2390 2391 return kv_send_msg_to_smc_with_parameter(rdev, 2392 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2393 new_mask); 2394 } 2395 2396 static int kv_set_enabled_levels(struct radeon_device *rdev) 2397 { 2398 struct kv_power_info *pi = kv_get_pi(rdev); 2399 u32 i, new_mask = 0; 2400 2401 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2402 new_mask |= (1 << i); 2403 2404 return kv_send_msg_to_smc_with_parameter(rdev, 2405 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2406 new_mask); 2407 } 2408 2409 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 2410 struct radeon_ps *new_rps) 2411 { 2412 struct kv_ps *new_ps = kv_get_ps(new_rps); 2413 struct kv_power_info *pi = kv_get_pi(rdev); 2414 u32 nbdpmconfig1; 2415 2416 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2417 return; 2418 2419 if (pi->sys_info.nb_dpm_enable) { 2420 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); 2421 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | 2422 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK); 2423 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) | 2424 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) | 2425 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) | 2426 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi)); 2427 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); 2428 } 2429 } 2430 2431 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 2432 int min_temp, int max_temp) 2433 { 2434 int low_temp = 0 * 1000; 2435 int high_temp = 255 * 1000; 2436 u32 tmp; 2437 2438 if (low_temp < min_temp) 2439 low_temp = min_temp; 2440 if (high_temp > max_temp) 2441 high_temp = max_temp; 2442 if (high_temp < low_temp) { 2443 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 2444 return -EINVAL; 2445 } 2446 2447 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); 2448 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK); 2449 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) | 2450 DIG_THERM_INTL(49 + (low_temp / 1000))); 2451 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); 2452 2453 rdev->pm.dpm.thermal.min_temp = low_temp; 2454 rdev->pm.dpm.thermal.max_temp = high_temp; 2455 2456 return 0; 2457 } 2458 2459 union igp_info { 2460 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 2461 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 2462 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 2463 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 2464 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 2465 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 2466 }; 2467 2468 static int kv_parse_sys_info_table(struct radeon_device *rdev) 2469 { 2470 struct kv_power_info *pi = kv_get_pi(rdev); 2471 struct radeon_mode_info *mode_info = &rdev->mode_info; 2472 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 2473 union igp_info *igp_info; 2474 u8 frev, crev; 2475 u16 data_offset; 2476 int i; 2477 2478 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2479 &frev, &crev, &data_offset)) { 2480 igp_info = (union igp_info *)(mode_info->atom_context->bios + 2481 data_offset); 2482 2483 if (crev != 8) { 2484 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 2485 return -EINVAL; 2486 } 2487 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); 2488 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); 2489 pi->sys_info.bootup_nb_voltage_index = 2490 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); 2491 if (igp_info->info_8.ucHtcTmpLmt == 0) 2492 pi->sys_info.htc_tmp_lmt = 203; 2493 else 2494 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; 2495 if (igp_info->info_8.ucHtcHystLmt == 0) 2496 pi->sys_info.htc_hyst_lmt = 5; 2497 else 2498 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; 2499 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 2500 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 2501 } 2502 2503 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) 2504 pi->sys_info.nb_dpm_enable = true; 2505 else 2506 pi->sys_info.nb_dpm_enable = false; 2507 2508 for (i = 0; i < KV_NUM_NBPSTATES; i++) { 2509 pi->sys_info.nbp_memory_clock[i] = 2510 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); 2511 pi->sys_info.nbp_n_clock[i] = 2512 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); 2513 } 2514 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & 2515 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) 2516 pi->caps_enable_dfs_bypass = true; 2517 2518 sumo_construct_sclk_voltage_mapping_table(rdev, 2519 &pi->sys_info.sclk_voltage_mapping_table, 2520 igp_info->info_8.sAvail_SCLK); 2521 2522 sumo_construct_vid_mapping_table(rdev, 2523 &pi->sys_info.vid_mapping_table, 2524 igp_info->info_8.sAvail_SCLK); 2525 2526 kv_construct_max_power_limits_table(rdev, 2527 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 2528 } 2529 return 0; 2530 } 2531 2532 union power_info { 2533 struct _ATOM_POWERPLAY_INFO info; 2534 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2535 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2536 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2537 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2538 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2539 }; 2540 2541 union pplib_clock_info { 2542 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2543 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2544 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2545 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2546 }; 2547 2548 union pplib_power_state { 2549 struct _ATOM_PPLIB_STATE v1; 2550 struct _ATOM_PPLIB_STATE_V2 v2; 2551 }; 2552 2553 static void kv_patch_boot_state(struct radeon_device *rdev, 2554 struct kv_ps *ps) 2555 { 2556 struct kv_power_info *pi = kv_get_pi(rdev); 2557 2558 ps->num_levels = 1; 2559 ps->levels[0] = pi->boot_pl; 2560 } 2561 2562 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev, 2563 struct radeon_ps *rps, 2564 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 2565 u8 table_rev) 2566 { 2567 struct kv_ps *ps = kv_get_ps(rps); 2568 2569 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2570 rps->class = le16_to_cpu(non_clock_info->usClassification); 2571 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 2572 2573 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 2574 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 2575 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 2576 } else { 2577 rps->vclk = 0; 2578 rps->dclk = 0; 2579 } 2580 2581 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2582 rdev->pm.dpm.boot_ps = rps; 2583 kv_patch_boot_state(rdev, ps); 2584 } 2585 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 2586 rdev->pm.dpm.uvd_ps = rps; 2587 } 2588 2589 static void kv_parse_pplib_clock_info(struct radeon_device *rdev, 2590 struct radeon_ps *rps, int index, 2591 union pplib_clock_info *clock_info) 2592 { 2593 struct kv_power_info *pi = kv_get_pi(rdev); 2594 struct kv_ps *ps = kv_get_ps(rps); 2595 struct kv_pl *pl = &ps->levels[index]; 2596 u32 sclk; 2597 2598 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2599 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2600 pl->sclk = sclk; 2601 pl->vddc_index = clock_info->sumo.vddcIndex; 2602 2603 ps->num_levels = index + 1; 2604 2605 if (pi->caps_sclk_ds) { 2606 pl->ds_divider_index = 5; 2607 pl->ss_divider_index = 5; 2608 } 2609 } 2610 2611 static int kv_parse_power_table(struct radeon_device *rdev) 2612 { 2613 struct radeon_mode_info *mode_info = &rdev->mode_info; 2614 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2615 union pplib_power_state *power_state; 2616 int i, j, k, non_clock_array_index, clock_array_index; 2617 union pplib_clock_info *clock_info; 2618 struct _StateArray *state_array; 2619 struct _ClockInfoArray *clock_info_array; 2620 struct _NonClockInfoArray *non_clock_info_array; 2621 union power_info *power_info; 2622 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2623 u16 data_offset; 2624 u8 frev, crev; 2625 u8 *power_state_offset; 2626 struct kv_ps *ps; 2627 2628 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2629 &frev, &crev, &data_offset)) 2630 return -EINVAL; 2631 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2632 2633 state_array = (struct _StateArray *) 2634 (mode_info->atom_context->bios + data_offset + 2635 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2636 clock_info_array = (struct _ClockInfoArray *) 2637 (mode_info->atom_context->bios + data_offset + 2638 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2639 non_clock_info_array = (struct _NonClockInfoArray *) 2640 (mode_info->atom_context->bios + data_offset + 2641 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2642 2643 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 2644 state_array->ucNumEntries, GFP_KERNEL); 2645 if (!rdev->pm.dpm.ps) 2646 return -ENOMEM; 2647 power_state_offset = (u8 *)state_array->states; 2648 for (i = 0; i < state_array->ucNumEntries; i++) { 2649 u8 *idx; 2650 power_state = (union pplib_power_state *)power_state_offset; 2651 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2652 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2653 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2654 if (!rdev->pm.power_state[i].clock_info) 2655 return -EINVAL; 2656 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); 2657 if (ps == NULL) { 2658 kfree(rdev->pm.dpm.ps); 2659 return -ENOMEM; 2660 } 2661 rdev->pm.dpm.ps[i].ps_priv = ps; 2662 k = 0; 2663 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2664 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2665 clock_array_index = idx[j]; 2666 if (clock_array_index >= clock_info_array->ucNumEntries) 2667 continue; 2668 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 2669 break; 2670 clock_info = (union pplib_clock_info *) 2671 ((u8 *)&clock_info_array->clockInfo[0] + 2672 (clock_array_index * clock_info_array->ucEntrySize)); 2673 kv_parse_pplib_clock_info(rdev, 2674 &rdev->pm.dpm.ps[i], k, 2675 clock_info); 2676 k++; 2677 } 2678 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 2679 non_clock_info, 2680 non_clock_info_array->ucEntrySize); 2681 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2682 } 2683 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 2684 2685 /* fill in the vce power states */ 2686 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 2687 u32 sclk; 2688 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 2689 clock_info = (union pplib_clock_info *) 2690 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2691 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2692 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2693 rdev->pm.dpm.vce_states[i].sclk = sclk; 2694 rdev->pm.dpm.vce_states[i].mclk = 0; 2695 } 2696 2697 return 0; 2698 } 2699 2700 int kv_dpm_init(struct radeon_device *rdev) 2701 { 2702 struct kv_power_info *pi; 2703 int ret, i; 2704 2705 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); 2706 if (pi == NULL) 2707 return -ENOMEM; 2708 rdev->pm.dpm.priv = pi; 2709 2710 ret = r600_get_platform_caps(rdev); 2711 if (ret) 2712 return ret; 2713 2714 ret = r600_parse_extended_power_table(rdev); 2715 if (ret) 2716 return ret; 2717 2718 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 2719 pi->at[i] = TRINITY_AT_DFLT; 2720 2721 pi->sram_end = SMC_RAM_END; 2722 2723 /* Enabling nb dpm on an asrock system prevents dpm from working */ 2724 if (rdev->pdev->subsystem_vendor == 0x1849) 2725 pi->enable_nb_dpm = false; 2726 else 2727 pi->enable_nb_dpm = true; 2728 2729 pi->caps_power_containment = true; 2730 pi->caps_cac = true; 2731 pi->enable_didt = false; 2732 if (pi->enable_didt) { 2733 pi->caps_sq_ramping = true; 2734 pi->caps_db_ramping = true; 2735 pi->caps_td_ramping = true; 2736 pi->caps_tcp_ramping = true; 2737 } 2738 2739 pi->caps_sclk_ds = true; 2740 pi->enable_auto_thermal_throttling = true; 2741 pi->disable_nb_ps3_in_battery = false; 2742 if (radeon_bapm == -1) { 2743 /* There are stability issues reported on with 2744 * bapm enabled on an asrock system. 2745 */ 2746 if (rdev->pdev->subsystem_vendor == 0x1849) 2747 pi->bapm_enable = false; 2748 else 2749 pi->bapm_enable = true; 2750 } else if (radeon_bapm == 0) { 2751 pi->bapm_enable = false; 2752 } else { 2753 pi->bapm_enable = true; 2754 } 2755 pi->voltage_drop_t = 0; 2756 pi->caps_sclk_throttle_low_notification = false; 2757 pi->caps_fps = false; /* true? */ 2758 pi->caps_uvd_pg = true; 2759 pi->caps_uvd_dpm = true; 2760 pi->caps_vce_pg = false; /* XXX true */ 2761 pi->caps_samu_pg = false; 2762 pi->caps_acp_pg = false; 2763 pi->caps_stable_p_state = false; 2764 2765 ret = kv_parse_sys_info_table(rdev); 2766 if (ret) 2767 return ret; 2768 2769 kv_patch_voltage_values(rdev); 2770 kv_construct_boot_state(rdev); 2771 2772 ret = kv_parse_power_table(rdev); 2773 if (ret) 2774 return ret; 2775 2776 pi->enable_dpm = true; 2777 2778 return 0; 2779 } 2780 2781 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 2782 struct seq_file *m) 2783 { 2784 struct kv_power_info *pi = kv_get_pi(rdev); 2785 u32 current_index = 2786 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> 2787 CURR_SCLK_INDEX_SHIFT; 2788 u32 sclk, tmp; 2789 u16 vddc; 2790 2791 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2792 seq_printf(m, "invalid dpm profile %d\n", current_index); 2793 } else { 2794 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2795 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2796 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT; 2797 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp); 2798 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); 2799 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); 2800 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2801 current_index, sclk, vddc); 2802 } 2803 } 2804 2805 void kv_dpm_print_power_state(struct radeon_device *rdev, 2806 struct radeon_ps *rps) 2807 { 2808 int i; 2809 struct kv_ps *ps = kv_get_ps(rps); 2810 2811 r600_dpm_print_class_info(rps->class, rps->class2); 2812 r600_dpm_print_cap_info(rps->caps); 2813 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2814 for (i = 0; i < ps->num_levels; i++) { 2815 struct kv_pl *pl = &ps->levels[i]; 2816 printk("\t\tpower level %d sclk: %u vddc: %u\n", 2817 i, pl->sclk, 2818 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index)); 2819 } 2820 r600_dpm_print_ps_status(rdev, rps); 2821 } 2822 2823 void kv_dpm_fini(struct radeon_device *rdev) 2824 { 2825 int i; 2826 2827 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 2828 kfree(rdev->pm.dpm.ps[i].ps_priv); 2829 } 2830 kfree(rdev->pm.dpm.ps); 2831 kfree(rdev->pm.dpm.priv); 2832 r600_free_extended_power_table(rdev); 2833 } 2834 2835 void kv_dpm_display_configuration_changed(struct radeon_device *rdev) 2836 { 2837 2838 } 2839 2840 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low) 2841 { 2842 struct kv_power_info *pi = kv_get_pi(rdev); 2843 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2844 2845 if (low) 2846 return requested_state->levels[0].sclk; 2847 else 2848 return requested_state->levels[requested_state->num_levels - 1].sclk; 2849 } 2850 2851 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low) 2852 { 2853 struct kv_power_info *pi = kv_get_pi(rdev); 2854 2855 return pi->sys_info.bootup_uma_clk; 2856 } 2857