1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "cikd.h" 28 #include "r600_dpm.h" 29 #include "kv_dpm.h" 30 #include "radeon_asic.h" 31 #include <linux/seq_file.h> 32 33 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 34 #define KV_MINIMUM_ENGINE_CLOCK 800 35 #define SMC_RAM_END 0x40000 36 37 static int kv_enable_nb_dpm(struct radeon_device *rdev, 38 bool enable); 39 static void kv_init_graphics_levels(struct radeon_device *rdev); 40 static int kv_calculate_ds_divider(struct radeon_device *rdev); 41 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev); 42 static int kv_calculate_dpm_settings(struct radeon_device *rdev); 43 static void kv_enable_new_levels(struct radeon_device *rdev); 44 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 45 struct radeon_ps *new_rps); 46 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level); 47 static int kv_set_enabled_levels(struct radeon_device *rdev); 48 static int kv_force_dpm_highest(struct radeon_device *rdev); 49 static int kv_force_dpm_lowest(struct radeon_device *rdev); 50 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 51 struct radeon_ps *new_rps, 52 struct radeon_ps *old_rps); 53 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 54 int min_temp, int max_temp); 55 static int kv_init_fps_limits(struct radeon_device *rdev); 56 57 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate); 58 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate); 59 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate); 60 61 #if 0 /* unused */ 62 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 63 { 64 { 0, 4, 1 }, 65 { 1, 4, 1 }, 66 { 2, 5, 1 }, 67 { 3, 4, 2 }, 68 { 4, 1, 1 }, 69 { 5, 5, 2 }, 70 { 6, 6, 1 }, 71 { 7, 9, 2 }, 72 { 0xffffffff } 73 }; 74 75 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = 76 { 77 { 0, 4, 1 }, 78 { 0xffffffff } 79 }; 80 81 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = 82 { 83 { 0, 4, 1 }, 84 { 0xffffffff } 85 }; 86 87 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = 88 { 89 { 0, 4, 1 }, 90 { 0xffffffff } 91 }; 92 93 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = 94 { 95 { 0, 4, 1 }, 96 { 0xffffffff } 97 }; 98 99 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = 100 { 101 { 0, 4, 1 }, 102 { 1, 4, 1 }, 103 { 2, 5, 1 }, 104 { 3, 4, 1 }, 105 { 4, 1, 1 }, 106 { 5, 5, 1 }, 107 { 6, 6, 1 }, 108 { 7, 9, 1 }, 109 { 8, 4, 1 }, 110 { 9, 2, 1 }, 111 { 10, 3, 1 }, 112 { 11, 6, 1 }, 113 { 12, 8, 2 }, 114 { 13, 1, 1 }, 115 { 14, 2, 1 }, 116 { 15, 3, 1 }, 117 { 16, 1, 1 }, 118 { 17, 4, 1 }, 119 { 18, 3, 1 }, 120 { 19, 1, 1 }, 121 { 20, 8, 1 }, 122 { 21, 5, 1 }, 123 { 22, 1, 1 }, 124 { 23, 1, 1 }, 125 { 24, 4, 1 }, 126 { 27, 6, 1 }, 127 { 28, 1, 1 }, 128 { 0xffffffff } 129 }; 130 131 static const struct kv_lcac_config_reg sx0_cac_config_reg[] = 132 { 133 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 134 }; 135 136 static const struct kv_lcac_config_reg mc0_cac_config_reg[] = 137 { 138 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 139 }; 140 141 static const struct kv_lcac_config_reg mc1_cac_config_reg[] = 142 { 143 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 144 }; 145 146 static const struct kv_lcac_config_reg mc2_cac_config_reg[] = 147 { 148 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 149 }; 150 151 static const struct kv_lcac_config_reg mc3_cac_config_reg[] = 152 { 153 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 154 }; 155 156 static const struct kv_lcac_config_reg cpl_cac_config_reg[] = 157 { 158 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 159 }; 160 #endif 161 162 static const struct kv_pt_config_reg didt_config_kv[] = 163 { 164 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 165 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 166 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 167 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 168 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 169 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 170 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 171 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 172 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 173 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 174 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 175 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 176 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 177 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 178 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 179 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 180 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 181 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 182 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 183 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 184 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 185 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 186 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 187 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 188 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 189 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 190 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 191 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 192 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 193 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 194 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 195 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 196 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 197 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 198 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 199 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 200 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 201 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 202 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 203 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 204 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 205 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 206 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 207 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 208 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 209 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 210 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 211 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 212 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 213 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 214 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 215 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 216 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 217 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 218 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 219 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 220 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 221 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 222 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 223 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 224 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 225 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 226 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 227 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 228 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 229 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 230 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 231 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 232 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 233 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 234 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 235 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 236 { 0xFFFFFFFF } 237 }; 238 239 static struct kv_ps *kv_get_ps(struct radeon_ps *rps) 240 { 241 struct kv_ps *ps = rps->ps_priv; 242 243 return ps; 244 } 245 246 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev) 247 { 248 struct kv_power_info *pi = rdev->pm.dpm.priv; 249 250 return pi; 251 } 252 253 #if 0 254 static void kv_program_local_cac_table(struct radeon_device *rdev, 255 const struct kv_lcac_config_values *local_cac_table, 256 const struct kv_lcac_config_reg *local_cac_reg) 257 { 258 u32 i, count, data; 259 const struct kv_lcac_config_values *values = local_cac_table; 260 261 while (values->block_id != 0xffffffff) { 262 count = values->signal_id; 263 for (i = 0; i < count; i++) { 264 data = ((values->block_id << local_cac_reg->block_shift) & 265 local_cac_reg->block_mask); 266 data |= ((i << local_cac_reg->signal_shift) & 267 local_cac_reg->signal_mask); 268 data |= ((values->t << local_cac_reg->t_shift) & 269 local_cac_reg->t_mask); 270 data |= ((1 << local_cac_reg->enable_shift) & 271 local_cac_reg->enable_mask); 272 WREG32_SMC(local_cac_reg->cntl, data); 273 } 274 values++; 275 } 276 } 277 #endif 278 279 static int kv_program_pt_config_registers(struct radeon_device *rdev, 280 const struct kv_pt_config_reg *cac_config_regs) 281 { 282 const struct kv_pt_config_reg *config_regs = cac_config_regs; 283 u32 data; 284 u32 cache = 0; 285 286 if (config_regs == NULL) 287 return -EINVAL; 288 289 while (config_regs->offset != 0xFFFFFFFF) { 290 if (config_regs->type == KV_CONFIGREG_CACHE) { 291 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 292 } else { 293 switch (config_regs->type) { 294 case KV_CONFIGREG_SMC_IND: 295 data = RREG32_SMC(config_regs->offset); 296 break; 297 case KV_CONFIGREG_DIDT_IND: 298 data = RREG32_DIDT(config_regs->offset); 299 break; 300 default: 301 data = RREG32(config_regs->offset << 2); 302 break; 303 } 304 305 data &= ~config_regs->mask; 306 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 307 data |= cache; 308 cache = 0; 309 310 switch (config_regs->type) { 311 case KV_CONFIGREG_SMC_IND: 312 WREG32_SMC(config_regs->offset, data); 313 break; 314 case KV_CONFIGREG_DIDT_IND: 315 WREG32_DIDT(config_regs->offset, data); 316 break; 317 default: 318 WREG32(config_regs->offset << 2, data); 319 break; 320 } 321 } 322 config_regs++; 323 } 324 325 return 0; 326 } 327 328 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable) 329 { 330 struct kv_power_info *pi = kv_get_pi(rdev); 331 u32 data; 332 333 if (pi->caps_sq_ramping) { 334 data = RREG32_DIDT(DIDT_SQ_CTRL0); 335 if (enable) 336 data |= DIDT_CTRL_EN; 337 else 338 data &= ~DIDT_CTRL_EN; 339 WREG32_DIDT(DIDT_SQ_CTRL0, data); 340 } 341 342 if (pi->caps_db_ramping) { 343 data = RREG32_DIDT(DIDT_DB_CTRL0); 344 if (enable) 345 data |= DIDT_CTRL_EN; 346 else 347 data &= ~DIDT_CTRL_EN; 348 WREG32_DIDT(DIDT_DB_CTRL0, data); 349 } 350 351 if (pi->caps_td_ramping) { 352 data = RREG32_DIDT(DIDT_TD_CTRL0); 353 if (enable) 354 data |= DIDT_CTRL_EN; 355 else 356 data &= ~DIDT_CTRL_EN; 357 WREG32_DIDT(DIDT_TD_CTRL0, data); 358 } 359 360 if (pi->caps_tcp_ramping) { 361 data = RREG32_DIDT(DIDT_TCP_CTRL0); 362 if (enable) 363 data |= DIDT_CTRL_EN; 364 else 365 data &= ~DIDT_CTRL_EN; 366 WREG32_DIDT(DIDT_TCP_CTRL0, data); 367 } 368 } 369 370 static int kv_enable_didt(struct radeon_device *rdev, bool enable) 371 { 372 struct kv_power_info *pi = kv_get_pi(rdev); 373 int ret; 374 375 if (pi->caps_sq_ramping || 376 pi->caps_db_ramping || 377 pi->caps_td_ramping || 378 pi->caps_tcp_ramping) { 379 cik_enter_rlc_safe_mode(rdev); 380 381 if (enable) { 382 ret = kv_program_pt_config_registers(rdev, didt_config_kv); 383 if (ret) { 384 cik_exit_rlc_safe_mode(rdev); 385 return ret; 386 } 387 } 388 389 kv_do_enable_didt(rdev, enable); 390 391 cik_exit_rlc_safe_mode(rdev); 392 } 393 394 return 0; 395 } 396 397 #if 0 398 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev) 399 { 400 struct kv_power_info *pi = kv_get_pi(rdev); 401 402 if (pi->caps_cac) { 403 WREG32_SMC(LCAC_SX0_OVR_SEL, 0); 404 WREG32_SMC(LCAC_SX0_OVR_VAL, 0); 405 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg); 406 407 WREG32_SMC(LCAC_MC0_OVR_SEL, 0); 408 WREG32_SMC(LCAC_MC0_OVR_VAL, 0); 409 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); 410 411 WREG32_SMC(LCAC_MC1_OVR_SEL, 0); 412 WREG32_SMC(LCAC_MC1_OVR_VAL, 0); 413 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); 414 415 WREG32_SMC(LCAC_MC2_OVR_SEL, 0); 416 WREG32_SMC(LCAC_MC2_OVR_VAL, 0); 417 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); 418 419 WREG32_SMC(LCAC_MC3_OVR_SEL, 0); 420 WREG32_SMC(LCAC_MC3_OVR_VAL, 0); 421 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); 422 423 WREG32_SMC(LCAC_CPL_OVR_SEL, 0); 424 WREG32_SMC(LCAC_CPL_OVR_VAL, 0); 425 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); 426 } 427 } 428 #endif 429 430 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable) 431 { 432 struct kv_power_info *pi = kv_get_pi(rdev); 433 int ret = 0; 434 435 if (pi->caps_cac) { 436 if (enable) { 437 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac); 438 if (ret) 439 pi->cac_enabled = false; 440 else 441 pi->cac_enabled = true; 442 } else if (pi->cac_enabled) { 443 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac); 444 pi->cac_enabled = false; 445 } 446 } 447 448 return ret; 449 } 450 451 static int kv_process_firmware_header(struct radeon_device *rdev) 452 { 453 struct kv_power_info *pi = kv_get_pi(rdev); 454 u32 tmp; 455 int ret; 456 457 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 458 offsetof(SMU7_Firmware_Header, DpmTable), 459 &tmp, pi->sram_end); 460 461 if (ret == 0) 462 pi->dpm_table_start = tmp; 463 464 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + 465 offsetof(SMU7_Firmware_Header, SoftRegisters), 466 &tmp, pi->sram_end); 467 468 if (ret == 0) 469 pi->soft_regs_start = tmp; 470 471 return ret; 472 } 473 474 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev) 475 { 476 struct kv_power_info *pi = kv_get_pi(rdev); 477 int ret; 478 479 pi->graphics_voltage_change_enable = 1; 480 481 ret = kv_copy_bytes_to_smc(rdev, 482 pi->dpm_table_start + 483 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), 484 &pi->graphics_voltage_change_enable, 485 sizeof(u8), pi->sram_end); 486 487 return ret; 488 } 489 490 static int kv_set_dpm_interval(struct radeon_device *rdev) 491 { 492 struct kv_power_info *pi = kv_get_pi(rdev); 493 int ret; 494 495 pi->graphics_interval = 1; 496 497 ret = kv_copy_bytes_to_smc(rdev, 498 pi->dpm_table_start + 499 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), 500 &pi->graphics_interval, 501 sizeof(u8), pi->sram_end); 502 503 return ret; 504 } 505 506 static int kv_set_dpm_boot_state(struct radeon_device *rdev) 507 { 508 struct kv_power_info *pi = kv_get_pi(rdev); 509 int ret; 510 511 ret = kv_copy_bytes_to_smc(rdev, 512 pi->dpm_table_start + 513 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), 514 &pi->graphics_boot_level, 515 sizeof(u8), pi->sram_end); 516 517 return ret; 518 } 519 520 static void kv_program_vc(struct radeon_device *rdev) 521 { 522 WREG32_SMC(CG_FTV_0, 0x3FFFC100); 523 } 524 525 static void kv_clear_vc(struct radeon_device *rdev) 526 { 527 WREG32_SMC(CG_FTV_0, 0); 528 } 529 530 static int kv_set_divider_value(struct radeon_device *rdev, 531 u32 index, u32 sclk) 532 { 533 struct kv_power_info *pi = kv_get_pi(rdev); 534 struct atom_clock_dividers dividers; 535 int ret; 536 537 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 538 sclk, false, ÷rs); 539 if (ret) 540 return ret; 541 542 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; 543 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); 544 545 return 0; 546 } 547 548 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev, 549 struct sumo_vid_mapping_table *vid_mapping_table, 550 u32 vid_2bit) 551 { 552 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 553 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 554 u32 i; 555 556 if (vddc_sclk_table && vddc_sclk_table->count) { 557 if (vid_2bit < vddc_sclk_table->count) 558 return vddc_sclk_table->entries[vid_2bit].v; 559 else 560 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; 561 } else { 562 for (i = 0; i < vid_mapping_table->num_entries; i++) { 563 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 564 return vid_mapping_table->entries[i].vid_7bit; 565 } 566 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 567 } 568 } 569 570 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev, 571 struct sumo_vid_mapping_table *vid_mapping_table, 572 u32 vid_7bit) 573 { 574 struct radeon_clock_voltage_dependency_table *vddc_sclk_table = 575 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 576 u32 i; 577 578 if (vddc_sclk_table && vddc_sclk_table->count) { 579 for (i = 0; i < vddc_sclk_table->count; i++) { 580 if (vddc_sclk_table->entries[i].v == vid_7bit) 581 return i; 582 } 583 return vddc_sclk_table->count - 1; 584 } else { 585 for (i = 0; i < vid_mapping_table->num_entries; i++) { 586 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 587 return vid_mapping_table->entries[i].vid_2bit; 588 } 589 590 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 591 } 592 } 593 594 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev, 595 u16 voltage) 596 { 597 return 6200 - (voltage * 25); 598 } 599 600 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev, 601 u32 vid_2bit) 602 { 603 struct kv_power_info *pi = kv_get_pi(rdev); 604 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev, 605 &pi->sys_info.vid_mapping_table, 606 vid_2bit); 607 608 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit); 609 } 610 611 612 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid) 613 { 614 struct kv_power_info *pi = kv_get_pi(rdev); 615 616 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; 617 pi->graphics_level[index].MinVddNb = 618 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid)); 619 620 return 0; 621 } 622 623 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at) 624 { 625 struct kv_power_info *pi = kv_get_pi(rdev); 626 627 pi->graphics_level[index].AT = cpu_to_be16((u16)at); 628 629 return 0; 630 } 631 632 static void kv_dpm_power_level_enable(struct radeon_device *rdev, 633 u32 index, bool enable) 634 { 635 struct kv_power_info *pi = kv_get_pi(rdev); 636 637 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; 638 } 639 640 static void kv_start_dpm(struct radeon_device *rdev) 641 { 642 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 643 644 tmp |= GLOBAL_PWRMGT_EN; 645 WREG32_SMC(GENERAL_PWRMGT, tmp); 646 647 kv_smc_dpm_enable(rdev, true); 648 } 649 650 static void kv_stop_dpm(struct radeon_device *rdev) 651 { 652 kv_smc_dpm_enable(rdev, false); 653 } 654 655 static void kv_start_am(struct radeon_device *rdev) 656 { 657 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 658 659 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 660 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN; 661 662 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 663 } 664 665 static void kv_reset_am(struct radeon_device *rdev) 666 { 667 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 668 669 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 670 671 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 672 } 673 674 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze) 675 { 676 return kv_notify_message_to_smu(rdev, freeze ? 677 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); 678 } 679 680 static int kv_force_lowest_valid(struct radeon_device *rdev) 681 { 682 return kv_force_dpm_lowest(rdev); 683 } 684 685 static int kv_unforce_levels(struct radeon_device *rdev) 686 { 687 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 688 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); 689 else 690 return kv_set_enabled_levels(rdev); 691 } 692 693 static int kv_update_sclk_t(struct radeon_device *rdev) 694 { 695 struct kv_power_info *pi = kv_get_pi(rdev); 696 u32 low_sclk_interrupt_t = 0; 697 int ret = 0; 698 699 if (pi->caps_sclk_throttle_low_notification) { 700 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 701 702 ret = kv_copy_bytes_to_smc(rdev, 703 pi->dpm_table_start + 704 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), 705 (u8 *)&low_sclk_interrupt_t, 706 sizeof(u32), pi->sram_end); 707 } 708 return ret; 709 } 710 711 static int kv_program_bootup_state(struct radeon_device *rdev) 712 { 713 struct kv_power_info *pi = kv_get_pi(rdev); 714 u32 i; 715 struct radeon_clock_voltage_dependency_table *table = 716 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 717 718 if (table && table->count) { 719 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 720 if (table->entries[i].clk == pi->boot_pl.sclk) 721 break; 722 } 723 724 pi->graphics_boot_level = (u8)i; 725 kv_dpm_power_level_enable(rdev, i, true); 726 } else { 727 struct sumo_sclk_voltage_mapping_table *table = 728 &pi->sys_info.sclk_voltage_mapping_table; 729 730 if (table->num_max_dpm_entries == 0) 731 return -EINVAL; 732 733 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 734 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) 735 break; 736 } 737 738 pi->graphics_boot_level = (u8)i; 739 kv_dpm_power_level_enable(rdev, i, true); 740 } 741 return 0; 742 } 743 744 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev) 745 { 746 struct kv_power_info *pi = kv_get_pi(rdev); 747 int ret; 748 749 pi->graphics_therm_throttle_enable = 1; 750 751 ret = kv_copy_bytes_to_smc(rdev, 752 pi->dpm_table_start + 753 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), 754 &pi->graphics_therm_throttle_enable, 755 sizeof(u8), pi->sram_end); 756 757 return ret; 758 } 759 760 static int kv_upload_dpm_settings(struct radeon_device *rdev) 761 { 762 struct kv_power_info *pi = kv_get_pi(rdev); 763 int ret; 764 765 ret = kv_copy_bytes_to_smc(rdev, 766 pi->dpm_table_start + 767 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), 768 (u8 *)&pi->graphics_level, 769 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, 770 pi->sram_end); 771 772 if (ret) 773 return ret; 774 775 ret = kv_copy_bytes_to_smc(rdev, 776 pi->dpm_table_start + 777 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), 778 &pi->graphics_dpm_level_count, 779 sizeof(u8), pi->sram_end); 780 781 return ret; 782 } 783 784 static u32 kv_get_clock_difference(u32 a, u32 b) 785 { 786 return (a >= b) ? a - b : b - a; 787 } 788 789 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk) 790 { 791 struct kv_power_info *pi = kv_get_pi(rdev); 792 u32 value; 793 794 if (pi->caps_enable_dfs_bypass) { 795 if (kv_get_clock_difference(clk, 40000) < 200) 796 value = 3; 797 else if (kv_get_clock_difference(clk, 30000) < 200) 798 value = 2; 799 else if (kv_get_clock_difference(clk, 20000) < 200) 800 value = 7; 801 else if (kv_get_clock_difference(clk, 15000) < 200) 802 value = 6; 803 else if (kv_get_clock_difference(clk, 10000) < 200) 804 value = 8; 805 else 806 value = 0; 807 } else { 808 value = 0; 809 } 810 811 return value; 812 } 813 814 static int kv_populate_uvd_table(struct radeon_device *rdev) 815 { 816 struct kv_power_info *pi = kv_get_pi(rdev); 817 struct radeon_uvd_clock_voltage_dependency_table *table = 818 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 819 struct atom_clock_dividers dividers; 820 int ret; 821 u32 i; 822 823 if (table == NULL || table->count == 0) 824 return 0; 825 826 pi->uvd_level_count = 0; 827 for (i = 0; i < table->count; i++) { 828 if (pi->high_voltage_t && 829 (pi->high_voltage_t < table->entries[i].v)) 830 break; 831 832 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); 833 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); 834 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); 835 836 pi->uvd_level[i].VClkBypassCntl = 837 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); 838 pi->uvd_level[i].DClkBypassCntl = 839 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); 840 841 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 842 table->entries[i].vclk, false, ÷rs); 843 if (ret) 844 return ret; 845 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; 846 847 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 848 table->entries[i].dclk, false, ÷rs); 849 if (ret) 850 return ret; 851 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; 852 853 pi->uvd_level_count++; 854 } 855 856 ret = kv_copy_bytes_to_smc(rdev, 857 pi->dpm_table_start + 858 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), 859 (u8 *)&pi->uvd_level_count, 860 sizeof(u8), pi->sram_end); 861 if (ret) 862 return ret; 863 864 pi->uvd_interval = 1; 865 866 ret = kv_copy_bytes_to_smc(rdev, 867 pi->dpm_table_start + 868 offsetof(SMU7_Fusion_DpmTable, UVDInterval), 869 &pi->uvd_interval, 870 sizeof(u8), pi->sram_end); 871 if (ret) 872 return ret; 873 874 ret = kv_copy_bytes_to_smc(rdev, 875 pi->dpm_table_start + 876 offsetof(SMU7_Fusion_DpmTable, UvdLevel), 877 (u8 *)&pi->uvd_level, 878 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, 879 pi->sram_end); 880 881 return ret; 882 883 } 884 885 static int kv_populate_vce_table(struct radeon_device *rdev) 886 { 887 struct kv_power_info *pi = kv_get_pi(rdev); 888 int ret; 889 u32 i; 890 struct radeon_vce_clock_voltage_dependency_table *table = 891 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 892 struct atom_clock_dividers dividers; 893 894 if (table == NULL || table->count == 0) 895 return 0; 896 897 pi->vce_level_count = 0; 898 for (i = 0; i < table->count; i++) { 899 if (pi->high_voltage_t && 900 pi->high_voltage_t < table->entries[i].v) 901 break; 902 903 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); 904 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 905 906 pi->vce_level[i].ClkBypassCntl = 907 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); 908 909 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 910 table->entries[i].evclk, false, ÷rs); 911 if (ret) 912 return ret; 913 pi->vce_level[i].Divider = (u8)dividers.post_div; 914 915 pi->vce_level_count++; 916 } 917 918 ret = kv_copy_bytes_to_smc(rdev, 919 pi->dpm_table_start + 920 offsetof(SMU7_Fusion_DpmTable, VceLevelCount), 921 (u8 *)&pi->vce_level_count, 922 sizeof(u8), 923 pi->sram_end); 924 if (ret) 925 return ret; 926 927 pi->vce_interval = 1; 928 929 ret = kv_copy_bytes_to_smc(rdev, 930 pi->dpm_table_start + 931 offsetof(SMU7_Fusion_DpmTable, VCEInterval), 932 (u8 *)&pi->vce_interval, 933 sizeof(u8), 934 pi->sram_end); 935 if (ret) 936 return ret; 937 938 ret = kv_copy_bytes_to_smc(rdev, 939 pi->dpm_table_start + 940 offsetof(SMU7_Fusion_DpmTable, VceLevel), 941 (u8 *)&pi->vce_level, 942 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, 943 pi->sram_end); 944 945 return ret; 946 } 947 948 static int kv_populate_samu_table(struct radeon_device *rdev) 949 { 950 struct kv_power_info *pi = kv_get_pi(rdev); 951 struct radeon_clock_voltage_dependency_table *table = 952 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 953 struct atom_clock_dividers dividers; 954 int ret; 955 u32 i; 956 957 if (table == NULL || table->count == 0) 958 return 0; 959 960 pi->samu_level_count = 0; 961 for (i = 0; i < table->count; i++) { 962 if (pi->high_voltage_t && 963 pi->high_voltage_t < table->entries[i].v) 964 break; 965 966 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 967 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 968 969 pi->samu_level[i].ClkBypassCntl = 970 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk); 971 972 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 973 table->entries[i].clk, false, ÷rs); 974 if (ret) 975 return ret; 976 pi->samu_level[i].Divider = (u8)dividers.post_div; 977 978 pi->samu_level_count++; 979 } 980 981 ret = kv_copy_bytes_to_smc(rdev, 982 pi->dpm_table_start + 983 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), 984 (u8 *)&pi->samu_level_count, 985 sizeof(u8), 986 pi->sram_end); 987 if (ret) 988 return ret; 989 990 pi->samu_interval = 1; 991 992 ret = kv_copy_bytes_to_smc(rdev, 993 pi->dpm_table_start + 994 offsetof(SMU7_Fusion_DpmTable, SAMUInterval), 995 (u8 *)&pi->samu_interval, 996 sizeof(u8), 997 pi->sram_end); 998 if (ret) 999 return ret; 1000 1001 ret = kv_copy_bytes_to_smc(rdev, 1002 pi->dpm_table_start + 1003 offsetof(SMU7_Fusion_DpmTable, SamuLevel), 1004 (u8 *)&pi->samu_level, 1005 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, 1006 pi->sram_end); 1007 if (ret) 1008 return ret; 1009 1010 return ret; 1011 } 1012 1013 1014 static int kv_populate_acp_table(struct radeon_device *rdev) 1015 { 1016 struct kv_power_info *pi = kv_get_pi(rdev); 1017 struct radeon_clock_voltage_dependency_table *table = 1018 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1019 struct atom_clock_dividers dividers; 1020 int ret; 1021 u32 i; 1022 1023 if (table == NULL || table->count == 0) 1024 return 0; 1025 1026 pi->acp_level_count = 0; 1027 for (i = 0; i < table->count; i++) { 1028 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1029 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1030 1031 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1032 table->entries[i].clk, false, ÷rs); 1033 if (ret) 1034 return ret; 1035 pi->acp_level[i].Divider = (u8)dividers.post_div; 1036 1037 pi->acp_level_count++; 1038 } 1039 1040 ret = kv_copy_bytes_to_smc(rdev, 1041 pi->dpm_table_start + 1042 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), 1043 (u8 *)&pi->acp_level_count, 1044 sizeof(u8), 1045 pi->sram_end); 1046 if (ret) 1047 return ret; 1048 1049 pi->acp_interval = 1; 1050 1051 ret = kv_copy_bytes_to_smc(rdev, 1052 pi->dpm_table_start + 1053 offsetof(SMU7_Fusion_DpmTable, ACPInterval), 1054 (u8 *)&pi->acp_interval, 1055 sizeof(u8), 1056 pi->sram_end); 1057 if (ret) 1058 return ret; 1059 1060 ret = kv_copy_bytes_to_smc(rdev, 1061 pi->dpm_table_start + 1062 offsetof(SMU7_Fusion_DpmTable, AcpLevel), 1063 (u8 *)&pi->acp_level, 1064 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, 1065 pi->sram_end); 1066 if (ret) 1067 return ret; 1068 1069 return ret; 1070 } 1071 1072 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev) 1073 { 1074 struct kv_power_info *pi = kv_get_pi(rdev); 1075 u32 i; 1076 struct radeon_clock_voltage_dependency_table *table = 1077 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1078 1079 if (table && table->count) { 1080 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1081 if (pi->caps_enable_dfs_bypass) { 1082 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) 1083 pi->graphics_level[i].ClkBypassCntl = 3; 1084 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) 1085 pi->graphics_level[i].ClkBypassCntl = 2; 1086 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) 1087 pi->graphics_level[i].ClkBypassCntl = 7; 1088 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) 1089 pi->graphics_level[i].ClkBypassCntl = 6; 1090 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) 1091 pi->graphics_level[i].ClkBypassCntl = 8; 1092 else 1093 pi->graphics_level[i].ClkBypassCntl = 0; 1094 } else { 1095 pi->graphics_level[i].ClkBypassCntl = 0; 1096 } 1097 } 1098 } else { 1099 struct sumo_sclk_voltage_mapping_table *table = 1100 &pi->sys_info.sclk_voltage_mapping_table; 1101 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1102 if (pi->caps_enable_dfs_bypass) { 1103 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) 1104 pi->graphics_level[i].ClkBypassCntl = 3; 1105 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) 1106 pi->graphics_level[i].ClkBypassCntl = 2; 1107 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) 1108 pi->graphics_level[i].ClkBypassCntl = 7; 1109 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) 1110 pi->graphics_level[i].ClkBypassCntl = 6; 1111 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) 1112 pi->graphics_level[i].ClkBypassCntl = 8; 1113 else 1114 pi->graphics_level[i].ClkBypassCntl = 0; 1115 } else { 1116 pi->graphics_level[i].ClkBypassCntl = 0; 1117 } 1118 } 1119 } 1120 } 1121 1122 static int kv_enable_ulv(struct radeon_device *rdev, bool enable) 1123 { 1124 return kv_notify_message_to_smu(rdev, enable ? 1125 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); 1126 } 1127 1128 static void kv_reset_acp_boot_level(struct radeon_device *rdev) 1129 { 1130 struct kv_power_info *pi = kv_get_pi(rdev); 1131 1132 pi->acp_boot_level = 0xff; 1133 } 1134 1135 static void kv_update_current_ps(struct radeon_device *rdev, 1136 struct radeon_ps *rps) 1137 { 1138 struct kv_ps *new_ps = kv_get_ps(rps); 1139 struct kv_power_info *pi = kv_get_pi(rdev); 1140 1141 pi->current_rps = *rps; 1142 pi->current_ps = *new_ps; 1143 pi->current_rps.ps_priv = &pi->current_ps; 1144 } 1145 1146 static void kv_update_requested_ps(struct radeon_device *rdev, 1147 struct radeon_ps *rps) 1148 { 1149 struct kv_ps *new_ps = kv_get_ps(rps); 1150 struct kv_power_info *pi = kv_get_pi(rdev); 1151 1152 pi->requested_rps = *rps; 1153 pi->requested_ps = *new_ps; 1154 pi->requested_rps.ps_priv = &pi->requested_ps; 1155 } 1156 1157 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable) 1158 { 1159 struct kv_power_info *pi = kv_get_pi(rdev); 1160 int ret; 1161 1162 if (pi->bapm_enable) { 1163 ret = kv_smc_bapm_enable(rdev, enable); 1164 if (ret) 1165 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1166 } 1167 } 1168 1169 int kv_dpm_enable(struct radeon_device *rdev) 1170 { 1171 struct kv_power_info *pi = kv_get_pi(rdev); 1172 int ret; 1173 1174 ret = kv_process_firmware_header(rdev); 1175 if (ret) { 1176 DRM_ERROR("kv_process_firmware_header failed\n"); 1177 return ret; 1178 } 1179 kv_init_fps_limits(rdev); 1180 kv_init_graphics_levels(rdev); 1181 ret = kv_program_bootup_state(rdev); 1182 if (ret) { 1183 DRM_ERROR("kv_program_bootup_state failed\n"); 1184 return ret; 1185 } 1186 kv_calculate_dfs_bypass_settings(rdev); 1187 ret = kv_upload_dpm_settings(rdev); 1188 if (ret) { 1189 DRM_ERROR("kv_upload_dpm_settings failed\n"); 1190 return ret; 1191 } 1192 ret = kv_populate_uvd_table(rdev); 1193 if (ret) { 1194 DRM_ERROR("kv_populate_uvd_table failed\n"); 1195 return ret; 1196 } 1197 ret = kv_populate_vce_table(rdev); 1198 if (ret) { 1199 DRM_ERROR("kv_populate_vce_table failed\n"); 1200 return ret; 1201 } 1202 ret = kv_populate_samu_table(rdev); 1203 if (ret) { 1204 DRM_ERROR("kv_populate_samu_table failed\n"); 1205 return ret; 1206 } 1207 ret = kv_populate_acp_table(rdev); 1208 if (ret) { 1209 DRM_ERROR("kv_populate_acp_table failed\n"); 1210 return ret; 1211 } 1212 kv_program_vc(rdev); 1213 #if 0 1214 kv_initialize_hardware_cac_manager(rdev); 1215 #endif 1216 kv_start_am(rdev); 1217 if (pi->enable_auto_thermal_throttling) { 1218 ret = kv_enable_auto_thermal_throttling(rdev); 1219 if (ret) { 1220 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); 1221 return ret; 1222 } 1223 } 1224 ret = kv_enable_dpm_voltage_scaling(rdev); 1225 if (ret) { 1226 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); 1227 return ret; 1228 } 1229 ret = kv_set_dpm_interval(rdev); 1230 if (ret) { 1231 DRM_ERROR("kv_set_dpm_interval failed\n"); 1232 return ret; 1233 } 1234 ret = kv_set_dpm_boot_state(rdev); 1235 if (ret) { 1236 DRM_ERROR("kv_set_dpm_boot_state failed\n"); 1237 return ret; 1238 } 1239 ret = kv_enable_ulv(rdev, true); 1240 if (ret) { 1241 DRM_ERROR("kv_enable_ulv failed\n"); 1242 return ret; 1243 } 1244 kv_start_dpm(rdev); 1245 ret = kv_enable_didt(rdev, true); 1246 if (ret) { 1247 DRM_ERROR("kv_enable_didt failed\n"); 1248 return ret; 1249 } 1250 ret = kv_enable_smc_cac(rdev, true); 1251 if (ret) { 1252 DRM_ERROR("kv_enable_smc_cac failed\n"); 1253 return ret; 1254 } 1255 1256 kv_reset_acp_boot_level(rdev); 1257 1258 ret = kv_smc_bapm_enable(rdev, false); 1259 if (ret) { 1260 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1261 return ret; 1262 } 1263 1264 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1265 1266 return ret; 1267 } 1268 1269 int kv_dpm_late_enable(struct radeon_device *rdev) 1270 { 1271 int ret = 0; 1272 1273 if (rdev->irq.installed && 1274 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1275 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1276 if (ret) { 1277 DRM_ERROR("kv_set_thermal_temperature_range failed\n"); 1278 return ret; 1279 } 1280 rdev->irq.dpm_thermal = true; 1281 radeon_irq_set(rdev); 1282 } 1283 1284 /* powerdown unused blocks for now */ 1285 kv_dpm_powergate_acp(rdev, true); 1286 kv_dpm_powergate_samu(rdev, true); 1287 kv_dpm_powergate_vce(rdev, true); 1288 kv_dpm_powergate_uvd(rdev, true); 1289 1290 return ret; 1291 } 1292 1293 void kv_dpm_disable(struct radeon_device *rdev) 1294 { 1295 kv_smc_bapm_enable(rdev, false); 1296 1297 if (rdev->family == CHIP_MULLINS) 1298 kv_enable_nb_dpm(rdev, false); 1299 1300 /* powerup blocks */ 1301 kv_dpm_powergate_acp(rdev, false); 1302 kv_dpm_powergate_samu(rdev, false); 1303 kv_dpm_powergate_vce(rdev, false); 1304 kv_dpm_powergate_uvd(rdev, false); 1305 1306 kv_enable_smc_cac(rdev, false); 1307 kv_enable_didt(rdev, false); 1308 kv_clear_vc(rdev); 1309 kv_stop_dpm(rdev); 1310 kv_enable_ulv(rdev, false); 1311 kv_reset_am(rdev); 1312 1313 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1314 } 1315 1316 #if 0 1317 static int kv_write_smc_soft_register(struct radeon_device *rdev, 1318 u16 reg_offset, u32 value) 1319 { 1320 struct kv_power_info *pi = kv_get_pi(rdev); 1321 1322 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, 1323 (u8 *)&value, sizeof(u16), pi->sram_end); 1324 } 1325 1326 static int kv_read_smc_soft_register(struct radeon_device *rdev, 1327 u16 reg_offset, u32 *value) 1328 { 1329 struct kv_power_info *pi = kv_get_pi(rdev); 1330 1331 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, 1332 value, pi->sram_end); 1333 } 1334 #endif 1335 1336 static void kv_init_sclk_t(struct radeon_device *rdev) 1337 { 1338 struct kv_power_info *pi = kv_get_pi(rdev); 1339 1340 pi->low_sclk_interrupt_t = 0; 1341 } 1342 1343 static int kv_init_fps_limits(struct radeon_device *rdev) 1344 { 1345 struct kv_power_info *pi = kv_get_pi(rdev); 1346 int ret = 0; 1347 1348 if (pi->caps_fps) { 1349 u16 tmp; 1350 1351 tmp = 45; 1352 pi->fps_high_t = cpu_to_be16(tmp); 1353 ret = kv_copy_bytes_to_smc(rdev, 1354 pi->dpm_table_start + 1355 offsetof(SMU7_Fusion_DpmTable, FpsHighT), 1356 (u8 *)&pi->fps_high_t, 1357 sizeof(u16), pi->sram_end); 1358 1359 tmp = 30; 1360 pi->fps_low_t = cpu_to_be16(tmp); 1361 1362 ret = kv_copy_bytes_to_smc(rdev, 1363 pi->dpm_table_start + 1364 offsetof(SMU7_Fusion_DpmTable, FpsLowT), 1365 (u8 *)&pi->fps_low_t, 1366 sizeof(u16), pi->sram_end); 1367 1368 } 1369 return ret; 1370 } 1371 1372 static void kv_init_powergate_state(struct radeon_device *rdev) 1373 { 1374 struct kv_power_info *pi = kv_get_pi(rdev); 1375 1376 pi->uvd_power_gated = false; 1377 pi->vce_power_gated = false; 1378 pi->samu_power_gated = false; 1379 pi->acp_power_gated = false; 1380 1381 } 1382 1383 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 1384 { 1385 return kv_notify_message_to_smu(rdev, enable ? 1386 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); 1387 } 1388 1389 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable) 1390 { 1391 return kv_notify_message_to_smu(rdev, enable ? 1392 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); 1393 } 1394 1395 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable) 1396 { 1397 return kv_notify_message_to_smu(rdev, enable ? 1398 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); 1399 } 1400 1401 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable) 1402 { 1403 return kv_notify_message_to_smu(rdev, enable ? 1404 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); 1405 } 1406 1407 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) 1408 { 1409 struct kv_power_info *pi = kv_get_pi(rdev); 1410 struct radeon_uvd_clock_voltage_dependency_table *table = 1411 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1412 int ret; 1413 u32 mask; 1414 1415 if (!gate) { 1416 if (table->count) 1417 pi->uvd_boot_level = table->count - 1; 1418 else 1419 pi->uvd_boot_level = 0; 1420 1421 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { 1422 mask = 1 << pi->uvd_boot_level; 1423 } else { 1424 mask = 0x1f; 1425 } 1426 1427 ret = kv_copy_bytes_to_smc(rdev, 1428 pi->dpm_table_start + 1429 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1430 (uint8_t *)&pi->uvd_boot_level, 1431 sizeof(u8), pi->sram_end); 1432 if (ret) 1433 return ret; 1434 1435 kv_send_msg_to_smc_with_parameter(rdev, 1436 PPSMC_MSG_UVDDPM_SetEnabledMask, 1437 mask); 1438 } 1439 1440 return kv_enable_uvd_dpm(rdev, !gate); 1441 } 1442 1443 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) 1444 { 1445 u8 i; 1446 struct radeon_vce_clock_voltage_dependency_table *table = 1447 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1448 1449 for (i = 0; i < table->count; i++) { 1450 if (table->entries[i].evclk >= evclk) 1451 break; 1452 } 1453 1454 return i; 1455 } 1456 1457 static int kv_update_vce_dpm(struct radeon_device *rdev, 1458 struct radeon_ps *radeon_new_state, 1459 struct radeon_ps *radeon_current_state) 1460 { 1461 struct kv_power_info *pi = kv_get_pi(rdev); 1462 struct radeon_vce_clock_voltage_dependency_table *table = 1463 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1464 int ret; 1465 1466 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { 1467 kv_dpm_powergate_vce(rdev, false); 1468 /* turn the clocks on when encoding */ 1469 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 1470 if (pi->caps_stable_p_state) 1471 pi->vce_boot_level = table->count - 1; 1472 else 1473 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); 1474 1475 ret = kv_copy_bytes_to_smc(rdev, 1476 pi->dpm_table_start + 1477 offsetof(SMU7_Fusion_DpmTable, VceBootLevel), 1478 (u8 *)&pi->vce_boot_level, 1479 sizeof(u8), 1480 pi->sram_end); 1481 if (ret) 1482 return ret; 1483 1484 if (pi->caps_stable_p_state) 1485 kv_send_msg_to_smc_with_parameter(rdev, 1486 PPSMC_MSG_VCEDPM_SetEnabledMask, 1487 (1 << pi->vce_boot_level)); 1488 1489 kv_enable_vce_dpm(rdev, true); 1490 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { 1491 kv_enable_vce_dpm(rdev, false); 1492 /* turn the clocks off when not encoding */ 1493 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 1494 kv_dpm_powergate_vce(rdev, true); 1495 } 1496 1497 return 0; 1498 } 1499 1500 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) 1501 { 1502 struct kv_power_info *pi = kv_get_pi(rdev); 1503 struct radeon_clock_voltage_dependency_table *table = 1504 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1505 int ret; 1506 1507 if (!gate) { 1508 if (pi->caps_stable_p_state) 1509 pi->samu_boot_level = table->count - 1; 1510 else 1511 pi->samu_boot_level = 0; 1512 1513 ret = kv_copy_bytes_to_smc(rdev, 1514 pi->dpm_table_start + 1515 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), 1516 (u8 *)&pi->samu_boot_level, 1517 sizeof(u8), 1518 pi->sram_end); 1519 if (ret) 1520 return ret; 1521 1522 if (pi->caps_stable_p_state) 1523 kv_send_msg_to_smc_with_parameter(rdev, 1524 PPSMC_MSG_SAMUDPM_SetEnabledMask, 1525 (1 << pi->samu_boot_level)); 1526 } 1527 1528 return kv_enable_samu_dpm(rdev, !gate); 1529 } 1530 1531 static u8 kv_get_acp_boot_level(struct radeon_device *rdev) 1532 { 1533 u8 i; 1534 struct radeon_clock_voltage_dependency_table *table = 1535 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1536 1537 for (i = 0; i < table->count; i++) { 1538 if (table->entries[i].clk >= 0) /* XXX */ 1539 break; 1540 } 1541 1542 if (i >= table->count) 1543 i = table->count - 1; 1544 1545 return i; 1546 } 1547 1548 static void kv_update_acp_boot_level(struct radeon_device *rdev) 1549 { 1550 struct kv_power_info *pi = kv_get_pi(rdev); 1551 u8 acp_boot_level; 1552 1553 if (!pi->caps_stable_p_state) { 1554 acp_boot_level = kv_get_acp_boot_level(rdev); 1555 if (acp_boot_level != pi->acp_boot_level) { 1556 pi->acp_boot_level = acp_boot_level; 1557 kv_send_msg_to_smc_with_parameter(rdev, 1558 PPSMC_MSG_ACPDPM_SetEnabledMask, 1559 (1 << pi->acp_boot_level)); 1560 } 1561 } 1562 } 1563 1564 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate) 1565 { 1566 struct kv_power_info *pi = kv_get_pi(rdev); 1567 struct radeon_clock_voltage_dependency_table *table = 1568 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1569 int ret; 1570 1571 if (!gate) { 1572 if (pi->caps_stable_p_state) 1573 pi->acp_boot_level = table->count - 1; 1574 else 1575 pi->acp_boot_level = kv_get_acp_boot_level(rdev); 1576 1577 ret = kv_copy_bytes_to_smc(rdev, 1578 pi->dpm_table_start + 1579 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), 1580 (u8 *)&pi->acp_boot_level, 1581 sizeof(u8), 1582 pi->sram_end); 1583 if (ret) 1584 return ret; 1585 1586 if (pi->caps_stable_p_state) 1587 kv_send_msg_to_smc_with_parameter(rdev, 1588 PPSMC_MSG_ACPDPM_SetEnabledMask, 1589 (1 << pi->acp_boot_level)); 1590 } 1591 1592 return kv_enable_acp_dpm(rdev, !gate); 1593 } 1594 1595 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 1596 { 1597 struct kv_power_info *pi = kv_get_pi(rdev); 1598 1599 if (pi->uvd_power_gated == gate) 1600 return; 1601 1602 pi->uvd_power_gated = gate; 1603 1604 if (gate) { 1605 if (pi->caps_uvd_pg) { 1606 uvd_v1_0_stop(rdev); 1607 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false); 1608 } 1609 kv_update_uvd_dpm(rdev, gate); 1610 if (pi->caps_uvd_pg) 1611 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF); 1612 } else { 1613 if (pi->caps_uvd_pg) { 1614 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON); 1615 uvd_v4_2_resume(rdev); 1616 uvd_v1_0_start(rdev); 1617 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true); 1618 } 1619 kv_update_uvd_dpm(rdev, gate); 1620 } 1621 } 1622 1623 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate) 1624 { 1625 struct kv_power_info *pi = kv_get_pi(rdev); 1626 1627 if (pi->vce_power_gated == gate) 1628 return; 1629 1630 pi->vce_power_gated = gate; 1631 1632 if (gate) { 1633 if (pi->caps_vce_pg) { 1634 /* XXX do we need a vce_v1_0_stop() ? */ 1635 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF); 1636 } 1637 } else { 1638 if (pi->caps_vce_pg) { 1639 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON); 1640 vce_v2_0_resume(rdev); 1641 vce_v1_0_start(rdev); 1642 } 1643 } 1644 } 1645 1646 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate) 1647 { 1648 struct kv_power_info *pi = kv_get_pi(rdev); 1649 1650 if (pi->samu_power_gated == gate) 1651 return; 1652 1653 pi->samu_power_gated = gate; 1654 1655 if (gate) { 1656 kv_update_samu_dpm(rdev, true); 1657 if (pi->caps_samu_pg) 1658 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF); 1659 } else { 1660 if (pi->caps_samu_pg) 1661 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON); 1662 kv_update_samu_dpm(rdev, false); 1663 } 1664 } 1665 1666 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate) 1667 { 1668 struct kv_power_info *pi = kv_get_pi(rdev); 1669 1670 if (pi->acp_power_gated == gate) 1671 return; 1672 1673 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 1674 return; 1675 1676 pi->acp_power_gated = gate; 1677 1678 if (gate) { 1679 kv_update_acp_dpm(rdev, true); 1680 if (pi->caps_acp_pg) 1681 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF); 1682 } else { 1683 if (pi->caps_acp_pg) 1684 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON); 1685 kv_update_acp_dpm(rdev, false); 1686 } 1687 } 1688 1689 static void kv_set_valid_clock_range(struct radeon_device *rdev, 1690 struct radeon_ps *new_rps) 1691 { 1692 struct kv_ps *new_ps = kv_get_ps(new_rps); 1693 struct kv_power_info *pi = kv_get_pi(rdev); 1694 u32 i; 1695 struct radeon_clock_voltage_dependency_table *table = 1696 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1697 1698 if (table && table->count) { 1699 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1700 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || 1701 (i == (pi->graphics_dpm_level_count - 1))) { 1702 pi->lowest_valid = i; 1703 break; 1704 } 1705 } 1706 1707 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1708 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) 1709 break; 1710 } 1711 pi->highest_valid = i; 1712 1713 if (pi->lowest_valid > pi->highest_valid) { 1714 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > 1715 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) 1716 pi->highest_valid = pi->lowest_valid; 1717 else 1718 pi->lowest_valid = pi->highest_valid; 1719 } 1720 } else { 1721 struct sumo_sclk_voltage_mapping_table *table = 1722 &pi->sys_info.sclk_voltage_mapping_table; 1723 1724 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { 1725 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || 1726 i == (int)(pi->graphics_dpm_level_count - 1)) { 1727 pi->lowest_valid = i; 1728 break; 1729 } 1730 } 1731 1732 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1733 if (table->entries[i].sclk_frequency <= 1734 new_ps->levels[new_ps->num_levels - 1].sclk) 1735 break; 1736 } 1737 pi->highest_valid = i; 1738 1739 if (pi->lowest_valid > pi->highest_valid) { 1740 if ((new_ps->levels[0].sclk - 1741 table->entries[pi->highest_valid].sclk_frequency) > 1742 (table->entries[pi->lowest_valid].sclk_frequency - 1743 new_ps->levels[new_ps->num_levels -1].sclk)) 1744 pi->highest_valid = pi->lowest_valid; 1745 else 1746 pi->lowest_valid = pi->highest_valid; 1747 } 1748 } 1749 } 1750 1751 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev, 1752 struct radeon_ps *new_rps) 1753 { 1754 struct kv_ps *new_ps = kv_get_ps(new_rps); 1755 struct kv_power_info *pi = kv_get_pi(rdev); 1756 int ret = 0; 1757 u8 clk_bypass_cntl; 1758 1759 if (pi->caps_enable_dfs_bypass) { 1760 clk_bypass_cntl = new_ps->need_dfs_bypass ? 1761 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; 1762 ret = kv_copy_bytes_to_smc(rdev, 1763 (pi->dpm_table_start + 1764 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + 1765 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + 1766 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), 1767 &clk_bypass_cntl, 1768 sizeof(u8), pi->sram_end); 1769 } 1770 1771 return ret; 1772 } 1773 1774 static int kv_enable_nb_dpm(struct radeon_device *rdev, 1775 bool enable) 1776 { 1777 struct kv_power_info *pi = kv_get_pi(rdev); 1778 int ret = 0; 1779 1780 if (enable) { 1781 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { 1782 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable); 1783 if (ret == 0) 1784 pi->nb_dpm_enabled = true; 1785 } 1786 } else { 1787 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { 1788 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable); 1789 if (ret == 0) 1790 pi->nb_dpm_enabled = false; 1791 } 1792 } 1793 1794 return ret; 1795 } 1796 1797 int kv_dpm_force_performance_level(struct radeon_device *rdev, 1798 enum radeon_dpm_forced_level level) 1799 { 1800 int ret; 1801 1802 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1803 ret = kv_force_dpm_highest(rdev); 1804 if (ret) 1805 return ret; 1806 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1807 ret = kv_force_dpm_lowest(rdev); 1808 if (ret) 1809 return ret; 1810 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1811 ret = kv_unforce_levels(rdev); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 rdev->pm.dpm.forced_level = level; 1817 1818 return 0; 1819 } 1820 1821 int kv_dpm_pre_set_power_state(struct radeon_device *rdev) 1822 { 1823 struct kv_power_info *pi = kv_get_pi(rdev); 1824 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 1825 struct radeon_ps *new_ps = &requested_ps; 1826 1827 kv_update_requested_ps(rdev, new_ps); 1828 1829 kv_apply_state_adjust_rules(rdev, 1830 &pi->requested_rps, 1831 &pi->current_rps); 1832 1833 return 0; 1834 } 1835 1836 int kv_dpm_set_power_state(struct radeon_device *rdev) 1837 { 1838 struct kv_power_info *pi = kv_get_pi(rdev); 1839 struct radeon_ps *new_ps = &pi->requested_rps; 1840 struct radeon_ps *old_ps = &pi->current_rps; 1841 int ret; 1842 1843 if (pi->bapm_enable) { 1844 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power); 1845 if (ret) { 1846 DRM_ERROR("kv_smc_bapm_enable failed\n"); 1847 return ret; 1848 } 1849 } 1850 1851 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1852 if (pi->enable_dpm) { 1853 kv_set_valid_clock_range(rdev, new_ps); 1854 kv_update_dfs_bypass_settings(rdev, new_ps); 1855 ret = kv_calculate_ds_divider(rdev); 1856 if (ret) { 1857 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1858 return ret; 1859 } 1860 kv_calculate_nbps_level_settings(rdev); 1861 kv_calculate_dpm_settings(rdev); 1862 kv_force_lowest_valid(rdev); 1863 kv_enable_new_levels(rdev); 1864 kv_upload_dpm_settings(rdev); 1865 kv_program_nbps_index_settings(rdev, new_ps); 1866 kv_unforce_levels(rdev); 1867 kv_set_enabled_levels(rdev); 1868 kv_force_lowest_valid(rdev); 1869 kv_unforce_levels(rdev); 1870 1871 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1872 if (ret) { 1873 DRM_ERROR("kv_update_vce_dpm failed\n"); 1874 return ret; 1875 } 1876 kv_update_sclk_t(rdev); 1877 if (rdev->family == CHIP_MULLINS) 1878 kv_enable_nb_dpm(rdev, true); 1879 } 1880 } else { 1881 if (pi->enable_dpm) { 1882 kv_set_valid_clock_range(rdev, new_ps); 1883 kv_update_dfs_bypass_settings(rdev, new_ps); 1884 ret = kv_calculate_ds_divider(rdev); 1885 if (ret) { 1886 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1887 return ret; 1888 } 1889 kv_calculate_nbps_level_settings(rdev); 1890 kv_calculate_dpm_settings(rdev); 1891 kv_freeze_sclk_dpm(rdev, true); 1892 kv_upload_dpm_settings(rdev); 1893 kv_program_nbps_index_settings(rdev, new_ps); 1894 kv_freeze_sclk_dpm(rdev, false); 1895 kv_set_enabled_levels(rdev); 1896 ret = kv_update_vce_dpm(rdev, new_ps, old_ps); 1897 if (ret) { 1898 DRM_ERROR("kv_update_vce_dpm failed\n"); 1899 return ret; 1900 } 1901 kv_update_acp_boot_level(rdev); 1902 kv_update_sclk_t(rdev); 1903 kv_enable_nb_dpm(rdev, true); 1904 } 1905 } 1906 1907 return 0; 1908 } 1909 1910 void kv_dpm_post_set_power_state(struct radeon_device *rdev) 1911 { 1912 struct kv_power_info *pi = kv_get_pi(rdev); 1913 struct radeon_ps *new_ps = &pi->requested_rps; 1914 1915 kv_update_current_ps(rdev, new_ps); 1916 } 1917 1918 void kv_dpm_setup_asic(struct radeon_device *rdev) 1919 { 1920 sumo_take_smu_control(rdev, true); 1921 kv_init_powergate_state(rdev); 1922 kv_init_sclk_t(rdev); 1923 } 1924 1925 #if 0 1926 void kv_dpm_reset_asic(struct radeon_device *rdev) 1927 { 1928 struct kv_power_info *pi = kv_get_pi(rdev); 1929 1930 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 1931 kv_force_lowest_valid(rdev); 1932 kv_init_graphics_levels(rdev); 1933 kv_program_bootup_state(rdev); 1934 kv_upload_dpm_settings(rdev); 1935 kv_force_lowest_valid(rdev); 1936 kv_unforce_levels(rdev); 1937 } else { 1938 kv_init_graphics_levels(rdev); 1939 kv_program_bootup_state(rdev); 1940 kv_freeze_sclk_dpm(rdev, true); 1941 kv_upload_dpm_settings(rdev); 1942 kv_freeze_sclk_dpm(rdev, false); 1943 kv_set_enabled_level(rdev, pi->graphics_boot_level); 1944 } 1945 } 1946 #endif 1947 1948 //XXX use sumo_dpm_display_configuration_changed 1949 1950 static void kv_construct_max_power_limits_table(struct radeon_device *rdev, 1951 struct radeon_clock_and_voltage_limits *table) 1952 { 1953 struct kv_power_info *pi = kv_get_pi(rdev); 1954 1955 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { 1956 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; 1957 table->sclk = 1958 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; 1959 table->vddc = 1960 kv_convert_2bit_index_to_voltage(rdev, 1961 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); 1962 } 1963 1964 table->mclk = pi->sys_info.nbp_memory_clock[0]; 1965 } 1966 1967 static void kv_patch_voltage_values(struct radeon_device *rdev) 1968 { 1969 int i; 1970 struct radeon_uvd_clock_voltage_dependency_table *uvd_table = 1971 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1972 struct radeon_vce_clock_voltage_dependency_table *vce_table = 1973 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1974 struct radeon_clock_voltage_dependency_table *samu_table = 1975 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1976 struct radeon_clock_voltage_dependency_table *acp_table = 1977 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1978 1979 if (uvd_table->count) { 1980 for (i = 0; i < uvd_table->count; i++) 1981 uvd_table->entries[i].v = 1982 kv_convert_8bit_index_to_voltage(rdev, 1983 uvd_table->entries[i].v); 1984 } 1985 1986 if (vce_table->count) { 1987 for (i = 0; i < vce_table->count; i++) 1988 vce_table->entries[i].v = 1989 kv_convert_8bit_index_to_voltage(rdev, 1990 vce_table->entries[i].v); 1991 } 1992 1993 if (samu_table->count) { 1994 for (i = 0; i < samu_table->count; i++) 1995 samu_table->entries[i].v = 1996 kv_convert_8bit_index_to_voltage(rdev, 1997 samu_table->entries[i].v); 1998 } 1999 2000 if (acp_table->count) { 2001 for (i = 0; i < acp_table->count; i++) 2002 acp_table->entries[i].v = 2003 kv_convert_8bit_index_to_voltage(rdev, 2004 acp_table->entries[i].v); 2005 } 2006 2007 } 2008 2009 static void kv_construct_boot_state(struct radeon_device *rdev) 2010 { 2011 struct kv_power_info *pi = kv_get_pi(rdev); 2012 2013 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 2014 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 2015 pi->boot_pl.ds_divider_index = 0; 2016 pi->boot_pl.ss_divider_index = 0; 2017 pi->boot_pl.allow_gnb_slow = 1; 2018 pi->boot_pl.force_nbp_state = 0; 2019 pi->boot_pl.display_wm = 0; 2020 pi->boot_pl.vce_wm = 0; 2021 } 2022 2023 static int kv_force_dpm_highest(struct radeon_device *rdev) 2024 { 2025 int ret; 2026 u32 enable_mask, i; 2027 2028 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2029 if (ret) 2030 return ret; 2031 2032 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { 2033 if (enable_mask & (1 << i)) 2034 break; 2035 } 2036 2037 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2038 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2039 else 2040 return kv_set_enabled_level(rdev, i); 2041 } 2042 2043 static int kv_force_dpm_lowest(struct radeon_device *rdev) 2044 { 2045 int ret; 2046 u32 enable_mask, i; 2047 2048 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); 2049 if (ret) 2050 return ret; 2051 2052 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2053 if (enable_mask & (1 << i)) 2054 break; 2055 } 2056 2057 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2058 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2059 else 2060 return kv_set_enabled_level(rdev, i); 2061 } 2062 2063 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2064 u32 sclk, u32 min_sclk_in_sr) 2065 { 2066 struct kv_power_info *pi = kv_get_pi(rdev); 2067 u32 i; 2068 u32 temp; 2069 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? 2070 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; 2071 2072 if (sclk < min) 2073 return 0; 2074 2075 if (!pi->caps_sclk_ds) 2076 return 0; 2077 2078 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { 2079 temp = sclk / sumo_get_sleep_divider_from_id(i); 2080 if (temp >= min) 2081 break; 2082 } 2083 2084 return (u8)i; 2085 } 2086 2087 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit) 2088 { 2089 struct kv_power_info *pi = kv_get_pi(rdev); 2090 struct radeon_clock_voltage_dependency_table *table = 2091 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2092 int i; 2093 2094 if (table && table->count) { 2095 for (i = table->count - 1; i >= 0; i--) { 2096 if (pi->high_voltage_t && 2097 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <= 2098 pi->high_voltage_t)) { 2099 *limit = i; 2100 return 0; 2101 } 2102 } 2103 } else { 2104 struct sumo_sclk_voltage_mapping_table *table = 2105 &pi->sys_info.sclk_voltage_mapping_table; 2106 2107 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { 2108 if (pi->high_voltage_t && 2109 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <= 2110 pi->high_voltage_t)) { 2111 *limit = i; 2112 return 0; 2113 } 2114 } 2115 } 2116 2117 *limit = 0; 2118 return 0; 2119 } 2120 2121 static void kv_apply_state_adjust_rules(struct radeon_device *rdev, 2122 struct radeon_ps *new_rps, 2123 struct radeon_ps *old_rps) 2124 { 2125 struct kv_ps *ps = kv_get_ps(new_rps); 2126 struct kv_power_info *pi = kv_get_pi(rdev); 2127 u32 min_sclk = 10000; /* ??? */ 2128 u32 sclk, mclk = 0; 2129 int i, limit; 2130 bool force_high; 2131 struct radeon_clock_voltage_dependency_table *table = 2132 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2133 u32 stable_p_state_sclk = 0; 2134 struct radeon_clock_and_voltage_limits *max_limits = 2135 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2136 2137 if (new_rps->vce_active) { 2138 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2139 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2140 } else { 2141 new_rps->evclk = 0; 2142 new_rps->ecclk = 0; 2143 } 2144 2145 mclk = max_limits->mclk; 2146 sclk = min_sclk; 2147 2148 if (pi->caps_stable_p_state) { 2149 stable_p_state_sclk = (max_limits->sclk * 75) / 100; 2150 2151 for (i = table->count - 1; i >= 0; i++) { 2152 if (stable_p_state_sclk >= table->entries[i].clk) { 2153 stable_p_state_sclk = table->entries[i].clk; 2154 break; 2155 } 2156 } 2157 2158 if (i > 0) 2159 stable_p_state_sclk = table->entries[0].clk; 2160 2161 sclk = stable_p_state_sclk; 2162 } 2163 2164 if (new_rps->vce_active) { 2165 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 2166 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 2167 } 2168 2169 ps->need_dfs_bypass = true; 2170 2171 for (i = 0; i < ps->num_levels; i++) { 2172 if (ps->levels[i].sclk < sclk) 2173 ps->levels[i].sclk = sclk; 2174 } 2175 2176 if (table && table->count) { 2177 for (i = 0; i < ps->num_levels; i++) { 2178 if (pi->high_voltage_t && 2179 (pi->high_voltage_t < 2180 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2181 kv_get_high_voltage_limit(rdev, &limit); 2182 ps->levels[i].sclk = table->entries[limit].clk; 2183 } 2184 } 2185 } else { 2186 struct sumo_sclk_voltage_mapping_table *table = 2187 &pi->sys_info.sclk_voltage_mapping_table; 2188 2189 for (i = 0; i < ps->num_levels; i++) { 2190 if (pi->high_voltage_t && 2191 (pi->high_voltage_t < 2192 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { 2193 kv_get_high_voltage_limit(rdev, &limit); 2194 ps->levels[i].sclk = table->entries[limit].sclk_frequency; 2195 } 2196 } 2197 } 2198 2199 if (pi->caps_stable_p_state) { 2200 for (i = 0; i < ps->num_levels; i++) { 2201 ps->levels[i].sclk = stable_p_state_sclk; 2202 } 2203 } 2204 2205 pi->video_start = new_rps->dclk || new_rps->vclk || 2206 new_rps->evclk || new_rps->ecclk; 2207 2208 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2209 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 2210 pi->battery_state = true; 2211 else 2212 pi->battery_state = false; 2213 2214 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2215 ps->dpm0_pg_nb_ps_lo = 0x1; 2216 ps->dpm0_pg_nb_ps_hi = 0x0; 2217 ps->dpmx_nb_ps_lo = 0x1; 2218 ps->dpmx_nb_ps_hi = 0x0; 2219 } else { 2220 ps->dpm0_pg_nb_ps_lo = 0x3; 2221 ps->dpm0_pg_nb_ps_hi = 0x0; 2222 ps->dpmx_nb_ps_lo = 0x3; 2223 ps->dpmx_nb_ps_hi = 0x0; 2224 2225 if (pi->sys_info.nb_dpm_enable) { 2226 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || 2227 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || 2228 pi->disable_nb_ps3_in_battery; 2229 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; 2230 ps->dpm0_pg_nb_ps_hi = 0x2; 2231 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; 2232 ps->dpmx_nb_ps_hi = 0x2; 2233 } 2234 } 2235 } 2236 2237 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev, 2238 u32 index, bool enable) 2239 { 2240 struct kv_power_info *pi = kv_get_pi(rdev); 2241 2242 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; 2243 } 2244 2245 static int kv_calculate_ds_divider(struct radeon_device *rdev) 2246 { 2247 struct kv_power_info *pi = kv_get_pi(rdev); 2248 u32 sclk_in_sr = 10000; /* ??? */ 2249 u32 i; 2250 2251 if (pi->lowest_valid > pi->highest_valid) 2252 return -EINVAL; 2253 2254 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2255 pi->graphics_level[i].DeepSleepDivId = 2256 kv_get_sleep_divider_id_from_clock(rdev, 2257 be32_to_cpu(pi->graphics_level[i].SclkFrequency), 2258 sclk_in_sr); 2259 } 2260 return 0; 2261 } 2262 2263 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev) 2264 { 2265 struct kv_power_info *pi = kv_get_pi(rdev); 2266 u32 i; 2267 bool force_high; 2268 struct radeon_clock_and_voltage_limits *max_limits = 2269 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2270 u32 mclk = max_limits->mclk; 2271 2272 if (pi->lowest_valid > pi->highest_valid) 2273 return -EINVAL; 2274 2275 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) { 2276 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2277 pi->graphics_level[i].GnbSlow = 1; 2278 pi->graphics_level[i].ForceNbPs1 = 0; 2279 pi->graphics_level[i].UpH = 0; 2280 } 2281 2282 if (!pi->sys_info.nb_dpm_enable) 2283 return 0; 2284 2285 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || 2286 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); 2287 2288 if (force_high) { 2289 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2290 pi->graphics_level[i].GnbSlow = 0; 2291 } else { 2292 if (pi->battery_state) 2293 pi->graphics_level[0].ForceNbPs1 = 1; 2294 2295 pi->graphics_level[1].GnbSlow = 0; 2296 pi->graphics_level[2].GnbSlow = 0; 2297 pi->graphics_level[3].GnbSlow = 0; 2298 pi->graphics_level[4].GnbSlow = 0; 2299 } 2300 } else { 2301 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2302 pi->graphics_level[i].GnbSlow = 1; 2303 pi->graphics_level[i].ForceNbPs1 = 0; 2304 pi->graphics_level[i].UpH = 0; 2305 } 2306 2307 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { 2308 pi->graphics_level[pi->lowest_valid].UpH = 0x28; 2309 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; 2310 if (pi->lowest_valid != pi->highest_valid) 2311 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; 2312 } 2313 } 2314 return 0; 2315 } 2316 2317 static int kv_calculate_dpm_settings(struct radeon_device *rdev) 2318 { 2319 struct kv_power_info *pi = kv_get_pi(rdev); 2320 u32 i; 2321 2322 if (pi->lowest_valid > pi->highest_valid) 2323 return -EINVAL; 2324 2325 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2326 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; 2327 2328 return 0; 2329 } 2330 2331 static void kv_init_graphics_levels(struct radeon_device *rdev) 2332 { 2333 struct kv_power_info *pi = kv_get_pi(rdev); 2334 u32 i; 2335 struct radeon_clock_voltage_dependency_table *table = 2336 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2337 2338 if (table && table->count) { 2339 u32 vid_2bit; 2340 2341 pi->graphics_dpm_level_count = 0; 2342 for (i = 0; i < table->count; i++) { 2343 if (pi->high_voltage_t && 2344 (pi->high_voltage_t < 2345 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v))) 2346 break; 2347 2348 kv_set_divider_value(rdev, i, table->entries[i].clk); 2349 vid_2bit = kv_convert_vid7_to_vid2(rdev, 2350 &pi->sys_info.vid_mapping_table, 2351 table->entries[i].v); 2352 kv_set_vid(rdev, i, vid_2bit); 2353 kv_set_at(rdev, i, pi->at[i]); 2354 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2355 pi->graphics_dpm_level_count++; 2356 } 2357 } else { 2358 struct sumo_sclk_voltage_mapping_table *table = 2359 &pi->sys_info.sclk_voltage_mapping_table; 2360 2361 pi->graphics_dpm_level_count = 0; 2362 for (i = 0; i < table->num_max_dpm_entries; i++) { 2363 if (pi->high_voltage_t && 2364 pi->high_voltage_t < 2365 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit)) 2366 break; 2367 2368 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency); 2369 kv_set_vid(rdev, i, table->entries[i].vid_2bit); 2370 kv_set_at(rdev, i, pi->at[i]); 2371 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2372 pi->graphics_dpm_level_count++; 2373 } 2374 } 2375 2376 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 2377 kv_dpm_power_level_enable(rdev, i, false); 2378 } 2379 2380 static void kv_enable_new_levels(struct radeon_device *rdev) 2381 { 2382 struct kv_power_info *pi = kv_get_pi(rdev); 2383 u32 i; 2384 2385 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2386 if (i >= pi->lowest_valid && i <= pi->highest_valid) 2387 kv_dpm_power_level_enable(rdev, i, true); 2388 } 2389 } 2390 2391 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level) 2392 { 2393 u32 new_mask = (1 << level); 2394 2395 return kv_send_msg_to_smc_with_parameter(rdev, 2396 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2397 new_mask); 2398 } 2399 2400 static int kv_set_enabled_levels(struct radeon_device *rdev) 2401 { 2402 struct kv_power_info *pi = kv_get_pi(rdev); 2403 u32 i, new_mask = 0; 2404 2405 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2406 new_mask |= (1 << i); 2407 2408 return kv_send_msg_to_smc_with_parameter(rdev, 2409 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2410 new_mask); 2411 } 2412 2413 static void kv_program_nbps_index_settings(struct radeon_device *rdev, 2414 struct radeon_ps *new_rps) 2415 { 2416 struct kv_ps *new_ps = kv_get_ps(new_rps); 2417 struct kv_power_info *pi = kv_get_pi(rdev); 2418 u32 nbdpmconfig1; 2419 2420 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2421 return; 2422 2423 if (pi->sys_info.nb_dpm_enable) { 2424 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); 2425 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | 2426 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK); 2427 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) | 2428 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) | 2429 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) | 2430 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi)); 2431 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); 2432 } 2433 } 2434 2435 static int kv_set_thermal_temperature_range(struct radeon_device *rdev, 2436 int min_temp, int max_temp) 2437 { 2438 int low_temp = 0 * 1000; 2439 int high_temp = 255 * 1000; 2440 u32 tmp; 2441 2442 if (low_temp < min_temp) 2443 low_temp = min_temp; 2444 if (high_temp > max_temp) 2445 high_temp = max_temp; 2446 if (high_temp < low_temp) { 2447 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 2448 return -EINVAL; 2449 } 2450 2451 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); 2452 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK); 2453 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) | 2454 DIG_THERM_INTL(49 + (low_temp / 1000))); 2455 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); 2456 2457 rdev->pm.dpm.thermal.min_temp = low_temp; 2458 rdev->pm.dpm.thermal.max_temp = high_temp; 2459 2460 return 0; 2461 } 2462 2463 union igp_info { 2464 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 2465 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 2466 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 2467 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 2468 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 2469 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 2470 }; 2471 2472 static int kv_parse_sys_info_table(struct radeon_device *rdev) 2473 { 2474 struct kv_power_info *pi = kv_get_pi(rdev); 2475 struct radeon_mode_info *mode_info = &rdev->mode_info; 2476 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 2477 union igp_info *igp_info; 2478 u8 frev, crev; 2479 u16 data_offset; 2480 int i; 2481 2482 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2483 &frev, &crev, &data_offset)) { 2484 igp_info = (union igp_info *)(mode_info->atom_context->bios + 2485 data_offset); 2486 2487 if (crev != 8) { 2488 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 2489 return -EINVAL; 2490 } 2491 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); 2492 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); 2493 pi->sys_info.bootup_nb_voltage_index = 2494 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); 2495 if (igp_info->info_8.ucHtcTmpLmt == 0) 2496 pi->sys_info.htc_tmp_lmt = 203; 2497 else 2498 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; 2499 if (igp_info->info_8.ucHtcHystLmt == 0) 2500 pi->sys_info.htc_hyst_lmt = 5; 2501 else 2502 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; 2503 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 2504 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 2505 } 2506 2507 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) 2508 pi->sys_info.nb_dpm_enable = true; 2509 else 2510 pi->sys_info.nb_dpm_enable = false; 2511 2512 for (i = 0; i < KV_NUM_NBPSTATES; i++) { 2513 pi->sys_info.nbp_memory_clock[i] = 2514 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); 2515 pi->sys_info.nbp_n_clock[i] = 2516 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); 2517 } 2518 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & 2519 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) 2520 pi->caps_enable_dfs_bypass = true; 2521 2522 sumo_construct_sclk_voltage_mapping_table(rdev, 2523 &pi->sys_info.sclk_voltage_mapping_table, 2524 igp_info->info_8.sAvail_SCLK); 2525 2526 sumo_construct_vid_mapping_table(rdev, 2527 &pi->sys_info.vid_mapping_table, 2528 igp_info->info_8.sAvail_SCLK); 2529 2530 kv_construct_max_power_limits_table(rdev, 2531 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 2532 } 2533 return 0; 2534 } 2535 2536 union power_info { 2537 struct _ATOM_POWERPLAY_INFO info; 2538 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2539 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2540 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2541 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2542 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2543 }; 2544 2545 union pplib_clock_info { 2546 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2547 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2548 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2549 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2550 }; 2551 2552 union pplib_power_state { 2553 struct _ATOM_PPLIB_STATE v1; 2554 struct _ATOM_PPLIB_STATE_V2 v2; 2555 }; 2556 2557 static void kv_patch_boot_state(struct radeon_device *rdev, 2558 struct kv_ps *ps) 2559 { 2560 struct kv_power_info *pi = kv_get_pi(rdev); 2561 2562 ps->num_levels = 1; 2563 ps->levels[0] = pi->boot_pl; 2564 } 2565 2566 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev, 2567 struct radeon_ps *rps, 2568 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 2569 u8 table_rev) 2570 { 2571 struct kv_ps *ps = kv_get_ps(rps); 2572 2573 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2574 rps->class = le16_to_cpu(non_clock_info->usClassification); 2575 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 2576 2577 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 2578 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 2579 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 2580 } else { 2581 rps->vclk = 0; 2582 rps->dclk = 0; 2583 } 2584 2585 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2586 rdev->pm.dpm.boot_ps = rps; 2587 kv_patch_boot_state(rdev, ps); 2588 } 2589 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 2590 rdev->pm.dpm.uvd_ps = rps; 2591 } 2592 2593 static void kv_parse_pplib_clock_info(struct radeon_device *rdev, 2594 struct radeon_ps *rps, int index, 2595 union pplib_clock_info *clock_info) 2596 { 2597 struct kv_power_info *pi = kv_get_pi(rdev); 2598 struct kv_ps *ps = kv_get_ps(rps); 2599 struct kv_pl *pl = &ps->levels[index]; 2600 u32 sclk; 2601 2602 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2603 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2604 pl->sclk = sclk; 2605 pl->vddc_index = clock_info->sumo.vddcIndex; 2606 2607 ps->num_levels = index + 1; 2608 2609 if (pi->caps_sclk_ds) { 2610 pl->ds_divider_index = 5; 2611 pl->ss_divider_index = 5; 2612 } 2613 } 2614 2615 static int kv_parse_power_table(struct radeon_device *rdev) 2616 { 2617 struct radeon_mode_info *mode_info = &rdev->mode_info; 2618 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2619 union pplib_power_state *power_state; 2620 int i, j, k, non_clock_array_index, clock_array_index; 2621 union pplib_clock_info *clock_info; 2622 struct _StateArray *state_array; 2623 struct _ClockInfoArray *clock_info_array; 2624 struct _NonClockInfoArray *non_clock_info_array; 2625 union power_info *power_info; 2626 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2627 u16 data_offset; 2628 u8 frev, crev; 2629 u8 *power_state_offset; 2630 struct kv_ps *ps; 2631 2632 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2633 &frev, &crev, &data_offset)) 2634 return -EINVAL; 2635 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2636 2637 state_array = (struct _StateArray *) 2638 (mode_info->atom_context->bios + data_offset + 2639 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2640 clock_info_array = (struct _ClockInfoArray *) 2641 (mode_info->atom_context->bios + data_offset + 2642 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2643 non_clock_info_array = (struct _NonClockInfoArray *) 2644 (mode_info->atom_context->bios + data_offset + 2645 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2646 2647 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 2648 state_array->ucNumEntries, GFP_KERNEL); 2649 if (!rdev->pm.dpm.ps) 2650 return -ENOMEM; 2651 power_state_offset = (u8 *)state_array->states; 2652 for (i = 0; i < state_array->ucNumEntries; i++) { 2653 u8 *idx; 2654 power_state = (union pplib_power_state *)power_state_offset; 2655 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2656 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2657 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2658 if (!rdev->pm.power_state[i].clock_info) 2659 return -EINVAL; 2660 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); 2661 if (ps == NULL) { 2662 kfree(rdev->pm.dpm.ps); 2663 return -ENOMEM; 2664 } 2665 rdev->pm.dpm.ps[i].ps_priv = ps; 2666 k = 0; 2667 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2668 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2669 clock_array_index = idx[j]; 2670 if (clock_array_index >= clock_info_array->ucNumEntries) 2671 continue; 2672 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 2673 break; 2674 clock_info = (union pplib_clock_info *) 2675 ((u8 *)&clock_info_array->clockInfo[0] + 2676 (clock_array_index * clock_info_array->ucEntrySize)); 2677 kv_parse_pplib_clock_info(rdev, 2678 &rdev->pm.dpm.ps[i], k, 2679 clock_info); 2680 k++; 2681 } 2682 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 2683 non_clock_info, 2684 non_clock_info_array->ucEntrySize); 2685 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2686 } 2687 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 2688 2689 /* fill in the vce power states */ 2690 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 2691 u32 sclk; 2692 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 2693 clock_info = (union pplib_clock_info *) 2694 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2695 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2696 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2697 rdev->pm.dpm.vce_states[i].sclk = sclk; 2698 rdev->pm.dpm.vce_states[i].mclk = 0; 2699 } 2700 2701 return 0; 2702 } 2703 2704 int kv_dpm_init(struct radeon_device *rdev) 2705 { 2706 struct kv_power_info *pi; 2707 int ret, i; 2708 2709 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); 2710 if (pi == NULL) 2711 return -ENOMEM; 2712 rdev->pm.dpm.priv = pi; 2713 2714 ret = r600_get_platform_caps(rdev); 2715 if (ret) 2716 return ret; 2717 2718 ret = r600_parse_extended_power_table(rdev); 2719 if (ret) 2720 return ret; 2721 2722 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 2723 pi->at[i] = TRINITY_AT_DFLT; 2724 2725 pi->sram_end = SMC_RAM_END; 2726 2727 /* Enabling nb dpm on an asrock system prevents dpm from working */ 2728 if (rdev->pdev->subsystem_vendor == 0x1849) 2729 pi->enable_nb_dpm = false; 2730 else 2731 pi->enable_nb_dpm = true; 2732 2733 pi->caps_power_containment = true; 2734 pi->caps_cac = true; 2735 pi->enable_didt = false; 2736 if (pi->enable_didt) { 2737 pi->caps_sq_ramping = true; 2738 pi->caps_db_ramping = true; 2739 pi->caps_td_ramping = true; 2740 pi->caps_tcp_ramping = true; 2741 } 2742 2743 pi->caps_sclk_ds = true; 2744 pi->enable_auto_thermal_throttling = true; 2745 pi->disable_nb_ps3_in_battery = false; 2746 if (radeon_bapm == -1) { 2747 /* There are stability issues reported on with 2748 * bapm enabled on an asrock system. 2749 */ 2750 if (rdev->pdev->subsystem_vendor == 0x1849) 2751 pi->bapm_enable = false; 2752 else 2753 pi->bapm_enable = true; 2754 } else if (radeon_bapm == 0) { 2755 pi->bapm_enable = false; 2756 } else { 2757 pi->bapm_enable = true; 2758 } 2759 pi->voltage_drop_t = 0; 2760 pi->caps_sclk_throttle_low_notification = false; 2761 pi->caps_fps = false; /* true? */ 2762 pi->caps_uvd_pg = true; 2763 pi->caps_uvd_dpm = true; 2764 pi->caps_vce_pg = false; /* XXX true */ 2765 pi->caps_samu_pg = false; 2766 pi->caps_acp_pg = false; 2767 pi->caps_stable_p_state = false; 2768 2769 ret = kv_parse_sys_info_table(rdev); 2770 if (ret) 2771 return ret; 2772 2773 kv_patch_voltage_values(rdev); 2774 kv_construct_boot_state(rdev); 2775 2776 ret = kv_parse_power_table(rdev); 2777 if (ret) 2778 return ret; 2779 2780 pi->enable_dpm = true; 2781 2782 return 0; 2783 } 2784 2785 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 2786 struct seq_file *m) 2787 { 2788 struct kv_power_info *pi = kv_get_pi(rdev); 2789 u32 current_index = 2790 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> 2791 CURR_SCLK_INDEX_SHIFT; 2792 u32 sclk, tmp; 2793 u16 vddc; 2794 2795 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2796 seq_printf(m, "invalid dpm profile %d\n", current_index); 2797 } else { 2798 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2799 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2800 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT; 2801 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp); 2802 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); 2803 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); 2804 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2805 current_index, sclk, vddc); 2806 } 2807 } 2808 2809 void kv_dpm_print_power_state(struct radeon_device *rdev, 2810 struct radeon_ps *rps) 2811 { 2812 int i; 2813 struct kv_ps *ps = kv_get_ps(rps); 2814 2815 r600_dpm_print_class_info(rps->class, rps->class2); 2816 r600_dpm_print_cap_info(rps->caps); 2817 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2818 for (i = 0; i < ps->num_levels; i++) { 2819 struct kv_pl *pl = &ps->levels[i]; 2820 printk("\t\tpower level %d sclk: %u vddc: %u\n", 2821 i, pl->sclk, 2822 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index)); 2823 } 2824 r600_dpm_print_ps_status(rdev, rps); 2825 } 2826 2827 void kv_dpm_fini(struct radeon_device *rdev) 2828 { 2829 int i; 2830 2831 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 2832 kfree(rdev->pm.dpm.ps[i].ps_priv); 2833 } 2834 kfree(rdev->pm.dpm.ps); 2835 kfree(rdev->pm.dpm.priv); 2836 r600_free_extended_power_table(rdev); 2837 } 2838 2839 void kv_dpm_display_configuration_changed(struct radeon_device *rdev) 2840 { 2841 2842 } 2843 2844 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low) 2845 { 2846 struct kv_power_info *pi = kv_get_pi(rdev); 2847 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2848 2849 if (low) 2850 return requested_state->levels[0].sclk; 2851 else 2852 return requested_state->levels[requested_state->num_levels - 1].sclk; 2853 } 2854 2855 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low) 2856 { 2857 struct kv_power_info *pi = kv_get_pi(rdev); 2858 2859 return pi->sys_info.bootup_uma_clk; 2860 } 2861