1*4cd92098Szrj /* 2*4cd92098Szrj * Copyright 2013 Advanced Micro Devices, Inc. 3*4cd92098Szrj * 4*4cd92098Szrj * Permission is hereby granted, free of charge, to any person obtaining a 5*4cd92098Szrj * copy of this software and associated documentation files (the "Software"), 6*4cd92098Szrj * to deal in the Software without restriction, including without limitation 7*4cd92098Szrj * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4cd92098Szrj * and/or sell copies of the Software, and to permit persons to whom the 9*4cd92098Szrj * Software is furnished to do so, subject to the following conditions: 10*4cd92098Szrj * 11*4cd92098Szrj * The above copyright notice and this permission notice shall be included in 12*4cd92098Szrj * all copies or substantial portions of the Software. 13*4cd92098Szrj * 14*4cd92098Szrj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4cd92098Szrj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4cd92098Szrj * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4cd92098Szrj * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4cd92098Szrj * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4cd92098Szrj * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4cd92098Szrj * OTHER DEALINGS IN THE SOFTWARE. 21*4cd92098Szrj * 22*4cd92098Szrj */ 23*4cd92098Szrj #ifndef __KV_DPM_H__ 24*4cd92098Szrj #define __KV_DPM_H__ 25*4cd92098Szrj 26*4cd92098Szrj #define SMU__NUM_SCLK_DPM_STATE 8 27*4cd92098Szrj #define SMU__NUM_MCLK_DPM_LEVELS 4 28*4cd92098Szrj #define SMU__NUM_LCLK_DPM_LEVELS 8 29*4cd92098Szrj #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ 30*4cd92098Szrj #include "smu7_fusion.h" 31*4cd92098Szrj #include "trinity_dpm.h" 32*4cd92098Szrj #include "ppsmc.h" 33*4cd92098Szrj 34*4cd92098Szrj #define KV_NUM_NBPSTATES 4 35*4cd92098Szrj 36*4cd92098Szrj enum kv_pt_config_reg_type { 37*4cd92098Szrj KV_CONFIGREG_MMR = 0, 38*4cd92098Szrj KV_CONFIGREG_SMC_IND, 39*4cd92098Szrj KV_CONFIGREG_DIDT_IND, 40*4cd92098Szrj KV_CONFIGREG_CACHE, 41*4cd92098Szrj KV_CONFIGREG_MAX 42*4cd92098Szrj }; 43*4cd92098Szrj 44*4cd92098Szrj struct kv_pt_config_reg { 45*4cd92098Szrj u32 offset; 46*4cd92098Szrj u32 mask; 47*4cd92098Szrj u32 shift; 48*4cd92098Szrj u32 value; 49*4cd92098Szrj enum kv_pt_config_reg_type type; 50*4cd92098Szrj }; 51*4cd92098Szrj 52*4cd92098Szrj struct kv_lcac_config_values { 53*4cd92098Szrj u32 block_id; 54*4cd92098Szrj u32 signal_id; 55*4cd92098Szrj u32 t; 56*4cd92098Szrj }; 57*4cd92098Szrj 58*4cd92098Szrj struct kv_lcac_config_reg { 59*4cd92098Szrj u32 cntl; 60*4cd92098Szrj u32 block_mask; 61*4cd92098Szrj u32 block_shift; 62*4cd92098Szrj u32 signal_mask; 63*4cd92098Szrj u32 signal_shift; 64*4cd92098Szrj u32 t_mask; 65*4cd92098Szrj u32 t_shift; 66*4cd92098Szrj u32 enable_mask; 67*4cd92098Szrj u32 enable_shift; 68*4cd92098Szrj }; 69*4cd92098Szrj 70*4cd92098Szrj struct kv_pl { 71*4cd92098Szrj u32 sclk; 72*4cd92098Szrj u8 vddc_index; 73*4cd92098Szrj u8 ds_divider_index; 74*4cd92098Szrj u8 ss_divider_index; 75*4cd92098Szrj u8 allow_gnb_slow; 76*4cd92098Szrj u8 force_nbp_state; 77*4cd92098Szrj u8 display_wm; 78*4cd92098Szrj u8 vce_wm; 79*4cd92098Szrj }; 80*4cd92098Szrj 81*4cd92098Szrj struct kv_ps { 82*4cd92098Szrj struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 83*4cd92098Szrj u32 num_levels; 84*4cd92098Szrj bool need_dfs_bypass; 85*4cd92098Szrj u8 dpm0_pg_nb_ps_lo; 86*4cd92098Szrj u8 dpm0_pg_nb_ps_hi; 87*4cd92098Szrj u8 dpmx_nb_ps_lo; 88*4cd92098Szrj u8 dpmx_nb_ps_hi; 89*4cd92098Szrj }; 90*4cd92098Szrj 91*4cd92098Szrj struct kv_sys_info { 92*4cd92098Szrj u32 bootup_uma_clk; 93*4cd92098Szrj u32 bootup_sclk; 94*4cd92098Szrj u32 dentist_vco_freq; 95*4cd92098Szrj u32 nb_dpm_enable; 96*4cd92098Szrj u32 nbp_memory_clock[KV_NUM_NBPSTATES]; 97*4cd92098Szrj u32 nbp_n_clock[KV_NUM_NBPSTATES]; 98*4cd92098Szrj u16 bootup_nb_voltage_index; 99*4cd92098Szrj u8 htc_tmp_lmt; 100*4cd92098Szrj u8 htc_hyst_lmt; 101*4cd92098Szrj struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 102*4cd92098Szrj struct sumo_vid_mapping_table vid_mapping_table; 103*4cd92098Szrj u32 uma_channel_number; 104*4cd92098Szrj }; 105*4cd92098Szrj 106*4cd92098Szrj struct kv_power_info { 107*4cd92098Szrj u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 108*4cd92098Szrj u32 voltage_drop_t; 109*4cd92098Szrj struct kv_sys_info sys_info; 110*4cd92098Szrj struct kv_pl boot_pl; 111*4cd92098Szrj bool enable_nb_ps_policy; 112*4cd92098Szrj bool disable_nb_ps3_in_battery; 113*4cd92098Szrj bool video_start; 114*4cd92098Szrj bool battery_state; 115*4cd92098Szrj u32 lowest_valid; 116*4cd92098Szrj u32 highest_valid; 117*4cd92098Szrj u16 high_voltage_t; 118*4cd92098Szrj bool cac_enabled; 119*4cd92098Szrj bool bapm_enable; 120*4cd92098Szrj /* smc offsets */ 121*4cd92098Szrj u32 sram_end; 122*4cd92098Szrj u32 dpm_table_start; 123*4cd92098Szrj u32 soft_regs_start; 124*4cd92098Szrj /* dpm SMU tables */ 125*4cd92098Szrj u8 graphics_dpm_level_count; 126*4cd92098Szrj u8 uvd_level_count; 127*4cd92098Szrj u8 vce_level_count; 128*4cd92098Szrj u8 acp_level_count; 129*4cd92098Szrj u8 samu_level_count; 130*4cd92098Szrj u16 fps_high_t; 131*4cd92098Szrj SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; 132*4cd92098Szrj SMU7_Fusion_ACPILevel acpi_level; 133*4cd92098Szrj SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; 134*4cd92098Szrj SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; 135*4cd92098Szrj SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; 136*4cd92098Szrj SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; 137*4cd92098Szrj u8 uvd_boot_level; 138*4cd92098Szrj u8 vce_boot_level; 139*4cd92098Szrj u8 acp_boot_level; 140*4cd92098Szrj u8 samu_boot_level; 141*4cd92098Szrj u8 uvd_interval; 142*4cd92098Szrj u8 vce_interval; 143*4cd92098Szrj u8 acp_interval; 144*4cd92098Szrj u8 samu_interval; 145*4cd92098Szrj u8 graphics_boot_level; 146*4cd92098Szrj u8 graphics_interval; 147*4cd92098Szrj u8 graphics_therm_throttle_enable; 148*4cd92098Szrj u8 graphics_voltage_change_enable; 149*4cd92098Szrj u8 graphics_clk_slow_enable; 150*4cd92098Szrj u8 graphics_clk_slow_divider; 151*4cd92098Szrj u8 fps_low_t; 152*4cd92098Szrj u32 low_sclk_interrupt_t; 153*4cd92098Szrj bool uvd_power_gated; 154*4cd92098Szrj bool vce_power_gated; 155*4cd92098Szrj bool acp_power_gated; 156*4cd92098Szrj bool samu_power_gated; 157*4cd92098Szrj bool nb_dpm_enabled; 158*4cd92098Szrj /* flags */ 159*4cd92098Szrj bool enable_didt; 160*4cd92098Szrj bool enable_dpm; 161*4cd92098Szrj bool enable_auto_thermal_throttling; 162*4cd92098Szrj bool enable_nb_dpm; 163*4cd92098Szrj /* caps */ 164*4cd92098Szrj bool caps_cac; 165*4cd92098Szrj bool caps_power_containment; 166*4cd92098Szrj bool caps_sq_ramping; 167*4cd92098Szrj bool caps_db_ramping; 168*4cd92098Szrj bool caps_td_ramping; 169*4cd92098Szrj bool caps_tcp_ramping; 170*4cd92098Szrj bool caps_sclk_throttle_low_notification; 171*4cd92098Szrj bool caps_fps; 172*4cd92098Szrj bool caps_uvd_dpm; 173*4cd92098Szrj bool caps_uvd_pg; 174*4cd92098Szrj bool caps_vce_pg; 175*4cd92098Szrj bool caps_samu_pg; 176*4cd92098Szrj bool caps_acp_pg; 177*4cd92098Szrj bool caps_stable_p_state; 178*4cd92098Szrj bool caps_enable_dfs_bypass; 179*4cd92098Szrj bool caps_sclk_ds; 180*4cd92098Szrj struct radeon_ps current_rps; 181*4cd92098Szrj struct kv_ps current_ps; 182*4cd92098Szrj struct radeon_ps requested_rps; 183*4cd92098Szrj struct kv_ps requested_ps; 184*4cd92098Szrj }; 185*4cd92098Szrj 186*4cd92098Szrj 187*4cd92098Szrj /* kv_smc.c */ 188*4cd92098Szrj int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id); 189*4cd92098Szrj int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask); 190*4cd92098Szrj int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 191*4cd92098Szrj PPSMC_Msg msg, u32 parameter); 192*4cd92098Szrj int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 193*4cd92098Szrj u32 *value, u32 limit); 194*4cd92098Szrj int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable); 195*4cd92098Szrj int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable); 196*4cd92098Szrj int kv_copy_bytes_to_smc(struct radeon_device *rdev, 197*4cd92098Szrj u32 smc_start_address, 198*4cd92098Szrj const u8 *src, u32 byte_count, u32 limit); 199*4cd92098Szrj 200*4cd92098Szrj #endif 201