1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2010 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * 4926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 5926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 6926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 7926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 9926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 10926deccbSFrançois Tigeot * 11926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 12926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 13926deccbSFrançois Tigeot * 14926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 21926deccbSFrançois Tigeot * 22926deccbSFrançois Tigeot * Authors: Alex Deucher 23926deccbSFrançois Tigeot */ 24926deccbSFrançois Tigeot #ifndef NI_H 25926deccbSFrançois Tigeot #define NI_H 26926deccbSFrançois Tigeot 27926deccbSFrançois Tigeot #define CAYMAN_MAX_SH_GPRS 256 28926deccbSFrançois Tigeot #define CAYMAN_MAX_TEMP_GPRS 16 29926deccbSFrançois Tigeot #define CAYMAN_MAX_SH_THREADS 256 30926deccbSFrançois Tigeot #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31926deccbSFrançois Tigeot #define CAYMAN_MAX_FRC_EOV_CNT 16384 32926deccbSFrançois Tigeot #define CAYMAN_MAX_BACKENDS 8 33926deccbSFrançois Tigeot #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34926deccbSFrançois Tigeot #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35926deccbSFrançois Tigeot #define CAYMAN_MAX_SIMDS 16 36926deccbSFrançois Tigeot #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37926deccbSFrançois Tigeot #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38926deccbSFrançois Tigeot #define CAYMAN_MAX_PIPES 8 39926deccbSFrançois Tigeot #define CAYMAN_MAX_PIPES_MASK 0xFF 40926deccbSFrançois Tigeot #define CAYMAN_MAX_LDS_NUM 0xFFFF 41926deccbSFrançois Tigeot #define CAYMAN_MAX_TCC 16 42926deccbSFrançois Tigeot #define CAYMAN_MAX_TCC_MASK 0xFF 43926deccbSFrançois Tigeot 44926deccbSFrançois Tigeot #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45926deccbSFrançois Tigeot #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46926deccbSFrançois Tigeot 47926deccbSFrançois Tigeot #define DMIF_ADDR_CONFIG 0xBD4 48f43cf1b1SMichael Neumann 49c59a5c48SFrançois Tigeot /* fusion vce clocks */ 50c59a5c48SFrançois Tigeot #define CG_ECLK_CNTL 0x620 51c59a5c48SFrançois Tigeot # define ECLK_DIVIDER_MASK 0x7f 52c59a5c48SFrançois Tigeot # define ECLK_DIR_CNTL_EN (1 << 8) 53c59a5c48SFrançois Tigeot #define CG_ECLK_STATUS 0x624 54c59a5c48SFrançois Tigeot # define ECLK_STATUS (1 << 0) 55c59a5c48SFrançois Tigeot 56f43cf1b1SMichael Neumann /* DCE6 only */ 57f43cf1b1SMichael Neumann #define DMIF_ADDR_CALC 0xC00 58f43cf1b1SMichael Neumann 59926deccbSFrançois Tigeot #define SRBM_GFX_CNTL 0x0E44 60926deccbSFrançois Tigeot #define RINGID(x) (((x) & 0x3) << 0) 61926deccbSFrançois Tigeot #define VMID(x) (((x) & 0x7) << 0) 62926deccbSFrançois Tigeot #define SRBM_STATUS 0x0E50 63b403bed8SMichael Neumann #define RLC_RQ_PENDING (1 << 3) 64b403bed8SMichael Neumann #define GRBM_RQ_PENDING (1 << 5) 65b403bed8SMichael Neumann #define VMC_BUSY (1 << 8) 66b403bed8SMichael Neumann #define MCB_BUSY (1 << 9) 67b403bed8SMichael Neumann #define MCB_NON_DISPLAY_BUSY (1 << 10) 68b403bed8SMichael Neumann #define MCC_BUSY (1 << 11) 69b403bed8SMichael Neumann #define MCD_BUSY (1 << 12) 70b403bed8SMichael Neumann #define SEM_BUSY (1 << 14) 71b403bed8SMichael Neumann #define RLC_BUSY (1 << 15) 72b403bed8SMichael Neumann #define IH_BUSY (1 << 17) 73926deccbSFrançois Tigeot 74926deccbSFrançois Tigeot #define SRBM_SOFT_RESET 0x0E60 75926deccbSFrançois Tigeot #define SOFT_RESET_BIF (1 << 1) 76926deccbSFrançois Tigeot #define SOFT_RESET_CG (1 << 2) 77926deccbSFrançois Tigeot #define SOFT_RESET_DC (1 << 5) 78926deccbSFrançois Tigeot #define SOFT_RESET_DMA1 (1 << 6) 79926deccbSFrançois Tigeot #define SOFT_RESET_GRBM (1 << 8) 80926deccbSFrançois Tigeot #define SOFT_RESET_HDP (1 << 9) 81926deccbSFrançois Tigeot #define SOFT_RESET_IH (1 << 10) 82926deccbSFrançois Tigeot #define SOFT_RESET_MC (1 << 11) 83926deccbSFrançois Tigeot #define SOFT_RESET_RLC (1 << 13) 84926deccbSFrançois Tigeot #define SOFT_RESET_ROM (1 << 14) 85926deccbSFrançois Tigeot #define SOFT_RESET_SEM (1 << 15) 86926deccbSFrançois Tigeot #define SOFT_RESET_VMC (1 << 17) 87926deccbSFrançois Tigeot #define SOFT_RESET_DMA (1 << 20) 88926deccbSFrançois Tigeot #define SOFT_RESET_TST (1 << 21) 89926deccbSFrançois Tigeot #define SOFT_RESET_REGBB (1 << 22) 90926deccbSFrançois Tigeot #define SOFT_RESET_ORB (1 << 23) 91926deccbSFrançois Tigeot 92c59a5c48SFrançois Tigeot #define SRBM_READ_ERROR 0xE98 93c59a5c48SFrançois Tigeot #define SRBM_INT_CNTL 0xEA0 94c59a5c48SFrançois Tigeot #define SRBM_INT_ACK 0xEA8 95c59a5c48SFrançois Tigeot 96b403bed8SMichael Neumann #define SRBM_STATUS2 0x0EC4 97b403bed8SMichael Neumann #define DMA_BUSY (1 << 5) 98b403bed8SMichael Neumann #define DMA1_BUSY (1 << 6) 99b403bed8SMichael Neumann 100926deccbSFrançois Tigeot #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 101926deccbSFrançois Tigeot #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 102926deccbSFrançois Tigeot #define RESPONSE_TYPE_MASK 0x000000F0 103926deccbSFrançois Tigeot #define RESPONSE_TYPE_SHIFT 4 104926deccbSFrançois Tigeot #define VM_L2_CNTL 0x1400 105926deccbSFrançois Tigeot #define ENABLE_L2_CACHE (1 << 0) 106926deccbSFrançois Tigeot #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 107926deccbSFrançois Tigeot #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 108926deccbSFrançois Tigeot #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 109926deccbSFrançois Tigeot #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 110926deccbSFrançois Tigeot #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 111926deccbSFrançois Tigeot /* CONTEXT1_IDENTITY_ACCESS_MODE 112926deccbSFrançois Tigeot * 0 physical = logical 113926deccbSFrançois Tigeot * 1 logical via context1 page table 114926deccbSFrançois Tigeot * 2 inside identity aperture use translation, outside physical = logical 115926deccbSFrançois Tigeot * 3 inside identity aperture physical = logical, outside use translation 116926deccbSFrançois Tigeot */ 117926deccbSFrançois Tigeot #define VM_L2_CNTL2 0x1404 118926deccbSFrançois Tigeot #define INVALIDATE_ALL_L1_TLBS (1 << 0) 119926deccbSFrançois Tigeot #define INVALIDATE_L2_CACHE (1 << 1) 120926deccbSFrançois Tigeot #define VM_L2_CNTL3 0x1408 121926deccbSFrançois Tigeot #define BANK_SELECT(x) ((x) << 0) 122926deccbSFrançois Tigeot #define CACHE_UPDATE_MODE(x) ((x) << 6) 123926deccbSFrançois Tigeot #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 124926deccbSFrançois Tigeot #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 125926deccbSFrançois Tigeot #define VM_L2_STATUS 0x140C 126926deccbSFrançois Tigeot #define L2_BUSY (1 << 0) 127926deccbSFrançois Tigeot #define VM_CONTEXT0_CNTL 0x1410 128926deccbSFrançois Tigeot #define ENABLE_CONTEXT (1 << 0) 129926deccbSFrançois Tigeot #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 130926deccbSFrançois Tigeot #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 131926deccbSFrançois Tigeot #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 132926deccbSFrançois Tigeot #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 133926deccbSFrançois Tigeot #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 134926deccbSFrançois Tigeot #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 135926deccbSFrançois Tigeot #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 136926deccbSFrançois Tigeot #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 137926deccbSFrançois Tigeot #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 138926deccbSFrançois Tigeot #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 139926deccbSFrançois Tigeot #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 140926deccbSFrançois Tigeot #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 141926deccbSFrançois Tigeot #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 142c6f73aabSFrançois Tigeot #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 143926deccbSFrançois Tigeot #define VM_CONTEXT1_CNTL 0x1414 144926deccbSFrançois Tigeot #define VM_CONTEXT0_CNTL2 0x1430 145926deccbSFrançois Tigeot #define VM_CONTEXT1_CNTL2 0x1434 146926deccbSFrançois Tigeot #define VM_INVALIDATE_REQUEST 0x1478 147926deccbSFrançois Tigeot #define VM_INVALIDATE_RESPONSE 0x147c 14857e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 14957e252bfSMichael Neumann #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 15057e252bfSMichael Neumann #define PROTECTIONS_MASK (0xf << 0) 15157e252bfSMichael Neumann #define PROTECTIONS_SHIFT 0 15257e252bfSMichael Neumann /* bit 0: range 15357e252bfSMichael Neumann * bit 2: pde0 15457e252bfSMichael Neumann * bit 3: valid 15557e252bfSMichael Neumann * bit 4: read 15657e252bfSMichael Neumann * bit 5: write 15757e252bfSMichael Neumann */ 15857e252bfSMichael Neumann #define MEMORY_CLIENT_ID_MASK (0xff << 12) 15957e252bfSMichael Neumann #define MEMORY_CLIENT_ID_SHIFT 12 16057e252bfSMichael Neumann #define MEMORY_CLIENT_RW_MASK (1 << 24) 16157e252bfSMichael Neumann #define MEMORY_CLIENT_RW_SHIFT 24 16257e252bfSMichael Neumann #define FAULT_VMID_MASK (0x7 << 25) 16357e252bfSMichael Neumann #define FAULT_VMID_SHIFT 25 164926deccbSFrançois Tigeot #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 165926deccbSFrançois Tigeot #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 166926deccbSFrançois Tigeot #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 167926deccbSFrançois Tigeot #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 168926deccbSFrançois Tigeot #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 169926deccbSFrançois Tigeot 170926deccbSFrançois Tigeot #define MC_SHARED_CHMAP 0x2004 171926deccbSFrançois Tigeot #define NOOFCHAN_SHIFT 12 172926deccbSFrançois Tigeot #define NOOFCHAN_MASK 0x00003000 173926deccbSFrançois Tigeot #define MC_SHARED_CHREMAP 0x2008 174926deccbSFrançois Tigeot 175926deccbSFrançois Tigeot #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 176926deccbSFrançois Tigeot #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 177926deccbSFrançois Tigeot #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 178926deccbSFrançois Tigeot #define MC_VM_MX_L1_TLB_CNTL 0x2064 179926deccbSFrançois Tigeot #define ENABLE_L1_TLB (1 << 0) 180926deccbSFrançois Tigeot #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 181926deccbSFrançois Tigeot #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 182926deccbSFrançois Tigeot #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 183926deccbSFrançois Tigeot #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 184926deccbSFrançois Tigeot #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 185926deccbSFrançois Tigeot #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 186926deccbSFrançois Tigeot #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 187926deccbSFrançois Tigeot #define FUS_MC_VM_FB_OFFSET 0x2068 188926deccbSFrançois Tigeot 189926deccbSFrançois Tigeot #define MC_SHARED_BLACKOUT_CNTL 0x20ac 190926deccbSFrançois Tigeot #define MC_ARB_RAMCFG 0x2760 191926deccbSFrançois Tigeot #define NOOFBANK_SHIFT 0 192926deccbSFrançois Tigeot #define NOOFBANK_MASK 0x00000003 193926deccbSFrançois Tigeot #define NOOFRANK_SHIFT 2 194926deccbSFrançois Tigeot #define NOOFRANK_MASK 0x00000004 195926deccbSFrançois Tigeot #define NOOFROWS_SHIFT 3 196926deccbSFrançois Tigeot #define NOOFROWS_MASK 0x00000038 197926deccbSFrançois Tigeot #define NOOFCOLS_SHIFT 6 198926deccbSFrançois Tigeot #define NOOFCOLS_MASK 0x000000C0 199926deccbSFrançois Tigeot #define CHANSIZE_SHIFT 8 200926deccbSFrançois Tigeot #define CHANSIZE_MASK 0x00000100 201926deccbSFrançois Tigeot #define BURSTLENGTH_SHIFT 9 202926deccbSFrançois Tigeot #define BURSTLENGTH_MASK 0x00000200 203926deccbSFrançois Tigeot #define CHANSIZE_OVERRIDE (1 << 11) 204926deccbSFrançois Tigeot #define MC_SEQ_SUP_CNTL 0x28c8 205926deccbSFrançois Tigeot #define RUN_MASK (1 << 0) 206926deccbSFrançois Tigeot #define MC_SEQ_SUP_PGM 0x28cc 207926deccbSFrançois Tigeot #define MC_IO_PAD_CNTL_D0 0x29d0 208926deccbSFrançois Tigeot #define MEM_FALL_OUT_CMD (1 << 8) 209926deccbSFrançois Tigeot #define MC_SEQ_MISC0 0x2a00 210926deccbSFrançois Tigeot #define MC_SEQ_MISC0_GDDR5_SHIFT 28 211926deccbSFrançois Tigeot #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 212926deccbSFrançois Tigeot #define MC_SEQ_MISC0_GDDR5_VALUE 5 213926deccbSFrançois Tigeot #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 214926deccbSFrançois Tigeot #define MC_SEQ_IO_DEBUG_DATA 0x2a48 215926deccbSFrançois Tigeot 216926deccbSFrançois Tigeot #define HDP_HOST_PATH_CNTL 0x2C00 217926deccbSFrançois Tigeot #define HDP_NONSURFACE_BASE 0x2C04 218926deccbSFrançois Tigeot #define HDP_NONSURFACE_INFO 0x2C08 219926deccbSFrançois Tigeot #define HDP_NONSURFACE_SIZE 0x2C0C 220926deccbSFrançois Tigeot #define HDP_ADDR_CONFIG 0x2F48 221926deccbSFrançois Tigeot #define HDP_MISC_CNTL 0x2F4C 222926deccbSFrançois Tigeot #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 223926deccbSFrançois Tigeot 224926deccbSFrançois Tigeot #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 225926deccbSFrançois Tigeot #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 226926deccbSFrançois Tigeot #define CGTS_SYS_TCC_DISABLE 0x3F90 227926deccbSFrançois Tigeot #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 228926deccbSFrançois Tigeot 229926deccbSFrançois Tigeot #define RLC_GFX_INDEX 0x3FC4 230926deccbSFrançois Tigeot 231926deccbSFrançois Tigeot #define CONFIG_MEMSIZE 0x5428 232926deccbSFrançois Tigeot 233926deccbSFrançois Tigeot #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 234926deccbSFrançois Tigeot #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 235926deccbSFrançois Tigeot 236926deccbSFrançois Tigeot #define GRBM_CNTL 0x8000 237926deccbSFrançois Tigeot #define GRBM_READ_TIMEOUT(x) ((x) << 0) 238926deccbSFrançois Tigeot #define GRBM_STATUS 0x8010 239926deccbSFrançois Tigeot #define CMDFIFO_AVAIL_MASK 0x0000000F 240926deccbSFrançois Tigeot #define RING2_RQ_PENDING (1 << 4) 241926deccbSFrançois Tigeot #define SRBM_RQ_PENDING (1 << 5) 242926deccbSFrançois Tigeot #define RING1_RQ_PENDING (1 << 6) 243926deccbSFrançois Tigeot #define CF_RQ_PENDING (1 << 7) 244926deccbSFrançois Tigeot #define PF_RQ_PENDING (1 << 8) 245926deccbSFrançois Tigeot #define GDS_DMA_RQ_PENDING (1 << 9) 246926deccbSFrançois Tigeot #define GRBM_EE_BUSY (1 << 10) 247926deccbSFrançois Tigeot #define SX_CLEAN (1 << 11) 248926deccbSFrançois Tigeot #define DB_CLEAN (1 << 12) 249926deccbSFrançois Tigeot #define CB_CLEAN (1 << 13) 250926deccbSFrançois Tigeot #define TA_BUSY (1 << 14) 251926deccbSFrançois Tigeot #define GDS_BUSY (1 << 15) 252926deccbSFrançois Tigeot #define VGT_BUSY_NO_DMA (1 << 16) 253926deccbSFrançois Tigeot #define VGT_BUSY (1 << 17) 254926deccbSFrançois Tigeot #define IA_BUSY_NO_DMA (1 << 18) 255926deccbSFrançois Tigeot #define IA_BUSY (1 << 19) 256926deccbSFrançois Tigeot #define SX_BUSY (1 << 20) 257926deccbSFrançois Tigeot #define SH_BUSY (1 << 21) 258926deccbSFrançois Tigeot #define SPI_BUSY (1 << 22) 259926deccbSFrançois Tigeot #define SC_BUSY (1 << 24) 260926deccbSFrançois Tigeot #define PA_BUSY (1 << 25) 261926deccbSFrançois Tigeot #define DB_BUSY (1 << 26) 262926deccbSFrançois Tigeot #define CP_COHERENCY_BUSY (1 << 28) 263926deccbSFrançois Tigeot #define CP_BUSY (1 << 29) 264926deccbSFrançois Tigeot #define CB_BUSY (1 << 30) 265926deccbSFrançois Tigeot #define GUI_ACTIVE (1 << 31) 266926deccbSFrançois Tigeot #define GRBM_STATUS_SE0 0x8014 267926deccbSFrançois Tigeot #define GRBM_STATUS_SE1 0x8018 268926deccbSFrançois Tigeot #define SE_SX_CLEAN (1 << 0) 269926deccbSFrançois Tigeot #define SE_DB_CLEAN (1 << 1) 270926deccbSFrançois Tigeot #define SE_CB_CLEAN (1 << 2) 271926deccbSFrançois Tigeot #define SE_VGT_BUSY (1 << 23) 272926deccbSFrançois Tigeot #define SE_PA_BUSY (1 << 24) 273926deccbSFrançois Tigeot #define SE_TA_BUSY (1 << 25) 274926deccbSFrançois Tigeot #define SE_SX_BUSY (1 << 26) 275926deccbSFrançois Tigeot #define SE_SPI_BUSY (1 << 27) 276926deccbSFrançois Tigeot #define SE_SH_BUSY (1 << 28) 277926deccbSFrançois Tigeot #define SE_SC_BUSY (1 << 29) 278926deccbSFrançois Tigeot #define SE_DB_BUSY (1 << 30) 279926deccbSFrançois Tigeot #define SE_CB_BUSY (1 << 31) 280926deccbSFrançois Tigeot #define GRBM_SOFT_RESET 0x8020 281926deccbSFrançois Tigeot #define SOFT_RESET_CP (1 << 0) 282926deccbSFrançois Tigeot #define SOFT_RESET_CB (1 << 1) 283926deccbSFrançois Tigeot #define SOFT_RESET_DB (1 << 3) 284926deccbSFrançois Tigeot #define SOFT_RESET_GDS (1 << 4) 285926deccbSFrançois Tigeot #define SOFT_RESET_PA (1 << 5) 286926deccbSFrançois Tigeot #define SOFT_RESET_SC (1 << 6) 287926deccbSFrançois Tigeot #define SOFT_RESET_SPI (1 << 8) 288926deccbSFrançois Tigeot #define SOFT_RESET_SH (1 << 9) 289926deccbSFrançois Tigeot #define SOFT_RESET_SX (1 << 10) 290926deccbSFrançois Tigeot #define SOFT_RESET_TC (1 << 11) 291926deccbSFrançois Tigeot #define SOFT_RESET_TA (1 << 12) 292926deccbSFrançois Tigeot #define SOFT_RESET_VGT (1 << 14) 293926deccbSFrançois Tigeot #define SOFT_RESET_IA (1 << 15) 294926deccbSFrançois Tigeot 295926deccbSFrançois Tigeot #define GRBM_GFX_INDEX 0x802C 296926deccbSFrançois Tigeot #define INSTANCE_INDEX(x) ((x) << 0) 297926deccbSFrançois Tigeot #define SE_INDEX(x) ((x) << 16) 298926deccbSFrançois Tigeot #define INSTANCE_BROADCAST_WRITES (1 << 30) 299926deccbSFrançois Tigeot #define SE_BROADCAST_WRITES (1 << 31) 300926deccbSFrançois Tigeot 301926deccbSFrançois Tigeot #define SCRATCH_REG0 0x8500 302926deccbSFrançois Tigeot #define SCRATCH_REG1 0x8504 303926deccbSFrançois Tigeot #define SCRATCH_REG2 0x8508 304926deccbSFrançois Tigeot #define SCRATCH_REG3 0x850C 305926deccbSFrançois Tigeot #define SCRATCH_REG4 0x8510 306926deccbSFrançois Tigeot #define SCRATCH_REG5 0x8514 307926deccbSFrançois Tigeot #define SCRATCH_REG6 0x8518 308926deccbSFrançois Tigeot #define SCRATCH_REG7 0x851C 309926deccbSFrançois Tigeot #define SCRATCH_UMSK 0x8540 310926deccbSFrançois Tigeot #define SCRATCH_ADDR 0x8544 311926deccbSFrançois Tigeot #define CP_SEM_WAIT_TIMER 0x85BC 312926deccbSFrançois Tigeot #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 313926deccbSFrançois Tigeot #define CP_COHER_CNTL2 0x85E8 314926deccbSFrançois Tigeot #define CP_STALLED_STAT1 0x8674 315926deccbSFrançois Tigeot #define CP_STALLED_STAT2 0x8678 316926deccbSFrançois Tigeot #define CP_BUSY_STAT 0x867C 317926deccbSFrançois Tigeot #define CP_STAT 0x8680 318926deccbSFrançois Tigeot #define CP_ME_CNTL 0x86D8 319926deccbSFrançois Tigeot #define CP_ME_HALT (1 << 28) 320926deccbSFrançois Tigeot #define CP_PFP_HALT (1 << 26) 321926deccbSFrançois Tigeot #define CP_RB2_RPTR 0x86f8 322926deccbSFrançois Tigeot #define CP_RB1_RPTR 0x86fc 323926deccbSFrançois Tigeot #define CP_RB0_RPTR 0x8700 324926deccbSFrançois Tigeot #define CP_RB_WPTR_DELAY 0x8704 325926deccbSFrançois Tigeot #define CP_MEQ_THRESHOLDS 0x8764 326926deccbSFrançois Tigeot #define MEQ1_START(x) ((x) << 0) 327926deccbSFrançois Tigeot #define MEQ2_START(x) ((x) << 8) 328926deccbSFrançois Tigeot #define CP_PERFMON_CNTL 0x87FC 329926deccbSFrançois Tigeot 330926deccbSFrançois Tigeot #define VGT_CACHE_INVALIDATION 0x88C4 331926deccbSFrançois Tigeot #define CACHE_INVALIDATION(x) ((x) << 0) 332926deccbSFrançois Tigeot #define VC_ONLY 0 333926deccbSFrançois Tigeot #define TC_ONLY 1 334926deccbSFrançois Tigeot #define VC_AND_TC 2 335926deccbSFrançois Tigeot #define AUTO_INVLD_EN(x) ((x) << 6) 336926deccbSFrançois Tigeot #define NO_AUTO 0 337926deccbSFrançois Tigeot #define ES_AUTO 1 338926deccbSFrançois Tigeot #define GS_AUTO 2 339926deccbSFrançois Tigeot #define ES_AND_GS_AUTO 3 340926deccbSFrançois Tigeot #define VGT_GS_VERTEX_REUSE 0x88D4 341926deccbSFrançois Tigeot 342926deccbSFrançois Tigeot #define CC_GC_SHADER_PIPE_CONFIG 0x8950 343926deccbSFrançois Tigeot #define GC_USER_SHADER_PIPE_CONFIG 0x8954 344926deccbSFrançois Tigeot #define INACTIVE_QD_PIPES(x) ((x) << 8) 345926deccbSFrançois Tigeot #define INACTIVE_QD_PIPES_MASK 0x0000FF00 346926deccbSFrançois Tigeot #define INACTIVE_QD_PIPES_SHIFT 8 347926deccbSFrançois Tigeot #define INACTIVE_SIMDS(x) ((x) << 16) 348926deccbSFrançois Tigeot #define INACTIVE_SIMDS_MASK 0xFFFF0000 349926deccbSFrançois Tigeot #define INACTIVE_SIMDS_SHIFT 16 350926deccbSFrançois Tigeot 351926deccbSFrançois Tigeot #define VGT_PRIMITIVE_TYPE 0x8958 352926deccbSFrançois Tigeot #define VGT_NUM_INSTANCES 0x8974 353926deccbSFrançois Tigeot #define VGT_TF_RING_SIZE 0x8988 354926deccbSFrançois Tigeot #define VGT_OFFCHIP_LDS_BASE 0x89b4 355926deccbSFrançois Tigeot 356926deccbSFrançois Tigeot #define PA_SC_LINE_STIPPLE_STATE 0x8B10 357926deccbSFrançois Tigeot #define PA_CL_ENHANCE 0x8A14 358926deccbSFrançois Tigeot #define CLIP_VTX_REORDER_ENA (1 << 0) 359926deccbSFrançois Tigeot #define NUM_CLIP_SEQ(x) ((x) << 1) 360926deccbSFrançois Tigeot #define PA_SC_FIFO_SIZE 0x8BCC 361926deccbSFrançois Tigeot #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 362926deccbSFrançois Tigeot #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 363926deccbSFrançois Tigeot #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 364926deccbSFrançois Tigeot #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 365926deccbSFrançois Tigeot #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 366926deccbSFrançois Tigeot #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 367926deccbSFrançois Tigeot 368926deccbSFrançois Tigeot #define SQ_CONFIG 0x8C00 369926deccbSFrançois Tigeot #define VC_ENABLE (1 << 0) 370926deccbSFrançois Tigeot #define EXPORT_SRC_C (1 << 1) 371926deccbSFrançois Tigeot #define GFX_PRIO(x) ((x) << 2) 372926deccbSFrançois Tigeot #define CS1_PRIO(x) ((x) << 4) 373926deccbSFrançois Tigeot #define CS2_PRIO(x) ((x) << 6) 374926deccbSFrançois Tigeot #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 375926deccbSFrançois Tigeot #define NUM_PS_GPRS(x) ((x) << 0) 376926deccbSFrançois Tigeot #define NUM_VS_GPRS(x) ((x) << 16) 377926deccbSFrançois Tigeot #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 378926deccbSFrançois Tigeot #define SQ_ESGS_RING_SIZE 0x8c44 379926deccbSFrançois Tigeot #define SQ_GSVS_RING_SIZE 0x8c4c 380926deccbSFrançois Tigeot #define SQ_ESTMP_RING_BASE 0x8c50 381926deccbSFrançois Tigeot #define SQ_ESTMP_RING_SIZE 0x8c54 382926deccbSFrançois Tigeot #define SQ_GSTMP_RING_BASE 0x8c58 383926deccbSFrançois Tigeot #define SQ_GSTMP_RING_SIZE 0x8c5c 384926deccbSFrançois Tigeot #define SQ_VSTMP_RING_BASE 0x8c60 385926deccbSFrançois Tigeot #define SQ_VSTMP_RING_SIZE 0x8c64 386926deccbSFrançois Tigeot #define SQ_PSTMP_RING_BASE 0x8c68 387926deccbSFrançois Tigeot #define SQ_PSTMP_RING_SIZE 0x8c6c 388926deccbSFrançois Tigeot #define SQ_MS_FIFO_SIZES 0x8CF0 389926deccbSFrançois Tigeot #define CACHE_FIFO_SIZE(x) ((x) << 0) 390926deccbSFrançois Tigeot #define FETCH_FIFO_HIWATER(x) ((x) << 8) 391926deccbSFrançois Tigeot #define DONE_FIFO_HIWATER(x) ((x) << 16) 392926deccbSFrançois Tigeot #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 393926deccbSFrançois Tigeot #define SQ_LSTMP_RING_BASE 0x8e10 394926deccbSFrançois Tigeot #define SQ_LSTMP_RING_SIZE 0x8e14 395926deccbSFrançois Tigeot #define SQ_HSTMP_RING_BASE 0x8e18 396926deccbSFrançois Tigeot #define SQ_HSTMP_RING_SIZE 0x8e1c 397926deccbSFrançois Tigeot #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 398926deccbSFrançois Tigeot #define DYN_GPR_ENABLE (1 << 8) 399926deccbSFrançois Tigeot #define SQ_CONST_MEM_BASE 0x8df8 400926deccbSFrançois Tigeot 401926deccbSFrançois Tigeot #define SX_EXPORT_BUFFER_SIZES 0x900C 402926deccbSFrançois Tigeot #define COLOR_BUFFER_SIZE(x) ((x) << 0) 403926deccbSFrançois Tigeot #define POSITION_BUFFER_SIZE(x) ((x) << 8) 404926deccbSFrançois Tigeot #define SMX_BUFFER_SIZE(x) ((x) << 16) 405926deccbSFrançois Tigeot #define SX_DEBUG_1 0x9058 406926deccbSFrançois Tigeot #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 407926deccbSFrançois Tigeot 408926deccbSFrançois Tigeot #define SPI_CONFIG_CNTL 0x9100 409926deccbSFrançois Tigeot #define GPR_WRITE_PRIORITY(x) ((x) << 0) 410926deccbSFrançois Tigeot #define SPI_CONFIG_CNTL_1 0x913C 411926deccbSFrançois Tigeot #define VTX_DONE_DELAY(x) ((x) << 0) 412926deccbSFrançois Tigeot #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 413926deccbSFrançois Tigeot #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 414926deccbSFrançois Tigeot 415926deccbSFrançois Tigeot #define CGTS_TCC_DISABLE 0x9148 416926deccbSFrançois Tigeot #define CGTS_USER_TCC_DISABLE 0x914C 417926deccbSFrançois Tigeot #define TCC_DISABLE_MASK 0xFFFF0000 418926deccbSFrançois Tigeot #define TCC_DISABLE_SHIFT 16 419926deccbSFrançois Tigeot #define CGTS_SM_CTRL_REG 0x9150 420926deccbSFrançois Tigeot #define OVERRIDE (1 << 21) 421926deccbSFrançois Tigeot 422926deccbSFrançois Tigeot #define TA_CNTL_AUX 0x9508 423926deccbSFrançois Tigeot #define DISABLE_CUBE_WRAP (1 << 0) 424926deccbSFrançois Tigeot #define DISABLE_CUBE_ANISO (1 << 1) 425926deccbSFrançois Tigeot 426926deccbSFrançois Tigeot #define TCP_CHAN_STEER_LO 0x960c 427926deccbSFrançois Tigeot #define TCP_CHAN_STEER_HI 0x9610 428926deccbSFrançois Tigeot 429926deccbSFrançois Tigeot #define CC_RB_BACKEND_DISABLE 0x98F4 430926deccbSFrançois Tigeot #define BACKEND_DISABLE(x) ((x) << 16) 431926deccbSFrançois Tigeot #define GB_ADDR_CONFIG 0x98F8 432926deccbSFrançois Tigeot #define NUM_PIPES(x) ((x) << 0) 433926deccbSFrançois Tigeot #define NUM_PIPES_MASK 0x00000007 434926deccbSFrançois Tigeot #define NUM_PIPES_SHIFT 0 435926deccbSFrançois Tigeot #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 436926deccbSFrançois Tigeot #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 437926deccbSFrançois Tigeot #define PIPE_INTERLEAVE_SIZE_SHIFT 4 438926deccbSFrançois Tigeot #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 439926deccbSFrançois Tigeot #define NUM_SHADER_ENGINES(x) ((x) << 12) 440926deccbSFrançois Tigeot #define NUM_SHADER_ENGINES_MASK 0x00003000 441926deccbSFrançois Tigeot #define NUM_SHADER_ENGINES_SHIFT 12 442926deccbSFrançois Tigeot #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 443926deccbSFrançois Tigeot #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 444926deccbSFrançois Tigeot #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 445926deccbSFrançois Tigeot #define NUM_GPUS(x) ((x) << 20) 446926deccbSFrançois Tigeot #define NUM_GPUS_MASK 0x00700000 447926deccbSFrançois Tigeot #define NUM_GPUS_SHIFT 20 448926deccbSFrançois Tigeot #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 449926deccbSFrançois Tigeot #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 450926deccbSFrançois Tigeot #define MULTI_GPU_TILE_SIZE_SHIFT 24 451926deccbSFrançois Tigeot #define ROW_SIZE(x) ((x) << 28) 452926deccbSFrançois Tigeot #define ROW_SIZE_MASK 0x30000000 453926deccbSFrançois Tigeot #define ROW_SIZE_SHIFT 28 454926deccbSFrançois Tigeot #define NUM_LOWER_PIPES(x) ((x) << 30) 455926deccbSFrançois Tigeot #define NUM_LOWER_PIPES_MASK 0x40000000 456926deccbSFrançois Tigeot #define NUM_LOWER_PIPES_SHIFT 30 457926deccbSFrançois Tigeot #define GB_BACKEND_MAP 0x98FC 458926deccbSFrançois Tigeot 459926deccbSFrançois Tigeot #define CB_PERF_CTR0_SEL_0 0x9A20 460926deccbSFrançois Tigeot #define CB_PERF_CTR0_SEL_1 0x9A24 461926deccbSFrançois Tigeot #define CB_PERF_CTR1_SEL_0 0x9A28 462926deccbSFrançois Tigeot #define CB_PERF_CTR1_SEL_1 0x9A2C 463926deccbSFrançois Tigeot #define CB_PERF_CTR2_SEL_0 0x9A30 464926deccbSFrançois Tigeot #define CB_PERF_CTR2_SEL_1 0x9A34 465926deccbSFrançois Tigeot #define CB_PERF_CTR3_SEL_0 0x9A38 466926deccbSFrançois Tigeot #define CB_PERF_CTR3_SEL_1 0x9A3C 467926deccbSFrançois Tigeot 468926deccbSFrançois Tigeot #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 469926deccbSFrançois Tigeot #define BACKEND_DISABLE_MASK 0x00FF0000 470926deccbSFrançois Tigeot #define BACKEND_DISABLE_SHIFT 16 471926deccbSFrançois Tigeot 472926deccbSFrançois Tigeot #define SMX_DC_CTL0 0xA020 473926deccbSFrançois Tigeot #define USE_HASH_FUNCTION (1 << 0) 474926deccbSFrançois Tigeot #define NUMBER_OF_SETS(x) ((x) << 1) 475926deccbSFrançois Tigeot #define FLUSH_ALL_ON_EVENT (1 << 10) 476926deccbSFrançois Tigeot #define STALL_ON_EVENT (1 << 11) 477926deccbSFrançois Tigeot #define SMX_EVENT_CTL 0xA02C 478926deccbSFrançois Tigeot #define ES_FLUSH_CTL(x) ((x) << 0) 479926deccbSFrançois Tigeot #define GS_FLUSH_CTL(x) ((x) << 3) 480926deccbSFrançois Tigeot #define ACK_FLUSH_CTL(x) ((x) << 6) 481926deccbSFrançois Tigeot #define SYNC_FLUSH_CTL (1 << 8) 482926deccbSFrançois Tigeot 483926deccbSFrançois Tigeot #define CP_RB0_BASE 0xC100 484926deccbSFrançois Tigeot #define CP_RB0_CNTL 0xC104 485926deccbSFrançois Tigeot #define RB_BUFSZ(x) ((x) << 0) 486926deccbSFrançois Tigeot #define RB_BLKSZ(x) ((x) << 8) 487926deccbSFrançois Tigeot #define RB_NO_UPDATE (1 << 27) 488926deccbSFrançois Tigeot #define RB_RPTR_WR_ENA (1 << 31) 489926deccbSFrançois Tigeot #define BUF_SWAP_32BIT (2 << 16) 490926deccbSFrançois Tigeot #define CP_RB0_RPTR_ADDR 0xC10C 491926deccbSFrançois Tigeot #define CP_RB0_RPTR_ADDR_HI 0xC110 492926deccbSFrançois Tigeot #define CP_RB0_WPTR 0xC114 493926deccbSFrançois Tigeot 494926deccbSFrançois Tigeot #define CP_INT_CNTL 0xC124 495926deccbSFrançois Tigeot # define CNTX_BUSY_INT_ENABLE (1 << 19) 496926deccbSFrançois Tigeot # define CNTX_EMPTY_INT_ENABLE (1 << 20) 497926deccbSFrançois Tigeot # define TIME_STAMP_INT_ENABLE (1 << 26) 498926deccbSFrançois Tigeot 499926deccbSFrançois Tigeot #define CP_RB1_BASE 0xC180 500926deccbSFrançois Tigeot #define CP_RB1_CNTL 0xC184 501926deccbSFrançois Tigeot #define CP_RB1_RPTR_ADDR 0xC188 502926deccbSFrançois Tigeot #define CP_RB1_RPTR_ADDR_HI 0xC18C 503926deccbSFrançois Tigeot #define CP_RB1_WPTR 0xC190 504926deccbSFrançois Tigeot #define CP_RB2_BASE 0xC194 505926deccbSFrançois Tigeot #define CP_RB2_CNTL 0xC198 506926deccbSFrançois Tigeot #define CP_RB2_RPTR_ADDR 0xC19C 507926deccbSFrançois Tigeot #define CP_RB2_RPTR_ADDR_HI 0xC1A0 508926deccbSFrançois Tigeot #define CP_RB2_WPTR 0xC1A4 509926deccbSFrançois Tigeot #define CP_PFP_UCODE_ADDR 0xC150 510926deccbSFrançois Tigeot #define CP_PFP_UCODE_DATA 0xC154 511926deccbSFrançois Tigeot #define CP_ME_RAM_RADDR 0xC158 512926deccbSFrançois Tigeot #define CP_ME_RAM_WADDR 0xC15C 513926deccbSFrançois Tigeot #define CP_ME_RAM_DATA 0xC160 514926deccbSFrançois Tigeot #define CP_DEBUG 0xC1FC 515926deccbSFrançois Tigeot 516926deccbSFrançois Tigeot #define VGT_EVENT_INITIATOR 0x28a90 517926deccbSFrançois Tigeot # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 518926deccbSFrançois Tigeot # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 519926deccbSFrançois Tigeot 52057e252bfSMichael Neumann /* TN SMU registers */ 52157e252bfSMichael Neumann #define TN_CURRENT_GNB_TEMP 0x1F390 52257e252bfSMichael Neumann 52357e252bfSMichael Neumann /* pm registers */ 52457e252bfSMichael Neumann #define SMC_MSG 0x20c 52557e252bfSMichael Neumann #define HOST_SMC_MSG(x) ((x) << 0) 52657e252bfSMichael Neumann #define HOST_SMC_MSG_MASK (0xff << 0) 52757e252bfSMichael Neumann #define HOST_SMC_MSG_SHIFT 0 52857e252bfSMichael Neumann #define HOST_SMC_RESP(x) ((x) << 8) 52957e252bfSMichael Neumann #define HOST_SMC_RESP_MASK (0xff << 8) 53057e252bfSMichael Neumann #define HOST_SMC_RESP_SHIFT 8 53157e252bfSMichael Neumann #define SMC_HOST_MSG(x) ((x) << 16) 53257e252bfSMichael Neumann #define SMC_HOST_MSG_MASK (0xff << 16) 53357e252bfSMichael Neumann #define SMC_HOST_MSG_SHIFT 16 53457e252bfSMichael Neumann #define SMC_HOST_RESP(x) ((x) << 24) 53557e252bfSMichael Neumann #define SMC_HOST_RESP_MASK (0xff << 24) 53657e252bfSMichael Neumann #define SMC_HOST_RESP_SHIFT 24 53757e252bfSMichael Neumann 53857e252bfSMichael Neumann #define CG_SPLL_FUNC_CNTL 0x600 53957e252bfSMichael Neumann #define SPLL_RESET (1 << 0) 54057e252bfSMichael Neumann #define SPLL_SLEEP (1 << 1) 54157e252bfSMichael Neumann #define SPLL_BYPASS_EN (1 << 3) 54257e252bfSMichael Neumann #define SPLL_REF_DIV(x) ((x) << 4) 54357e252bfSMichael Neumann #define SPLL_REF_DIV_MASK (0x3f << 4) 54457e252bfSMichael Neumann #define SPLL_PDIV_A(x) ((x) << 20) 54557e252bfSMichael Neumann #define SPLL_PDIV_A_MASK (0x7f << 20) 54657e252bfSMichael Neumann #define SPLL_PDIV_A_SHIFT 20 54757e252bfSMichael Neumann #define CG_SPLL_FUNC_CNTL_2 0x604 54857e252bfSMichael Neumann #define SCLK_MUX_SEL(x) ((x) << 0) 54957e252bfSMichael Neumann #define SCLK_MUX_SEL_MASK (0x1ff << 0) 55057e252bfSMichael Neumann #define CG_SPLL_FUNC_CNTL_3 0x608 55157e252bfSMichael Neumann #define SPLL_FB_DIV(x) ((x) << 0) 55257e252bfSMichael Neumann #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 55357e252bfSMichael Neumann #define SPLL_FB_DIV_SHIFT 0 55457e252bfSMichael Neumann #define SPLL_DITHEN (1 << 28) 55557e252bfSMichael Neumann 55657e252bfSMichael Neumann #define MPLL_CNTL_MODE 0x61c 55757e252bfSMichael Neumann # define SS_SSEN (1 << 24) 55857e252bfSMichael Neumann # define SS_DSMODE_EN (1 << 25) 55957e252bfSMichael Neumann 56057e252bfSMichael Neumann #define MPLL_AD_FUNC_CNTL 0x624 56157e252bfSMichael Neumann #define CLKF(x) ((x) << 0) 56257e252bfSMichael Neumann #define CLKF_MASK (0x7f << 0) 56357e252bfSMichael Neumann #define CLKR(x) ((x) << 7) 56457e252bfSMichael Neumann #define CLKR_MASK (0x1f << 7) 56557e252bfSMichael Neumann #define CLKFRAC(x) ((x) << 12) 56657e252bfSMichael Neumann #define CLKFRAC_MASK (0x1f << 12) 56757e252bfSMichael Neumann #define YCLK_POST_DIV(x) ((x) << 17) 56857e252bfSMichael Neumann #define YCLK_POST_DIV_MASK (3 << 17) 56957e252bfSMichael Neumann #define IBIAS(x) ((x) << 20) 57057e252bfSMichael Neumann #define IBIAS_MASK (0x3ff << 20) 57157e252bfSMichael Neumann #define RESET (1 << 30) 57257e252bfSMichael Neumann #define PDNB (1 << 31) 57357e252bfSMichael Neumann #define MPLL_AD_FUNC_CNTL_2 0x628 57457e252bfSMichael Neumann #define BYPASS (1 << 19) 57557e252bfSMichael Neumann #define BIAS_GEN_PDNB (1 << 24) 57657e252bfSMichael Neumann #define RESET_EN (1 << 25) 57757e252bfSMichael Neumann #define VCO_MODE (1 << 29) 57857e252bfSMichael Neumann #define MPLL_DQ_FUNC_CNTL 0x62c 57957e252bfSMichael Neumann #define MPLL_DQ_FUNC_CNTL_2 0x630 58057e252bfSMichael Neumann 58157e252bfSMichael Neumann #define GENERAL_PWRMGT 0x63c 58257e252bfSMichael Neumann # define GLOBAL_PWRMGT_EN (1 << 0) 58357e252bfSMichael Neumann # define STATIC_PM_EN (1 << 1) 58457e252bfSMichael Neumann # define THERMAL_PROTECTION_DIS (1 << 2) 58557e252bfSMichael Neumann # define THERMAL_PROTECTION_TYPE (1 << 3) 58657e252bfSMichael Neumann # define ENABLE_GEN2PCIE (1 << 4) 58757e252bfSMichael Neumann # define ENABLE_GEN2XSP (1 << 5) 58857e252bfSMichael Neumann # define SW_SMIO_INDEX(x) ((x) << 6) 58957e252bfSMichael Neumann # define SW_SMIO_INDEX_MASK (3 << 6) 59057e252bfSMichael Neumann # define SW_SMIO_INDEX_SHIFT 6 59157e252bfSMichael Neumann # define LOW_VOLT_D2_ACPI (1 << 8) 59257e252bfSMichael Neumann # define LOW_VOLT_D3_ACPI (1 << 9) 59357e252bfSMichael Neumann # define VOLT_PWRMGT_EN (1 << 10) 59457e252bfSMichael Neumann # define BACKBIAS_PAD_EN (1 << 18) 59557e252bfSMichael Neumann # define BACKBIAS_VALUE (1 << 19) 59657e252bfSMichael Neumann # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 59757e252bfSMichael Neumann # define AC_DC_SW (1 << 24) 59857e252bfSMichael Neumann 59957e252bfSMichael Neumann #define SCLK_PWRMGT_CNTL 0x644 60057e252bfSMichael Neumann # define SCLK_PWRMGT_OFF (1 << 0) 60157e252bfSMichael Neumann # define SCLK_LOW_D1 (1 << 1) 60257e252bfSMichael Neumann # define FIR_RESET (1 << 4) 60357e252bfSMichael Neumann # define FIR_FORCE_TREND_SEL (1 << 5) 60457e252bfSMichael Neumann # define FIR_TREND_MODE (1 << 6) 60557e252bfSMichael Neumann # define DYN_GFX_CLK_OFF_EN (1 << 7) 60657e252bfSMichael Neumann # define GFX_CLK_FORCE_ON (1 << 8) 60757e252bfSMichael Neumann # define GFX_CLK_REQUEST_OFF (1 << 9) 60857e252bfSMichael Neumann # define GFX_CLK_FORCE_OFF (1 << 10) 60957e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 61057e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 61157e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 61257e252bfSMichael Neumann # define DYN_LIGHT_SLEEP_EN (1 << 14) 61357e252bfSMichael Neumann #define MCLK_PWRMGT_CNTL 0x648 61457e252bfSMichael Neumann # define DLL_SPEED(x) ((x) << 0) 61557e252bfSMichael Neumann # define DLL_SPEED_MASK (0x1f << 0) 61657e252bfSMichael Neumann # define MPLL_PWRMGT_OFF (1 << 5) 61757e252bfSMichael Neumann # define DLL_READY (1 << 6) 61857e252bfSMichael Neumann # define MC_INT_CNTL (1 << 7) 61957e252bfSMichael Neumann # define MRDCKA0_PDNB (1 << 8) 62057e252bfSMichael Neumann # define MRDCKA1_PDNB (1 << 9) 62157e252bfSMichael Neumann # define MRDCKB0_PDNB (1 << 10) 62257e252bfSMichael Neumann # define MRDCKB1_PDNB (1 << 11) 62357e252bfSMichael Neumann # define MRDCKC0_PDNB (1 << 12) 62457e252bfSMichael Neumann # define MRDCKC1_PDNB (1 << 13) 62557e252bfSMichael Neumann # define MRDCKD0_PDNB (1 << 14) 62657e252bfSMichael Neumann # define MRDCKD1_PDNB (1 << 15) 62757e252bfSMichael Neumann # define MRDCKA0_RESET (1 << 16) 62857e252bfSMichael Neumann # define MRDCKA1_RESET (1 << 17) 62957e252bfSMichael Neumann # define MRDCKB0_RESET (1 << 18) 63057e252bfSMichael Neumann # define MRDCKB1_RESET (1 << 19) 63157e252bfSMichael Neumann # define MRDCKC0_RESET (1 << 20) 63257e252bfSMichael Neumann # define MRDCKC1_RESET (1 << 21) 63357e252bfSMichael Neumann # define MRDCKD0_RESET (1 << 22) 63457e252bfSMichael Neumann # define MRDCKD1_RESET (1 << 23) 63557e252bfSMichael Neumann # define DLL_READY_READ (1 << 24) 63657e252bfSMichael Neumann # define USE_DISPLAY_GAP (1 << 25) 63757e252bfSMichael Neumann # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 63857e252bfSMichael Neumann # define MPLL_TURNOFF_D2 (1 << 28) 63957e252bfSMichael Neumann #define DLL_CNTL 0x64c 64057e252bfSMichael Neumann # define MRDCKA0_BYPASS (1 << 24) 64157e252bfSMichael Neumann # define MRDCKA1_BYPASS (1 << 25) 64257e252bfSMichael Neumann # define MRDCKB0_BYPASS (1 << 26) 64357e252bfSMichael Neumann # define MRDCKB1_BYPASS (1 << 27) 64457e252bfSMichael Neumann # define MRDCKC0_BYPASS (1 << 28) 64557e252bfSMichael Neumann # define MRDCKC1_BYPASS (1 << 29) 64657e252bfSMichael Neumann # define MRDCKD0_BYPASS (1 << 30) 64757e252bfSMichael Neumann # define MRDCKD1_BYPASS (1 << 31) 64857e252bfSMichael Neumann 64957e252bfSMichael Neumann #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 65057e252bfSMichael Neumann # define CURRENT_STATE_INDEX_MASK (0xf << 4) 65157e252bfSMichael Neumann # define CURRENT_STATE_INDEX_SHIFT 4 65257e252bfSMichael Neumann 65357e252bfSMichael Neumann #define CG_AT 0x6d4 65457e252bfSMichael Neumann # define CG_R(x) ((x) << 0) 65557e252bfSMichael Neumann # define CG_R_MASK (0xffff << 0) 65657e252bfSMichael Neumann # define CG_L(x) ((x) << 16) 65757e252bfSMichael Neumann # define CG_L_MASK (0xffff << 16) 65857e252bfSMichael Neumann 65957e252bfSMichael Neumann #define CG_BIF_REQ_AND_RSP 0x7f4 66057e252bfSMichael Neumann #define CG_CLIENT_REQ(x) ((x) << 0) 66157e252bfSMichael Neumann #define CG_CLIENT_REQ_MASK (0xff << 0) 66257e252bfSMichael Neumann #define CG_CLIENT_REQ_SHIFT 0 66357e252bfSMichael Neumann #define CG_CLIENT_RESP(x) ((x) << 8) 66457e252bfSMichael Neumann #define CG_CLIENT_RESP_MASK (0xff << 8) 66557e252bfSMichael Neumann #define CG_CLIENT_RESP_SHIFT 8 66657e252bfSMichael Neumann #define CLIENT_CG_REQ(x) ((x) << 16) 66757e252bfSMichael Neumann #define CLIENT_CG_REQ_MASK (0xff << 16) 66857e252bfSMichael Neumann #define CLIENT_CG_REQ_SHIFT 16 66957e252bfSMichael Neumann #define CLIENT_CG_RESP(x) ((x) << 24) 67057e252bfSMichael Neumann #define CLIENT_CG_RESP_MASK (0xff << 24) 67157e252bfSMichael Neumann #define CLIENT_CG_RESP_SHIFT 24 67257e252bfSMichael Neumann 67357e252bfSMichael Neumann #define CG_SPLL_SPREAD_SPECTRUM 0x790 67457e252bfSMichael Neumann #define SSEN (1 << 0) 67557e252bfSMichael Neumann #define CLK_S(x) ((x) << 4) 67657e252bfSMichael Neumann #define CLK_S_MASK (0xfff << 4) 67757e252bfSMichael Neumann #define CLK_S_SHIFT 4 67857e252bfSMichael Neumann #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 67957e252bfSMichael Neumann #define CLK_V(x) ((x) << 0) 68057e252bfSMichael Neumann #define CLK_V_MASK (0x3ffffff << 0) 68157e252bfSMichael Neumann #define CLK_V_SHIFT 0 68257e252bfSMichael Neumann 68357e252bfSMichael Neumann #define SMC_SCRATCH0 0x81c 68457e252bfSMichael Neumann 68557e252bfSMichael Neumann #define CG_SPLL_FUNC_CNTL_4 0x850 68657e252bfSMichael Neumann 68757e252bfSMichael Neumann #define MPLL_SS1 0x85c 68857e252bfSMichael Neumann #define CLKV(x) ((x) << 0) 68957e252bfSMichael Neumann #define CLKV_MASK (0x3ffffff << 0) 69057e252bfSMichael Neumann #define MPLL_SS2 0x860 69157e252bfSMichael Neumann #define CLKS(x) ((x) << 0) 69257e252bfSMichael Neumann #define CLKS_MASK (0xfff << 0) 69357e252bfSMichael Neumann 69457e252bfSMichael Neumann #define CG_CAC_CTRL 0x88c 69557e252bfSMichael Neumann #define TID_CNT(x) ((x) << 0) 69657e252bfSMichael Neumann #define TID_CNT_MASK (0x3fff << 0) 69757e252bfSMichael Neumann #define TID_UNIT(x) ((x) << 14) 69857e252bfSMichael Neumann #define TID_UNIT_MASK (0xf << 14) 69957e252bfSMichael Neumann 70057e252bfSMichael Neumann #define CG_IND_ADDR 0x8f8 70157e252bfSMichael Neumann #define CG_IND_DATA 0x8fc 70257e252bfSMichael Neumann /* CGIND regs */ 70357e252bfSMichael Neumann #define CG_CGTT_LOCAL_0 0x00 70457e252bfSMichael Neumann #define CG_CGTT_LOCAL_1 0x01 70557e252bfSMichael Neumann 70657e252bfSMichael Neumann #define MC_CG_CONFIG 0x25bc 70757e252bfSMichael Neumann #define MCDW_WR_ENABLE (1 << 0) 70857e252bfSMichael Neumann #define MCDX_WR_ENABLE (1 << 1) 70957e252bfSMichael Neumann #define MCDY_WR_ENABLE (1 << 2) 71057e252bfSMichael Neumann #define MCDZ_WR_ENABLE (1 << 3) 71157e252bfSMichael Neumann #define MC_RD_ENABLE(x) ((x) << 4) 71257e252bfSMichael Neumann #define MC_RD_ENABLE_MASK (3 << 4) 71357e252bfSMichael Neumann #define INDEX(x) ((x) << 6) 71457e252bfSMichael Neumann #define INDEX_MASK (0xfff << 6) 71557e252bfSMichael Neumann #define INDEX_SHIFT 6 71657e252bfSMichael Neumann 71757e252bfSMichael Neumann #define MC_ARB_CAC_CNTL 0x2750 71857e252bfSMichael Neumann #define ENABLE (1 << 0) 71957e252bfSMichael Neumann #define READ_WEIGHT(x) ((x) << 1) 72057e252bfSMichael Neumann #define READ_WEIGHT_MASK (0x3f << 1) 72157e252bfSMichael Neumann #define READ_WEIGHT_SHIFT 1 72257e252bfSMichael Neumann #define WRITE_WEIGHT(x) ((x) << 7) 72357e252bfSMichael Neumann #define WRITE_WEIGHT_MASK (0x3f << 7) 72457e252bfSMichael Neumann #define WRITE_WEIGHT_SHIFT 7 72557e252bfSMichael Neumann #define ALLOW_OVERFLOW (1 << 13) 72657e252bfSMichael Neumann 72757e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING 0x2774 72857e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING2 0x2778 72957e252bfSMichael Neumann 73057e252bfSMichael Neumann #define MC_ARB_RFSH_RATE 0x27b0 73157e252bfSMichael Neumann #define POWERMODE0(x) ((x) << 0) 73257e252bfSMichael Neumann #define POWERMODE0_MASK (0xff << 0) 73357e252bfSMichael Neumann #define POWERMODE0_SHIFT 0 73457e252bfSMichael Neumann #define POWERMODE1(x) ((x) << 8) 73557e252bfSMichael Neumann #define POWERMODE1_MASK (0xff << 8) 73657e252bfSMichael Neumann #define POWERMODE1_SHIFT 8 73757e252bfSMichael Neumann #define POWERMODE2(x) ((x) << 16) 73857e252bfSMichael Neumann #define POWERMODE2_MASK (0xff << 16) 73957e252bfSMichael Neumann #define POWERMODE2_SHIFT 16 74057e252bfSMichael Neumann #define POWERMODE3(x) ((x) << 24) 74157e252bfSMichael Neumann #define POWERMODE3_MASK (0xff << 24) 74257e252bfSMichael Neumann #define POWERMODE3_SHIFT 24 74357e252bfSMichael Neumann 74457e252bfSMichael Neumann #define MC_ARB_CG 0x27e8 74557e252bfSMichael Neumann #define CG_ARB_REQ(x) ((x) << 0) 74657e252bfSMichael Neumann #define CG_ARB_REQ_MASK (0xff << 0) 74757e252bfSMichael Neumann #define CG_ARB_REQ_SHIFT 0 74857e252bfSMichael Neumann #define CG_ARB_RESP(x) ((x) << 8) 74957e252bfSMichael Neumann #define CG_ARB_RESP_MASK (0xff << 8) 75057e252bfSMichael Neumann #define CG_ARB_RESP_SHIFT 8 75157e252bfSMichael Neumann #define ARB_CG_REQ(x) ((x) << 16) 75257e252bfSMichael Neumann #define ARB_CG_REQ_MASK (0xff << 16) 75357e252bfSMichael Neumann #define ARB_CG_REQ_SHIFT 16 75457e252bfSMichael Neumann #define ARB_CG_RESP(x) ((x) << 24) 75557e252bfSMichael Neumann #define ARB_CG_RESP_MASK (0xff << 24) 75657e252bfSMichael Neumann #define ARB_CG_RESP_SHIFT 24 75757e252bfSMichael Neumann 75857e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING_1 0x27f0 75957e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING_2 0x27f4 76057e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING_3 0x27f8 76157e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING2_1 0x27fc 76257e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING2_2 0x2800 76357e252bfSMichael Neumann #define MC_ARB_DRAM_TIMING2_3 0x2804 76457e252bfSMichael Neumann #define MC_ARB_BURST_TIME 0x2808 76557e252bfSMichael Neumann #define STATE0(x) ((x) << 0) 76657e252bfSMichael Neumann #define STATE0_MASK (0x1f << 0) 76757e252bfSMichael Neumann #define STATE0_SHIFT 0 76857e252bfSMichael Neumann #define STATE1(x) ((x) << 5) 76957e252bfSMichael Neumann #define STATE1_MASK (0x1f << 5) 77057e252bfSMichael Neumann #define STATE1_SHIFT 5 77157e252bfSMichael Neumann #define STATE2(x) ((x) << 10) 77257e252bfSMichael Neumann #define STATE2_MASK (0x1f << 10) 77357e252bfSMichael Neumann #define STATE2_SHIFT 10 77457e252bfSMichael Neumann #define STATE3(x) ((x) << 15) 77557e252bfSMichael Neumann #define STATE3_MASK (0x1f << 15) 77657e252bfSMichael Neumann #define STATE3_SHIFT 15 77757e252bfSMichael Neumann 77857e252bfSMichael Neumann #define MC_CG_DATAPORT 0x2884 77957e252bfSMichael Neumann 78057e252bfSMichael Neumann #define MC_SEQ_RAS_TIMING 0x28a0 78157e252bfSMichael Neumann #define MC_SEQ_CAS_TIMING 0x28a4 78257e252bfSMichael Neumann #define MC_SEQ_MISC_TIMING 0x28a8 78357e252bfSMichael Neumann #define MC_SEQ_MISC_TIMING2 0x28ac 78457e252bfSMichael Neumann #define MC_SEQ_PMG_TIMING 0x28b0 78557e252bfSMichael Neumann #define MC_SEQ_RD_CTL_D0 0x28b4 78657e252bfSMichael Neumann #define MC_SEQ_RD_CTL_D1 0x28b8 78757e252bfSMichael Neumann #define MC_SEQ_WR_CTL_D0 0x28bc 78857e252bfSMichael Neumann #define MC_SEQ_WR_CTL_D1 0x28c0 78957e252bfSMichael Neumann 79057e252bfSMichael Neumann #define MC_SEQ_MISC0 0x2a00 79157e252bfSMichael Neumann #define MC_SEQ_MISC0_GDDR5_SHIFT 28 79257e252bfSMichael Neumann #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 79357e252bfSMichael Neumann #define MC_SEQ_MISC0_GDDR5_VALUE 5 79457e252bfSMichael Neumann #define MC_SEQ_MISC1 0x2a04 79557e252bfSMichael Neumann #define MC_SEQ_RESERVE_M 0x2a08 79657e252bfSMichael Neumann #define MC_PMG_CMD_EMRS 0x2a0c 79757e252bfSMichael Neumann 79857e252bfSMichael Neumann #define MC_SEQ_MISC3 0x2a2c 79957e252bfSMichael Neumann 80057e252bfSMichael Neumann #define MC_SEQ_MISC5 0x2a54 80157e252bfSMichael Neumann #define MC_SEQ_MISC6 0x2a58 80257e252bfSMichael Neumann 80357e252bfSMichael Neumann #define MC_SEQ_MISC7 0x2a64 80457e252bfSMichael Neumann 80557e252bfSMichael Neumann #define MC_SEQ_RAS_TIMING_LP 0x2a6c 80657e252bfSMichael Neumann #define MC_SEQ_CAS_TIMING_LP 0x2a70 80757e252bfSMichael Neumann #define MC_SEQ_MISC_TIMING_LP 0x2a74 80857e252bfSMichael Neumann #define MC_SEQ_MISC_TIMING2_LP 0x2a78 80957e252bfSMichael Neumann #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 81057e252bfSMichael Neumann #define MC_SEQ_WR_CTL_D1_LP 0x2a80 81157e252bfSMichael Neumann #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 81257e252bfSMichael Neumann #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 81357e252bfSMichael Neumann 81457e252bfSMichael Neumann #define MC_PMG_CMD_MRS 0x2aac 81557e252bfSMichael Neumann 81657e252bfSMichael Neumann #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 81757e252bfSMichael Neumann #define MC_SEQ_RD_CTL_D1_LP 0x2b20 81857e252bfSMichael Neumann 81957e252bfSMichael Neumann #define MC_PMG_CMD_MRS1 0x2b44 82057e252bfSMichael Neumann #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 82157e252bfSMichael Neumann #define MC_SEQ_PMG_TIMING_LP 0x2b4c 82257e252bfSMichael Neumann 82357e252bfSMichael Neumann #define MC_PMG_CMD_MRS2 0x2b5c 82457e252bfSMichael Neumann #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 82557e252bfSMichael Neumann 826c59a5c48SFrançois Tigeot #define AUX_CONTROL 0x6200 827c59a5c48SFrançois Tigeot #define AUX_EN (1 << 0) 828c59a5c48SFrançois Tigeot #define AUX_LS_READ_EN (1 << 8) 829c59a5c48SFrançois Tigeot #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) 830c59a5c48SFrançois Tigeot #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) 831c59a5c48SFrançois Tigeot #define AUX_DET_EN (1 << 18) 832c59a5c48SFrançois Tigeot #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) 833c59a5c48SFrançois Tigeot #define AUX_IMPCAL_REQ_EN (1 << 24) 834c59a5c48SFrançois Tigeot #define AUX_TEST_MODE (1 << 28) 835c59a5c48SFrançois Tigeot #define AUX_DEGLITCH_EN (1 << 29) 836c59a5c48SFrançois Tigeot #define AUX_SW_CONTROL 0x6204 837c59a5c48SFrançois Tigeot #define AUX_SW_GO (1 << 0) 838c59a5c48SFrançois Tigeot #define AUX_LS_READ_TRIG (1 << 2) 839c59a5c48SFrançois Tigeot #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) 840c59a5c48SFrançois Tigeot #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) 841c59a5c48SFrançois Tigeot 842c59a5c48SFrançois Tigeot #define AUX_SW_INTERRUPT_CONTROL 0x620c 843c59a5c48SFrançois Tigeot #define AUX_SW_DONE_INT (1 << 0) 844c59a5c48SFrançois Tigeot #define AUX_SW_DONE_ACK (1 << 1) 845c59a5c48SFrançois Tigeot #define AUX_SW_DONE_MASK (1 << 2) 846c59a5c48SFrançois Tigeot #define AUX_SW_LS_DONE_INT (1 << 4) 847c59a5c48SFrançois Tigeot #define AUX_SW_LS_DONE_MASK (1 << 6) 848c59a5c48SFrançois Tigeot #define AUX_SW_STATUS 0x6210 849c59a5c48SFrançois Tigeot #define AUX_SW_DONE (1 << 0) 850c59a5c48SFrançois Tigeot #define AUX_SW_REQ (1 << 1) 851c59a5c48SFrançois Tigeot #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) 852c59a5c48SFrançois Tigeot #define AUX_SW_RX_TIMEOUT (1 << 7) 853c59a5c48SFrançois Tigeot #define AUX_SW_RX_OVERFLOW (1 << 8) 854c59a5c48SFrançois Tigeot #define AUX_SW_RX_HPD_DISCON (1 << 9) 855c59a5c48SFrançois Tigeot #define AUX_SW_RX_PARTIAL_BYTE (1 << 10) 856c59a5c48SFrançois Tigeot #define AUX_SW_NON_AUX_MODE (1 << 11) 857c59a5c48SFrançois Tigeot #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12) 858c59a5c48SFrançois Tigeot #define AUX_SW_RX_INVALID_STOP (1 << 14) 859c59a5c48SFrançois Tigeot #define AUX_SW_RX_SYNC_INVALID_L (1 << 17) 860c59a5c48SFrançois Tigeot #define AUX_SW_RX_SYNC_INVALID_H (1 << 18) 861c59a5c48SFrançois Tigeot #define AUX_SW_RX_INVALID_START (1 << 19) 862c59a5c48SFrançois Tigeot #define AUX_SW_RX_RECV_NO_DET (1 << 20) 863c59a5c48SFrançois Tigeot #define AUX_SW_RX_RECV_INVALID_H (1 << 22) 864c59a5c48SFrançois Tigeot #define AUX_SW_RX_RECV_INVALID_V (1 << 23) 865c59a5c48SFrançois Tigeot 866c59a5c48SFrançois Tigeot #define AUX_SW_DATA 0x6218 867c59a5c48SFrançois Tigeot #define AUX_SW_DATA_RW (1 << 0) 868c59a5c48SFrançois Tigeot #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) 869c59a5c48SFrançois Tigeot #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) 870c59a5c48SFrançois Tigeot #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) 871c59a5c48SFrançois Tigeot 87257e252bfSMichael Neumann #define LB_SYNC_RESET_SEL 0x6b28 87357e252bfSMichael Neumann #define LB_SYNC_RESET_SEL_MASK (3 << 0) 87457e252bfSMichael Neumann #define LB_SYNC_RESET_SEL_SHIFT 0 87557e252bfSMichael Neumann 87657e252bfSMichael Neumann #define DC_STUTTER_CNTL 0x6b30 87757e252bfSMichael Neumann #define DC_STUTTER_ENABLE_A (1 << 0) 87857e252bfSMichael Neumann #define DC_STUTTER_ENABLE_B (1 << 1) 87957e252bfSMichael Neumann 88057e252bfSMichael Neumann #define SQ_CAC_THRESHOLD 0x8e4c 88157e252bfSMichael Neumann #define VSP(x) ((x) << 0) 88257e252bfSMichael Neumann #define VSP_MASK (0xff << 0) 88357e252bfSMichael Neumann #define VSP_SHIFT 0 88457e252bfSMichael Neumann #define VSP0(x) ((x) << 8) 88557e252bfSMichael Neumann #define VSP0_MASK (0xff << 8) 88657e252bfSMichael Neumann #define VSP0_SHIFT 8 88757e252bfSMichael Neumann #define GPR(x) ((x) << 16) 88857e252bfSMichael Neumann #define GPR_MASK (0xff << 16) 88957e252bfSMichael Neumann #define GPR_SHIFT 16 89057e252bfSMichael Neumann 89157e252bfSMichael Neumann #define SQ_POWER_THROTTLE 0x8e58 89257e252bfSMichael Neumann #define MIN_POWER(x) ((x) << 0) 89357e252bfSMichael Neumann #define MIN_POWER_MASK (0x3fff << 0) 89457e252bfSMichael Neumann #define MIN_POWER_SHIFT 0 89557e252bfSMichael Neumann #define MAX_POWER(x) ((x) << 16) 89657e252bfSMichael Neumann #define MAX_POWER_MASK (0x3fff << 16) 89757e252bfSMichael Neumann #define MAX_POWER_SHIFT 0 89857e252bfSMichael Neumann #define SQ_POWER_THROTTLE2 0x8e5c 89957e252bfSMichael Neumann #define MAX_POWER_DELTA(x) ((x) << 0) 90057e252bfSMichael Neumann #define MAX_POWER_DELTA_MASK (0x3fff << 0) 90157e252bfSMichael Neumann #define MAX_POWER_DELTA_SHIFT 0 90257e252bfSMichael Neumann #define STI_SIZE(x) ((x) << 16) 90357e252bfSMichael Neumann #define STI_SIZE_MASK (0x3ff << 16) 90457e252bfSMichael Neumann #define STI_SIZE_SHIFT 16 90557e252bfSMichael Neumann #define LTI_RATIO(x) ((x) << 27) 90657e252bfSMichael Neumann #define LTI_RATIO_MASK (0xf << 27) 90757e252bfSMichael Neumann #define LTI_RATIO_SHIFT 27 90857e252bfSMichael Neumann 90957e252bfSMichael Neumann /* CG indirect registers */ 91057e252bfSMichael Neumann #define CG_CAC_REGION_1_WEIGHT_0 0x83 91157e252bfSMichael Neumann #define WEIGHT_TCP_SIG0(x) ((x) << 0) 91257e252bfSMichael Neumann #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) 91357e252bfSMichael Neumann #define WEIGHT_TCP_SIG0_SHIFT 0 91457e252bfSMichael Neumann #define WEIGHT_TCP_SIG1(x) ((x) << 6) 91557e252bfSMichael Neumann #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) 91657e252bfSMichael Neumann #define WEIGHT_TCP_SIG1_SHIFT 6 91757e252bfSMichael Neumann #define WEIGHT_TA_SIG(x) ((x) << 12) 91857e252bfSMichael Neumann #define WEIGHT_TA_SIG_MASK (0x3f << 12) 91957e252bfSMichael Neumann #define WEIGHT_TA_SIG_SHIFT 12 92057e252bfSMichael Neumann #define CG_CAC_REGION_1_WEIGHT_1 0x84 92157e252bfSMichael Neumann #define WEIGHT_TCC_EN0(x) ((x) << 0) 92257e252bfSMichael Neumann #define WEIGHT_TCC_EN0_MASK (0x3f << 0) 92357e252bfSMichael Neumann #define WEIGHT_TCC_EN0_SHIFT 0 92457e252bfSMichael Neumann #define WEIGHT_TCC_EN1(x) ((x) << 6) 92557e252bfSMichael Neumann #define WEIGHT_TCC_EN1_MASK (0x3f << 6) 92657e252bfSMichael Neumann #define WEIGHT_TCC_EN1_SHIFT 6 92757e252bfSMichael Neumann #define WEIGHT_TCC_EN2(x) ((x) << 12) 92857e252bfSMichael Neumann #define WEIGHT_TCC_EN2_MASK (0x3f << 12) 92957e252bfSMichael Neumann #define WEIGHT_TCC_EN2_SHIFT 12 93057e252bfSMichael Neumann #define WEIGHT_TCC_EN3(x) ((x) << 18) 93157e252bfSMichael Neumann #define WEIGHT_TCC_EN3_MASK (0x3f << 18) 93257e252bfSMichael Neumann #define WEIGHT_TCC_EN3_SHIFT 18 93357e252bfSMichael Neumann #define CG_CAC_REGION_2_WEIGHT_0 0x85 93457e252bfSMichael Neumann #define WEIGHT_CB_EN0(x) ((x) << 0) 93557e252bfSMichael Neumann #define WEIGHT_CB_EN0_MASK (0x3f << 0) 93657e252bfSMichael Neumann #define WEIGHT_CB_EN0_SHIFT 0 93757e252bfSMichael Neumann #define WEIGHT_CB_EN1(x) ((x) << 6) 93857e252bfSMichael Neumann #define WEIGHT_CB_EN1_MASK (0x3f << 6) 93957e252bfSMichael Neumann #define WEIGHT_CB_EN1_SHIFT 6 94057e252bfSMichael Neumann #define WEIGHT_CB_EN2(x) ((x) << 12) 94157e252bfSMichael Neumann #define WEIGHT_CB_EN2_MASK (0x3f << 12) 94257e252bfSMichael Neumann #define WEIGHT_CB_EN2_SHIFT 12 94357e252bfSMichael Neumann #define WEIGHT_CB_EN3(x) ((x) << 18) 94457e252bfSMichael Neumann #define WEIGHT_CB_EN3_MASK (0x3f << 18) 94557e252bfSMichael Neumann #define WEIGHT_CB_EN3_SHIFT 18 94657e252bfSMichael Neumann #define CG_CAC_REGION_2_WEIGHT_1 0x86 94757e252bfSMichael Neumann #define WEIGHT_DB_SIG0(x) ((x) << 0) 94857e252bfSMichael Neumann #define WEIGHT_DB_SIG0_MASK (0x3f << 0) 94957e252bfSMichael Neumann #define WEIGHT_DB_SIG0_SHIFT 0 95057e252bfSMichael Neumann #define WEIGHT_DB_SIG1(x) ((x) << 6) 95157e252bfSMichael Neumann #define WEIGHT_DB_SIG1_MASK (0x3f << 6) 95257e252bfSMichael Neumann #define WEIGHT_DB_SIG1_SHIFT 6 95357e252bfSMichael Neumann #define WEIGHT_DB_SIG2(x) ((x) << 12) 95457e252bfSMichael Neumann #define WEIGHT_DB_SIG2_MASK (0x3f << 12) 95557e252bfSMichael Neumann #define WEIGHT_DB_SIG2_SHIFT 12 95657e252bfSMichael Neumann #define WEIGHT_DB_SIG3(x) ((x) << 18) 95757e252bfSMichael Neumann #define WEIGHT_DB_SIG3_MASK (0x3f << 18) 95857e252bfSMichael Neumann #define WEIGHT_DB_SIG3_SHIFT 18 95957e252bfSMichael Neumann #define CG_CAC_REGION_2_WEIGHT_2 0x87 96057e252bfSMichael Neumann #define WEIGHT_SXM_SIG0(x) ((x) << 0) 96157e252bfSMichael Neumann #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) 96257e252bfSMichael Neumann #define WEIGHT_SXM_SIG0_SHIFT 0 96357e252bfSMichael Neumann #define WEIGHT_SXM_SIG1(x) ((x) << 6) 96457e252bfSMichael Neumann #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) 96557e252bfSMichael Neumann #define WEIGHT_SXM_SIG1_SHIFT 6 96657e252bfSMichael Neumann #define WEIGHT_SXM_SIG2(x) ((x) << 12) 96757e252bfSMichael Neumann #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) 96857e252bfSMichael Neumann #define WEIGHT_SXM_SIG2_SHIFT 12 96957e252bfSMichael Neumann #define WEIGHT_SXS_SIG0(x) ((x) << 18) 97057e252bfSMichael Neumann #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) 97157e252bfSMichael Neumann #define WEIGHT_SXS_SIG0_SHIFT 18 97257e252bfSMichael Neumann #define WEIGHT_SXS_SIG1(x) ((x) << 24) 97357e252bfSMichael Neumann #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) 97457e252bfSMichael Neumann #define WEIGHT_SXS_SIG1_SHIFT 24 97557e252bfSMichael Neumann #define CG_CAC_REGION_3_WEIGHT_0 0x88 97657e252bfSMichael Neumann #define WEIGHT_XBR_0(x) ((x) << 0) 97757e252bfSMichael Neumann #define WEIGHT_XBR_0_MASK (0x3f << 0) 97857e252bfSMichael Neumann #define WEIGHT_XBR_0_SHIFT 0 97957e252bfSMichael Neumann #define WEIGHT_XBR_1(x) ((x) << 6) 98057e252bfSMichael Neumann #define WEIGHT_XBR_1_MASK (0x3f << 6) 98157e252bfSMichael Neumann #define WEIGHT_XBR_1_SHIFT 6 98257e252bfSMichael Neumann #define WEIGHT_XBR_2(x) ((x) << 12) 98357e252bfSMichael Neumann #define WEIGHT_XBR_2_MASK (0x3f << 12) 98457e252bfSMichael Neumann #define WEIGHT_XBR_2_SHIFT 12 98557e252bfSMichael Neumann #define WEIGHT_SPI_SIG0(x) ((x) << 18) 98657e252bfSMichael Neumann #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) 98757e252bfSMichael Neumann #define WEIGHT_SPI_SIG0_SHIFT 18 98857e252bfSMichael Neumann #define CG_CAC_REGION_3_WEIGHT_1 0x89 98957e252bfSMichael Neumann #define WEIGHT_SPI_SIG1(x) ((x) << 0) 99057e252bfSMichael Neumann #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) 99157e252bfSMichael Neumann #define WEIGHT_SPI_SIG1_SHIFT 0 99257e252bfSMichael Neumann #define WEIGHT_SPI_SIG2(x) ((x) << 6) 99357e252bfSMichael Neumann #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) 99457e252bfSMichael Neumann #define WEIGHT_SPI_SIG2_SHIFT 6 99557e252bfSMichael Neumann #define WEIGHT_SPI_SIG3(x) ((x) << 12) 99657e252bfSMichael Neumann #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) 99757e252bfSMichael Neumann #define WEIGHT_SPI_SIG3_SHIFT 12 99857e252bfSMichael Neumann #define WEIGHT_SPI_SIG4(x) ((x) << 18) 99957e252bfSMichael Neumann #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) 100057e252bfSMichael Neumann #define WEIGHT_SPI_SIG4_SHIFT 18 100157e252bfSMichael Neumann #define WEIGHT_SPI_SIG5(x) ((x) << 24) 100257e252bfSMichael Neumann #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) 100357e252bfSMichael Neumann #define WEIGHT_SPI_SIG5_SHIFT 24 100457e252bfSMichael Neumann #define CG_CAC_REGION_4_WEIGHT_0 0x8a 100557e252bfSMichael Neumann #define WEIGHT_LDS_SIG0(x) ((x) << 0) 100657e252bfSMichael Neumann #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) 100757e252bfSMichael Neumann #define WEIGHT_LDS_SIG0_SHIFT 0 100857e252bfSMichael Neumann #define WEIGHT_LDS_SIG1(x) ((x) << 6) 100957e252bfSMichael Neumann #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) 101057e252bfSMichael Neumann #define WEIGHT_LDS_SIG1_SHIFT 6 101157e252bfSMichael Neumann #define WEIGHT_SC(x) ((x) << 24) 101257e252bfSMichael Neumann #define WEIGHT_SC_MASK (0x3f << 24) 101357e252bfSMichael Neumann #define WEIGHT_SC_SHIFT 24 101457e252bfSMichael Neumann #define CG_CAC_REGION_4_WEIGHT_1 0x8b 101557e252bfSMichael Neumann #define WEIGHT_BIF(x) ((x) << 0) 101657e252bfSMichael Neumann #define WEIGHT_BIF_MASK (0x3f << 0) 101757e252bfSMichael Neumann #define WEIGHT_BIF_SHIFT 0 101857e252bfSMichael Neumann #define WEIGHT_CP(x) ((x) << 6) 101957e252bfSMichael Neumann #define WEIGHT_CP_MASK (0x3f << 6) 102057e252bfSMichael Neumann #define WEIGHT_CP_SHIFT 6 102157e252bfSMichael Neumann #define WEIGHT_PA_SIG0(x) ((x) << 12) 102257e252bfSMichael Neumann #define WEIGHT_PA_SIG0_MASK (0x3f << 12) 102357e252bfSMichael Neumann #define WEIGHT_PA_SIG0_SHIFT 12 102457e252bfSMichael Neumann #define WEIGHT_PA_SIG1(x) ((x) << 18) 102557e252bfSMichael Neumann #define WEIGHT_PA_SIG1_MASK (0x3f << 18) 102657e252bfSMichael Neumann #define WEIGHT_PA_SIG1_SHIFT 18 102757e252bfSMichael Neumann #define WEIGHT_VGT_SIG0(x) ((x) << 24) 102857e252bfSMichael Neumann #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) 102957e252bfSMichael Neumann #define WEIGHT_VGT_SIG0_SHIFT 24 103057e252bfSMichael Neumann #define CG_CAC_REGION_4_WEIGHT_2 0x8c 103157e252bfSMichael Neumann #define WEIGHT_VGT_SIG1(x) ((x) << 0) 103257e252bfSMichael Neumann #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) 103357e252bfSMichael Neumann #define WEIGHT_VGT_SIG1_SHIFT 0 103457e252bfSMichael Neumann #define WEIGHT_VGT_SIG2(x) ((x) << 6) 103557e252bfSMichael Neumann #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) 103657e252bfSMichael Neumann #define WEIGHT_VGT_SIG2_SHIFT 6 103757e252bfSMichael Neumann #define WEIGHT_DC_SIG0(x) ((x) << 12) 103857e252bfSMichael Neumann #define WEIGHT_DC_SIG0_MASK (0x3f << 12) 103957e252bfSMichael Neumann #define WEIGHT_DC_SIG0_SHIFT 12 104057e252bfSMichael Neumann #define WEIGHT_DC_SIG1(x) ((x) << 18) 104157e252bfSMichael Neumann #define WEIGHT_DC_SIG1_MASK (0x3f << 18) 104257e252bfSMichael Neumann #define WEIGHT_DC_SIG1_SHIFT 18 104357e252bfSMichael Neumann #define WEIGHT_DC_SIG2(x) ((x) << 24) 104457e252bfSMichael Neumann #define WEIGHT_DC_SIG2_MASK (0x3f << 24) 104557e252bfSMichael Neumann #define WEIGHT_DC_SIG2_SHIFT 24 104657e252bfSMichael Neumann #define CG_CAC_REGION_4_WEIGHT_3 0x8d 104757e252bfSMichael Neumann #define WEIGHT_DC_SIG3(x) ((x) << 0) 104857e252bfSMichael Neumann #define WEIGHT_DC_SIG3_MASK (0x3f << 0) 104957e252bfSMichael Neumann #define WEIGHT_DC_SIG3_SHIFT 0 105057e252bfSMichael Neumann #define WEIGHT_UVD_SIG0(x) ((x) << 6) 105157e252bfSMichael Neumann #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) 105257e252bfSMichael Neumann #define WEIGHT_UVD_SIG0_SHIFT 6 105357e252bfSMichael Neumann #define WEIGHT_UVD_SIG1(x) ((x) << 12) 105457e252bfSMichael Neumann #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) 105557e252bfSMichael Neumann #define WEIGHT_UVD_SIG1_SHIFT 12 105657e252bfSMichael Neumann #define WEIGHT_SPARE0(x) ((x) << 18) 105757e252bfSMichael Neumann #define WEIGHT_SPARE0_MASK (0x3f << 18) 105857e252bfSMichael Neumann #define WEIGHT_SPARE0_SHIFT 18 105957e252bfSMichael Neumann #define WEIGHT_SPARE1(x) ((x) << 24) 106057e252bfSMichael Neumann #define WEIGHT_SPARE1_MASK (0x3f << 24) 106157e252bfSMichael Neumann #define WEIGHT_SPARE1_SHIFT 24 106257e252bfSMichael Neumann #define CG_CAC_REGION_5_WEIGHT_0 0x8e 106357e252bfSMichael Neumann #define WEIGHT_SQ_VSP(x) ((x) << 0) 106457e252bfSMichael Neumann #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) 106557e252bfSMichael Neumann #define WEIGHT_SQ_VSP_SHIFT 0 106657e252bfSMichael Neumann #define WEIGHT_SQ_VSP0(x) ((x) << 14) 106757e252bfSMichael Neumann #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) 106857e252bfSMichael Neumann #define WEIGHT_SQ_VSP0_SHIFT 14 106957e252bfSMichael Neumann #define CG_CAC_REGION_4_OVERRIDE_4 0xab 107057e252bfSMichael Neumann #define OVR_MODE_SPARE_0(x) ((x) << 16) 107157e252bfSMichael Neumann #define OVR_MODE_SPARE_0_MASK (0x1 << 16) 107257e252bfSMichael Neumann #define OVR_MODE_SPARE_0_SHIFT 16 107357e252bfSMichael Neumann #define OVR_VAL_SPARE_0(x) ((x) << 17) 107457e252bfSMichael Neumann #define OVR_VAL_SPARE_0_MASK (0x1 << 17) 107557e252bfSMichael Neumann #define OVR_VAL_SPARE_0_SHIFT 17 107657e252bfSMichael Neumann #define OVR_MODE_SPARE_1(x) ((x) << 18) 107757e252bfSMichael Neumann #define OVR_MODE_SPARE_1_MASK (0x3f << 18) 107857e252bfSMichael Neumann #define OVR_MODE_SPARE_1_SHIFT 18 107957e252bfSMichael Neumann #define OVR_VAL_SPARE_1(x) ((x) << 19) 108057e252bfSMichael Neumann #define OVR_VAL_SPARE_1_MASK (0x3f << 19) 108157e252bfSMichael Neumann #define OVR_VAL_SPARE_1_SHIFT 19 108257e252bfSMichael Neumann #define CG_CAC_REGION_5_WEIGHT_1 0xb7 108357e252bfSMichael Neumann #define WEIGHT_SQ_GPR(x) ((x) << 0) 108457e252bfSMichael Neumann #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) 108557e252bfSMichael Neumann #define WEIGHT_SQ_GPR_SHIFT 0 108657e252bfSMichael Neumann #define WEIGHT_SQ_LDS(x) ((x) << 14) 108757e252bfSMichael Neumann #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) 108857e252bfSMichael Neumann #define WEIGHT_SQ_LDS_SHIFT 14 108957e252bfSMichael Neumann 109057e252bfSMichael Neumann /* PCIE link stuff */ 109157e252bfSMichael Neumann #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 109257e252bfSMichael Neumann #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 109357e252bfSMichael Neumann # define LC_LINK_WIDTH_SHIFT 0 109457e252bfSMichael Neumann # define LC_LINK_WIDTH_MASK 0x7 109557e252bfSMichael Neumann # define LC_LINK_WIDTH_X0 0 109657e252bfSMichael Neumann # define LC_LINK_WIDTH_X1 1 109757e252bfSMichael Neumann # define LC_LINK_WIDTH_X2 2 109857e252bfSMichael Neumann # define LC_LINK_WIDTH_X4 3 109957e252bfSMichael Neumann # define LC_LINK_WIDTH_X8 4 110057e252bfSMichael Neumann # define LC_LINK_WIDTH_X16 6 110157e252bfSMichael Neumann # define LC_LINK_WIDTH_RD_SHIFT 4 110257e252bfSMichael Neumann # define LC_LINK_WIDTH_RD_MASK 0x70 110357e252bfSMichael Neumann # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 110457e252bfSMichael Neumann # define LC_RECONFIG_NOW (1 << 8) 110557e252bfSMichael Neumann # define LC_RENEGOTIATION_SUPPORT (1 << 9) 110657e252bfSMichael Neumann # define LC_RENEGOTIATE_EN (1 << 10) 110757e252bfSMichael Neumann # define LC_SHORT_RECONFIG_EN (1 << 11) 110857e252bfSMichael Neumann # define LC_UPCONFIGURE_SUPPORT (1 << 12) 110957e252bfSMichael Neumann # define LC_UPCONFIGURE_DIS (1 << 13) 111057e252bfSMichael Neumann #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 111157e252bfSMichael Neumann # define LC_GEN2_EN_STRAP (1 << 0) 111257e252bfSMichael Neumann # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 111357e252bfSMichael Neumann # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 111457e252bfSMichael Neumann # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 111557e252bfSMichael Neumann # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 111657e252bfSMichael Neumann # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 111757e252bfSMichael Neumann # define LC_CURRENT_DATA_RATE (1 << 11) 111857e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 111957e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 112057e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 112157e252bfSMichael Neumann # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 112257e252bfSMichael Neumann # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 112357e252bfSMichael Neumann # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 112457e252bfSMichael Neumann # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 112557e252bfSMichael Neumann #define MM_CFGREGS_CNTL 0x544c 112657e252bfSMichael Neumann # define MM_WR_TO_CFG_EN (1 << 3) 112757e252bfSMichael Neumann #define LINK_CNTL2 0x88 /* F0 */ 112857e252bfSMichael Neumann # define TARGET_LINK_SPEED_MASK (0xf << 0) 112957e252bfSMichael Neumann # define SELECTABLE_DEEMPHASIS (1 << 6) 113057e252bfSMichael Neumann 1131926deccbSFrançois Tigeot /* 1132f43cf1b1SMichael Neumann * UVD 1133f43cf1b1SMichael Neumann */ 1134f43cf1b1SMichael Neumann #define UVD_SEMA_ADDR_LOW 0xEF00 1135f43cf1b1SMichael Neumann #define UVD_SEMA_ADDR_HIGH 0xEF04 1136f43cf1b1SMichael Neumann #define UVD_SEMA_CMD 0xEF08 1137f43cf1b1SMichael Neumann #define UVD_UDEC_ADDR_CONFIG 0xEF4C 1138f43cf1b1SMichael Neumann #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 1139f43cf1b1SMichael Neumann #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1140*1dedbd3bSFrançois Tigeot #define UVD_NO_OP 0xEFFC 1141f43cf1b1SMichael Neumann #define UVD_RBC_RB_RPTR 0xF690 1142f43cf1b1SMichael Neumann #define UVD_RBC_RB_WPTR 0xF694 1143c59a5c48SFrançois Tigeot #define UVD_STATUS 0xf6bc 1144f43cf1b1SMichael Neumann 1145f43cf1b1SMichael Neumann /* 1146926deccbSFrançois Tigeot * PM4 1147926deccbSFrançois Tigeot */ 1148b403bed8SMichael Neumann #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1149926deccbSFrançois Tigeot (((reg) >> 2) & 0xFFFF) | \ 1150926deccbSFrançois Tigeot ((n) & 0x3FFF) << 16) 1151926deccbSFrançois Tigeot #define CP_PACKET2 0x80000000 1152926deccbSFrançois Tigeot #define PACKET2_PAD_SHIFT 0 1153926deccbSFrançois Tigeot #define PACKET2_PAD_MASK (0x3fffffff << 0) 1154926deccbSFrançois Tigeot 1155926deccbSFrançois Tigeot #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1156926deccbSFrançois Tigeot 1157b403bed8SMichael Neumann #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1158926deccbSFrançois Tigeot (((op) & 0xFF) << 8) | \ 1159926deccbSFrançois Tigeot ((n) & 0x3FFF) << 16) 1160926deccbSFrançois Tigeot 1161926deccbSFrançois Tigeot /* Packet 3 types */ 1162926deccbSFrançois Tigeot #define PACKET3_NOP 0x10 1163926deccbSFrançois Tigeot #define PACKET3_SET_BASE 0x11 1164926deccbSFrançois Tigeot #define PACKET3_CLEAR_STATE 0x12 1165926deccbSFrançois Tigeot #define PACKET3_INDEX_BUFFER_SIZE 0x13 1166926deccbSFrançois Tigeot #define PACKET3_DEALLOC_STATE 0x14 1167926deccbSFrançois Tigeot #define PACKET3_DISPATCH_DIRECT 0x15 1168926deccbSFrançois Tigeot #define PACKET3_DISPATCH_INDIRECT 0x16 1169926deccbSFrançois Tigeot #define PACKET3_INDIRECT_BUFFER_END 0x17 1170926deccbSFrançois Tigeot #define PACKET3_MODE_CONTROL 0x18 1171926deccbSFrançois Tigeot #define PACKET3_SET_PREDICATION 0x20 1172926deccbSFrançois Tigeot #define PACKET3_REG_RMW 0x21 1173926deccbSFrançois Tigeot #define PACKET3_COND_EXEC 0x22 1174926deccbSFrançois Tigeot #define PACKET3_PRED_EXEC 0x23 1175926deccbSFrançois Tigeot #define PACKET3_DRAW_INDIRECT 0x24 1176926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1177926deccbSFrançois Tigeot #define PACKET3_INDEX_BASE 0x26 1178926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_2 0x27 1179926deccbSFrançois Tigeot #define PACKET3_CONTEXT_CONTROL 0x28 1180926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_OFFSET 0x29 1181926deccbSFrançois Tigeot #define PACKET3_INDEX_TYPE 0x2A 1182926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX 0x2B 1183926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_AUTO 0x2D 1184926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_IMMD 0x2E 1185926deccbSFrançois Tigeot #define PACKET3_NUM_INSTANCES 0x2F 1186926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1187926deccbSFrançois Tigeot #define PACKET3_INDIRECT_BUFFER 0x32 1188926deccbSFrançois Tigeot #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1189926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1190926deccbSFrançois Tigeot #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1191926deccbSFrançois Tigeot #define PACKET3_WRITE_DATA 0x37 1192926deccbSFrançois Tigeot #define PACKET3_MEM_SEMAPHORE 0x39 1193926deccbSFrançois Tigeot #define PACKET3_MPEG_INDEX 0x3A 1194926deccbSFrançois Tigeot #define PACKET3_WAIT_REG_MEM 0x3C 11957dcf36dcSFrançois Tigeot #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 11967dcf36dcSFrançois Tigeot /* 0 - always 11977dcf36dcSFrançois Tigeot * 1 - < 11987dcf36dcSFrançois Tigeot * 2 - <= 11997dcf36dcSFrançois Tigeot * 3 - == 12007dcf36dcSFrançois Tigeot * 4 - != 12017dcf36dcSFrançois Tigeot * 5 - >= 12027dcf36dcSFrançois Tigeot * 6 - > 12037dcf36dcSFrançois Tigeot */ 12047dcf36dcSFrançois Tigeot #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 12057dcf36dcSFrançois Tigeot /* 0 - reg 12067dcf36dcSFrançois Tigeot * 1 - mem 12077dcf36dcSFrançois Tigeot */ 12087dcf36dcSFrançois Tigeot #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 12097dcf36dcSFrançois Tigeot /* 0 - me 12107dcf36dcSFrançois Tigeot * 1 - pfp 12117dcf36dcSFrançois Tigeot */ 1212926deccbSFrançois Tigeot #define PACKET3_MEM_WRITE 0x3D 1213926deccbSFrançois Tigeot #define PACKET3_PFP_SYNC_ME 0x42 1214926deccbSFrançois Tigeot #define PACKET3_SURFACE_SYNC 0x43 1215926deccbSFrançois Tigeot # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1216926deccbSFrançois Tigeot # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1217926deccbSFrançois Tigeot # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1218926deccbSFrançois Tigeot # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1219926deccbSFrançois Tigeot # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1220926deccbSFrançois Tigeot # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1221926deccbSFrançois Tigeot # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1222926deccbSFrançois Tigeot # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1223926deccbSFrançois Tigeot # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1224926deccbSFrançois Tigeot # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1225926deccbSFrançois Tigeot # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1226926deccbSFrançois Tigeot # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1227926deccbSFrançois Tigeot # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1228926deccbSFrançois Tigeot # define PACKET3_FULL_CACHE_ENA (1 << 20) 1229926deccbSFrançois Tigeot # define PACKET3_TC_ACTION_ENA (1 << 23) 1230926deccbSFrançois Tigeot # define PACKET3_CB_ACTION_ENA (1 << 25) 1231926deccbSFrançois Tigeot # define PACKET3_DB_ACTION_ENA (1 << 26) 1232926deccbSFrançois Tigeot # define PACKET3_SH_ACTION_ENA (1 << 27) 1233926deccbSFrançois Tigeot # define PACKET3_SX_ACTION_ENA (1 << 28) 1234c6f73aabSFrançois Tigeot # define PACKET3_ENGINE_ME (1 << 31) 1235926deccbSFrançois Tigeot #define PACKET3_ME_INITIALIZE 0x44 1236926deccbSFrançois Tigeot #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1237926deccbSFrançois Tigeot #define PACKET3_COND_WRITE 0x45 1238926deccbSFrançois Tigeot #define PACKET3_EVENT_WRITE 0x46 1239926deccbSFrançois Tigeot #define EVENT_TYPE(x) ((x) << 0) 1240926deccbSFrançois Tigeot #define EVENT_INDEX(x) ((x) << 8) 1241926deccbSFrançois Tigeot /* 0 - any non-TS event 1242926deccbSFrançois Tigeot * 1 - ZPASS_DONE 1243926deccbSFrançois Tigeot * 2 - SAMPLE_PIPELINESTAT 1244926deccbSFrançois Tigeot * 3 - SAMPLE_STREAMOUTSTAT* 1245926deccbSFrançois Tigeot * 4 - *S_PARTIAL_FLUSH 1246926deccbSFrançois Tigeot * 5 - TS events 1247926deccbSFrançois Tigeot */ 1248926deccbSFrançois Tigeot #define PACKET3_EVENT_WRITE_EOP 0x47 1249926deccbSFrançois Tigeot #define DATA_SEL(x) ((x) << 29) 1250926deccbSFrançois Tigeot /* 0 - discard 1251926deccbSFrançois Tigeot * 1 - send low 32bit data 1252926deccbSFrançois Tigeot * 2 - send 64bit data 1253926deccbSFrançois Tigeot * 3 - send 64bit counter value 1254926deccbSFrançois Tigeot */ 1255926deccbSFrançois Tigeot #define INT_SEL(x) ((x) << 24) 1256926deccbSFrançois Tigeot /* 0 - none 1257926deccbSFrançois Tigeot * 1 - interrupt only (DATA_SEL = 0) 1258926deccbSFrançois Tigeot * 2 - interrupt when data write is confirmed 1259926deccbSFrançois Tigeot */ 1260926deccbSFrançois Tigeot #define PACKET3_EVENT_WRITE_EOS 0x48 1261926deccbSFrançois Tigeot #define PACKET3_PREAMBLE_CNTL 0x4A 1262926deccbSFrançois Tigeot # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1263926deccbSFrançois Tigeot # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1264926deccbSFrançois Tigeot #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1265926deccbSFrançois Tigeot #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1266926deccbSFrançois Tigeot #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1267926deccbSFrançois Tigeot #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1268926deccbSFrançois Tigeot #define PACKET3_ONE_REG_WRITE 0x57 1269926deccbSFrançois Tigeot #define PACKET3_SET_CONFIG_REG 0x68 1270926deccbSFrançois Tigeot #define PACKET3_SET_CONFIG_REG_START 0x00008000 1271926deccbSFrançois Tigeot #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1272926deccbSFrançois Tigeot #define PACKET3_SET_CONTEXT_REG 0x69 1273926deccbSFrançois Tigeot #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1274926deccbSFrançois Tigeot #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1275926deccbSFrançois Tigeot #define PACKET3_SET_ALU_CONST 0x6A 1276926deccbSFrançois Tigeot /* alu const buffers only; no reg file */ 1277926deccbSFrançois Tigeot #define PACKET3_SET_BOOL_CONST 0x6B 1278926deccbSFrançois Tigeot #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1279926deccbSFrançois Tigeot #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1280926deccbSFrançois Tigeot #define PACKET3_SET_LOOP_CONST 0x6C 1281926deccbSFrançois Tigeot #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1282926deccbSFrançois Tigeot #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1283926deccbSFrançois Tigeot #define PACKET3_SET_RESOURCE 0x6D 1284926deccbSFrançois Tigeot #define PACKET3_SET_RESOURCE_START 0x00030000 1285926deccbSFrançois Tigeot #define PACKET3_SET_RESOURCE_END 0x00038000 1286926deccbSFrançois Tigeot #define PACKET3_SET_SAMPLER 0x6E 1287926deccbSFrançois Tigeot #define PACKET3_SET_SAMPLER_START 0x0003c000 1288926deccbSFrançois Tigeot #define PACKET3_SET_SAMPLER_END 0x0003c600 1289926deccbSFrançois Tigeot #define PACKET3_SET_CTL_CONST 0x6F 1290926deccbSFrançois Tigeot #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1291926deccbSFrançois Tigeot #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1292926deccbSFrançois Tigeot #define PACKET3_SET_RESOURCE_OFFSET 0x70 1293926deccbSFrançois Tigeot #define PACKET3_SET_ALU_CONST_VS 0x71 1294926deccbSFrançois Tigeot #define PACKET3_SET_ALU_CONST_DI 0x72 1295926deccbSFrançois Tigeot #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1296926deccbSFrançois Tigeot #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1297926deccbSFrançois Tigeot #define PACKET3_SET_APPEND_CNT 0x75 1298926deccbSFrançois Tigeot #define PACKET3_ME_WRITE 0x7A 1299926deccbSFrançois Tigeot 1300926deccbSFrançois Tigeot /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1301926deccbSFrançois Tigeot #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1302926deccbSFrançois Tigeot #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1303926deccbSFrançois Tigeot 1304926deccbSFrançois Tigeot #define DMA_RB_CNTL 0xd000 1305926deccbSFrançois Tigeot # define DMA_RB_ENABLE (1 << 0) 1306926deccbSFrançois Tigeot # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1307926deccbSFrançois Tigeot # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1308926deccbSFrançois Tigeot # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1309926deccbSFrançois Tigeot # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1310926deccbSFrançois Tigeot # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1311926deccbSFrançois Tigeot #define DMA_RB_BASE 0xd004 1312926deccbSFrançois Tigeot #define DMA_RB_RPTR 0xd008 1313926deccbSFrançois Tigeot #define DMA_RB_WPTR 0xd00c 1314926deccbSFrançois Tigeot 1315926deccbSFrançois Tigeot #define DMA_RB_RPTR_ADDR_HI 0xd01c 1316926deccbSFrançois Tigeot #define DMA_RB_RPTR_ADDR_LO 0xd020 1317926deccbSFrançois Tigeot 1318926deccbSFrançois Tigeot #define DMA_IB_CNTL 0xd024 1319926deccbSFrançois Tigeot # define DMA_IB_ENABLE (1 << 0) 1320926deccbSFrançois Tigeot # define DMA_IB_SWAP_ENABLE (1 << 4) 1321926deccbSFrançois Tigeot # define CMD_VMID_FORCE (1 << 31) 1322926deccbSFrançois Tigeot #define DMA_IB_RPTR 0xd028 1323926deccbSFrançois Tigeot #define DMA_CNTL 0xd02c 1324926deccbSFrançois Tigeot # define TRAP_ENABLE (1 << 0) 1325926deccbSFrançois Tigeot # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1326926deccbSFrançois Tigeot # define SEM_WAIT_INT_ENABLE (1 << 2) 1327926deccbSFrançois Tigeot # define DATA_SWAP_ENABLE (1 << 3) 1328926deccbSFrançois Tigeot # define FENCE_SWAP_ENABLE (1 << 4) 1329926deccbSFrançois Tigeot # define CTXEMPTY_INT_ENABLE (1 << 28) 1330926deccbSFrançois Tigeot #define DMA_STATUS_REG 0xd034 1331926deccbSFrançois Tigeot # define DMA_IDLE (1 << 0) 1332926deccbSFrançois Tigeot #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 1333926deccbSFrançois Tigeot #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 1334926deccbSFrançois Tigeot #define DMA_TILING_CONFIG 0xd0b8 1335926deccbSFrançois Tigeot #define DMA_MODE 0xd0bc 1336926deccbSFrançois Tigeot 1337926deccbSFrançois Tigeot #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 1338926deccbSFrançois Tigeot (((t) & 0x1) << 23) | \ 1339926deccbSFrançois Tigeot (((s) & 0x1) << 22) | \ 1340926deccbSFrançois Tigeot (((n) & 0xFFFFF) << 0)) 1341926deccbSFrançois Tigeot 1342926deccbSFrançois Tigeot #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1343926deccbSFrançois Tigeot (((vmid) & 0xF) << 20) | \ 1344926deccbSFrançois Tigeot (((n) & 0xFFFFF) << 0)) 1345926deccbSFrançois Tigeot 1346f43cf1b1SMichael Neumann #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1347f43cf1b1SMichael Neumann (1 << 26) | \ 1348f43cf1b1SMichael Neumann (1 << 21) | \ 1349f43cf1b1SMichael Neumann (((n) & 0xFFFFF) << 0)) 1350f43cf1b1SMichael Neumann 13517dcf36dcSFrançois Tigeot #define DMA_SRBM_POLL_PACKET ((9 << 28) | \ 13527dcf36dcSFrançois Tigeot (1 << 27) | \ 13537dcf36dcSFrançois Tigeot (1 << 26)) 13547dcf36dcSFrançois Tigeot 13557dcf36dcSFrançois Tigeot #define DMA_SRBM_READ_PACKET ((9 << 28) | \ 13567dcf36dcSFrançois Tigeot (1 << 27)) 13577dcf36dcSFrançois Tigeot 1358926deccbSFrançois Tigeot /* async DMA Packet types */ 1359926deccbSFrançois Tigeot #define DMA_PACKET_WRITE 0x2 1360926deccbSFrançois Tigeot #define DMA_PACKET_COPY 0x3 1361926deccbSFrançois Tigeot #define DMA_PACKET_INDIRECT_BUFFER 0x4 1362926deccbSFrançois Tigeot #define DMA_PACKET_SEMAPHORE 0x5 1363926deccbSFrançois Tigeot #define DMA_PACKET_FENCE 0x6 1364926deccbSFrançois Tigeot #define DMA_PACKET_TRAP 0x7 1365926deccbSFrançois Tigeot #define DMA_PACKET_SRBM_WRITE 0x9 1366926deccbSFrançois Tigeot #define DMA_PACKET_CONSTANT_FILL 0xd 1367926deccbSFrançois Tigeot #define DMA_PACKET_NOP 0xf 1368926deccbSFrançois Tigeot 1369926deccbSFrançois Tigeot #endif 1370