xref: /dragonfly/sys/dev/drm/radeon/r100_track.h (revision cfd1aba3)
1 /* $FreeBSD: head/sys/dev/drm2/radeon/r100_track.h 254885 2013-08-25 19:37:15Z dumbbell $ */
2 
3 #define R100_TRACK_MAX_TEXTURE 3
4 #define R200_TRACK_MAX_TEXTURE 6
5 #define R300_TRACK_MAX_TEXTURE 16
6 
7 #define R100_MAX_CB 1
8 #define R300_MAX_CB 4
9 
10 /*
11  * CS functions
12  */
13 struct r100_cs_track_cb {
14 	struct radeon_bo	*robj;
15 	unsigned		pitch;
16 	unsigned		cpp;
17 	unsigned		offset;
18 };
19 
20 struct r100_cs_track_array {
21 	struct radeon_bo	*robj;
22 	unsigned		esize;
23 };
24 
25 struct r100_cs_cube_info {
26 	struct radeon_bo	*robj;
27 	unsigned		offset;
28 	unsigned		width;
29 	unsigned		height;
30 };
31 
32 #define R100_TRACK_COMP_NONE   0
33 #define R100_TRACK_COMP_DXT1   1
34 #define R100_TRACK_COMP_DXT35  2
35 
36 struct r100_cs_track_texture {
37 	struct radeon_bo	*robj;
38 	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
39 	unsigned		pitch;
40 	unsigned		width;
41 	unsigned		height;
42 	unsigned		num_levels;
43 	unsigned		cpp;
44 	unsigned		tex_coord_type;
45 	unsigned		txdepth;
46 	unsigned		width_11;
47 	unsigned		height_11;
48 	bool			use_pitch;
49 	bool			enabled;
50 	bool                    lookup_disable;
51 	bool			roundup_w;
52 	bool			roundup_h;
53 	unsigned                compress_format;
54 };
55 
56 struct r100_cs_track {
57 	unsigned			num_cb;
58 	unsigned                        num_texture;
59 	unsigned			maxy;
60 	unsigned			vtx_size;
61 	unsigned			vap_vf_cntl;
62 	unsigned			vap_alt_nverts;
63 	unsigned			immd_dwords;
64 	unsigned			num_arrays;
65 	unsigned			max_indx;
66 	unsigned			color_channel_mask;
67 	struct r100_cs_track_array	arrays[16];
68 	struct r100_cs_track_cb 	cb[R300_MAX_CB];
69 	struct r100_cs_track_cb 	zb;
70 	struct r100_cs_track_cb 	aa;
71 	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
72 	bool				z_enabled;
73 	bool                            separate_cube;
74 	bool				zb_cb_clear;
75 	bool				blend_read_enable;
76 	bool				cb_dirty;
77 	bool				zb_dirty;
78 	bool				tex_dirty;
79 	bool				aa_dirty;
80 	bool				aaresolve;
81 };
82 
83 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
84 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
85 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
86 			      struct radeon_cs_reloc **cs_reloc);
87 void r100_cs_dump_packet(struct radeon_cs_parser *p,
88 			 struct radeon_cs_packet *pkt);
89 
90 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
91 
92 int r200_packet0_check(struct radeon_cs_parser *p,
93 		       struct radeon_cs_packet *pkt,
94 		       unsigned idx, unsigned reg);
95 
96 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
97 			    struct radeon_cs_packet *pkt,
98 			    unsigned idx,
99 			    unsigned reg);
100 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
101 			     struct radeon_cs_packet *pkt,
102 			     int idx);
103