1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r100d.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 #ifndef __R100D_H__ 31 #define __R100D_H__ 32 33 #define CP_PACKET0 0x00000000 34 #define PACKET0_BASE_INDEX_SHIFT 0 35 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 36 #define PACKET0_COUNT_SHIFT 16 37 #define PACKET0_COUNT_MASK (0x3fff << 16) 38 #define CP_PACKET1 0x40000000 39 #define CP_PACKET2 0x80000000 40 #define PACKET2_PAD_SHIFT 0 41 #define PACKET2_PAD_MASK (0x3fffffff << 0) 42 #define CP_PACKET3 0xC0000000 43 #define PACKET3_IT_OPCODE_SHIFT 8 44 #define PACKET3_IT_OPCODE_MASK (0xff << 8) 45 #define PACKET3_COUNT_SHIFT 16 46 #define PACKET3_COUNT_MASK (0x3fff << 16) 47 /* PACKET3 op code */ 48 #define PACKET3_NOP 0x10 49 #define PACKET3_3D_DRAW_VBUF 0x28 50 #define PACKET3_3D_DRAW_IMMD 0x29 51 #define PACKET3_3D_DRAW_INDX 0x2A 52 #define PACKET3_3D_LOAD_VBPNTR 0x2F 53 #define PACKET3_3D_CLEAR_ZMASK 0x32 54 #define PACKET3_INDX_BUFFER 0x33 55 #define PACKET3_3D_DRAW_VBUF_2 0x34 56 #define PACKET3_3D_DRAW_IMMD_2 0x35 57 #define PACKET3_3D_DRAW_INDX_2 0x36 58 #define PACKET3_3D_CLEAR_HIZ 0x37 59 #define PACKET3_BITBLT_MULTI 0x9B 60 61 #define PACKET0(reg, n) (CP_PACKET0 | \ 62 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 63 REG_SET(PACKET0_COUNT, (n))) 64 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 65 #define PACKET3(op, n) (CP_PACKET3 | \ 66 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 67 REG_SET(PACKET3_COUNT, (n))) 68 69 #define PACKET_TYPE0 0 70 #define PACKET_TYPE1 1 71 #define PACKET_TYPE2 2 72 #define PACKET_TYPE3 3 73 74 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 75 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 76 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 77 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 78 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 79 80 /* Registers */ 81 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 82 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 83 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 84 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 85 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 86 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 87 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 88 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 89 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 90 #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 91 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 92 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 93 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 94 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 95 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 96 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 97 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 98 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 99 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 100 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 101 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 102 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 103 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 104 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 105 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 106 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 107 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 108 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 109 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 110 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 111 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 112 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 113 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 114 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 115 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 116 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 117 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 118 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 119 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 120 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 121 #define R_000030_BUS_CNTL 0x000030 122 #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 123 #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 124 #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 125 #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 126 #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 127 #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 128 #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 129 #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 130 #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 131 #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 132 #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 133 #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 134 #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 135 #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 136 #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 137 #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 138 #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 139 #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 140 #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 141 #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 142 #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 143 #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 144 #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 145 #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 146 #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 147 #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 148 #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 149 #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 150 #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 151 #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 152 #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 153 #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 154 #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 155 #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 156 #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 157 #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 158 #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 159 #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 160 #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 161 #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 162 #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 163 #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 164 #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 165 #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 166 #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 167 #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 168 #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 169 #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 170 #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 171 #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 172 #define C_000030_BUS_RETRY_WS 0xFFF0FFFF 173 #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 174 #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 175 #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 176 #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 177 #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 178 #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 179 #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 180 #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 181 #define C_000030_BUS_SUSPEND 0xFFBFFFFF 182 #define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 183 #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 184 #define C_000030_LAT_16X 0xFF7FFFFF 185 #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 186 #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 187 #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 188 #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 189 #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 190 #define C_000030_ENFRCWRDY 0xFDFFFFFF 191 #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 192 #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 193 #define C_000030_BUS_MSTR_WS 0xFBFFFFFF 194 #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 195 #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 196 #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 197 #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 198 #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 199 #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 200 #define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 201 #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 202 #define C_000030_SERR_EN 0xDFFFFFFF 203 #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 204 #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 205 #define C_000030_BUS_READ_BURST 0xBFFFFFFF 206 #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 207 #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 208 #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 209 #define R_000040_GEN_INT_CNTL 0x000040 210 #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 211 #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 212 #define C_000040_CRTC_VBLANK 0xFFFFFFFE 213 #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 214 #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 215 #define C_000040_CRTC_VLINE 0xFFFFFFFD 216 #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 217 #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 218 #define C_000040_CRTC_VSYNC 0xFFFFFFFB 219 #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 220 #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 221 #define C_000040_SNAPSHOT 0xFFFFFFF7 222 #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 223 #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 224 #define C_000040_FP_DETECT 0xFFFFFFEF 225 #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 226 #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 227 #define C_000040_CRTC2_VLINE 0xFFFFFFDF 228 #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 229 #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 230 #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 231 #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 232 #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 233 #define C_000040_CRTC2_VSYNC 0xFFFFFFBF 234 #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 235 #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 236 #define C_000040_SNAPSHOT2 0xFFFFFF7F 237 #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 238 #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 239 #define C_000040_CRTC2_VBLANK 0xFFFFFDFF 240 #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 241 #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 242 #define C_000040_FP2_DETECT 0xFFFFFBFF 243 #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 244 #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 245 #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 246 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 247 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 248 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 249 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 250 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 251 #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 252 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 253 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 254 #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 255 #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 256 #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 257 #define C_000040_I2C_INT_EN 0xFFFDFFFF 258 #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 259 #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 260 #define C_000040_GUI_IDLE 0xFFF7FFFF 261 #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 262 #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 263 #define C_000040_VIPH_INT_EN 0xFEFFFFFF 264 #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 265 #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 266 #define C_000040_SW_INT_EN 0xFDFFFFFF 267 #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 268 #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 269 #define C_000040_GEYSERVILLE 0xF7FFFFFF 270 #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 271 #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 272 #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 273 #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 274 #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 275 #define C_000040_DVI_I2C_INT 0xDFFFFFFF 276 #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 277 #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 278 #define C_000040_GUIDMA 0xBFFFFFFF 279 #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 280 #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 281 #define C_000040_VIDDMA 0x7FFFFFFF 282 #define R_000044_GEN_INT_STATUS 0x000044 283 #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 284 #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 285 #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 286 #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 287 #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 288 #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 289 #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 290 #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 291 #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 292 #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 293 #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 294 #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 295 #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 296 #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 297 #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 298 #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 299 #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 300 #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 301 #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 302 #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 303 #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 304 #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 305 #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 306 #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 307 #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 308 #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 309 #define C_000044_FP_DETECT_STAT 0xFFFFFFEF 310 #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 311 #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 312 #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 313 #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 314 #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 315 #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 316 #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 317 #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 318 #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 319 #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 320 #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 321 #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 322 #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 323 #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 324 #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 325 #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 326 #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 327 #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 328 #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 329 #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 330 #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 331 #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 332 #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 333 #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 334 #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 335 #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 336 #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 337 #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 338 #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 339 #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 340 #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 341 #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 342 #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 343 #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 344 #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 345 #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 346 #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 347 #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 348 #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 349 #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 350 #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 351 #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 352 #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 353 #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 354 #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 355 #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 356 #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 357 #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 358 #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 359 #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 360 #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 361 #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 362 #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 363 #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 364 #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 365 #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 366 #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 367 #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 368 #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 369 #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 370 #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 371 #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 372 #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 373 #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 374 #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 375 #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 376 #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 377 #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 378 #define C_000044_I2C_INT 0xFFFDFFFF 379 #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 380 #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 381 #define C_000044_I2C_INT_AK 0xFFFDFFFF 382 #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 383 #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 384 #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 385 #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 386 #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 387 #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 388 #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 389 #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 390 #define C_000044_VIPH_INT 0xFEFFFFFF 391 #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 392 #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 393 #define C_000044_SW_INT 0xFDFFFFFF 394 #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 395 #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 396 #define C_000044_SW_INT_AK 0xFDFFFFFF 397 #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 398 #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 399 #define C_000044_SW_INT_SET 0xFBFFFFFF 400 #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 401 #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 402 #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 403 #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 404 #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 405 #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 406 #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 407 #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 408 #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 409 #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 410 #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 411 #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 412 #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 413 #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 414 #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 415 #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 416 #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 417 #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 418 #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 419 #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 420 #define C_000044_GUIDMA_STAT 0xBFFFFFFF 421 #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 422 #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 423 #define C_000044_GUIDMA_AK 0xBFFFFFFF 424 #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 425 #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 426 #define C_000044_VIDDMA_STAT 0x7FFFFFFF 427 #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 428 #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 429 #define C_000044_VIDDMA_AK 0x7FFFFFFF 430 #define R_000050_CRTC_GEN_CNTL 0x000050 431 #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 432 #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 433 #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 434 #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 435 #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 436 #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 437 #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 438 #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 439 #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 440 #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 441 #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 442 #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 443 #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 444 #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 445 #define C_000050_CRTC_ICON_EN 0xFFFF7FFF 446 #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 447 #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 448 #define C_000050_CRTC_CUR_EN 0xFFFEFFFF 449 #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 450 #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 451 #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 452 #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 453 #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 454 #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 455 #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 456 #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 457 #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 458 #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 459 #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 460 #define C_000050_CRTC_EN 0xFDFFFFFF 461 #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 462 #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 463 #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 464 #define R_000054_CRTC_EXT_CNTL 0x000054 465 #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 466 #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 467 #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 468 #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 469 #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 470 #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 471 #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 472 #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 473 #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 474 #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 475 #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 476 #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 477 #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 478 #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 479 #define C_000054_VGA_TEXT_132 0xFFFFFFDF 480 #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 481 #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 482 #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 483 #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 484 #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 485 #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 486 #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 487 #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 488 #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 489 #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 490 #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 491 #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 492 #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 493 #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 494 #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 495 #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 496 #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 497 #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 498 #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 499 #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 500 #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 501 #define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 502 #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 503 #define C_000054_CRT_ON 0xFFFF7FFF 504 #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 505 #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 506 #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 507 #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 508 #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 509 #define C_000054_VGA_PACK_DIS 0xFFFBFFFF 510 #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 511 #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 512 #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 513 #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 514 #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 515 #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 516 #define R_000148_MC_FB_LOCATION 0x000148 517 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 518 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 519 #define C_000148_MC_FB_START 0xFFFF0000 520 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 521 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 522 #define C_000148_MC_FB_TOP 0x0000FFFF 523 #define R_00014C_MC_AGP_LOCATION 0x00014C 524 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 525 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 526 #define C_00014C_MC_AGP_START 0xFFFF0000 527 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 528 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 529 #define C_00014C_MC_AGP_TOP 0x0000FFFF 530 #define R_000170_AGP_BASE 0x000170 531 #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 532 #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 533 #define C_000170_AGP_BASE_ADDR 0x00000000 534 #define R_00023C_DISPLAY_BASE_ADDR 0x00023C 535 #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 536 #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 537 #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 538 #define R_000260_CUR_OFFSET 0x000260 539 #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 540 #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 541 #define C_000260_CUR_OFFSET 0xF8000000 542 #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 543 #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 544 #define C_000260_CUR_LOCK 0x7FFFFFFF 545 #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 546 #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 547 #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 548 #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 549 #define R_000360_CUR2_OFFSET 0x000360 550 #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 551 #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 552 #define C_000360_CUR2_OFFSET 0xF8000000 553 #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 554 #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 555 #define C_000360_CUR2_LOCK 0x7FFFFFFF 556 #define R_0003C2_GENMO_WT 0x0003C2 557 #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 558 #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 559 #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 560 #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 561 #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 562 #define C_0003C2_VGA_RAM_EN 0xFD 563 #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 564 #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 565 #define C_0003C2_VGA_CKSEL 0xF3 566 #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 567 #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 568 #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 569 #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 570 #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 571 #define C_0003C2_VGA_HSYNC_POL 0xBF 572 #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 573 #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 574 #define C_0003C2_VGA_VSYNC_POL 0x7F 575 #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 576 #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 577 #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 578 #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 579 #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 580 #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 581 #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 582 #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 583 #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 584 #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 585 #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 586 #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 587 #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 588 #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 589 #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 590 #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 591 #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 592 #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 593 #define C_0003F8_CRT2_ON 0xFFFFFF7F 594 #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 595 #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 596 #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 597 #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 598 #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 599 #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 600 #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 601 #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 602 #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 603 #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 604 #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 605 #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 606 #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 607 #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 608 #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 609 #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 610 #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 611 #define C_0003F8_CRTC2_EN 0xFDFFFFFF 612 #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 613 #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 614 #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 615 #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 616 #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 617 #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 618 #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 619 #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 620 #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 621 #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 622 #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 623 #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 624 #define R_000420_OV0_SCALE_CNTL 0x000420 625 #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 626 #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 627 #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 628 #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 629 #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 630 #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 631 #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 632 #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 633 #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 634 #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 635 #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 636 #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 637 #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 638 #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 639 #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 640 #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 641 #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 642 #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 643 #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 644 #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 645 #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 646 #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 647 #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 648 #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 649 #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 650 #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 651 #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 652 #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 653 #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 654 #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 655 #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 656 #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 657 #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 658 #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 659 #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 660 #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 661 #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 662 #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 663 #define C_000420_OV0_INT_EMU 0xDFFFFFFF 664 #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 665 #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 666 #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 667 #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 668 #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 669 #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 670 #define R_00070C_CP_RB_RPTR_ADDR 0x00070C 671 #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 672 #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 673 #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 674 #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 675 #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 676 #define C_00070C_RB_RPTR_ADDR 0x00000003 677 #define R_000740_CP_CSQ_CNTL 0x000740 678 #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 679 #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 680 #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 681 #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 682 #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 683 #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 684 #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 685 #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 686 #define C_000740_CSQ_MODE 0x0FFFFFFF 687 #define R_000770_SCRATCH_UMSK 0x000770 688 #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 689 #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 690 #define C_000770_SCRATCH_UMSK 0xFFFFFFC0 691 #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 692 #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 693 #define C_000770_SCRATCH_SWAP 0xFFFCFFFF 694 #define R_000774_SCRATCH_ADDR 0x000774 695 #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 696 #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 697 #define C_000774_SCRATCH_ADDR 0x0000001F 698 #define R_0007C0_CP_STAT 0x0007C0 699 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 700 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 701 #define C_0007C0_MRU_BUSY 0xFFFFFFFE 702 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 703 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 704 #define C_0007C0_MWU_BUSY 0xFFFFFFFD 705 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 706 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 707 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 708 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 709 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 710 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 711 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 712 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 713 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 714 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 715 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 716 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 717 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 718 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 719 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 720 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 721 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 722 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 723 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 724 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 725 #define C_0007C0_CSI_BUSY 0xFFFFDFFF 726 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 727 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 728 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 729 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 730 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 731 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 732 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 733 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 734 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 735 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 736 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 737 #define C_0007C0_CP_BUSY 0x7FFFFFFF 738 #define R_000E40_RBBM_STATUS 0x000E40 739 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 740 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 741 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 742 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 743 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 744 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 745 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 746 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 747 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 748 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 749 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 750 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 751 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 752 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 753 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 754 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 755 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 756 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 757 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 758 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 759 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 760 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 761 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 762 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 763 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 764 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 765 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 766 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 767 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 768 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 769 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 770 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 771 #define C_000E40_E2_BUSY 0xFFFDFFFF 772 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 773 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 774 #define C_000E40_RB2D_BUSY 0xFFFBFFFF 775 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 776 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 777 #define C_000E40_RB3D_BUSY 0xFFF7FFFF 778 #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 779 #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 780 #define C_000E40_SE_BUSY 0xFFEFFFFF 781 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 782 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 783 #define C_000E40_RE_BUSY 0xFFDFFFFF 784 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 785 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 786 #define C_000E40_TAM_BUSY 0xFFBFFFFF 787 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 788 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 789 #define C_000E40_TDM_BUSY 0xFF7FFFFF 790 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 791 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 792 #define C_000E40_PB_BUSY 0xFEFFFFFF 793 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 794 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 795 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 796 797 798 #define R_00000D_SCLK_CNTL 0x00000D 799 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 800 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 801 #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 802 #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 803 #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 804 #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 805 #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 806 #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 807 #define C_00000D_FORCE_CP 0xFFFEFFFF 808 #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 809 #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 810 #define C_00000D_FORCE_HDP 0xFFFDFFFF 811 #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 812 #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 813 #define C_00000D_FORCE_DISP 0xFFFBFFFF 814 #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 815 #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 816 #define C_00000D_FORCE_TOP 0xFFF7FFFF 817 #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 818 #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 819 #define C_00000D_FORCE_E2 0xFFEFFFFF 820 #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 821 #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 822 #define C_00000D_FORCE_SE 0xFFDFFFFF 823 #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 824 #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 825 #define C_00000D_FORCE_IDCT 0xFFBFFFFF 826 #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 827 #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 828 #define C_00000D_FORCE_VIP 0xFF7FFFFF 829 #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 830 #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 831 #define C_00000D_FORCE_RE 0xFEFFFFFF 832 #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 833 #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 834 #define C_00000D_FORCE_PB 0xFDFFFFFF 835 #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 836 #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 837 #define C_00000D_FORCE_TAM 0xFBFFFFFF 838 #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 839 #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 840 #define C_00000D_FORCE_TDM 0xF7FFFFFF 841 #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 842 #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 843 #define C_00000D_FORCE_RB 0xEFFFFFFF 844 845 /* PLL regs */ 846 #define SCLK_CNTL 0xd 847 #define FORCE_HDP (1 << 17) 848 #define CLK_PWRMGT_CNTL 0x14 849 #define GLOBAL_PMAN_EN (1 << 10) 850 #define DISP_PM (1 << 20) 851 #define PLL_PWRMGT_CNTL 0x15 852 #define MPLL_TURNOFF (1 << 0) 853 #define SPLL_TURNOFF (1 << 1) 854 #define PPLL_TURNOFF (1 << 2) 855 #define P2PLL_TURNOFF (1 << 3) 856 #define TVPLL_TURNOFF (1 << 4) 857 #define MOBILE_SU (1 << 16) 858 #define SU_SCLK_USE_BCLK (1 << 17) 859 #define SCLK_CNTL2 0x1e 860 #define REDUCED_SPEED_SCLK_MODE (1 << 16) 861 #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 862 #define MCLK_MISC 0x1f 863 #define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 864 #define SCLK_MORE_CNTL 0x35 865 #define REDUCED_SPEED_SCLK_EN (1 << 16) 866 #define IO_CG_VOLTAGE_DROP (1 << 17) 867 #define VOLTAGE_DELAY_SEL(x) ((x) << 20) 868 #define VOLTAGE_DROP_SYNC (1 << 19) 869 870 /* mmreg */ 871 #define DISP_PWR_MAN 0xd08 872 #define DISP_D3_GRPH_RST (1 << 18) 873 #define DISP_D3_SUBPIC_RST (1 << 19) 874 #define DISP_D3_OV0_RST (1 << 20) 875 #define DISP_D1D2_GRPH_RST (1 << 21) 876 #define DISP_D1D2_SUBPIC_RST (1 << 22) 877 #define DISP_D1D2_OV0_RST (1 << 23) 878 #define DISP_DVO_ENABLE_RST (1 << 24) 879 #define TV_ENABLE_RST (1 << 25) 880 #define AUTO_PWRUP_EN (1 << 26) 881 882 #endif 883