1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <drm/drmP.h> 30 #include <drm/drm.h> 31 #include <drm/drm_crtc_helper.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include <drm/radeon_drm.h> 36 #include "r100_track.h" 37 #include "r300d.h" 38 #include "rv350d.h" 39 #include "r300_reg_safe.h" 40 41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 42 * 43 * GPU Errata: 44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 46 * However, scheduling such write to the ring seems harmless, i suspect 47 * the CP read collide with the flush somehow, or maybe the MC, hard to 48 * tell. (Jerome Glisse) 49 */ 50 51 /* 52 * Indirect registers accessor 53 */ 54 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 55 { 56 uint32_t r; 57 58 lockmgr(&rdev->pcie_idx_lock, LK_EXCLUSIVE); 59 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 60 r = RREG32(RADEON_PCIE_DATA); 61 lockmgr(&rdev->pcie_idx_lock, LK_RELEASE); 62 return r; 63 } 64 65 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 66 { 67 lockmgr(&rdev->pcie_idx_lock, LK_EXCLUSIVE); 68 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 69 WREG32(RADEON_PCIE_DATA, (v)); 70 lockmgr(&rdev->pcie_idx_lock, LK_RELEASE); 71 } 72 73 /* 74 * rv370,rv380 PCIE GART 75 */ 76 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 77 78 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 79 { 80 uint32_t tmp; 81 int i; 82 83 /* Workaround HW bug do flush 2 times */ 84 for (i = 0; i < 2; i++) { 85 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 86 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 87 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 88 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 89 } 90 mb(); 91 } 92 93 #define R300_PTE_UNSNOOPED (1 << 0) 94 #define R300_PTE_WRITEABLE (1 << 2) 95 #define R300_PTE_READABLE (1 << 3) 96 97 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 98 { 99 addr = (lower_32_bits(addr) >> 8) | 100 ((upper_32_bits(addr) & 0xff) << 24); 101 if (flags & RADEON_GART_PAGE_READ) 102 addr |= R300_PTE_READABLE; 103 if (flags & RADEON_GART_PAGE_WRITE) 104 addr |= R300_PTE_WRITEABLE; 105 if (!(flags & RADEON_GART_PAGE_SNOOP)) 106 addr |= R300_PTE_UNSNOOPED; 107 return addr; 108 } 109 110 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 111 uint64_t entry) 112 { 113 void __iomem *ptr = rdev->gart.ptr; 114 115 /* on x86 we want this to be CPU endian, on powerpc 116 * on powerpc without HW swappers, it'll get swapped on way 117 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 118 writel(entry, ((uint8_t __iomem *)ptr) + (i * 4)); 119 } 120 121 int rv370_pcie_gart_init(struct radeon_device *rdev) 122 { 123 int r; 124 125 if (rdev->gart.robj) { 126 WARN(1, "RV370 PCIE GART already initialized\n"); 127 return 0; 128 } 129 /* Initialize common gart structure */ 130 r = radeon_gart_init(rdev); 131 if (r) 132 return r; 133 r = rv370_debugfs_pcie_gart_info_init(rdev); 134 if (r) 135 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 136 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 137 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 138 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 139 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 140 return radeon_gart_table_vram_alloc(rdev); 141 } 142 143 int rv370_pcie_gart_enable(struct radeon_device *rdev) 144 { 145 uint32_t table_addr; 146 uint32_t tmp; 147 int r; 148 149 if (rdev->gart.robj == NULL) { 150 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 151 return -EINVAL; 152 } 153 r = radeon_gart_table_vram_pin(rdev); 154 if (r) 155 return r; 156 /* discard memory request outside of configured range */ 157 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 158 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 160 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 162 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 163 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 164 table_addr = rdev->gart.table_addr; 165 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 166 /* FIXME: setup default page */ 167 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 168 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 169 /* Clear error */ 170 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 171 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 172 tmp |= RADEON_PCIE_TX_GART_EN; 173 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 174 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 175 rv370_pcie_gart_tlb_flush(rdev); 176 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 177 (unsigned)(rdev->mc.gtt_size >> 20), 178 (unsigned long long)table_addr); 179 rdev->gart.ready = true; 180 return 0; 181 } 182 183 void rv370_pcie_gart_disable(struct radeon_device *rdev) 184 { 185 u32 tmp; 186 187 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 188 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 189 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 190 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 191 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 192 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 193 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 194 radeon_gart_table_vram_unpin(rdev); 195 } 196 197 void rv370_pcie_gart_fini(struct radeon_device *rdev) 198 { 199 radeon_gart_fini(rdev); 200 rv370_pcie_gart_disable(rdev); 201 radeon_gart_table_vram_free(rdev); 202 } 203 204 void r300_fence_ring_emit(struct radeon_device *rdev, 205 struct radeon_fence *fence) 206 { 207 struct radeon_ring *ring = &rdev->ring[fence->ring]; 208 209 /* Who ever call radeon_fence_emit should call ring_lock and ask 210 * for enough space (today caller are ib schedule and buffer move) */ 211 /* Write SC register so SC & US assert idle */ 212 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 213 radeon_ring_write(ring, 0); 214 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 215 radeon_ring_write(ring, 0); 216 /* Flush 3D cache */ 217 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 218 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 219 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 220 radeon_ring_write(ring, R300_ZC_FLUSH); 221 /* Wait until IDLE & CLEAN */ 222 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 223 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 224 RADEON_WAIT_2D_IDLECLEAN | 225 RADEON_WAIT_DMA_GUI_IDLE)); 226 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 227 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 228 RADEON_HDP_READ_BUFFER_INVALIDATE); 229 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 230 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 231 /* Emit fence sequence & fire IRQ */ 232 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 233 radeon_ring_write(ring, fence->seq); 234 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 235 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 236 } 237 238 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 239 { 240 unsigned gb_tile_config; 241 int r; 242 243 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 244 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 245 switch(rdev->num_gb_pipes) { 246 case 2: 247 gb_tile_config |= R300_PIPE_COUNT_R300; 248 break; 249 case 3: 250 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 251 break; 252 case 4: 253 gb_tile_config |= R300_PIPE_COUNT_R420; 254 break; 255 case 1: 256 default: 257 gb_tile_config |= R300_PIPE_COUNT_RV350; 258 break; 259 } 260 261 r = radeon_ring_lock(rdev, ring, 64); 262 if (r) { 263 return; 264 } 265 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 266 radeon_ring_write(ring, 267 RADEON_ISYNC_ANY2D_IDLE3D | 268 RADEON_ISYNC_ANY3D_IDLE2D | 269 RADEON_ISYNC_WAIT_IDLEGUI | 270 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 271 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 272 radeon_ring_write(ring, gb_tile_config); 273 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 274 radeon_ring_write(ring, 275 RADEON_WAIT_2D_IDLECLEAN | 276 RADEON_WAIT_3D_IDLECLEAN); 277 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 278 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 279 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 280 radeon_ring_write(ring, 0); 281 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 282 radeon_ring_write(ring, 0); 283 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 284 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 285 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 286 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 287 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 288 radeon_ring_write(ring, 289 RADEON_WAIT_2D_IDLECLEAN | 290 RADEON_WAIT_3D_IDLECLEAN); 291 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 292 radeon_ring_write(ring, 0); 293 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 294 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 295 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 296 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 297 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 298 radeon_ring_write(ring, 299 ((6 << R300_MS_X0_SHIFT) | 300 (6 << R300_MS_Y0_SHIFT) | 301 (6 << R300_MS_X1_SHIFT) | 302 (6 << R300_MS_Y1_SHIFT) | 303 (6 << R300_MS_X2_SHIFT) | 304 (6 << R300_MS_Y2_SHIFT) | 305 (6 << R300_MSBD0_Y_SHIFT) | 306 (6 << R300_MSBD0_X_SHIFT))); 307 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 308 radeon_ring_write(ring, 309 ((6 << R300_MS_X3_SHIFT) | 310 (6 << R300_MS_Y3_SHIFT) | 311 (6 << R300_MS_X4_SHIFT) | 312 (6 << R300_MS_Y4_SHIFT) | 313 (6 << R300_MS_X5_SHIFT) | 314 (6 << R300_MS_Y5_SHIFT) | 315 (6 << R300_MSBD1_SHIFT))); 316 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 317 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 318 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 319 radeon_ring_write(ring, 320 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 321 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 322 radeon_ring_write(ring, 323 R300_GEOMETRY_ROUND_NEAREST | 324 R300_COLOR_ROUND_NEAREST); 325 radeon_ring_unlock_commit(rdev, ring, false); 326 } 327 328 static void r300_errata(struct radeon_device *rdev) 329 { 330 rdev->pll_errata = 0; 331 332 if (rdev->family == CHIP_R300 && 333 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 334 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 335 } 336 } 337 338 int r300_mc_wait_for_idle(struct radeon_device *rdev) 339 { 340 unsigned i; 341 uint32_t tmp; 342 343 for (i = 0; i < rdev->usec_timeout; i++) { 344 /* read MC_STATUS */ 345 tmp = RREG32(RADEON_MC_STATUS); 346 if (tmp & R300_MC_IDLE) { 347 return 0; 348 } 349 DRM_UDELAY(1); 350 } 351 return -1; 352 } 353 354 static void r300_gpu_init(struct radeon_device *rdev) 355 { 356 uint32_t gb_tile_config, tmp; 357 358 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 359 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 360 /* r300,r350 */ 361 rdev->num_gb_pipes = 2; 362 } else { 363 /* rv350,rv370,rv380,r300 AD, r350 AH */ 364 rdev->num_gb_pipes = 1; 365 } 366 rdev->num_z_pipes = 1; 367 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 368 switch (rdev->num_gb_pipes) { 369 case 2: 370 gb_tile_config |= R300_PIPE_COUNT_R300; 371 break; 372 case 3: 373 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 374 break; 375 case 4: 376 gb_tile_config |= R300_PIPE_COUNT_R420; 377 break; 378 default: 379 case 1: 380 gb_tile_config |= R300_PIPE_COUNT_RV350; 381 break; 382 } 383 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 384 385 if (r100_gui_wait_for_idle(rdev)) { 386 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 387 } 388 389 tmp = RREG32(R300_DST_PIPE_CONFIG); 390 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 391 392 WREG32(R300_RB2D_DSTCACHE_MODE, 393 R300_DC_AUTOFLUSH_ENABLE | 394 R300_DC_DC_DISABLE_IGNORE_PE); 395 396 if (r100_gui_wait_for_idle(rdev)) { 397 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 398 } 399 if (r300_mc_wait_for_idle(rdev)) { 400 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 401 } 402 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n", 403 rdev->num_gb_pipes, rdev->num_z_pipes); 404 } 405 406 int r300_asic_reset(struct radeon_device *rdev, bool hard) 407 { 408 struct r100_mc_save save; 409 u32 status, tmp; 410 int ret = 0; 411 412 status = RREG32(R_000E40_RBBM_STATUS); 413 if (!G_000E40_GUI_ACTIVE(status)) { 414 return 0; 415 } 416 r100_mc_stop(rdev, &save); 417 status = RREG32(R_000E40_RBBM_STATUS); 418 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 419 /* stop CP */ 420 WREG32(RADEON_CP_CSQ_CNTL, 0); 421 tmp = RREG32(RADEON_CP_RB_CNTL); 422 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 423 WREG32(RADEON_CP_RB_RPTR_WR, 0); 424 WREG32(RADEON_CP_RB_WPTR, 0); 425 WREG32(RADEON_CP_RB_CNTL, tmp); 426 /* save PCI state */ 427 pci_save_state(device_get_parent(rdev->dev->bsddev)); 428 /* disable bus mastering */ 429 r100_bm_disable(rdev); 430 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 431 S_0000F0_SOFT_RESET_GA(1)); 432 RREG32(R_0000F0_RBBM_SOFT_RESET); 433 mdelay(500); 434 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 435 mdelay(1); 436 status = RREG32(R_000E40_RBBM_STATUS); 437 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 438 /* resetting the CP seems to be problematic sometimes it end up 439 * hard locking the computer, but it's necessary for successful 440 * reset more test & playing is needed on R3XX/R4XX to find a 441 * reliable (if any solution) 442 */ 443 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 444 RREG32(R_0000F0_RBBM_SOFT_RESET); 445 mdelay(500); 446 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 447 mdelay(1); 448 status = RREG32(R_000E40_RBBM_STATUS); 449 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 450 /* restore PCI & busmastering */ 451 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 452 r100_enable_bm(rdev); 453 /* Check if GPU is idle */ 454 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 455 dev_err(rdev->dev, "failed to reset GPU\n"); 456 ret = -1; 457 } else 458 dev_info(rdev->dev, "GPU reset succeed\n"); 459 r100_mc_resume(rdev, &save); 460 return ret; 461 } 462 463 /* 464 * r300,r350,rv350,rv380 VRAM info 465 */ 466 void r300_mc_init(struct radeon_device *rdev) 467 { 468 u64 base; 469 u32 tmp; 470 471 /* DDR for all card after R300 & IGP */ 472 rdev->mc.vram_is_ddr = true; 473 tmp = RREG32(RADEON_MEM_CNTL); 474 tmp &= R300_MEM_NUM_CHANNELS_MASK; 475 switch (tmp) { 476 case 0: rdev->mc.vram_width = 64; break; 477 case 1: rdev->mc.vram_width = 128; break; 478 case 2: rdev->mc.vram_width = 256; break; 479 default: rdev->mc.vram_width = 128; break; 480 } 481 r100_vram_init_sizes(rdev); 482 base = rdev->mc.aper_base; 483 if (rdev->flags & RADEON_IS_IGP) 484 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 485 radeon_vram_location(rdev, &rdev->mc, base); 486 rdev->mc.gtt_base_align = 0; 487 if (!(rdev->flags & RADEON_IS_AGP)) 488 radeon_gtt_location(rdev, &rdev->mc); 489 radeon_update_bandwidth_info(rdev); 490 } 491 492 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 493 { 494 uint32_t link_width_cntl, mask; 495 496 if (rdev->flags & RADEON_IS_IGP) 497 return; 498 499 if (!(rdev->flags & RADEON_IS_PCIE)) 500 return; 501 502 /* FIXME wait for idle */ 503 504 switch (lanes) { 505 case 0: 506 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 507 break; 508 case 1: 509 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 510 break; 511 case 2: 512 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 513 break; 514 case 4: 515 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 516 break; 517 case 8: 518 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 519 break; 520 case 12: 521 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 522 break; 523 case 16: 524 default: 525 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 526 break; 527 } 528 529 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 530 531 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 532 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 533 return; 534 535 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 536 RADEON_PCIE_LC_RECONFIG_NOW | 537 RADEON_PCIE_LC_RECONFIG_LATER | 538 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 539 link_width_cntl |= mask; 540 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 541 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 542 RADEON_PCIE_LC_RECONFIG_NOW)); 543 544 /* wait for lane set to complete */ 545 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 546 while (link_width_cntl == 0xffffffff) 547 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 548 549 } 550 551 int rv370_get_pcie_lanes(struct radeon_device *rdev) 552 { 553 u32 link_width_cntl; 554 555 if (rdev->flags & RADEON_IS_IGP) 556 return 0; 557 558 if (!(rdev->flags & RADEON_IS_PCIE)) 559 return 0; 560 561 /* FIXME wait for idle */ 562 563 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 564 565 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 566 case RADEON_PCIE_LC_LINK_WIDTH_X0: 567 return 0; 568 case RADEON_PCIE_LC_LINK_WIDTH_X1: 569 return 1; 570 case RADEON_PCIE_LC_LINK_WIDTH_X2: 571 return 2; 572 case RADEON_PCIE_LC_LINK_WIDTH_X4: 573 return 4; 574 case RADEON_PCIE_LC_LINK_WIDTH_X8: 575 return 8; 576 case RADEON_PCIE_LC_LINK_WIDTH_X16: 577 default: 578 return 16; 579 } 580 } 581 582 #if defined(CONFIG_DEBUG_FS) 583 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 584 { 585 struct drm_info_node *node = (struct drm_info_node *) m->private; 586 struct drm_device *dev = node->minor->dev; 587 struct radeon_device *rdev = dev->dev_private; 588 uint32_t tmp; 589 590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 591 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 593 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 595 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 597 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 599 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 601 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 603 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 604 return 0; 605 } 606 607 static struct drm_info_list rv370_pcie_gart_info_list[] = { 608 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 609 }; 610 #endif 611 612 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 613 { 614 #if defined(CONFIG_DEBUG_FS) 615 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 616 #else 617 return 0; 618 #endif 619 } 620 621 static int r300_packet0_check(struct radeon_cs_parser *p, 622 struct radeon_cs_packet *pkt, 623 unsigned idx, unsigned reg) 624 { 625 struct radeon_bo_list *reloc; 626 struct r100_cs_track *track; 627 volatile uint32_t *ib; 628 uint32_t tmp, tile_flags = 0; 629 unsigned i; 630 int r; 631 u32 idx_value; 632 633 ib = p->ib.ptr; 634 track = (struct r100_cs_track *)p->track; 635 idx_value = radeon_get_ib_value(p, idx); 636 637 switch(reg) { 638 case AVIVO_D1MODE_VLINE_START_END: 639 case RADEON_CRTC_GUI_TRIG_VLINE: 640 r = r100_cs_packet_parse_vline(p); 641 if (r) { 642 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 643 idx, reg); 644 radeon_cs_dump_packet(p, pkt); 645 return r; 646 } 647 break; 648 case RADEON_DST_PITCH_OFFSET: 649 case RADEON_SRC_PITCH_OFFSET: 650 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 651 if (r) 652 return r; 653 break; 654 case R300_RB3D_COLOROFFSET0: 655 case R300_RB3D_COLOROFFSET1: 656 case R300_RB3D_COLOROFFSET2: 657 case R300_RB3D_COLOROFFSET3: 658 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 659 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 660 if (r) { 661 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 662 idx, reg); 663 radeon_cs_dump_packet(p, pkt); 664 return r; 665 } 666 track->cb[i].robj = reloc->robj; 667 track->cb[i].offset = idx_value; 668 track->cb_dirty = true; 669 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 670 break; 671 case R300_ZB_DEPTHOFFSET: 672 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 673 if (r) { 674 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 675 idx, reg); 676 radeon_cs_dump_packet(p, pkt); 677 return r; 678 } 679 track->zb.robj = reloc->robj; 680 track->zb.offset = idx_value; 681 track->zb_dirty = true; 682 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 683 break; 684 case R300_TX_OFFSET_0: 685 case R300_TX_OFFSET_0+4: 686 case R300_TX_OFFSET_0+8: 687 case R300_TX_OFFSET_0+12: 688 case R300_TX_OFFSET_0+16: 689 case R300_TX_OFFSET_0+20: 690 case R300_TX_OFFSET_0+24: 691 case R300_TX_OFFSET_0+28: 692 case R300_TX_OFFSET_0+32: 693 case R300_TX_OFFSET_0+36: 694 case R300_TX_OFFSET_0+40: 695 case R300_TX_OFFSET_0+44: 696 case R300_TX_OFFSET_0+48: 697 case R300_TX_OFFSET_0+52: 698 case R300_TX_OFFSET_0+56: 699 case R300_TX_OFFSET_0+60: 700 i = (reg - R300_TX_OFFSET_0) >> 2; 701 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 702 if (r) { 703 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 704 idx, reg); 705 radeon_cs_dump_packet(p, pkt); 706 return r; 707 } 708 709 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 710 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 711 ((idx_value & ~31) + (u32)reloc->gpu_offset); 712 } else { 713 if (reloc->tiling_flags & RADEON_TILING_MACRO) 714 tile_flags |= R300_TXO_MACRO_TILE; 715 if (reloc->tiling_flags & RADEON_TILING_MICRO) 716 tile_flags |= R300_TXO_MICRO_TILE; 717 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 718 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 719 720 tmp = idx_value + ((u32)reloc->gpu_offset); 721 tmp |= tile_flags; 722 ib[idx] = tmp; 723 } 724 track->textures[i].robj = reloc->robj; 725 track->tex_dirty = true; 726 break; 727 /* Tracked registers */ 728 case 0x2084: 729 /* VAP_VF_CNTL */ 730 track->vap_vf_cntl = idx_value; 731 break; 732 case 0x20B4: 733 /* VAP_VTX_SIZE */ 734 track->vtx_size = idx_value & 0x7F; 735 break; 736 case 0x2134: 737 /* VAP_VF_MAX_VTX_INDX */ 738 track->max_indx = idx_value & 0x00FFFFFFUL; 739 break; 740 case 0x2088: 741 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 742 if (p->rdev->family < CHIP_RV515) 743 goto fail; 744 track->vap_alt_nverts = idx_value & 0xFFFFFF; 745 break; 746 case 0x43E4: 747 /* SC_SCISSOR1 */ 748 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 749 if (p->rdev->family < CHIP_RV515) { 750 track->maxy -= 1440; 751 } 752 track->cb_dirty = true; 753 track->zb_dirty = true; 754 break; 755 case 0x4E00: 756 /* RB3D_CCTL */ 757 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 758 p->rdev->cmask_filp != p->filp) { 759 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 760 return -EINVAL; 761 } 762 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 763 track->cb_dirty = true; 764 break; 765 case 0x4E38: 766 case 0x4E3C: 767 case 0x4E40: 768 case 0x4E44: 769 /* RB3D_COLORPITCH0 */ 770 /* RB3D_COLORPITCH1 */ 771 /* RB3D_COLORPITCH2 */ 772 /* RB3D_COLORPITCH3 */ 773 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 774 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 775 if (r) { 776 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 777 idx, reg); 778 radeon_cs_dump_packet(p, pkt); 779 return r; 780 } 781 782 if (reloc->tiling_flags & RADEON_TILING_MACRO) 783 tile_flags |= R300_COLOR_TILE_ENABLE; 784 if (reloc->tiling_flags & RADEON_TILING_MICRO) 785 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 786 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 787 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 788 789 tmp = idx_value & ~(0x7 << 16); 790 tmp |= tile_flags; 791 ib[idx] = tmp; 792 } 793 i = (reg - 0x4E38) >> 2; 794 track->cb[i].pitch = idx_value & 0x3FFE; 795 switch (((idx_value >> 21) & 0xF)) { 796 case 9: 797 case 11: 798 case 12: 799 track->cb[i].cpp = 1; 800 break; 801 case 3: 802 case 4: 803 case 13: 804 case 15: 805 track->cb[i].cpp = 2; 806 break; 807 case 5: 808 if (p->rdev->family < CHIP_RV515) { 809 DRM_ERROR("Invalid color buffer format (%d)!\n", 810 ((idx_value >> 21) & 0xF)); 811 return -EINVAL; 812 } 813 /* Pass through. */ 814 case 6: 815 track->cb[i].cpp = 4; 816 break; 817 case 10: 818 track->cb[i].cpp = 8; 819 break; 820 case 7: 821 track->cb[i].cpp = 16; 822 break; 823 default: 824 DRM_ERROR("Invalid color buffer format (%d) !\n", 825 ((idx_value >> 21) & 0xF)); 826 return -EINVAL; 827 } 828 track->cb_dirty = true; 829 break; 830 case 0x4F00: 831 /* ZB_CNTL */ 832 if (idx_value & 2) { 833 track->z_enabled = true; 834 } else { 835 track->z_enabled = false; 836 } 837 track->zb_dirty = true; 838 break; 839 case 0x4F10: 840 /* ZB_FORMAT */ 841 switch ((idx_value & 0xF)) { 842 case 0: 843 case 1: 844 track->zb.cpp = 2; 845 break; 846 case 2: 847 track->zb.cpp = 4; 848 break; 849 default: 850 DRM_ERROR("Invalid z buffer format (%d) !\n", 851 (idx_value & 0xF)); 852 return -EINVAL; 853 } 854 track->zb_dirty = true; 855 break; 856 case 0x4F24: 857 /* ZB_DEPTHPITCH */ 858 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 859 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 860 if (r) { 861 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 862 idx, reg); 863 radeon_cs_dump_packet(p, pkt); 864 return r; 865 } 866 867 if (reloc->tiling_flags & RADEON_TILING_MACRO) 868 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 869 if (reloc->tiling_flags & RADEON_TILING_MICRO) 870 tile_flags |= R300_DEPTHMICROTILE_TILED; 871 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 872 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 873 874 tmp = idx_value & ~(0x7 << 16); 875 tmp |= tile_flags; 876 ib[idx] = tmp; 877 } 878 track->zb.pitch = idx_value & 0x3FFC; 879 track->zb_dirty = true; 880 break; 881 case 0x4104: 882 /* TX_ENABLE */ 883 for (i = 0; i < 16; i++) { 884 bool enabled; 885 886 enabled = !!(idx_value & (1 << i)); 887 track->textures[i].enabled = enabled; 888 } 889 track->tex_dirty = true; 890 break; 891 case 0x44C0: 892 case 0x44C4: 893 case 0x44C8: 894 case 0x44CC: 895 case 0x44D0: 896 case 0x44D4: 897 case 0x44D8: 898 case 0x44DC: 899 case 0x44E0: 900 case 0x44E4: 901 case 0x44E8: 902 case 0x44EC: 903 case 0x44F0: 904 case 0x44F4: 905 case 0x44F8: 906 case 0x44FC: 907 /* TX_FORMAT1_[0-15] */ 908 i = (reg - 0x44C0) >> 2; 909 tmp = (idx_value >> 25) & 0x3; 910 track->textures[i].tex_coord_type = tmp; 911 switch ((idx_value & 0x1F)) { 912 case R300_TX_FORMAT_X8: 913 case R300_TX_FORMAT_Y4X4: 914 case R300_TX_FORMAT_Z3Y3X2: 915 track->textures[i].cpp = 1; 916 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 917 break; 918 case R300_TX_FORMAT_X16: 919 case R300_TX_FORMAT_FL_I16: 920 case R300_TX_FORMAT_Y8X8: 921 case R300_TX_FORMAT_Z5Y6X5: 922 case R300_TX_FORMAT_Z6Y5X5: 923 case R300_TX_FORMAT_W4Z4Y4X4: 924 case R300_TX_FORMAT_W1Z5Y5X5: 925 case R300_TX_FORMAT_D3DMFT_CxV8U8: 926 case R300_TX_FORMAT_B8G8_B8G8: 927 case R300_TX_FORMAT_G8R8_G8B8: 928 track->textures[i].cpp = 2; 929 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 930 break; 931 case R300_TX_FORMAT_Y16X16: 932 case R300_TX_FORMAT_FL_I16A16: 933 case R300_TX_FORMAT_Z11Y11X10: 934 case R300_TX_FORMAT_Z10Y11X11: 935 case R300_TX_FORMAT_W8Z8Y8X8: 936 case R300_TX_FORMAT_W2Z10Y10X10: 937 case 0x17: 938 case R300_TX_FORMAT_FL_I32: 939 case 0x1e: 940 track->textures[i].cpp = 4; 941 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 942 break; 943 case R300_TX_FORMAT_W16Z16Y16X16: 944 case R300_TX_FORMAT_FL_R16G16B16A16: 945 case R300_TX_FORMAT_FL_I32A32: 946 track->textures[i].cpp = 8; 947 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 948 break; 949 case R300_TX_FORMAT_FL_R32G32B32A32: 950 track->textures[i].cpp = 16; 951 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 952 break; 953 case R300_TX_FORMAT_DXT1: 954 track->textures[i].cpp = 1; 955 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 956 break; 957 case R300_TX_FORMAT_ATI2N: 958 if (p->rdev->family < CHIP_R420) { 959 DRM_ERROR("Invalid texture format %u\n", 960 (idx_value & 0x1F)); 961 return -EINVAL; 962 } 963 /* The same rules apply as for DXT3/5. */ 964 /* Pass through. */ 965 case R300_TX_FORMAT_DXT3: 966 case R300_TX_FORMAT_DXT5: 967 track->textures[i].cpp = 1; 968 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 969 break; 970 default: 971 DRM_ERROR("Invalid texture format %u\n", 972 (idx_value & 0x1F)); 973 return -EINVAL; 974 } 975 track->tex_dirty = true; 976 break; 977 case 0x4400: 978 case 0x4404: 979 case 0x4408: 980 case 0x440C: 981 case 0x4410: 982 case 0x4414: 983 case 0x4418: 984 case 0x441C: 985 case 0x4420: 986 case 0x4424: 987 case 0x4428: 988 case 0x442C: 989 case 0x4430: 990 case 0x4434: 991 case 0x4438: 992 case 0x443C: 993 /* TX_FILTER0_[0-15] */ 994 i = (reg - 0x4400) >> 2; 995 tmp = idx_value & 0x7; 996 if (tmp == 2 || tmp == 4 || tmp == 6) { 997 track->textures[i].roundup_w = false; 998 } 999 tmp = (idx_value >> 3) & 0x7; 1000 if (tmp == 2 || tmp == 4 || tmp == 6) { 1001 track->textures[i].roundup_h = false; 1002 } 1003 track->tex_dirty = true; 1004 break; 1005 case 0x4500: 1006 case 0x4504: 1007 case 0x4508: 1008 case 0x450C: 1009 case 0x4510: 1010 case 0x4514: 1011 case 0x4518: 1012 case 0x451C: 1013 case 0x4520: 1014 case 0x4524: 1015 case 0x4528: 1016 case 0x452C: 1017 case 0x4530: 1018 case 0x4534: 1019 case 0x4538: 1020 case 0x453C: 1021 /* TX_FORMAT2_[0-15] */ 1022 i = (reg - 0x4500) >> 2; 1023 tmp = idx_value & 0x3FFF; 1024 track->textures[i].pitch = tmp + 1; 1025 if (p->rdev->family >= CHIP_RV515) { 1026 tmp = ((idx_value >> 15) & 1) << 11; 1027 track->textures[i].width_11 = tmp; 1028 tmp = ((idx_value >> 16) & 1) << 11; 1029 track->textures[i].height_11 = tmp; 1030 1031 /* ATI1N */ 1032 if (idx_value & (1 << 14)) { 1033 /* The same rules apply as for DXT1. */ 1034 track->textures[i].compress_format = 1035 R100_TRACK_COMP_DXT1; 1036 } 1037 } else if (idx_value & (1 << 14)) { 1038 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1039 return -EINVAL; 1040 } 1041 track->tex_dirty = true; 1042 break; 1043 case 0x4480: 1044 case 0x4484: 1045 case 0x4488: 1046 case 0x448C: 1047 case 0x4490: 1048 case 0x4494: 1049 case 0x4498: 1050 case 0x449C: 1051 case 0x44A0: 1052 case 0x44A4: 1053 case 0x44A8: 1054 case 0x44AC: 1055 case 0x44B0: 1056 case 0x44B4: 1057 case 0x44B8: 1058 case 0x44BC: 1059 /* TX_FORMAT0_[0-15] */ 1060 i = (reg - 0x4480) >> 2; 1061 tmp = idx_value & 0x7FF; 1062 track->textures[i].width = tmp + 1; 1063 tmp = (idx_value >> 11) & 0x7FF; 1064 track->textures[i].height = tmp + 1; 1065 tmp = (idx_value >> 26) & 0xF; 1066 track->textures[i].num_levels = tmp; 1067 tmp = idx_value & (1 << 31); 1068 track->textures[i].use_pitch = !!tmp; 1069 tmp = (idx_value >> 22) & 0xF; 1070 track->textures[i].txdepth = tmp; 1071 track->tex_dirty = true; 1072 break; 1073 case R300_ZB_ZPASS_ADDR: 1074 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1075 if (r) { 1076 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1077 idx, reg); 1078 radeon_cs_dump_packet(p, pkt); 1079 return r; 1080 } 1081 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1082 break; 1083 case 0x4e0c: 1084 /* RB3D_COLOR_CHANNEL_MASK */ 1085 track->color_channel_mask = idx_value; 1086 track->cb_dirty = true; 1087 break; 1088 case 0x43a4: 1089 /* SC_HYPERZ_EN */ 1090 /* r300c emits this register - we need to disable hyperz for it 1091 * without complaining */ 1092 if (p->rdev->hyperz_filp != p->filp) { 1093 if (idx_value & 0x1) 1094 ib[idx] = idx_value & ~1; 1095 } 1096 break; 1097 case 0x4f1c: 1098 /* ZB_BW_CNTL */ 1099 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1100 track->cb_dirty = true; 1101 track->zb_dirty = true; 1102 if (p->rdev->hyperz_filp != p->filp) { 1103 if (idx_value & (R300_HIZ_ENABLE | 1104 R300_RD_COMP_ENABLE | 1105 R300_WR_COMP_ENABLE | 1106 R300_FAST_FILL_ENABLE)) 1107 goto fail; 1108 } 1109 break; 1110 case 0x4e04: 1111 /* RB3D_BLENDCNTL */ 1112 track->blend_read_enable = !!(idx_value & (1 << 2)); 1113 track->cb_dirty = true; 1114 break; 1115 case R300_RB3D_AARESOLVE_OFFSET: 1116 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1117 if (r) { 1118 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1119 idx, reg); 1120 radeon_cs_dump_packet(p, pkt); 1121 return r; 1122 } 1123 track->aa.robj = reloc->robj; 1124 track->aa.offset = idx_value; 1125 track->aa_dirty = true; 1126 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1127 break; 1128 case R300_RB3D_AARESOLVE_PITCH: 1129 track->aa.pitch = idx_value & 0x3FFE; 1130 track->aa_dirty = true; 1131 break; 1132 case R300_RB3D_AARESOLVE_CTL: 1133 track->aaresolve = idx_value & 0x1; 1134 track->aa_dirty = true; 1135 break; 1136 case 0x4f30: /* ZB_MASK_OFFSET */ 1137 case 0x4f34: /* ZB_ZMASK_PITCH */ 1138 case 0x4f44: /* ZB_HIZ_OFFSET */ 1139 case 0x4f54: /* ZB_HIZ_PITCH */ 1140 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1141 goto fail; 1142 break; 1143 case 0x4028: 1144 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1145 goto fail; 1146 /* GB_Z_PEQ_CONFIG */ 1147 if (p->rdev->family >= CHIP_RV350) 1148 break; 1149 goto fail; 1150 break; 1151 case 0x4be8: 1152 /* valid register only on RV530 */ 1153 if (p->rdev->family == CHIP_RV530) 1154 break; 1155 /* fallthrough do not move */ 1156 default: 1157 goto fail; 1158 } 1159 return 0; 1160 fail: 1161 pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1162 reg, idx, idx_value); 1163 return -EINVAL; 1164 } 1165 1166 static int r300_packet3_check(struct radeon_cs_parser *p, 1167 struct radeon_cs_packet *pkt) 1168 { 1169 struct radeon_bo_list *reloc; 1170 struct r100_cs_track *track; 1171 volatile uint32_t *ib; 1172 unsigned idx; 1173 int r; 1174 1175 ib = p->ib.ptr; 1176 idx = pkt->idx + 1; 1177 track = (struct r100_cs_track *)p->track; 1178 switch(pkt->opcode) { 1179 case PACKET3_3D_LOAD_VBPNTR: 1180 r = r100_packet3_load_vbpntr(p, pkt, idx); 1181 if (r) 1182 return r; 1183 break; 1184 case PACKET3_INDX_BUFFER: 1185 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1186 if (r) { 1187 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1188 radeon_cs_dump_packet(p, pkt); 1189 return r; 1190 } 1191 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1192 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1193 if (r) { 1194 return r; 1195 } 1196 break; 1197 /* Draw packet */ 1198 case PACKET3_3D_DRAW_IMMD: 1199 /* Number of dwords is vtx_size * (num_vertices - 1) 1200 * PRIM_WALK must be equal to 3 vertex data in embedded 1201 * in cmd stream */ 1202 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1203 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1204 return -EINVAL; 1205 } 1206 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1207 track->immd_dwords = pkt->count - 1; 1208 r = r100_cs_track_check(p->rdev, track); 1209 if (r) { 1210 return r; 1211 } 1212 break; 1213 case PACKET3_3D_DRAW_IMMD_2: 1214 /* Number of dwords is vtx_size * (num_vertices - 1) 1215 * PRIM_WALK must be equal to 3 vertex data in embedded 1216 * in cmd stream */ 1217 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1218 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1219 return -EINVAL; 1220 } 1221 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1222 track->immd_dwords = pkt->count; 1223 r = r100_cs_track_check(p->rdev, track); 1224 if (r) { 1225 return r; 1226 } 1227 break; 1228 case PACKET3_3D_DRAW_VBUF: 1229 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1230 r = r100_cs_track_check(p->rdev, track); 1231 if (r) { 1232 return r; 1233 } 1234 break; 1235 case PACKET3_3D_DRAW_VBUF_2: 1236 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1237 r = r100_cs_track_check(p->rdev, track); 1238 if (r) { 1239 return r; 1240 } 1241 break; 1242 case PACKET3_3D_DRAW_INDX: 1243 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1244 r = r100_cs_track_check(p->rdev, track); 1245 if (r) { 1246 return r; 1247 } 1248 break; 1249 case PACKET3_3D_DRAW_INDX_2: 1250 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1251 r = r100_cs_track_check(p->rdev, track); 1252 if (r) { 1253 return r; 1254 } 1255 break; 1256 case PACKET3_3D_CLEAR_HIZ: 1257 case PACKET3_3D_CLEAR_ZMASK: 1258 if (p->rdev->hyperz_filp != p->filp) 1259 return -EINVAL; 1260 break; 1261 case PACKET3_3D_CLEAR_CMASK: 1262 if (p->rdev->cmask_filp != p->filp) 1263 return -EINVAL; 1264 break; 1265 case PACKET3_NOP: 1266 break; 1267 default: 1268 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1269 return -EINVAL; 1270 } 1271 return 0; 1272 } 1273 1274 int r300_cs_parse(struct radeon_cs_parser *p) 1275 { 1276 struct radeon_cs_packet pkt; 1277 struct r100_cs_track *track; 1278 int r; 1279 1280 track = kzalloc(sizeof(*track), GFP_KERNEL); 1281 if (track == NULL) 1282 return -ENOMEM; 1283 r100_cs_track_clear(p->rdev, track); 1284 p->track = track; 1285 do { 1286 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1287 if (r) { 1288 return r; 1289 } 1290 p->idx += pkt.count + 2; 1291 switch (pkt.type) { 1292 case RADEON_PACKET_TYPE0: 1293 r = r100_cs_parse_packet0(p, &pkt, 1294 p->rdev->config.r300.reg_safe_bm, 1295 p->rdev->config.r300.reg_safe_bm_size, 1296 &r300_packet0_check); 1297 break; 1298 case RADEON_PACKET_TYPE2: 1299 break; 1300 case RADEON_PACKET_TYPE3: 1301 r = r300_packet3_check(p, &pkt); 1302 break; 1303 default: 1304 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1305 return -EINVAL; 1306 } 1307 if (r) { 1308 return r; 1309 } 1310 } while (p->idx < p->chunk_ib->length_dw); 1311 return 0; 1312 } 1313 1314 void r300_set_reg_safe(struct radeon_device *rdev) 1315 { 1316 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1317 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1318 } 1319 1320 void r300_mc_program(struct radeon_device *rdev) 1321 { 1322 struct r100_mc_save save; 1323 int r; 1324 1325 r = r100_debugfs_mc_info_init(rdev); 1326 if (r) { 1327 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1328 } 1329 1330 /* Stops all mc clients */ 1331 r100_mc_stop(rdev, &save); 1332 if (rdev->flags & RADEON_IS_AGP) { 1333 WREG32(R_00014C_MC_AGP_LOCATION, 1334 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1335 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1336 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1337 WREG32(R_00015C_AGP_BASE_2, 1338 upper_32_bits(rdev->mc.agp_base) & 0xff); 1339 } else { 1340 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1341 WREG32(R_000170_AGP_BASE, 0); 1342 WREG32(R_00015C_AGP_BASE_2, 0); 1343 } 1344 /* Wait for mc idle */ 1345 if (r300_mc_wait_for_idle(rdev)) 1346 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1347 /* Program MC, should be a 32bits limited address space */ 1348 WREG32(R_000148_MC_FB_LOCATION, 1349 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1350 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1351 r100_mc_resume(rdev, &save); 1352 } 1353 1354 void r300_clock_startup(struct radeon_device *rdev) 1355 { 1356 u32 tmp; 1357 1358 if (radeon_dynclks != -1 && radeon_dynclks) 1359 radeon_legacy_set_clock_gating(rdev, 1); 1360 /* We need to force on some of the block */ 1361 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1362 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1363 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1364 tmp |= S_00000D_FORCE_VAP(1); 1365 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1366 } 1367 1368 static int r300_startup(struct radeon_device *rdev) 1369 { 1370 int r; 1371 1372 /* set common regs */ 1373 r100_set_common_regs(rdev); 1374 /* program mc */ 1375 r300_mc_program(rdev); 1376 /* Resume clock */ 1377 r300_clock_startup(rdev); 1378 /* Initialize GPU configuration (# pipes, ...) */ 1379 r300_gpu_init(rdev); 1380 /* Initialize GART (initialize after TTM so we can allocate 1381 * memory through TTM but finalize after TTM) */ 1382 if (rdev->flags & RADEON_IS_PCIE) { 1383 r = rv370_pcie_gart_enable(rdev); 1384 if (r) 1385 return r; 1386 } 1387 1388 if (rdev->family == CHIP_R300 || 1389 rdev->family == CHIP_R350 || 1390 rdev->family == CHIP_RV350) 1391 r100_enable_bm(rdev); 1392 1393 if (rdev->flags & RADEON_IS_PCI) { 1394 r = r100_pci_gart_enable(rdev); 1395 if (r) 1396 return r; 1397 } 1398 1399 /* allocate wb buffer */ 1400 r = radeon_wb_init(rdev); 1401 if (r) 1402 return r; 1403 1404 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1405 if (r) { 1406 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1407 return r; 1408 } 1409 1410 /* Enable IRQ */ 1411 if (!rdev->irq.installed) { 1412 r = radeon_irq_kms_init(rdev); 1413 if (r) 1414 return r; 1415 } 1416 1417 r100_irq_set(rdev); 1418 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1419 /* 1M ring buffer */ 1420 r = r100_cp_init(rdev, 1024 * 1024); 1421 if (r) { 1422 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1423 return r; 1424 } 1425 1426 r = radeon_ib_pool_init(rdev); 1427 if (r) { 1428 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1429 return r; 1430 } 1431 1432 return 0; 1433 } 1434 1435 int r300_resume(struct radeon_device *rdev) 1436 { 1437 int r; 1438 1439 /* Make sur GART are not working */ 1440 if (rdev->flags & RADEON_IS_PCIE) 1441 rv370_pcie_gart_disable(rdev); 1442 if (rdev->flags & RADEON_IS_PCI) 1443 r100_pci_gart_disable(rdev); 1444 /* Resume clock before doing reset */ 1445 r300_clock_startup(rdev); 1446 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1447 if (radeon_asic_reset(rdev)) { 1448 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1449 RREG32(R_000E40_RBBM_STATUS), 1450 RREG32(R_0007C0_CP_STAT)); 1451 } 1452 /* post */ 1453 radeon_combios_asic_init(rdev->ddev); 1454 /* Resume clock after posting */ 1455 r300_clock_startup(rdev); 1456 /* Initialize surface registers */ 1457 radeon_surface_init(rdev); 1458 1459 rdev->accel_working = true; 1460 r = r300_startup(rdev); 1461 if (r) { 1462 rdev->accel_working = false; 1463 } 1464 return r; 1465 } 1466 1467 int r300_suspend(struct radeon_device *rdev) 1468 { 1469 radeon_pm_suspend(rdev); 1470 r100_cp_disable(rdev); 1471 radeon_wb_disable(rdev); 1472 r100_irq_disable(rdev); 1473 if (rdev->flags & RADEON_IS_PCIE) 1474 rv370_pcie_gart_disable(rdev); 1475 if (rdev->flags & RADEON_IS_PCI) 1476 r100_pci_gart_disable(rdev); 1477 return 0; 1478 } 1479 1480 void r300_fini(struct radeon_device *rdev) 1481 { 1482 radeon_pm_fini(rdev); 1483 r100_cp_fini(rdev); 1484 radeon_wb_fini(rdev); 1485 radeon_ib_pool_fini(rdev); 1486 radeon_gem_fini(rdev); 1487 if (rdev->flags & RADEON_IS_PCIE) 1488 rv370_pcie_gart_fini(rdev); 1489 if (rdev->flags & RADEON_IS_PCI) 1490 r100_pci_gart_fini(rdev); 1491 radeon_agp_fini(rdev); 1492 radeon_irq_kms_fini(rdev); 1493 radeon_fence_driver_fini(rdev); 1494 radeon_bo_fini(rdev); 1495 radeon_atombios_fini(rdev); 1496 kfree(rdev->bios); 1497 rdev->bios = NULL; 1498 } 1499 1500 int r300_init(struct radeon_device *rdev) 1501 { 1502 int r; 1503 1504 /* Disable VGA */ 1505 r100_vga_render_disable(rdev); 1506 /* Initialize scratch registers */ 1507 radeon_scratch_init(rdev); 1508 /* Initialize surface registers */ 1509 radeon_surface_init(rdev); 1510 /* TODO: disable VGA need to use VGA request */ 1511 /* restore some register to sane defaults */ 1512 r100_restore_sanity(rdev); 1513 /* BIOS*/ 1514 if (!radeon_get_bios(rdev)) { 1515 if (ASIC_IS_AVIVO(rdev)) 1516 return -EINVAL; 1517 } 1518 if (rdev->is_atom_bios) { 1519 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1520 return -EINVAL; 1521 } else { 1522 r = radeon_combios_init(rdev); 1523 if (r) 1524 return r; 1525 } 1526 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1527 if (radeon_asic_reset(rdev)) { 1528 dev_warn(rdev->dev, 1529 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1530 RREG32(R_000E40_RBBM_STATUS), 1531 RREG32(R_0007C0_CP_STAT)); 1532 } 1533 /* check if cards are posted or not */ 1534 if (radeon_boot_test_post_card(rdev) == false) 1535 return -EINVAL; 1536 /* Set asic errata */ 1537 r300_errata(rdev); 1538 /* Initialize clocks */ 1539 radeon_get_clock_info(rdev->ddev); 1540 /* initialize AGP */ 1541 if (rdev->flags & RADEON_IS_AGP) { 1542 r = radeon_agp_init(rdev); 1543 if (r) { 1544 radeon_agp_disable(rdev); 1545 } 1546 } 1547 /* initialize memory controller */ 1548 r300_mc_init(rdev); 1549 /* Fence driver */ 1550 r = radeon_fence_driver_init(rdev); 1551 if (r) 1552 return r; 1553 /* Memory manager */ 1554 r = radeon_bo_init(rdev); 1555 if (r) 1556 return r; 1557 if (rdev->flags & RADEON_IS_PCIE) { 1558 r = rv370_pcie_gart_init(rdev); 1559 if (r) 1560 return r; 1561 } 1562 if (rdev->flags & RADEON_IS_PCI) { 1563 r = r100_pci_gart_init(rdev); 1564 if (r) 1565 return r; 1566 } 1567 r300_set_reg_safe(rdev); 1568 1569 /* Initialize power management */ 1570 radeon_pm_init(rdev); 1571 1572 rdev->accel_working = true; 1573 r = r300_startup(rdev); 1574 if (r) { 1575 /* Something went wrong with the accel init, so stop accel */ 1576 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1577 r100_cp_fini(rdev); 1578 radeon_wb_fini(rdev); 1579 radeon_ib_pool_fini(rdev); 1580 radeon_irq_kms_fini(rdev); 1581 if (rdev->flags & RADEON_IS_PCIE) 1582 rv370_pcie_gart_fini(rdev); 1583 if (rdev->flags & RADEON_IS_PCI) 1584 r100_pci_gart_fini(rdev); 1585 radeon_agp_fini(rdev); 1586 rdev->accel_working = false; 1587 } 1588 return 0; 1589 } 1590