1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <drm/drmP.h> 30 #include <drm/drm.h> 31 #include <drm/drm_crtc_helper.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include <drm/radeon_drm.h> 36 #include "r100_track.h" 37 #include "r300d.h" 38 #include "rv350d.h" 39 #include "r300_reg_safe.h" 40 41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 42 * 43 * GPU Errata: 44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 46 * However, scheduling such write to the ring seems harmless, i suspect 47 * the CP read collide with the flush somehow, or maybe the MC, hard to 48 * tell. (Jerome Glisse) 49 */ 50 51 /* 52 * Indirect registers accessor 53 */ 54 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 55 { 56 uint32_t r; 57 58 lockmgr(&rdev->pcie_idx_lock, LK_EXCLUSIVE); 59 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 60 r = RREG32(RADEON_PCIE_DATA); 61 lockmgr(&rdev->pcie_idx_lock, LK_RELEASE); 62 return r; 63 } 64 65 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 66 { 67 lockmgr(&rdev->pcie_idx_lock, LK_EXCLUSIVE); 68 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 69 WREG32(RADEON_PCIE_DATA, (v)); 70 lockmgr(&rdev->pcie_idx_lock, LK_RELEASE); 71 } 72 73 /* 74 * rv370,rv380 PCIE GART 75 */ 76 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 77 78 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 79 { 80 uint32_t tmp; 81 int i; 82 83 /* Workaround HW bug do flush 2 times */ 84 for (i = 0; i < 2; i++) { 85 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 86 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 87 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 88 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 89 } 90 mb(); 91 } 92 93 #define R300_PTE_UNSNOOPED (1 << 0) 94 #define R300_PTE_WRITEABLE (1 << 2) 95 #define R300_PTE_READABLE (1 << 3) 96 97 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 98 { 99 addr = (lower_32_bits(addr) >> 8) | 100 ((upper_32_bits(addr) & 0xff) << 24); 101 if (flags & RADEON_GART_PAGE_READ) 102 addr |= R300_PTE_READABLE; 103 if (flags & RADEON_GART_PAGE_WRITE) 104 addr |= R300_PTE_WRITEABLE; 105 if (!(flags & RADEON_GART_PAGE_SNOOP)) 106 addr |= R300_PTE_UNSNOOPED; 107 return addr; 108 } 109 110 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 111 uint64_t entry) 112 { 113 void __iomem *ptr = rdev->gart.ptr; 114 115 /* on x86 we want this to be CPU endian, on powerpc 116 * on powerpc without HW swappers, it'll get swapped on way 117 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 118 writel(entry, ((uint8_t __iomem *)ptr) + (i * 4)); 119 } 120 121 int rv370_pcie_gart_init(struct radeon_device *rdev) 122 { 123 int r; 124 125 if (rdev->gart.robj) { 126 WARN(1, "RV370 PCIE GART already initialized\n"); 127 return 0; 128 } 129 /* Initialize common gart structure */ 130 r = radeon_gart_init(rdev); 131 if (r) 132 return r; 133 r = rv370_debugfs_pcie_gart_info_init(rdev); 134 if (r) 135 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 136 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 137 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 138 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 139 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 140 return radeon_gart_table_vram_alloc(rdev); 141 } 142 143 int rv370_pcie_gart_enable(struct radeon_device *rdev) 144 { 145 uint32_t table_addr; 146 uint32_t tmp; 147 int r; 148 149 if (rdev->gart.robj == NULL) { 150 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 151 return -EINVAL; 152 } 153 r = radeon_gart_table_vram_pin(rdev); 154 if (r) 155 return r; 156 /* discard memory request outside of configured range */ 157 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 158 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 160 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 162 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 163 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 164 table_addr = rdev->gart.table_addr; 165 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 166 /* FIXME: setup default page */ 167 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 168 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 169 /* Clear error */ 170 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 171 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 172 tmp |= RADEON_PCIE_TX_GART_EN; 173 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 174 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 175 rv370_pcie_gart_tlb_flush(rdev); 176 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 177 (unsigned)(rdev->mc.gtt_size >> 20), 178 (unsigned long long)table_addr); 179 rdev->gart.ready = true; 180 return 0; 181 } 182 183 void rv370_pcie_gart_disable(struct radeon_device *rdev) 184 { 185 u32 tmp; 186 187 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 188 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 189 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 190 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 191 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 192 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 193 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 194 radeon_gart_table_vram_unpin(rdev); 195 } 196 197 void rv370_pcie_gart_fini(struct radeon_device *rdev) 198 { 199 radeon_gart_fini(rdev); 200 rv370_pcie_gart_disable(rdev); 201 radeon_gart_table_vram_free(rdev); 202 } 203 204 void r300_fence_ring_emit(struct radeon_device *rdev, 205 struct radeon_fence *fence) 206 { 207 struct radeon_ring *ring = &rdev->ring[fence->ring]; 208 209 /* Who ever call radeon_fence_emit should call ring_lock and ask 210 * for enough space (today caller are ib schedule and buffer move) */ 211 /* Write SC register so SC & US assert idle */ 212 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 213 radeon_ring_write(ring, 0); 214 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 215 radeon_ring_write(ring, 0); 216 /* Flush 3D cache */ 217 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 218 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 219 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 220 radeon_ring_write(ring, R300_ZC_FLUSH); 221 /* Wait until IDLE & CLEAN */ 222 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 223 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 224 RADEON_WAIT_2D_IDLECLEAN | 225 RADEON_WAIT_DMA_GUI_IDLE)); 226 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 227 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 228 RADEON_HDP_READ_BUFFER_INVALIDATE); 229 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 230 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 231 /* Emit fence sequence & fire IRQ */ 232 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 233 radeon_ring_write(ring, fence->seq); 234 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 235 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 236 } 237 238 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 239 { 240 unsigned gb_tile_config; 241 int r; 242 243 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 244 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 245 switch(rdev->num_gb_pipes) { 246 case 2: 247 gb_tile_config |= R300_PIPE_COUNT_R300; 248 break; 249 case 3: 250 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 251 break; 252 case 4: 253 gb_tile_config |= R300_PIPE_COUNT_R420; 254 break; 255 case 1: 256 default: 257 gb_tile_config |= R300_PIPE_COUNT_RV350; 258 break; 259 } 260 261 r = radeon_ring_lock(rdev, ring, 64); 262 if (r) { 263 return; 264 } 265 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 266 radeon_ring_write(ring, 267 RADEON_ISYNC_ANY2D_IDLE3D | 268 RADEON_ISYNC_ANY3D_IDLE2D | 269 RADEON_ISYNC_WAIT_IDLEGUI | 270 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 271 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 272 radeon_ring_write(ring, gb_tile_config); 273 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 274 radeon_ring_write(ring, 275 RADEON_WAIT_2D_IDLECLEAN | 276 RADEON_WAIT_3D_IDLECLEAN); 277 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 278 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 279 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 280 radeon_ring_write(ring, 0); 281 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 282 radeon_ring_write(ring, 0); 283 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 284 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 285 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 286 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 287 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 288 radeon_ring_write(ring, 289 RADEON_WAIT_2D_IDLECLEAN | 290 RADEON_WAIT_3D_IDLECLEAN); 291 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 292 radeon_ring_write(ring, 0); 293 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 294 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 295 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 296 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 297 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 298 radeon_ring_write(ring, 299 ((6 << R300_MS_X0_SHIFT) | 300 (6 << R300_MS_Y0_SHIFT) | 301 (6 << R300_MS_X1_SHIFT) | 302 (6 << R300_MS_Y1_SHIFT) | 303 (6 << R300_MS_X2_SHIFT) | 304 (6 << R300_MS_Y2_SHIFT) | 305 (6 << R300_MSBD0_Y_SHIFT) | 306 (6 << R300_MSBD0_X_SHIFT))); 307 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 308 radeon_ring_write(ring, 309 ((6 << R300_MS_X3_SHIFT) | 310 (6 << R300_MS_Y3_SHIFT) | 311 (6 << R300_MS_X4_SHIFT) | 312 (6 << R300_MS_Y4_SHIFT) | 313 (6 << R300_MS_X5_SHIFT) | 314 (6 << R300_MS_Y5_SHIFT) | 315 (6 << R300_MSBD1_SHIFT))); 316 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 317 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 318 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 319 radeon_ring_write(ring, 320 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 321 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 322 radeon_ring_write(ring, 323 R300_GEOMETRY_ROUND_NEAREST | 324 R300_COLOR_ROUND_NEAREST); 325 radeon_ring_unlock_commit(rdev, ring, false); 326 } 327 328 static void r300_errata(struct radeon_device *rdev) 329 { 330 rdev->pll_errata = 0; 331 332 if (rdev->family == CHIP_R300 && 333 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 334 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 335 } 336 } 337 338 int r300_mc_wait_for_idle(struct radeon_device *rdev) 339 { 340 unsigned i; 341 uint32_t tmp; 342 343 for (i = 0; i < rdev->usec_timeout; i++) { 344 /* read MC_STATUS */ 345 tmp = RREG32(RADEON_MC_STATUS); 346 if (tmp & R300_MC_IDLE) { 347 return 0; 348 } 349 DRM_UDELAY(1); 350 } 351 return -1; 352 } 353 354 static void r300_gpu_init(struct radeon_device *rdev) 355 { 356 uint32_t gb_tile_config, tmp; 357 358 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 359 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 360 /* r300,r350 */ 361 rdev->num_gb_pipes = 2; 362 } else { 363 /* rv350,rv370,rv380,r300 AD, r350 AH */ 364 rdev->num_gb_pipes = 1; 365 } 366 rdev->num_z_pipes = 1; 367 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 368 switch (rdev->num_gb_pipes) { 369 case 2: 370 gb_tile_config |= R300_PIPE_COUNT_R300; 371 break; 372 case 3: 373 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 374 break; 375 case 4: 376 gb_tile_config |= R300_PIPE_COUNT_R420; 377 break; 378 default: 379 case 1: 380 gb_tile_config |= R300_PIPE_COUNT_RV350; 381 break; 382 } 383 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 384 385 if (r100_gui_wait_for_idle(rdev)) { 386 printk(KERN_WARNING "Failed to wait GUI idle while " 387 "programming pipes. Bad things might happen.\n"); 388 } 389 390 tmp = RREG32(R300_DST_PIPE_CONFIG); 391 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 392 393 WREG32(R300_RB2D_DSTCACHE_MODE, 394 R300_DC_AUTOFLUSH_ENABLE | 395 R300_DC_DC_DISABLE_IGNORE_PE); 396 397 if (r100_gui_wait_for_idle(rdev)) { 398 printk(KERN_WARNING "Failed to wait GUI idle while " 399 "programming pipes. Bad things might happen.\n"); 400 } 401 if (r300_mc_wait_for_idle(rdev)) { 402 printk(KERN_WARNING "Failed to wait MC idle while " 403 "programming pipes. Bad things might happen.\n"); 404 } 405 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 406 rdev->num_gb_pipes, rdev->num_z_pipes); 407 } 408 409 int r300_asic_reset(struct radeon_device *rdev, bool hard) 410 { 411 struct r100_mc_save save; 412 u32 status, tmp; 413 int ret = 0; 414 415 status = RREG32(R_000E40_RBBM_STATUS); 416 if (!G_000E40_GUI_ACTIVE(status)) { 417 return 0; 418 } 419 r100_mc_stop(rdev, &save); 420 status = RREG32(R_000E40_RBBM_STATUS); 421 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 422 /* stop CP */ 423 WREG32(RADEON_CP_CSQ_CNTL, 0); 424 tmp = RREG32(RADEON_CP_RB_CNTL); 425 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 426 WREG32(RADEON_CP_RB_RPTR_WR, 0); 427 WREG32(RADEON_CP_RB_WPTR, 0); 428 WREG32(RADEON_CP_RB_CNTL, tmp); 429 /* save PCI state */ 430 pci_save_state(device_get_parent(rdev->dev->bsddev)); 431 /* disable bus mastering */ 432 r100_bm_disable(rdev); 433 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 434 S_0000F0_SOFT_RESET_GA(1)); 435 RREG32(R_0000F0_RBBM_SOFT_RESET); 436 mdelay(500); 437 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 438 mdelay(1); 439 status = RREG32(R_000E40_RBBM_STATUS); 440 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 441 /* resetting the CP seems to be problematic sometimes it end up 442 * hard locking the computer, but it's necessary for successful 443 * reset more test & playing is needed on R3XX/R4XX to find a 444 * reliable (if any solution) 445 */ 446 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 447 RREG32(R_0000F0_RBBM_SOFT_RESET); 448 mdelay(500); 449 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 450 mdelay(1); 451 status = RREG32(R_000E40_RBBM_STATUS); 452 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 453 /* restore PCI & busmastering */ 454 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 455 r100_enable_bm(rdev); 456 /* Check if GPU is idle */ 457 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 458 dev_err(rdev->dev, "failed to reset GPU\n"); 459 ret = -1; 460 } else 461 dev_info(rdev->dev, "GPU reset succeed\n"); 462 r100_mc_resume(rdev, &save); 463 return ret; 464 } 465 466 /* 467 * r300,r350,rv350,rv380 VRAM info 468 */ 469 void r300_mc_init(struct radeon_device *rdev) 470 { 471 u64 base; 472 u32 tmp; 473 474 /* DDR for all card after R300 & IGP */ 475 rdev->mc.vram_is_ddr = true; 476 tmp = RREG32(RADEON_MEM_CNTL); 477 tmp &= R300_MEM_NUM_CHANNELS_MASK; 478 switch (tmp) { 479 case 0: rdev->mc.vram_width = 64; break; 480 case 1: rdev->mc.vram_width = 128; break; 481 case 2: rdev->mc.vram_width = 256; break; 482 default: rdev->mc.vram_width = 128; break; 483 } 484 r100_vram_init_sizes(rdev); 485 base = rdev->mc.aper_base; 486 if (rdev->flags & RADEON_IS_IGP) 487 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 488 radeon_vram_location(rdev, &rdev->mc, base); 489 rdev->mc.gtt_base_align = 0; 490 if (!(rdev->flags & RADEON_IS_AGP)) 491 radeon_gtt_location(rdev, &rdev->mc); 492 radeon_update_bandwidth_info(rdev); 493 } 494 495 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 496 { 497 uint32_t link_width_cntl, mask; 498 499 if (rdev->flags & RADEON_IS_IGP) 500 return; 501 502 if (!(rdev->flags & RADEON_IS_PCIE)) 503 return; 504 505 /* FIXME wait for idle */ 506 507 switch (lanes) { 508 case 0: 509 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 510 break; 511 case 1: 512 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 513 break; 514 case 2: 515 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 516 break; 517 case 4: 518 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 519 break; 520 case 8: 521 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 522 break; 523 case 12: 524 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 525 break; 526 case 16: 527 default: 528 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 529 break; 530 } 531 532 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 533 534 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 535 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 536 return; 537 538 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 539 RADEON_PCIE_LC_RECONFIG_NOW | 540 RADEON_PCIE_LC_RECONFIG_LATER | 541 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 542 link_width_cntl |= mask; 543 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 544 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 545 RADEON_PCIE_LC_RECONFIG_NOW)); 546 547 /* wait for lane set to complete */ 548 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 549 while (link_width_cntl == 0xffffffff) 550 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 551 552 } 553 554 int rv370_get_pcie_lanes(struct radeon_device *rdev) 555 { 556 u32 link_width_cntl; 557 558 if (rdev->flags & RADEON_IS_IGP) 559 return 0; 560 561 if (!(rdev->flags & RADEON_IS_PCIE)) 562 return 0; 563 564 /* FIXME wait for idle */ 565 566 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 567 568 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 569 case RADEON_PCIE_LC_LINK_WIDTH_X0: 570 return 0; 571 case RADEON_PCIE_LC_LINK_WIDTH_X1: 572 return 1; 573 case RADEON_PCIE_LC_LINK_WIDTH_X2: 574 return 2; 575 case RADEON_PCIE_LC_LINK_WIDTH_X4: 576 return 4; 577 case RADEON_PCIE_LC_LINK_WIDTH_X8: 578 return 8; 579 case RADEON_PCIE_LC_LINK_WIDTH_X16: 580 default: 581 return 16; 582 } 583 } 584 585 #if defined(CONFIG_DEBUG_FS) 586 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 587 { 588 struct drm_info_node *node = (struct drm_info_node *) m->private; 589 struct drm_device *dev = node->minor->dev; 590 struct radeon_device *rdev = dev->dev_private; 591 uint32_t tmp; 592 593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 594 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 596 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 598 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 600 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 602 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 604 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 606 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 607 return 0; 608 } 609 610 static struct drm_info_list rv370_pcie_gart_info_list[] = { 611 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 612 }; 613 #endif 614 615 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 616 { 617 #if defined(CONFIG_DEBUG_FS) 618 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 619 #else 620 return 0; 621 #endif 622 } 623 624 static int r300_packet0_check(struct radeon_cs_parser *p, 625 struct radeon_cs_packet *pkt, 626 unsigned idx, unsigned reg) 627 { 628 struct radeon_bo_list *reloc; 629 struct r100_cs_track *track; 630 volatile uint32_t *ib; 631 uint32_t tmp, tile_flags = 0; 632 unsigned i; 633 int r; 634 u32 idx_value; 635 636 ib = p->ib.ptr; 637 track = (struct r100_cs_track *)p->track; 638 idx_value = radeon_get_ib_value(p, idx); 639 640 switch(reg) { 641 case AVIVO_D1MODE_VLINE_START_END: 642 case RADEON_CRTC_GUI_TRIG_VLINE: 643 r = r100_cs_packet_parse_vline(p); 644 if (r) { 645 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 646 idx, reg); 647 radeon_cs_dump_packet(p, pkt); 648 return r; 649 } 650 break; 651 case RADEON_DST_PITCH_OFFSET: 652 case RADEON_SRC_PITCH_OFFSET: 653 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 654 if (r) 655 return r; 656 break; 657 case R300_RB3D_COLOROFFSET0: 658 case R300_RB3D_COLOROFFSET1: 659 case R300_RB3D_COLOROFFSET2: 660 case R300_RB3D_COLOROFFSET3: 661 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 662 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 663 if (r) { 664 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 665 idx, reg); 666 radeon_cs_dump_packet(p, pkt); 667 return r; 668 } 669 track->cb[i].robj = reloc->robj; 670 track->cb[i].offset = idx_value; 671 track->cb_dirty = true; 672 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 673 break; 674 case R300_ZB_DEPTHOFFSET: 675 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 676 if (r) { 677 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 678 idx, reg); 679 radeon_cs_dump_packet(p, pkt); 680 return r; 681 } 682 track->zb.robj = reloc->robj; 683 track->zb.offset = idx_value; 684 track->zb_dirty = true; 685 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 686 break; 687 case R300_TX_OFFSET_0: 688 case R300_TX_OFFSET_0+4: 689 case R300_TX_OFFSET_0+8: 690 case R300_TX_OFFSET_0+12: 691 case R300_TX_OFFSET_0+16: 692 case R300_TX_OFFSET_0+20: 693 case R300_TX_OFFSET_0+24: 694 case R300_TX_OFFSET_0+28: 695 case R300_TX_OFFSET_0+32: 696 case R300_TX_OFFSET_0+36: 697 case R300_TX_OFFSET_0+40: 698 case R300_TX_OFFSET_0+44: 699 case R300_TX_OFFSET_0+48: 700 case R300_TX_OFFSET_0+52: 701 case R300_TX_OFFSET_0+56: 702 case R300_TX_OFFSET_0+60: 703 i = (reg - R300_TX_OFFSET_0) >> 2; 704 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 705 if (r) { 706 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 707 idx, reg); 708 radeon_cs_dump_packet(p, pkt); 709 return r; 710 } 711 712 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 713 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 714 ((idx_value & ~31) + (u32)reloc->gpu_offset); 715 } else { 716 if (reloc->tiling_flags & RADEON_TILING_MACRO) 717 tile_flags |= R300_TXO_MACRO_TILE; 718 if (reloc->tiling_flags & RADEON_TILING_MICRO) 719 tile_flags |= R300_TXO_MICRO_TILE; 720 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 721 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 722 723 tmp = idx_value + ((u32)reloc->gpu_offset); 724 tmp |= tile_flags; 725 ib[idx] = tmp; 726 } 727 track->textures[i].robj = reloc->robj; 728 track->tex_dirty = true; 729 break; 730 /* Tracked registers */ 731 case 0x2084: 732 /* VAP_VF_CNTL */ 733 track->vap_vf_cntl = idx_value; 734 break; 735 case 0x20B4: 736 /* VAP_VTX_SIZE */ 737 track->vtx_size = idx_value & 0x7F; 738 break; 739 case 0x2134: 740 /* VAP_VF_MAX_VTX_INDX */ 741 track->max_indx = idx_value & 0x00FFFFFFUL; 742 break; 743 case 0x2088: 744 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 745 if (p->rdev->family < CHIP_RV515) 746 goto fail; 747 track->vap_alt_nverts = idx_value & 0xFFFFFF; 748 break; 749 case 0x43E4: 750 /* SC_SCISSOR1 */ 751 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 752 if (p->rdev->family < CHIP_RV515) { 753 track->maxy -= 1440; 754 } 755 track->cb_dirty = true; 756 track->zb_dirty = true; 757 break; 758 case 0x4E00: 759 /* RB3D_CCTL */ 760 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 761 p->rdev->cmask_filp != p->filp) { 762 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 763 return -EINVAL; 764 } 765 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 766 track->cb_dirty = true; 767 break; 768 case 0x4E38: 769 case 0x4E3C: 770 case 0x4E40: 771 case 0x4E44: 772 /* RB3D_COLORPITCH0 */ 773 /* RB3D_COLORPITCH1 */ 774 /* RB3D_COLORPITCH2 */ 775 /* RB3D_COLORPITCH3 */ 776 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 777 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 778 if (r) { 779 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 780 idx, reg); 781 radeon_cs_dump_packet(p, pkt); 782 return r; 783 } 784 785 if (reloc->tiling_flags & RADEON_TILING_MACRO) 786 tile_flags |= R300_COLOR_TILE_ENABLE; 787 if (reloc->tiling_flags & RADEON_TILING_MICRO) 788 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 789 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 790 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 791 792 tmp = idx_value & ~(0x7 << 16); 793 tmp |= tile_flags; 794 ib[idx] = tmp; 795 } 796 i = (reg - 0x4E38) >> 2; 797 track->cb[i].pitch = idx_value & 0x3FFE; 798 switch (((idx_value >> 21) & 0xF)) { 799 case 9: 800 case 11: 801 case 12: 802 track->cb[i].cpp = 1; 803 break; 804 case 3: 805 case 4: 806 case 13: 807 case 15: 808 track->cb[i].cpp = 2; 809 break; 810 case 5: 811 if (p->rdev->family < CHIP_RV515) { 812 DRM_ERROR("Invalid color buffer format (%d)!\n", 813 ((idx_value >> 21) & 0xF)); 814 return -EINVAL; 815 } 816 /* Pass through. */ 817 case 6: 818 track->cb[i].cpp = 4; 819 break; 820 case 10: 821 track->cb[i].cpp = 8; 822 break; 823 case 7: 824 track->cb[i].cpp = 16; 825 break; 826 default: 827 DRM_ERROR("Invalid color buffer format (%d) !\n", 828 ((idx_value >> 21) & 0xF)); 829 return -EINVAL; 830 } 831 track->cb_dirty = true; 832 break; 833 case 0x4F00: 834 /* ZB_CNTL */ 835 if (idx_value & 2) { 836 track->z_enabled = true; 837 } else { 838 track->z_enabled = false; 839 } 840 track->zb_dirty = true; 841 break; 842 case 0x4F10: 843 /* ZB_FORMAT */ 844 switch ((idx_value & 0xF)) { 845 case 0: 846 case 1: 847 track->zb.cpp = 2; 848 break; 849 case 2: 850 track->zb.cpp = 4; 851 break; 852 default: 853 DRM_ERROR("Invalid z buffer format (%d) !\n", 854 (idx_value & 0xF)); 855 return -EINVAL; 856 } 857 track->zb_dirty = true; 858 break; 859 case 0x4F24: 860 /* ZB_DEPTHPITCH */ 861 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 862 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 863 if (r) { 864 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 865 idx, reg); 866 radeon_cs_dump_packet(p, pkt); 867 return r; 868 } 869 870 if (reloc->tiling_flags & RADEON_TILING_MACRO) 871 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 872 if (reloc->tiling_flags & RADEON_TILING_MICRO) 873 tile_flags |= R300_DEPTHMICROTILE_TILED; 874 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 875 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 876 877 tmp = idx_value & ~(0x7 << 16); 878 tmp |= tile_flags; 879 ib[idx] = tmp; 880 } 881 track->zb.pitch = idx_value & 0x3FFC; 882 track->zb_dirty = true; 883 break; 884 case 0x4104: 885 /* TX_ENABLE */ 886 for (i = 0; i < 16; i++) { 887 bool enabled; 888 889 enabled = !!(idx_value & (1 << i)); 890 track->textures[i].enabled = enabled; 891 } 892 track->tex_dirty = true; 893 break; 894 case 0x44C0: 895 case 0x44C4: 896 case 0x44C8: 897 case 0x44CC: 898 case 0x44D0: 899 case 0x44D4: 900 case 0x44D8: 901 case 0x44DC: 902 case 0x44E0: 903 case 0x44E4: 904 case 0x44E8: 905 case 0x44EC: 906 case 0x44F0: 907 case 0x44F4: 908 case 0x44F8: 909 case 0x44FC: 910 /* TX_FORMAT1_[0-15] */ 911 i = (reg - 0x44C0) >> 2; 912 tmp = (idx_value >> 25) & 0x3; 913 track->textures[i].tex_coord_type = tmp; 914 switch ((idx_value & 0x1F)) { 915 case R300_TX_FORMAT_X8: 916 case R300_TX_FORMAT_Y4X4: 917 case R300_TX_FORMAT_Z3Y3X2: 918 track->textures[i].cpp = 1; 919 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 920 break; 921 case R300_TX_FORMAT_X16: 922 case R300_TX_FORMAT_FL_I16: 923 case R300_TX_FORMAT_Y8X8: 924 case R300_TX_FORMAT_Z5Y6X5: 925 case R300_TX_FORMAT_Z6Y5X5: 926 case R300_TX_FORMAT_W4Z4Y4X4: 927 case R300_TX_FORMAT_W1Z5Y5X5: 928 case R300_TX_FORMAT_D3DMFT_CxV8U8: 929 case R300_TX_FORMAT_B8G8_B8G8: 930 case R300_TX_FORMAT_G8R8_G8B8: 931 track->textures[i].cpp = 2; 932 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 933 break; 934 case R300_TX_FORMAT_Y16X16: 935 case R300_TX_FORMAT_FL_I16A16: 936 case R300_TX_FORMAT_Z11Y11X10: 937 case R300_TX_FORMAT_Z10Y11X11: 938 case R300_TX_FORMAT_W8Z8Y8X8: 939 case R300_TX_FORMAT_W2Z10Y10X10: 940 case 0x17: 941 case R300_TX_FORMAT_FL_I32: 942 case 0x1e: 943 track->textures[i].cpp = 4; 944 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 945 break; 946 case R300_TX_FORMAT_W16Z16Y16X16: 947 case R300_TX_FORMAT_FL_R16G16B16A16: 948 case R300_TX_FORMAT_FL_I32A32: 949 track->textures[i].cpp = 8; 950 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 951 break; 952 case R300_TX_FORMAT_FL_R32G32B32A32: 953 track->textures[i].cpp = 16; 954 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 955 break; 956 case R300_TX_FORMAT_DXT1: 957 track->textures[i].cpp = 1; 958 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 959 break; 960 case R300_TX_FORMAT_ATI2N: 961 if (p->rdev->family < CHIP_R420) { 962 DRM_ERROR("Invalid texture format %u\n", 963 (idx_value & 0x1F)); 964 return -EINVAL; 965 } 966 /* The same rules apply as for DXT3/5. */ 967 /* Pass through. */ 968 case R300_TX_FORMAT_DXT3: 969 case R300_TX_FORMAT_DXT5: 970 track->textures[i].cpp = 1; 971 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 972 break; 973 default: 974 DRM_ERROR("Invalid texture format %u\n", 975 (idx_value & 0x1F)); 976 return -EINVAL; 977 } 978 track->tex_dirty = true; 979 break; 980 case 0x4400: 981 case 0x4404: 982 case 0x4408: 983 case 0x440C: 984 case 0x4410: 985 case 0x4414: 986 case 0x4418: 987 case 0x441C: 988 case 0x4420: 989 case 0x4424: 990 case 0x4428: 991 case 0x442C: 992 case 0x4430: 993 case 0x4434: 994 case 0x4438: 995 case 0x443C: 996 /* TX_FILTER0_[0-15] */ 997 i = (reg - 0x4400) >> 2; 998 tmp = idx_value & 0x7; 999 if (tmp == 2 || tmp == 4 || tmp == 6) { 1000 track->textures[i].roundup_w = false; 1001 } 1002 tmp = (idx_value >> 3) & 0x7; 1003 if (tmp == 2 || tmp == 4 || tmp == 6) { 1004 track->textures[i].roundup_h = false; 1005 } 1006 track->tex_dirty = true; 1007 break; 1008 case 0x4500: 1009 case 0x4504: 1010 case 0x4508: 1011 case 0x450C: 1012 case 0x4510: 1013 case 0x4514: 1014 case 0x4518: 1015 case 0x451C: 1016 case 0x4520: 1017 case 0x4524: 1018 case 0x4528: 1019 case 0x452C: 1020 case 0x4530: 1021 case 0x4534: 1022 case 0x4538: 1023 case 0x453C: 1024 /* TX_FORMAT2_[0-15] */ 1025 i = (reg - 0x4500) >> 2; 1026 tmp = idx_value & 0x3FFF; 1027 track->textures[i].pitch = tmp + 1; 1028 if (p->rdev->family >= CHIP_RV515) { 1029 tmp = ((idx_value >> 15) & 1) << 11; 1030 track->textures[i].width_11 = tmp; 1031 tmp = ((idx_value >> 16) & 1) << 11; 1032 track->textures[i].height_11 = tmp; 1033 1034 /* ATI1N */ 1035 if (idx_value & (1 << 14)) { 1036 /* The same rules apply as for DXT1. */ 1037 track->textures[i].compress_format = 1038 R100_TRACK_COMP_DXT1; 1039 } 1040 } else if (idx_value & (1 << 14)) { 1041 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1042 return -EINVAL; 1043 } 1044 track->tex_dirty = true; 1045 break; 1046 case 0x4480: 1047 case 0x4484: 1048 case 0x4488: 1049 case 0x448C: 1050 case 0x4490: 1051 case 0x4494: 1052 case 0x4498: 1053 case 0x449C: 1054 case 0x44A0: 1055 case 0x44A4: 1056 case 0x44A8: 1057 case 0x44AC: 1058 case 0x44B0: 1059 case 0x44B4: 1060 case 0x44B8: 1061 case 0x44BC: 1062 /* TX_FORMAT0_[0-15] */ 1063 i = (reg - 0x4480) >> 2; 1064 tmp = idx_value & 0x7FF; 1065 track->textures[i].width = tmp + 1; 1066 tmp = (idx_value >> 11) & 0x7FF; 1067 track->textures[i].height = tmp + 1; 1068 tmp = (idx_value >> 26) & 0xF; 1069 track->textures[i].num_levels = tmp; 1070 tmp = idx_value & (1 << 31); 1071 track->textures[i].use_pitch = !!tmp; 1072 tmp = (idx_value >> 22) & 0xF; 1073 track->textures[i].txdepth = tmp; 1074 track->tex_dirty = true; 1075 break; 1076 case R300_ZB_ZPASS_ADDR: 1077 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1078 if (r) { 1079 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1080 idx, reg); 1081 radeon_cs_dump_packet(p, pkt); 1082 return r; 1083 } 1084 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1085 break; 1086 case 0x4e0c: 1087 /* RB3D_COLOR_CHANNEL_MASK */ 1088 track->color_channel_mask = idx_value; 1089 track->cb_dirty = true; 1090 break; 1091 case 0x43a4: 1092 /* SC_HYPERZ_EN */ 1093 /* r300c emits this register - we need to disable hyperz for it 1094 * without complaining */ 1095 if (p->rdev->hyperz_filp != p->filp) { 1096 if (idx_value & 0x1) 1097 ib[idx] = idx_value & ~1; 1098 } 1099 break; 1100 case 0x4f1c: 1101 /* ZB_BW_CNTL */ 1102 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1103 track->cb_dirty = true; 1104 track->zb_dirty = true; 1105 if (p->rdev->hyperz_filp != p->filp) { 1106 if (idx_value & (R300_HIZ_ENABLE | 1107 R300_RD_COMP_ENABLE | 1108 R300_WR_COMP_ENABLE | 1109 R300_FAST_FILL_ENABLE)) 1110 goto fail; 1111 } 1112 break; 1113 case 0x4e04: 1114 /* RB3D_BLENDCNTL */ 1115 track->blend_read_enable = !!(idx_value & (1 << 2)); 1116 track->cb_dirty = true; 1117 break; 1118 case R300_RB3D_AARESOLVE_OFFSET: 1119 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1120 if (r) { 1121 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1122 idx, reg); 1123 radeon_cs_dump_packet(p, pkt); 1124 return r; 1125 } 1126 track->aa.robj = reloc->robj; 1127 track->aa.offset = idx_value; 1128 track->aa_dirty = true; 1129 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1130 break; 1131 case R300_RB3D_AARESOLVE_PITCH: 1132 track->aa.pitch = idx_value & 0x3FFE; 1133 track->aa_dirty = true; 1134 break; 1135 case R300_RB3D_AARESOLVE_CTL: 1136 track->aaresolve = idx_value & 0x1; 1137 track->aa_dirty = true; 1138 break; 1139 case 0x4f30: /* ZB_MASK_OFFSET */ 1140 case 0x4f34: /* ZB_ZMASK_PITCH */ 1141 case 0x4f44: /* ZB_HIZ_OFFSET */ 1142 case 0x4f54: /* ZB_HIZ_PITCH */ 1143 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1144 goto fail; 1145 break; 1146 case 0x4028: 1147 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1148 goto fail; 1149 /* GB_Z_PEQ_CONFIG */ 1150 if (p->rdev->family >= CHIP_RV350) 1151 break; 1152 goto fail; 1153 break; 1154 case 0x4be8: 1155 /* valid register only on RV530 */ 1156 if (p->rdev->family == CHIP_RV530) 1157 break; 1158 /* fallthrough do not move */ 1159 default: 1160 goto fail; 1161 } 1162 return 0; 1163 fail: 1164 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1165 reg, idx, idx_value); 1166 return -EINVAL; 1167 } 1168 1169 static int r300_packet3_check(struct radeon_cs_parser *p, 1170 struct radeon_cs_packet *pkt) 1171 { 1172 struct radeon_bo_list *reloc; 1173 struct r100_cs_track *track; 1174 volatile uint32_t *ib; 1175 unsigned idx; 1176 int r; 1177 1178 ib = p->ib.ptr; 1179 idx = pkt->idx + 1; 1180 track = (struct r100_cs_track *)p->track; 1181 switch(pkt->opcode) { 1182 case PACKET3_3D_LOAD_VBPNTR: 1183 r = r100_packet3_load_vbpntr(p, pkt, idx); 1184 if (r) 1185 return r; 1186 break; 1187 case PACKET3_INDX_BUFFER: 1188 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1189 if (r) { 1190 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1191 radeon_cs_dump_packet(p, pkt); 1192 return r; 1193 } 1194 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1195 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1196 if (r) { 1197 return r; 1198 } 1199 break; 1200 /* Draw packet */ 1201 case PACKET3_3D_DRAW_IMMD: 1202 /* Number of dwords is vtx_size * (num_vertices - 1) 1203 * PRIM_WALK must be equal to 3 vertex data in embedded 1204 * in cmd stream */ 1205 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1206 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1207 return -EINVAL; 1208 } 1209 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1210 track->immd_dwords = pkt->count - 1; 1211 r = r100_cs_track_check(p->rdev, track); 1212 if (r) { 1213 return r; 1214 } 1215 break; 1216 case PACKET3_3D_DRAW_IMMD_2: 1217 /* Number of dwords is vtx_size * (num_vertices - 1) 1218 * PRIM_WALK must be equal to 3 vertex data in embedded 1219 * in cmd stream */ 1220 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1221 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1222 return -EINVAL; 1223 } 1224 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1225 track->immd_dwords = pkt->count; 1226 r = r100_cs_track_check(p->rdev, track); 1227 if (r) { 1228 return r; 1229 } 1230 break; 1231 case PACKET3_3D_DRAW_VBUF: 1232 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1233 r = r100_cs_track_check(p->rdev, track); 1234 if (r) { 1235 return r; 1236 } 1237 break; 1238 case PACKET3_3D_DRAW_VBUF_2: 1239 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1240 r = r100_cs_track_check(p->rdev, track); 1241 if (r) { 1242 return r; 1243 } 1244 break; 1245 case PACKET3_3D_DRAW_INDX: 1246 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1247 r = r100_cs_track_check(p->rdev, track); 1248 if (r) { 1249 return r; 1250 } 1251 break; 1252 case PACKET3_3D_DRAW_INDX_2: 1253 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1254 r = r100_cs_track_check(p->rdev, track); 1255 if (r) { 1256 return r; 1257 } 1258 break; 1259 case PACKET3_3D_CLEAR_HIZ: 1260 case PACKET3_3D_CLEAR_ZMASK: 1261 if (p->rdev->hyperz_filp != p->filp) 1262 return -EINVAL; 1263 break; 1264 case PACKET3_3D_CLEAR_CMASK: 1265 if (p->rdev->cmask_filp != p->filp) 1266 return -EINVAL; 1267 break; 1268 case PACKET3_NOP: 1269 break; 1270 default: 1271 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1272 return -EINVAL; 1273 } 1274 return 0; 1275 } 1276 1277 int r300_cs_parse(struct radeon_cs_parser *p) 1278 { 1279 struct radeon_cs_packet pkt; 1280 struct r100_cs_track *track; 1281 int r; 1282 1283 track = kzalloc(sizeof(*track), GFP_KERNEL); 1284 if (track == NULL) 1285 return -ENOMEM; 1286 r100_cs_track_clear(p->rdev, track); 1287 p->track = track; 1288 do { 1289 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1290 if (r) { 1291 return r; 1292 } 1293 p->idx += pkt.count + 2; 1294 switch (pkt.type) { 1295 case RADEON_PACKET_TYPE0: 1296 r = r100_cs_parse_packet0(p, &pkt, 1297 p->rdev->config.r300.reg_safe_bm, 1298 p->rdev->config.r300.reg_safe_bm_size, 1299 &r300_packet0_check); 1300 break; 1301 case RADEON_PACKET_TYPE2: 1302 break; 1303 case RADEON_PACKET_TYPE3: 1304 r = r300_packet3_check(p, &pkt); 1305 break; 1306 default: 1307 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1308 return -EINVAL; 1309 } 1310 if (r) { 1311 return r; 1312 } 1313 } while (p->idx < p->chunk_ib->length_dw); 1314 return 0; 1315 } 1316 1317 void r300_set_reg_safe(struct radeon_device *rdev) 1318 { 1319 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1320 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1321 } 1322 1323 void r300_mc_program(struct radeon_device *rdev) 1324 { 1325 struct r100_mc_save save; 1326 int r; 1327 1328 r = r100_debugfs_mc_info_init(rdev); 1329 if (r) { 1330 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1331 } 1332 1333 /* Stops all mc clients */ 1334 r100_mc_stop(rdev, &save); 1335 if (rdev->flags & RADEON_IS_AGP) { 1336 WREG32(R_00014C_MC_AGP_LOCATION, 1337 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1338 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1339 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1340 WREG32(R_00015C_AGP_BASE_2, 1341 upper_32_bits(rdev->mc.agp_base) & 0xff); 1342 } else { 1343 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1344 WREG32(R_000170_AGP_BASE, 0); 1345 WREG32(R_00015C_AGP_BASE_2, 0); 1346 } 1347 /* Wait for mc idle */ 1348 if (r300_mc_wait_for_idle(rdev)) 1349 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1350 /* Program MC, should be a 32bits limited address space */ 1351 WREG32(R_000148_MC_FB_LOCATION, 1352 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1353 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1354 r100_mc_resume(rdev, &save); 1355 } 1356 1357 void r300_clock_startup(struct radeon_device *rdev) 1358 { 1359 u32 tmp; 1360 1361 if (radeon_dynclks != -1 && radeon_dynclks) 1362 radeon_legacy_set_clock_gating(rdev, 1); 1363 /* We need to force on some of the block */ 1364 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1365 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1366 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1367 tmp |= S_00000D_FORCE_VAP(1); 1368 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1369 } 1370 1371 static int r300_startup(struct radeon_device *rdev) 1372 { 1373 int r; 1374 1375 /* set common regs */ 1376 r100_set_common_regs(rdev); 1377 /* program mc */ 1378 r300_mc_program(rdev); 1379 /* Resume clock */ 1380 r300_clock_startup(rdev); 1381 /* Initialize GPU configuration (# pipes, ...) */ 1382 r300_gpu_init(rdev); 1383 /* Initialize GART (initialize after TTM so we can allocate 1384 * memory through TTM but finalize after TTM) */ 1385 if (rdev->flags & RADEON_IS_PCIE) { 1386 r = rv370_pcie_gart_enable(rdev); 1387 if (r) 1388 return r; 1389 } 1390 1391 if (rdev->family == CHIP_R300 || 1392 rdev->family == CHIP_R350 || 1393 rdev->family == CHIP_RV350) 1394 r100_enable_bm(rdev); 1395 1396 if (rdev->flags & RADEON_IS_PCI) { 1397 r = r100_pci_gart_enable(rdev); 1398 if (r) 1399 return r; 1400 } 1401 1402 /* allocate wb buffer */ 1403 r = radeon_wb_init(rdev); 1404 if (r) 1405 return r; 1406 1407 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1408 if (r) { 1409 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1410 return r; 1411 } 1412 1413 /* Enable IRQ */ 1414 if (!rdev->irq.installed) { 1415 r = radeon_irq_kms_init(rdev); 1416 if (r) 1417 return r; 1418 } 1419 1420 r100_irq_set(rdev); 1421 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1422 /* 1M ring buffer */ 1423 r = r100_cp_init(rdev, 1024 * 1024); 1424 if (r) { 1425 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1426 return r; 1427 } 1428 1429 r = radeon_ib_pool_init(rdev); 1430 if (r) { 1431 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1432 return r; 1433 } 1434 1435 return 0; 1436 } 1437 1438 int r300_resume(struct radeon_device *rdev) 1439 { 1440 int r; 1441 1442 /* Make sur GART are not working */ 1443 if (rdev->flags & RADEON_IS_PCIE) 1444 rv370_pcie_gart_disable(rdev); 1445 if (rdev->flags & RADEON_IS_PCI) 1446 r100_pci_gart_disable(rdev); 1447 /* Resume clock before doing reset */ 1448 r300_clock_startup(rdev); 1449 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1450 if (radeon_asic_reset(rdev)) { 1451 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1452 RREG32(R_000E40_RBBM_STATUS), 1453 RREG32(R_0007C0_CP_STAT)); 1454 } 1455 /* post */ 1456 radeon_combios_asic_init(rdev->ddev); 1457 /* Resume clock after posting */ 1458 r300_clock_startup(rdev); 1459 /* Initialize surface registers */ 1460 radeon_surface_init(rdev); 1461 1462 rdev->accel_working = true; 1463 r = r300_startup(rdev); 1464 if (r) { 1465 rdev->accel_working = false; 1466 } 1467 return r; 1468 } 1469 1470 int r300_suspend(struct radeon_device *rdev) 1471 { 1472 radeon_pm_suspend(rdev); 1473 r100_cp_disable(rdev); 1474 radeon_wb_disable(rdev); 1475 r100_irq_disable(rdev); 1476 if (rdev->flags & RADEON_IS_PCIE) 1477 rv370_pcie_gart_disable(rdev); 1478 if (rdev->flags & RADEON_IS_PCI) 1479 r100_pci_gart_disable(rdev); 1480 return 0; 1481 } 1482 1483 void r300_fini(struct radeon_device *rdev) 1484 { 1485 radeon_pm_fini(rdev); 1486 r100_cp_fini(rdev); 1487 radeon_wb_fini(rdev); 1488 radeon_ib_pool_fini(rdev); 1489 radeon_gem_fini(rdev); 1490 if (rdev->flags & RADEON_IS_PCIE) 1491 rv370_pcie_gart_fini(rdev); 1492 if (rdev->flags & RADEON_IS_PCI) 1493 r100_pci_gart_fini(rdev); 1494 radeon_agp_fini(rdev); 1495 radeon_irq_kms_fini(rdev); 1496 radeon_fence_driver_fini(rdev); 1497 radeon_bo_fini(rdev); 1498 radeon_atombios_fini(rdev); 1499 kfree(rdev->bios); 1500 rdev->bios = NULL; 1501 } 1502 1503 int r300_init(struct radeon_device *rdev) 1504 { 1505 int r; 1506 1507 /* Disable VGA */ 1508 r100_vga_render_disable(rdev); 1509 /* Initialize scratch registers */ 1510 radeon_scratch_init(rdev); 1511 /* Initialize surface registers */ 1512 radeon_surface_init(rdev); 1513 /* TODO: disable VGA need to use VGA request */ 1514 /* restore some register to sane defaults */ 1515 r100_restore_sanity(rdev); 1516 /* BIOS*/ 1517 if (!radeon_get_bios(rdev)) { 1518 if (ASIC_IS_AVIVO(rdev)) 1519 return -EINVAL; 1520 } 1521 if (rdev->is_atom_bios) { 1522 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1523 return -EINVAL; 1524 } else { 1525 r = radeon_combios_init(rdev); 1526 if (r) 1527 return r; 1528 } 1529 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1530 if (radeon_asic_reset(rdev)) { 1531 dev_warn(rdev->dev, 1532 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1533 RREG32(R_000E40_RBBM_STATUS), 1534 RREG32(R_0007C0_CP_STAT)); 1535 } 1536 /* check if cards are posted or not */ 1537 if (radeon_boot_test_post_card(rdev) == false) 1538 return -EINVAL; 1539 /* Set asic errata */ 1540 r300_errata(rdev); 1541 /* Initialize clocks */ 1542 radeon_get_clock_info(rdev->ddev); 1543 /* initialize AGP */ 1544 if (rdev->flags & RADEON_IS_AGP) { 1545 r = radeon_agp_init(rdev); 1546 if (r) { 1547 radeon_agp_disable(rdev); 1548 } 1549 } 1550 /* initialize memory controller */ 1551 r300_mc_init(rdev); 1552 /* Fence driver */ 1553 r = radeon_fence_driver_init(rdev); 1554 if (r) 1555 return r; 1556 /* Memory manager */ 1557 r = radeon_bo_init(rdev); 1558 if (r) 1559 return r; 1560 if (rdev->flags & RADEON_IS_PCIE) { 1561 r = rv370_pcie_gart_init(rdev); 1562 if (r) 1563 return r; 1564 } 1565 if (rdev->flags & RADEON_IS_PCI) { 1566 r = r100_pci_gart_init(rdev); 1567 if (r) 1568 return r; 1569 } 1570 r300_set_reg_safe(rdev); 1571 1572 /* Initialize power management */ 1573 radeon_pm_init(rdev); 1574 1575 rdev->accel_working = true; 1576 r = r300_startup(rdev); 1577 if (r) { 1578 /* Something went wrong with the accel init, so stop accel */ 1579 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1580 r100_cp_fini(rdev); 1581 radeon_wb_fini(rdev); 1582 radeon_ib_pool_fini(rdev); 1583 radeon_irq_kms_fini(rdev); 1584 if (rdev->flags & RADEON_IS_PCIE) 1585 rv370_pcie_gart_fini(rdev); 1586 if (rdev->flags & RADEON_IS_PCI) 1587 r100_pci_gart_fini(rdev); 1588 radeon_agp_fini(rdev); 1589 rdev->accel_working = false; 1590 } 1591 return 0; 1592 } 1593