1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r420.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "r100d.h" 37 #include "r420d.h" 38 #include "r420_reg_safe.h" 39 40 void r420_pm_init_profile(struct radeon_device *rdev) 41 { 42 /* default */ 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 46 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 47 /* low sh */ 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 51 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 52 /* mid sh */ 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 56 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 57 /* high sh */ 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 61 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 62 /* low mh */ 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 66 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 67 /* mid mh */ 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 71 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 72 /* high mh */ 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 76 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 77 } 78 79 static void r420_set_reg_safe(struct radeon_device *rdev) 80 { 81 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 82 rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(r420_reg_safe_bm); 83 } 84 85 void r420_pipes_init(struct radeon_device *rdev) 86 { 87 unsigned tmp; 88 unsigned gb_pipe_select; 89 unsigned num_pipes; 90 91 /* GA_ENHANCE workaround TCL deadlock issue */ 92 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 93 (1 << 2) | (1 << 3)); 94 /* add idle wait as per freedesktop.org bug 24041 */ 95 if (r100_gui_wait_for_idle(rdev)) { 96 DRM_ERROR("Failed to wait GUI idle while " 97 "programming pipes. Bad things might happen.\n"); 98 } 99 /* get max number of pipes */ 100 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 101 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 102 103 /* SE chips have 1 pipe */ 104 if ((rdev->ddev->pci_device == 0x5e4c) || 105 (rdev->ddev->pci_device == 0x5e4f)) 106 num_pipes = 1; 107 108 rdev->num_gb_pipes = num_pipes; 109 tmp = 0; 110 switch (num_pipes) { 111 default: 112 /* force to 1 pipe */ 113 num_pipes = 1; 114 case 1: 115 tmp = (0 << 1); 116 break; 117 case 2: 118 tmp = (3 << 1); 119 break; 120 case 3: 121 tmp = (6 << 1); 122 break; 123 case 4: 124 tmp = (7 << 1); 125 break; 126 } 127 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 128 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 129 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 130 WREG32(R300_GB_TILE_CONFIG, tmp); 131 if (r100_gui_wait_for_idle(rdev)) { 132 DRM_ERROR("Failed to wait GUI idle while " 133 "programming pipes. Bad things might happen.\n"); 134 } 135 136 tmp = RREG32(R300_DST_PIPE_CONFIG); 137 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 138 139 WREG32(R300_RB2D_DSTCACHE_MODE, 140 RREG32(R300_RB2D_DSTCACHE_MODE) | 141 R300_DC_AUTOFLUSH_ENABLE | 142 R300_DC_DC_DISABLE_IGNORE_PE); 143 144 if (r100_gui_wait_for_idle(rdev)) { 145 DRM_ERROR("Failed to wait GUI idle while " 146 "programming pipes. Bad things might happen.\n"); 147 } 148 149 if (rdev->family == CHIP_RV530) { 150 tmp = RREG32(RV530_GB_PIPE_SELECT2); 151 if ((tmp & 3) == 3) 152 rdev->num_z_pipes = 2; 153 else 154 rdev->num_z_pipes = 1; 155 } else 156 rdev->num_z_pipes = 1; 157 158 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 159 rdev->num_gb_pipes, rdev->num_z_pipes); 160 } 161 162 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 163 { 164 u32 r; 165 166 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 167 r = RREG32(R_0001FC_MC_IND_DATA); 168 return r; 169 } 170 171 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 172 { 173 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 174 S_0001F8_MC_IND_WR_EN(1)); 175 WREG32(R_0001FC_MC_IND_DATA, v); 176 } 177 178 static void r420_debugfs(struct radeon_device *rdev) 179 { 180 if (r100_debugfs_rbbm_init(rdev)) { 181 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 182 } 183 if (r420_debugfs_pipes_info_init(rdev)) { 184 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 185 } 186 } 187 188 static void r420_clock_resume(struct radeon_device *rdev) 189 { 190 u32 sclk_cntl; 191 192 if (radeon_dynclks != -1 && radeon_dynclks) 193 radeon_atom_set_clock_gating(rdev, 1); 194 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 195 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 196 if (rdev->family == CHIP_R420) 197 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 198 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 199 } 200 201 static void r420_cp_errata_init(struct radeon_device *rdev) 202 { 203 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 204 205 /* RV410 and R420 can lock up if CP DMA to host memory happens 206 * while the 2D engine is busy. 207 * 208 * The proper workaround is to queue a RESYNC at the beginning 209 * of the CP init, apparently. 210 */ 211 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 212 radeon_ring_lock(rdev, ring, 8); 213 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 214 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 215 radeon_ring_write(ring, 0xDEADBEEF); 216 radeon_ring_unlock_commit(rdev, ring); 217 } 218 219 static void r420_cp_errata_fini(struct radeon_device *rdev) 220 { 221 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 222 223 /* Catch the RESYNC we dispatched all the way back, 224 * at the very beginning of the CP init. 225 */ 226 radeon_ring_lock(rdev, ring, 8); 227 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 228 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 229 radeon_ring_unlock_commit(rdev, ring); 230 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 231 } 232 233 static int r420_startup(struct radeon_device *rdev) 234 { 235 int r; 236 237 /* set common regs */ 238 r100_set_common_regs(rdev); 239 /* program mc */ 240 r300_mc_program(rdev); 241 /* Resume clock */ 242 r420_clock_resume(rdev); 243 /* Initialize GART (initialize after TTM so we can allocate 244 * memory through TTM but finalize after TTM) */ 245 if (rdev->flags & RADEON_IS_PCIE) { 246 r = rv370_pcie_gart_enable(rdev); 247 if (r) 248 return r; 249 } 250 if (rdev->flags & RADEON_IS_PCI) { 251 r = r100_pci_gart_enable(rdev); 252 if (r) 253 return r; 254 } 255 r420_pipes_init(rdev); 256 257 /* allocate wb buffer */ 258 r = radeon_wb_init(rdev); 259 if (r) 260 return r; 261 262 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 263 if (r) { 264 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 265 return r; 266 } 267 268 /* Enable IRQ */ 269 r100_irq_set(rdev); 270 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 271 /* 1M ring buffer */ 272 r = r100_cp_init(rdev, 1024 * 1024); 273 if (r) { 274 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 275 return r; 276 } 277 r420_cp_errata_init(rdev); 278 279 r = radeon_ib_pool_init(rdev); 280 if (r) { 281 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 282 return r; 283 } 284 285 return 0; 286 } 287 288 int r420_resume(struct radeon_device *rdev) 289 { 290 int r; 291 292 /* Make sur GART are not working */ 293 if (rdev->flags & RADEON_IS_PCIE) 294 rv370_pcie_gart_disable(rdev); 295 if (rdev->flags & RADEON_IS_PCI) 296 r100_pci_gart_disable(rdev); 297 /* Resume clock before doing reset */ 298 r420_clock_resume(rdev); 299 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 300 if (radeon_asic_reset(rdev)) { 301 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 302 RREG32(R_000E40_RBBM_STATUS), 303 RREG32(R_0007C0_CP_STAT)); 304 } 305 /* check if cards are posted or not */ 306 if (rdev->is_atom_bios) { 307 atom_asic_init(rdev->mode_info.atom_context); 308 } else { 309 radeon_combios_asic_init(rdev->ddev); 310 } 311 /* Resume clock after posting */ 312 r420_clock_resume(rdev); 313 /* Initialize surface registers */ 314 radeon_surface_init(rdev); 315 316 rdev->accel_working = true; 317 r = r420_startup(rdev); 318 if (r) { 319 rdev->accel_working = false; 320 } 321 return r; 322 } 323 324 int r420_suspend(struct radeon_device *rdev) 325 { 326 r420_cp_errata_fini(rdev); 327 r100_cp_disable(rdev); 328 radeon_wb_disable(rdev); 329 r100_irq_disable(rdev); 330 if (rdev->flags & RADEON_IS_PCIE) 331 rv370_pcie_gart_disable(rdev); 332 if (rdev->flags & RADEON_IS_PCI) 333 r100_pci_gart_disable(rdev); 334 return 0; 335 } 336 337 void r420_fini(struct radeon_device *rdev) 338 { 339 r100_cp_fini(rdev); 340 radeon_wb_fini(rdev); 341 radeon_ib_pool_fini(rdev); 342 radeon_gem_fini(rdev); 343 if (rdev->flags & RADEON_IS_PCIE) 344 rv370_pcie_gart_fini(rdev); 345 if (rdev->flags & RADEON_IS_PCI) 346 r100_pci_gart_fini(rdev); 347 radeon_agp_fini(rdev); 348 radeon_irq_kms_fini(rdev); 349 radeon_fence_driver_fini(rdev); 350 radeon_bo_fini(rdev); 351 if (rdev->is_atom_bios) { 352 radeon_atombios_fini(rdev); 353 } else { 354 radeon_combios_fini(rdev); 355 } 356 drm_free(rdev->bios, M_DRM); 357 rdev->bios = NULL; 358 } 359 360 int r420_init(struct radeon_device *rdev) 361 { 362 int r; 363 364 /* Initialize scratch registers */ 365 radeon_scratch_init(rdev); 366 /* Initialize surface registers */ 367 radeon_surface_init(rdev); 368 /* TODO: disable VGA need to use VGA request */ 369 /* restore some register to sane defaults */ 370 r100_restore_sanity(rdev); 371 /* BIOS*/ 372 if (!radeon_get_bios(rdev)) { 373 if (ASIC_IS_AVIVO(rdev)) 374 return -EINVAL; 375 } 376 if (rdev->is_atom_bios) { 377 r = radeon_atombios_init(rdev); 378 if (r) { 379 return r; 380 } 381 } else { 382 r = radeon_combios_init(rdev); 383 if (r) { 384 return r; 385 } 386 } 387 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 388 if (radeon_asic_reset(rdev)) { 389 dev_warn(rdev->dev, 390 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 391 RREG32(R_000E40_RBBM_STATUS), 392 RREG32(R_0007C0_CP_STAT)); 393 } 394 /* check if cards are posted or not */ 395 if (radeon_boot_test_post_card(rdev) == false) 396 return -EINVAL; 397 398 /* Initialize clocks */ 399 radeon_get_clock_info(rdev->ddev); 400 /* initialize AGP */ 401 if (rdev->flags & RADEON_IS_AGP) { 402 r = radeon_agp_init(rdev); 403 if (r) { 404 radeon_agp_disable(rdev); 405 } 406 } 407 /* initialize memory controller */ 408 r300_mc_init(rdev); 409 r420_debugfs(rdev); 410 /* Fence driver */ 411 r = radeon_fence_driver_init(rdev); 412 if (r) { 413 return r; 414 } 415 r = radeon_irq_kms_init(rdev); 416 if (r) { 417 return r; 418 } 419 /* Memory manager */ 420 r = radeon_bo_init(rdev); 421 if (r) { 422 return r; 423 } 424 if (rdev->family == CHIP_R420) 425 r100_enable_bm(rdev); 426 427 if (rdev->flags & RADEON_IS_PCIE) { 428 r = rv370_pcie_gart_init(rdev); 429 if (r) 430 return r; 431 } 432 if (rdev->flags & RADEON_IS_PCI) { 433 r = r100_pci_gart_init(rdev); 434 if (r) 435 return r; 436 } 437 r420_set_reg_safe(rdev); 438 439 rdev->accel_working = true; 440 r = r420_startup(rdev); 441 if (r) { 442 /* Somethings want wront with the accel init stop accel */ 443 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 444 r100_cp_fini(rdev); 445 radeon_wb_fini(rdev); 446 radeon_ib_pool_fini(rdev); 447 radeon_irq_kms_fini(rdev); 448 if (rdev->flags & RADEON_IS_PCIE) 449 rv370_pcie_gart_fini(rdev); 450 if (rdev->flags & RADEON_IS_PCI) 451 r100_pci_gart_fini(rdev); 452 radeon_agp_fini(rdev); 453 rdev->accel_working = false; 454 } 455 return 0; 456 } 457 458 /* 459 * Debugfs info 460 */ 461 #if defined(CONFIG_DEBUG_FS) 462 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 463 { 464 struct drm_info_node *node = (struct drm_info_node *) m->private; 465 struct drm_device *dev = node->minor->dev; 466 struct radeon_device *rdev = dev->dev_private; 467 uint32_t tmp; 468 469 tmp = RREG32(R400_GB_PIPE_SELECT); 470 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 471 tmp = RREG32(R300_GB_TILE_CONFIG); 472 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 473 tmp = RREG32(R300_DST_PIPE_CONFIG); 474 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 475 return 0; 476 } 477 478 static struct drm_info_list r420_pipes_info_list[] = { 479 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 480 }; 481 #endif 482 483 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 484 { 485 #if defined(CONFIG_DEBUG_FS) 486 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 487 #else 488 return 0; 489 #endif 490 } 491