1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include "r100d.h" 34 #include "r420d.h" 35 #include "r420_reg_safe.h" 36 37 void r420_pm_init_profile(struct radeon_device *rdev) 38 { 39 /* default */ 40 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 41 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 44 /* low sh */ 45 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 46 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 49 /* mid sh */ 50 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 51 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 54 /* high sh */ 55 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 56 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 59 /* low mh */ 60 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 61 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 64 /* mid mh */ 65 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 66 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 69 /* high mh */ 70 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 71 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 74 } 75 76 static void r420_set_reg_safe(struct radeon_device *rdev) 77 { 78 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 79 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 80 } 81 82 void r420_pipes_init(struct radeon_device *rdev) 83 { 84 unsigned tmp; 85 unsigned gb_pipe_select; 86 unsigned num_pipes; 87 88 /* GA_ENHANCE workaround TCL deadlock issue */ 89 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 90 (1 << 2) | (1 << 3)); 91 /* add idle wait as per freedesktop.org bug 24041 */ 92 if (r100_gui_wait_for_idle(rdev)) { 93 printk(KERN_WARNING "Failed to wait GUI idle while " 94 "programming pipes. Bad things might happen.\n"); 95 } 96 /* get max number of pipes */ 97 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 98 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 99 100 /* SE chips have 1 pipe */ 101 if ((rdev->pdev->device == 0x5e4c) || 102 (rdev->pdev->device == 0x5e4f)) 103 num_pipes = 1; 104 105 rdev->num_gb_pipes = num_pipes; 106 tmp = 0; 107 switch (num_pipes) { 108 default: 109 /* force to 1 pipe */ 110 num_pipes = 1; 111 case 1: 112 tmp = (0 << 1); 113 break; 114 case 2: 115 tmp = (3 << 1); 116 break; 117 case 3: 118 tmp = (6 << 1); 119 break; 120 case 4: 121 tmp = (7 << 1); 122 break; 123 } 124 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 125 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 126 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 127 WREG32(R300_GB_TILE_CONFIG, tmp); 128 if (r100_gui_wait_for_idle(rdev)) { 129 printk(KERN_WARNING "Failed to wait GUI idle while " 130 "programming pipes. Bad things might happen.\n"); 131 } 132 133 tmp = RREG32(R300_DST_PIPE_CONFIG); 134 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 135 136 WREG32(R300_RB2D_DSTCACHE_MODE, 137 RREG32(R300_RB2D_DSTCACHE_MODE) | 138 R300_DC_AUTOFLUSH_ENABLE | 139 R300_DC_DC_DISABLE_IGNORE_PE); 140 141 if (r100_gui_wait_for_idle(rdev)) { 142 printk(KERN_WARNING "Failed to wait GUI idle while " 143 "programming pipes. Bad things might happen.\n"); 144 } 145 146 if (rdev->family == CHIP_RV530) { 147 tmp = RREG32(RV530_GB_PIPE_SELECT2); 148 if ((tmp & 3) == 3) 149 rdev->num_z_pipes = 2; 150 else 151 rdev->num_z_pipes = 1; 152 } else 153 rdev->num_z_pipes = 1; 154 155 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 156 rdev->num_gb_pipes, rdev->num_z_pipes); 157 } 158 159 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 160 { 161 u32 r; 162 163 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 164 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 165 r = RREG32(R_0001FC_MC_IND_DATA); 166 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 167 return r; 168 } 169 170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 171 { 172 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 173 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 174 S_0001F8_MC_IND_WR_EN(1)); 175 WREG32(R_0001FC_MC_IND_DATA, v); 176 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 177 } 178 179 static void r420_debugfs(struct radeon_device *rdev) 180 { 181 if (r100_debugfs_rbbm_init(rdev)) { 182 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 183 } 184 if (r420_debugfs_pipes_info_init(rdev)) { 185 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 186 } 187 } 188 189 static void r420_clock_resume(struct radeon_device *rdev) 190 { 191 u32 sclk_cntl; 192 193 if (radeon_dynclks != -1 && radeon_dynclks) 194 radeon_atom_set_clock_gating(rdev, 1); 195 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 196 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 197 if (rdev->family == CHIP_R420) 198 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 199 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 200 } 201 202 static void r420_cp_errata_init(struct radeon_device *rdev) 203 { 204 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 205 206 /* RV410 and R420 can lock up if CP DMA to host memory happens 207 * while the 2D engine is busy. 208 * 209 * The proper workaround is to queue a RESYNC at the beginning 210 * of the CP init, apparently. 211 */ 212 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 213 radeon_ring_lock(rdev, ring, 8); 214 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 215 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 216 radeon_ring_write(ring, 0xDEADBEEF); 217 radeon_ring_unlock_commit(rdev, ring, false); 218 } 219 220 static void r420_cp_errata_fini(struct radeon_device *rdev) 221 { 222 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 223 224 /* Catch the RESYNC we dispatched all the way back, 225 * at the very beginning of the CP init. 226 */ 227 radeon_ring_lock(rdev, ring, 8); 228 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 229 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 230 radeon_ring_unlock_commit(rdev, ring, false); 231 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 232 } 233 234 static int r420_startup(struct radeon_device *rdev) 235 { 236 int r; 237 238 /* set common regs */ 239 r100_set_common_regs(rdev); 240 /* program mc */ 241 r300_mc_program(rdev); 242 /* Resume clock */ 243 r420_clock_resume(rdev); 244 /* Initialize GART (initialize after TTM so we can allocate 245 * memory through TTM but finalize after TTM) */ 246 if (rdev->flags & RADEON_IS_PCIE) { 247 r = rv370_pcie_gart_enable(rdev); 248 if (r) 249 return r; 250 } 251 if (rdev->flags & RADEON_IS_PCI) { 252 r = r100_pci_gart_enable(rdev); 253 if (r) 254 return r; 255 } 256 r420_pipes_init(rdev); 257 258 /* allocate wb buffer */ 259 r = radeon_wb_init(rdev); 260 if (r) 261 return r; 262 263 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 264 if (r) { 265 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 266 return r; 267 } 268 269 /* Enable IRQ */ 270 if (!rdev->irq.installed) { 271 r = radeon_irq_kms_init(rdev); 272 if (r) 273 return r; 274 } 275 276 r100_irq_set(rdev); 277 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 278 /* 1M ring buffer */ 279 r = r100_cp_init(rdev, 1024 * 1024); 280 if (r) { 281 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 282 return r; 283 } 284 r420_cp_errata_init(rdev); 285 286 r = radeon_ib_pool_init(rdev); 287 if (r) { 288 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 289 return r; 290 } 291 292 return 0; 293 } 294 295 int r420_resume(struct radeon_device *rdev) 296 { 297 int r; 298 299 /* Make sur GART are not working */ 300 if (rdev->flags & RADEON_IS_PCIE) 301 rv370_pcie_gart_disable(rdev); 302 if (rdev->flags & RADEON_IS_PCI) 303 r100_pci_gart_disable(rdev); 304 /* Resume clock before doing reset */ 305 r420_clock_resume(rdev); 306 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 307 if (radeon_asic_reset(rdev)) { 308 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 309 RREG32(R_000E40_RBBM_STATUS), 310 RREG32(R_0007C0_CP_STAT)); 311 } 312 /* check if cards are posted or not */ 313 if (rdev->is_atom_bios) { 314 atom_asic_init(rdev->mode_info.atom_context); 315 } else { 316 radeon_combios_asic_init(rdev->ddev); 317 } 318 /* Resume clock after posting */ 319 r420_clock_resume(rdev); 320 /* Initialize surface registers */ 321 radeon_surface_init(rdev); 322 323 rdev->accel_working = true; 324 r = r420_startup(rdev); 325 if (r) { 326 rdev->accel_working = false; 327 } 328 return r; 329 } 330 331 int r420_suspend(struct radeon_device *rdev) 332 { 333 radeon_pm_suspend(rdev); 334 r420_cp_errata_fini(rdev); 335 r100_cp_disable(rdev); 336 radeon_wb_disable(rdev); 337 r100_irq_disable(rdev); 338 if (rdev->flags & RADEON_IS_PCIE) 339 rv370_pcie_gart_disable(rdev); 340 if (rdev->flags & RADEON_IS_PCI) 341 r100_pci_gart_disable(rdev); 342 return 0; 343 } 344 345 void r420_fini(struct radeon_device *rdev) 346 { 347 radeon_pm_fini(rdev); 348 r100_cp_fini(rdev); 349 radeon_wb_fini(rdev); 350 radeon_ib_pool_fini(rdev); 351 radeon_gem_fini(rdev); 352 if (rdev->flags & RADEON_IS_PCIE) 353 rv370_pcie_gart_fini(rdev); 354 if (rdev->flags & RADEON_IS_PCI) 355 r100_pci_gart_fini(rdev); 356 radeon_agp_fini(rdev); 357 radeon_irq_kms_fini(rdev); 358 radeon_fence_driver_fini(rdev); 359 radeon_bo_fini(rdev); 360 if (rdev->is_atom_bios) { 361 radeon_atombios_fini(rdev); 362 } else { 363 radeon_combios_fini(rdev); 364 } 365 kfree(rdev->bios); 366 rdev->bios = NULL; 367 } 368 369 int r420_init(struct radeon_device *rdev) 370 { 371 int r; 372 373 /* Initialize scratch registers */ 374 radeon_scratch_init(rdev); 375 /* Initialize surface registers */ 376 radeon_surface_init(rdev); 377 /* TODO: disable VGA need to use VGA request */ 378 /* restore some register to sane defaults */ 379 r100_restore_sanity(rdev); 380 /* BIOS*/ 381 if (!radeon_get_bios(rdev)) { 382 if (ASIC_IS_AVIVO(rdev)) 383 return -EINVAL; 384 } 385 if (rdev->is_atom_bios) { 386 r = radeon_atombios_init(rdev); 387 if (r) { 388 return r; 389 } 390 } else { 391 r = radeon_combios_init(rdev); 392 if (r) { 393 return r; 394 } 395 } 396 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 397 if (radeon_asic_reset(rdev)) { 398 dev_warn(rdev->dev, 399 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 400 RREG32(R_000E40_RBBM_STATUS), 401 RREG32(R_0007C0_CP_STAT)); 402 } 403 /* check if cards are posted or not */ 404 if (radeon_boot_test_post_card(rdev) == false) 405 return -EINVAL; 406 407 /* Initialize clocks */ 408 radeon_get_clock_info(rdev->ddev); 409 /* initialize AGP */ 410 if (rdev->flags & RADEON_IS_AGP) { 411 r = radeon_agp_init(rdev); 412 if (r) { 413 radeon_agp_disable(rdev); 414 } 415 } 416 /* initialize memory controller */ 417 r300_mc_init(rdev); 418 r420_debugfs(rdev); 419 /* Fence driver */ 420 r = radeon_fence_driver_init(rdev); 421 if (r) { 422 return r; 423 } 424 /* Memory manager */ 425 r = radeon_bo_init(rdev); 426 if (r) { 427 return r; 428 } 429 if (rdev->family == CHIP_R420) 430 r100_enable_bm(rdev); 431 432 if (rdev->flags & RADEON_IS_PCIE) { 433 r = rv370_pcie_gart_init(rdev); 434 if (r) 435 return r; 436 } 437 if (rdev->flags & RADEON_IS_PCI) { 438 r = r100_pci_gart_init(rdev); 439 if (r) 440 return r; 441 } 442 r420_set_reg_safe(rdev); 443 444 /* Initialize power management */ 445 radeon_pm_init(rdev); 446 447 rdev->accel_working = true; 448 r = r420_startup(rdev); 449 if (r) { 450 /* Somethings want wront with the accel init stop accel */ 451 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 452 r100_cp_fini(rdev); 453 radeon_wb_fini(rdev); 454 radeon_ib_pool_fini(rdev); 455 radeon_irq_kms_fini(rdev); 456 if (rdev->flags & RADEON_IS_PCIE) 457 rv370_pcie_gart_fini(rdev); 458 if (rdev->flags & RADEON_IS_PCI) 459 r100_pci_gart_fini(rdev); 460 radeon_agp_fini(rdev); 461 rdev->accel_working = false; 462 } 463 return 0; 464 } 465 466 /* 467 * Debugfs info 468 */ 469 #if defined(CONFIG_DEBUG_FS) 470 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 471 { 472 struct drm_info_node *node = (struct drm_info_node *) m->private; 473 struct drm_device *dev = node->minor->dev; 474 struct radeon_device *rdev = dev->dev_private; 475 uint32_t tmp; 476 477 tmp = RREG32(R400_GB_PIPE_SELECT); 478 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 479 tmp = RREG32(R300_GB_TILE_CONFIG); 480 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 481 tmp = RREG32(R300_DST_PIPE_CONFIG); 482 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 483 return 0; 484 } 485 486 static struct drm_info_list r420_pipes_info_list[] = { 487 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 488 }; 489 #endif 490 491 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 492 { 493 #if defined(CONFIG_DEBUG_FS) 494 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 495 #else 496 return 0; 497 #endif 498 } 499