1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include "r100d.h" 34 #include "r420d.h" 35 #include "r420_reg_safe.h" 36 37 void r420_pm_init_profile(struct radeon_device *rdev) 38 { 39 /* default */ 40 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 41 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 44 /* low sh */ 45 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 46 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 49 /* mid sh */ 50 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 51 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 54 /* high sh */ 55 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 56 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 59 /* low mh */ 60 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 61 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 64 /* mid mh */ 65 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 66 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 69 /* high mh */ 70 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 71 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 74 } 75 76 static void r420_set_reg_safe(struct radeon_device *rdev) 77 { 78 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 79 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 80 } 81 82 void r420_pipes_init(struct radeon_device *rdev) 83 { 84 unsigned tmp; 85 unsigned gb_pipe_select; 86 unsigned num_pipes; 87 88 /* GA_ENHANCE workaround TCL deadlock issue */ 89 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 90 (1 << 2) | (1 << 3)); 91 /* add idle wait as per freedesktop.org bug 24041 */ 92 if (r100_gui_wait_for_idle(rdev)) { 93 printk(KERN_WARNING "Failed to wait GUI idle while " 94 "programming pipes. Bad things might happen.\n"); 95 } 96 /* get max number of pipes */ 97 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 98 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 99 100 /* SE chips have 1 pipe */ 101 if ((rdev->pdev->device == 0x5e4c) || 102 (rdev->pdev->device == 0x5e4f)) 103 num_pipes = 1; 104 105 rdev->num_gb_pipes = num_pipes; 106 tmp = 0; 107 switch (num_pipes) { 108 default: 109 /* force to 1 pipe */ 110 num_pipes = 1; 111 case 1: 112 tmp = (0 << 1); 113 break; 114 case 2: 115 tmp = (3 << 1); 116 break; 117 case 3: 118 tmp = (6 << 1); 119 break; 120 case 4: 121 tmp = (7 << 1); 122 break; 123 } 124 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 125 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 126 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 127 WREG32(R300_GB_TILE_CONFIG, tmp); 128 if (r100_gui_wait_for_idle(rdev)) { 129 printk(KERN_WARNING "Failed to wait GUI idle while " 130 "programming pipes. Bad things might happen.\n"); 131 } 132 133 tmp = RREG32(R300_DST_PIPE_CONFIG); 134 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 135 136 WREG32(R300_RB2D_DSTCACHE_MODE, 137 RREG32(R300_RB2D_DSTCACHE_MODE) | 138 R300_DC_AUTOFLUSH_ENABLE | 139 R300_DC_DC_DISABLE_IGNORE_PE); 140 141 if (r100_gui_wait_for_idle(rdev)) { 142 printk(KERN_WARNING "Failed to wait GUI idle while " 143 "programming pipes. Bad things might happen.\n"); 144 } 145 146 if (rdev->family == CHIP_RV530) { 147 tmp = RREG32(RV530_GB_PIPE_SELECT2); 148 if ((tmp & 3) == 3) 149 rdev->num_z_pipes = 2; 150 else 151 rdev->num_z_pipes = 1; 152 } else 153 rdev->num_z_pipes = 1; 154 155 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 156 rdev->num_gb_pipes, rdev->num_z_pipes); 157 } 158 159 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 160 { 161 unsigned long flags; 162 u32 r; 163 164 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 165 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 166 r = RREG32(R_0001FC_MC_IND_DATA); 167 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 168 return r; 169 } 170 171 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 172 { 173 unsigned long flags; 174 175 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 176 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 177 S_0001F8_MC_IND_WR_EN(1)); 178 WREG32(R_0001FC_MC_IND_DATA, v); 179 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 180 } 181 182 static void r420_debugfs(struct radeon_device *rdev) 183 { 184 if (r100_debugfs_rbbm_init(rdev)) { 185 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 186 } 187 if (r420_debugfs_pipes_info_init(rdev)) { 188 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 189 } 190 } 191 192 static void r420_clock_resume(struct radeon_device *rdev) 193 { 194 u32 sclk_cntl; 195 196 if (radeon_dynclks != -1 && radeon_dynclks) 197 radeon_atom_set_clock_gating(rdev, 1); 198 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 199 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 200 if (rdev->family == CHIP_R420) 201 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 202 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 203 } 204 205 static void r420_cp_errata_init(struct radeon_device *rdev) 206 { 207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 208 209 /* RV410 and R420 can lock up if CP DMA to host memory happens 210 * while the 2D engine is busy. 211 * 212 * The proper workaround is to queue a RESYNC at the beginning 213 * of the CP init, apparently. 214 */ 215 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 216 radeon_ring_lock(rdev, ring, 8); 217 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 218 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 219 radeon_ring_write(ring, 0xDEADBEEF); 220 radeon_ring_unlock_commit(rdev, ring, false); 221 } 222 223 static void r420_cp_errata_fini(struct radeon_device *rdev) 224 { 225 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 226 227 /* Catch the RESYNC we dispatched all the way back, 228 * at the very beginning of the CP init. 229 */ 230 radeon_ring_lock(rdev, ring, 8); 231 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 232 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 233 radeon_ring_unlock_commit(rdev, ring, false); 234 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 235 } 236 237 static int r420_startup(struct radeon_device *rdev) 238 { 239 int r; 240 241 /* set common regs */ 242 r100_set_common_regs(rdev); 243 /* program mc */ 244 r300_mc_program(rdev); 245 /* Resume clock */ 246 r420_clock_resume(rdev); 247 /* Initialize GART (initialize after TTM so we can allocate 248 * memory through TTM but finalize after TTM) */ 249 if (rdev->flags & RADEON_IS_PCIE) { 250 r = rv370_pcie_gart_enable(rdev); 251 if (r) 252 return r; 253 } 254 if (rdev->flags & RADEON_IS_PCI) { 255 r = r100_pci_gart_enable(rdev); 256 if (r) 257 return r; 258 } 259 r420_pipes_init(rdev); 260 261 /* allocate wb buffer */ 262 r = radeon_wb_init(rdev); 263 if (r) 264 return r; 265 266 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 267 if (r) { 268 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 269 return r; 270 } 271 272 /* Enable IRQ */ 273 if (!rdev->irq.installed) { 274 r = radeon_irq_kms_init(rdev); 275 if (r) 276 return r; 277 } 278 279 r100_irq_set(rdev); 280 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 281 /* 1M ring buffer */ 282 r = r100_cp_init(rdev, 1024 * 1024); 283 if (r) { 284 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 285 return r; 286 } 287 r420_cp_errata_init(rdev); 288 289 r = radeon_ib_pool_init(rdev); 290 if (r) { 291 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 292 return r; 293 } 294 295 return 0; 296 } 297 298 int r420_resume(struct radeon_device *rdev) 299 { 300 int r; 301 302 /* Make sur GART are not working */ 303 if (rdev->flags & RADEON_IS_PCIE) 304 rv370_pcie_gart_disable(rdev); 305 if (rdev->flags & RADEON_IS_PCI) 306 r100_pci_gart_disable(rdev); 307 /* Resume clock before doing reset */ 308 r420_clock_resume(rdev); 309 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 310 if (radeon_asic_reset(rdev)) { 311 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 312 RREG32(R_000E40_RBBM_STATUS), 313 RREG32(R_0007C0_CP_STAT)); 314 } 315 /* check if cards are posted or not */ 316 if (rdev->is_atom_bios) { 317 atom_asic_init(rdev->mode_info.atom_context); 318 } else { 319 radeon_combios_asic_init(rdev->ddev); 320 } 321 /* Resume clock after posting */ 322 r420_clock_resume(rdev); 323 /* Initialize surface registers */ 324 radeon_surface_init(rdev); 325 326 rdev->accel_working = true; 327 r = r420_startup(rdev); 328 if (r) { 329 rdev->accel_working = false; 330 } 331 return r; 332 } 333 334 int r420_suspend(struct radeon_device *rdev) 335 { 336 radeon_pm_suspend(rdev); 337 r420_cp_errata_fini(rdev); 338 r100_cp_disable(rdev); 339 radeon_wb_disable(rdev); 340 r100_irq_disable(rdev); 341 if (rdev->flags & RADEON_IS_PCIE) 342 rv370_pcie_gart_disable(rdev); 343 if (rdev->flags & RADEON_IS_PCI) 344 r100_pci_gart_disable(rdev); 345 return 0; 346 } 347 348 void r420_fini(struct radeon_device *rdev) 349 { 350 radeon_pm_fini(rdev); 351 r100_cp_fini(rdev); 352 radeon_wb_fini(rdev); 353 radeon_ib_pool_fini(rdev); 354 radeon_gem_fini(rdev); 355 if (rdev->flags & RADEON_IS_PCIE) 356 rv370_pcie_gart_fini(rdev); 357 if (rdev->flags & RADEON_IS_PCI) 358 r100_pci_gart_fini(rdev); 359 radeon_agp_fini(rdev); 360 radeon_irq_kms_fini(rdev); 361 radeon_fence_driver_fini(rdev); 362 radeon_bo_fini(rdev); 363 if (rdev->is_atom_bios) { 364 radeon_atombios_fini(rdev); 365 } else { 366 radeon_combios_fini(rdev); 367 } 368 kfree(rdev->bios); 369 rdev->bios = NULL; 370 } 371 372 int r420_init(struct radeon_device *rdev) 373 { 374 int r; 375 376 /* Initialize scratch registers */ 377 radeon_scratch_init(rdev); 378 /* Initialize surface registers */ 379 radeon_surface_init(rdev); 380 /* TODO: disable VGA need to use VGA request */ 381 /* restore some register to sane defaults */ 382 r100_restore_sanity(rdev); 383 /* BIOS*/ 384 if (!radeon_get_bios(rdev)) { 385 if (ASIC_IS_AVIVO(rdev)) 386 return -EINVAL; 387 } 388 if (rdev->is_atom_bios) { 389 r = radeon_atombios_init(rdev); 390 if (r) { 391 return r; 392 } 393 } else { 394 r = radeon_combios_init(rdev); 395 if (r) { 396 return r; 397 } 398 } 399 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 400 if (radeon_asic_reset(rdev)) { 401 dev_warn(rdev->dev, 402 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 403 RREG32(R_000E40_RBBM_STATUS), 404 RREG32(R_0007C0_CP_STAT)); 405 } 406 /* check if cards are posted or not */ 407 if (radeon_boot_test_post_card(rdev) == false) 408 return -EINVAL; 409 410 /* Initialize clocks */ 411 radeon_get_clock_info(rdev->ddev); 412 /* initialize AGP */ 413 if (rdev->flags & RADEON_IS_AGP) { 414 r = radeon_agp_init(rdev); 415 if (r) { 416 radeon_agp_disable(rdev); 417 } 418 } 419 /* initialize memory controller */ 420 r300_mc_init(rdev); 421 r420_debugfs(rdev); 422 /* Fence driver */ 423 r = radeon_fence_driver_init(rdev); 424 if (r) { 425 return r; 426 } 427 /* Memory manager */ 428 r = radeon_bo_init(rdev); 429 if (r) { 430 return r; 431 } 432 if (rdev->family == CHIP_R420) 433 r100_enable_bm(rdev); 434 435 if (rdev->flags & RADEON_IS_PCIE) { 436 r = rv370_pcie_gart_init(rdev); 437 if (r) 438 return r; 439 } 440 if (rdev->flags & RADEON_IS_PCI) { 441 r = r100_pci_gart_init(rdev); 442 if (r) 443 return r; 444 } 445 r420_set_reg_safe(rdev); 446 447 /* Initialize power management */ 448 radeon_pm_init(rdev); 449 450 rdev->accel_working = true; 451 r = r420_startup(rdev); 452 if (r) { 453 /* Somethings want wront with the accel init stop accel */ 454 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 455 r100_cp_fini(rdev); 456 radeon_wb_fini(rdev); 457 radeon_ib_pool_fini(rdev); 458 radeon_irq_kms_fini(rdev); 459 if (rdev->flags & RADEON_IS_PCIE) 460 rv370_pcie_gart_fini(rdev); 461 if (rdev->flags & RADEON_IS_PCI) 462 r100_pci_gart_fini(rdev); 463 radeon_agp_fini(rdev); 464 rdev->accel_working = false; 465 } 466 return 0; 467 } 468 469 /* 470 * Debugfs info 471 */ 472 #if defined(CONFIG_DEBUG_FS) 473 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 474 { 475 struct drm_info_node *node = (struct drm_info_node *) m->private; 476 struct drm_device *dev = node->minor->dev; 477 struct radeon_device *rdev = dev->dev_private; 478 uint32_t tmp; 479 480 tmp = RREG32(R400_GB_PIPE_SELECT); 481 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 482 tmp = RREG32(R300_GB_TILE_CONFIG); 483 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 484 tmp = RREG32(R300_DST_PIPE_CONFIG); 485 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 486 return 0; 487 } 488 489 static struct drm_info_list r420_pipes_info_list[] = { 490 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 491 }; 492 #endif 493 494 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 495 { 496 #if defined(CONFIG_DEBUG_FS) 497 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 498 #else 499 return 0; 500 #endif 501 } 502