1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r520.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "r520d.h" 36 37 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ 38 39 int r520_mc_wait_for_idle(struct radeon_device *rdev) 40 { 41 unsigned i; 42 uint32_t tmp; 43 44 for (i = 0; i < rdev->usec_timeout; i++) { 45 /* read MC_STATUS */ 46 tmp = RREG32_MC(R520_MC_STATUS); 47 if (tmp & R520_MC_STATUS_IDLE) { 48 return 0; 49 } 50 DRM_UDELAY(1); 51 } 52 return -1; 53 } 54 55 static void r520_gpu_init(struct radeon_device *rdev) 56 { 57 unsigned pipe_select_current, gb_pipe_select, tmp; 58 59 rv515_vga_render_disable(rdev); 60 /* 61 * DST_PIPE_CONFIG 0x170C 62 * GB_TILE_CONFIG 0x4018 63 * GB_FIFO_SIZE 0x4024 64 * GB_PIPE_SELECT 0x402C 65 * GB_PIPE_SELECT2 0x4124 66 * Z_PIPE_SHIFT 0 67 * Z_PIPE_MASK 0x000000003 68 * GB_FIFO_SIZE2 0x4128 69 * SC_SFIFO_SIZE_SHIFT 0 70 * SC_SFIFO_SIZE_MASK 0x000000003 71 * SC_MFIFO_SIZE_SHIFT 2 72 * SC_MFIFO_SIZE_MASK 0x00000000C 73 * FG_SFIFO_SIZE_SHIFT 4 74 * FG_SFIFO_SIZE_MASK 0x000000030 75 * ZB_MFIFO_SIZE_SHIFT 6 76 * ZB_MFIFO_SIZE_MASK 0x0000000C0 77 * GA_ENHANCE 0x4274 78 * SU_REG_DEST 0x42C8 79 */ 80 /* workaround for RV530 */ 81 if (rdev->family == CHIP_RV530) { 82 WREG32(0x4128, 0xFF); 83 } 84 r420_pipes_init(rdev); 85 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 86 tmp = RREG32(R300_DST_PIPE_CONFIG); 87 pipe_select_current = (tmp >> 2) & 3; 88 tmp = (1 << pipe_select_current) | 89 (((gb_pipe_select >> 8) & 0xF) << 4); 90 WREG32_PLL(0x000D, tmp); 91 if (r520_mc_wait_for_idle(rdev)) { 92 DRM_ERROR("Failed to wait MC idle while " 93 "programming pipes. Bad things might happen.\n"); 94 } 95 } 96 97 static void r520_vram_get_type(struct radeon_device *rdev) 98 { 99 uint32_t tmp; 100 101 rdev->mc.vram_width = 128; 102 rdev->mc.vram_is_ddr = true; 103 tmp = RREG32_MC(R520_MC_CNTL0); 104 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 105 case 0: 106 rdev->mc.vram_width = 32; 107 break; 108 case 1: 109 rdev->mc.vram_width = 64; 110 break; 111 case 2: 112 rdev->mc.vram_width = 128; 113 break; 114 case 3: 115 rdev->mc.vram_width = 256; 116 break; 117 default: 118 rdev->mc.vram_width = 128; 119 break; 120 } 121 if (tmp & R520_MC_CHANNEL_SIZE) 122 rdev->mc.vram_width *= 2; 123 } 124 125 static void r520_mc_init(struct radeon_device *rdev) 126 { 127 128 r520_vram_get_type(rdev); 129 r100_vram_init_sizes(rdev); 130 radeon_vram_location(rdev, &rdev->mc, 0); 131 rdev->mc.gtt_base_align = 0; 132 if (!(rdev->flags & RADEON_IS_AGP)) 133 radeon_gtt_location(rdev, &rdev->mc); 134 radeon_update_bandwidth_info(rdev); 135 } 136 137 static void r520_mc_program(struct radeon_device *rdev) 138 { 139 struct rv515_mc_save save; 140 141 /* Stops all mc clients */ 142 rv515_mc_stop(rdev, &save); 143 144 /* Wait for mc idle */ 145 if (r520_mc_wait_for_idle(rdev)) 146 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 147 /* Write VRAM size in case we are limiting it */ 148 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 149 /* Program MC, should be a 32bits limited address space */ 150 WREG32_MC(R_000004_MC_FB_LOCATION, 151 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 152 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 153 WREG32(R_000134_HDP_FB_LOCATION, 154 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 155 if (rdev->flags & RADEON_IS_AGP) { 156 WREG32_MC(R_000005_MC_AGP_LOCATION, 157 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | 158 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 159 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 160 WREG32_MC(R_000007_AGP_BASE_2, 161 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 162 } else { 163 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 164 WREG32_MC(R_000006_AGP_BASE, 0); 165 WREG32_MC(R_000007_AGP_BASE_2, 0); 166 } 167 168 rv515_mc_resume(rdev, &save); 169 } 170 171 static int r520_startup(struct radeon_device *rdev) 172 { 173 int r; 174 175 r520_mc_program(rdev); 176 /* Resume clock */ 177 rv515_clock_startup(rdev); 178 /* Initialize GPU configuration (# pipes, ...) */ 179 r520_gpu_init(rdev); 180 /* Initialize GART (initialize after TTM so we can allocate 181 * memory through TTM but finalize after TTM) */ 182 if (rdev->flags & RADEON_IS_PCIE) { 183 r = rv370_pcie_gart_enable(rdev); 184 if (r) 185 return r; 186 } 187 188 /* allocate wb buffer */ 189 r = radeon_wb_init(rdev); 190 if (r) 191 return r; 192 193 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 194 if (r) { 195 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 196 return r; 197 } 198 199 /* Enable IRQ */ 200 if (!rdev->irq.installed) { 201 r = radeon_irq_kms_init(rdev); 202 if (r) 203 return r; 204 } 205 206 rs600_irq_set(rdev); 207 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 208 /* 1M ring buffer */ 209 r = r100_cp_init(rdev, 1024 * 1024); 210 if (r) { 211 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 212 return r; 213 } 214 215 r = radeon_ib_pool_init(rdev); 216 if (r) { 217 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 218 return r; 219 } 220 221 return 0; 222 } 223 224 int r520_resume(struct radeon_device *rdev) 225 { 226 int r; 227 228 /* Make sur GART are not working */ 229 if (rdev->flags & RADEON_IS_PCIE) 230 rv370_pcie_gart_disable(rdev); 231 /* Resume clock before doing reset */ 232 rv515_clock_startup(rdev); 233 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 234 if (radeon_asic_reset(rdev)) { 235 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 236 RREG32(R_000E40_RBBM_STATUS), 237 RREG32(R_0007C0_CP_STAT)); 238 } 239 /* post */ 240 atom_asic_init(rdev->mode_info.atom_context); 241 /* Resume clock after posting */ 242 rv515_clock_startup(rdev); 243 /* Initialize surface registers */ 244 radeon_surface_init(rdev); 245 246 rdev->accel_working = true; 247 r = r520_startup(rdev); 248 if (r) { 249 rdev->accel_working = false; 250 } 251 return r; 252 } 253 254 int r520_init(struct radeon_device *rdev) 255 { 256 int r; 257 258 /* Initialize scratch registers */ 259 radeon_scratch_init(rdev); 260 /* Initialize surface registers */ 261 radeon_surface_init(rdev); 262 /* restore some register to sane defaults */ 263 r100_restore_sanity(rdev); 264 /* TODO: disable VGA need to use VGA request */ 265 /* BIOS*/ 266 if (!radeon_get_bios(rdev)) { 267 if (ASIC_IS_AVIVO(rdev)) 268 return -EINVAL; 269 } 270 if (rdev->is_atom_bios) { 271 r = radeon_atombios_init(rdev); 272 if (r) 273 return r; 274 } else { 275 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 276 return -EINVAL; 277 } 278 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 279 if (radeon_asic_reset(rdev)) { 280 dev_warn(rdev->dev, 281 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 282 RREG32(R_000E40_RBBM_STATUS), 283 RREG32(R_0007C0_CP_STAT)); 284 } 285 /* check if cards are posted or not */ 286 if (radeon_boot_test_post_card(rdev) == false) 287 return -EINVAL; 288 289 if (!radeon_card_posted(rdev) && rdev->bios) { 290 DRM_INFO("GPU not posted. posting now...\n"); 291 atom_asic_init(rdev->mode_info.atom_context); 292 } 293 /* Initialize clocks */ 294 radeon_get_clock_info(rdev->ddev); 295 /* initialize AGP */ 296 if (rdev->flags & RADEON_IS_AGP) { 297 r = radeon_agp_init(rdev); 298 if (r) { 299 radeon_agp_disable(rdev); 300 } 301 } 302 /* initialize memory controller */ 303 r520_mc_init(rdev); 304 rv515_debugfs(rdev); 305 /* Fence driver */ 306 r = radeon_fence_driver_init(rdev); 307 if (r) 308 return r; 309 /* Memory manager */ 310 r = radeon_bo_init(rdev); 311 if (r) 312 return r; 313 r = rv370_pcie_gart_init(rdev); 314 if (r) 315 return r; 316 rv515_set_safe_registers(rdev); 317 318 rdev->accel_working = true; 319 r = r520_startup(rdev); 320 if (r) { 321 /* Somethings want wront with the accel init stop accel */ 322 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 323 r100_cp_fini(rdev); 324 radeon_wb_fini(rdev); 325 radeon_ib_pool_fini(rdev); 326 radeon_irq_kms_fini(rdev); 327 rv370_pcie_gart_fini(rdev); 328 radeon_agp_fini(rdev); 329 rdev->accel_working = false; 330 } 331 return 0; 332 } 333