1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r600.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 #include <linux/seq_file.h> 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <uapi_drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 #include "radeon_ucode.h" 42 43 /* Firmware Names */ 44 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 45 MODULE_FIRMWARE("radeon/R600_me.bin"); 46 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 47 MODULE_FIRMWARE("radeon/RV610_me.bin"); 48 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 49 MODULE_FIRMWARE("radeon/RV630_me.bin"); 50 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV620_me.bin"); 52 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV635_me.bin"); 54 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV670_me.bin"); 56 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RS780_me.bin"); 58 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV770_me.bin"); 60 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 61 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV730_me.bin"); 63 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 64 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 65 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV710_me.bin"); 67 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 68 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 69 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 72 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 73 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 77 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 81 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 85 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 86 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 87 MODULE_FIRMWARE("radeon/PALM_me.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 90 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 92 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 93 MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 94 MODULE_FIRMWARE("radeon/OLAND_me.bin"); 95 MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 96 MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 97 MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 98 99 static const u32 crtc_offsets[2] = 100 { 101 0, 102 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 103 }; 104 105 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 106 107 /* r600,rv610,rv630,rv620,rv635,rv670 */ 108 static void r600_gpu_init(struct radeon_device *rdev); 109 void r600_irq_disable(struct radeon_device *rdev); 110 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 111 112 /** 113 * r600_get_xclk - get the xclk 114 * 115 * @rdev: radeon_device pointer 116 * 117 * Returns the reference clock used by the gfx engine 118 * (r6xx, IGPs, APUs). 119 */ 120 u32 r600_get_xclk(struct radeon_device *rdev) 121 { 122 return rdev->clock.spll.reference_freq; 123 } 124 125 /* get temperature in millidegrees */ 126 int rv6xx_get_temp(struct radeon_device *rdev) 127 { 128 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 129 ASIC_T_SHIFT; 130 int actual_temp = temp & 0xff; 131 132 if (temp & 0x100) 133 actual_temp -= 256; 134 135 return actual_temp * 1000; 136 } 137 138 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 139 { 140 int i; 141 142 rdev->pm.dynpm_can_upclock = true; 143 rdev->pm.dynpm_can_downclock = true; 144 145 /* power state array is low to high, default is first */ 146 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 147 int min_power_state_index = 0; 148 149 if (rdev->pm.num_power_states > 2) 150 min_power_state_index = 1; 151 152 switch (rdev->pm.dynpm_planned_action) { 153 case DYNPM_ACTION_MINIMUM: 154 rdev->pm.requested_power_state_index = min_power_state_index; 155 rdev->pm.requested_clock_mode_index = 0; 156 rdev->pm.dynpm_can_downclock = false; 157 break; 158 case DYNPM_ACTION_DOWNCLOCK: 159 if (rdev->pm.current_power_state_index == min_power_state_index) { 160 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 161 rdev->pm.dynpm_can_downclock = false; 162 } else { 163 if (rdev->pm.active_crtc_count > 1) { 164 for (i = 0; i < rdev->pm.num_power_states; i++) { 165 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 166 continue; 167 else if (i >= rdev->pm.current_power_state_index) { 168 rdev->pm.requested_power_state_index = 169 rdev->pm.current_power_state_index; 170 break; 171 } else { 172 rdev->pm.requested_power_state_index = i; 173 break; 174 } 175 } 176 } else { 177 if (rdev->pm.current_power_state_index == 0) 178 rdev->pm.requested_power_state_index = 179 rdev->pm.num_power_states - 1; 180 else 181 rdev->pm.requested_power_state_index = 182 rdev->pm.current_power_state_index - 1; 183 } 184 } 185 rdev->pm.requested_clock_mode_index = 0; 186 /* don't use the power state if crtcs are active and no display flag is set */ 187 if ((rdev->pm.active_crtc_count > 0) && 188 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 189 clock_info[rdev->pm.requested_clock_mode_index].flags & 190 RADEON_PM_MODE_NO_DISPLAY)) { 191 rdev->pm.requested_power_state_index++; 192 } 193 break; 194 case DYNPM_ACTION_UPCLOCK: 195 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 196 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 197 rdev->pm.dynpm_can_upclock = false; 198 } else { 199 if (rdev->pm.active_crtc_count > 1) { 200 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 201 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 202 continue; 203 else if (i <= rdev->pm.current_power_state_index) { 204 rdev->pm.requested_power_state_index = 205 rdev->pm.current_power_state_index; 206 break; 207 } else { 208 rdev->pm.requested_power_state_index = i; 209 break; 210 } 211 } 212 } else 213 rdev->pm.requested_power_state_index = 214 rdev->pm.current_power_state_index + 1; 215 } 216 rdev->pm.requested_clock_mode_index = 0; 217 break; 218 case DYNPM_ACTION_DEFAULT: 219 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 220 rdev->pm.requested_clock_mode_index = 0; 221 rdev->pm.dynpm_can_upclock = false; 222 break; 223 case DYNPM_ACTION_NONE: 224 default: 225 DRM_ERROR("Requested mode for not defined action\n"); 226 return; 227 } 228 } else { 229 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 230 /* for now just select the first power state and switch between clock modes */ 231 /* power state array is low to high, default is first (0) */ 232 if (rdev->pm.active_crtc_count > 1) { 233 rdev->pm.requested_power_state_index = -1; 234 /* start at 1 as we don't want the default mode */ 235 for (i = 1; i < rdev->pm.num_power_states; i++) { 236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 237 continue; 238 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 239 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 240 rdev->pm.requested_power_state_index = i; 241 break; 242 } 243 } 244 /* if nothing selected, grab the default state. */ 245 if (rdev->pm.requested_power_state_index == -1) 246 rdev->pm.requested_power_state_index = 0; 247 } else 248 rdev->pm.requested_power_state_index = 1; 249 250 switch (rdev->pm.dynpm_planned_action) { 251 case DYNPM_ACTION_MINIMUM: 252 rdev->pm.requested_clock_mode_index = 0; 253 rdev->pm.dynpm_can_downclock = false; 254 break; 255 case DYNPM_ACTION_DOWNCLOCK: 256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 257 if (rdev->pm.current_clock_mode_index == 0) { 258 rdev->pm.requested_clock_mode_index = 0; 259 rdev->pm.dynpm_can_downclock = false; 260 } else 261 rdev->pm.requested_clock_mode_index = 262 rdev->pm.current_clock_mode_index - 1; 263 } else { 264 rdev->pm.requested_clock_mode_index = 0; 265 rdev->pm.dynpm_can_downclock = false; 266 } 267 /* don't use the power state if crtcs are active and no display flag is set */ 268 if ((rdev->pm.active_crtc_count > 0) && 269 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 270 clock_info[rdev->pm.requested_clock_mode_index].flags & 271 RADEON_PM_MODE_NO_DISPLAY)) { 272 rdev->pm.requested_clock_mode_index++; 273 } 274 break; 275 case DYNPM_ACTION_UPCLOCK: 276 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 277 if (rdev->pm.current_clock_mode_index == 278 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 279 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 280 rdev->pm.dynpm_can_upclock = false; 281 } else 282 rdev->pm.requested_clock_mode_index = 283 rdev->pm.current_clock_mode_index + 1; 284 } else { 285 rdev->pm.requested_clock_mode_index = 286 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 287 rdev->pm.dynpm_can_upclock = false; 288 } 289 break; 290 case DYNPM_ACTION_DEFAULT: 291 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 292 rdev->pm.requested_clock_mode_index = 0; 293 rdev->pm.dynpm_can_upclock = false; 294 break; 295 case DYNPM_ACTION_NONE: 296 default: 297 DRM_ERROR("Requested mode for not defined action\n"); 298 return; 299 } 300 } 301 302 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 303 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 304 clock_info[rdev->pm.requested_clock_mode_index].sclk, 305 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 306 clock_info[rdev->pm.requested_clock_mode_index].mclk, 307 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 308 pcie_lanes); 309 } 310 311 void rs780_pm_init_profile(struct radeon_device *rdev) 312 { 313 if (rdev->pm.num_power_states == 2) { 314 /* default */ 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 319 /* low sh */ 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 324 /* mid sh */ 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 329 /* high sh */ 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 334 /* low mh */ 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 339 /* mid mh */ 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 344 /* high mh */ 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 349 } else if (rdev->pm.num_power_states == 3) { 350 /* default */ 351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 353 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 354 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 355 /* low sh */ 356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 358 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 359 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 360 /* mid sh */ 361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 363 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 364 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 365 /* high sh */ 366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 368 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 369 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 370 /* low mh */ 371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 373 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 374 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 375 /* mid mh */ 376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 378 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 379 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 380 /* high mh */ 381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 383 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 384 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 385 } else { 386 /* default */ 387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 391 /* low sh */ 392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 394 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 395 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 396 /* mid sh */ 397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 399 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 400 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 401 /* high sh */ 402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 404 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 405 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 406 /* low mh */ 407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 409 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 410 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 411 /* mid mh */ 412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 416 /* high mh */ 417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 419 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 420 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 421 } 422 } 423 424 void r600_pm_init_profile(struct radeon_device *rdev) 425 { 426 int idx; 427 428 if (rdev->family == CHIP_R600) { 429 /* XXX */ 430 /* default */ 431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 432 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 434 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 435 /* low sh */ 436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 440 /* mid sh */ 441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 442 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 444 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 445 /* high sh */ 446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 447 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 448 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 449 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 450 /* low mh */ 451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 452 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 454 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 455 /* mid mh */ 456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 457 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 458 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 459 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 460 /* high mh */ 461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 462 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 463 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 464 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 465 } else { 466 if (rdev->pm.num_power_states < 4) { 467 /* default */ 468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 469 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 470 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 471 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 472 /* low sh */ 473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 474 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 475 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 476 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 477 /* mid sh */ 478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 481 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 482 /* high sh */ 483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 484 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 485 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 486 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 487 /* low mh */ 488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 489 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 490 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 491 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 492 /* low mh */ 493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 494 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 495 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 496 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 497 /* high mh */ 498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 499 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 500 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 501 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 502 } else { 503 /* default */ 504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 505 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 506 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 507 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 508 /* low sh */ 509 if (rdev->flags & RADEON_IS_MOBILITY) 510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 511 else 512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 517 /* mid sh */ 518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 522 /* high sh */ 523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 526 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 528 /* low mh */ 529 if (rdev->flags & RADEON_IS_MOBILITY) 530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 531 else 532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 537 /* mid mh */ 538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 542 /* high mh */ 543 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 545 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 546 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 548 } 549 } 550 } 551 552 void r600_pm_misc(struct radeon_device *rdev) 553 { 554 int req_ps_idx = rdev->pm.requested_power_state_index; 555 int req_cm_idx = rdev->pm.requested_clock_mode_index; 556 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 557 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 558 559 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 560 /* 0xff01 is a flag rather then an actual voltage */ 561 if (voltage->voltage == 0xff01) 562 return; 563 if (voltage->voltage != rdev->pm.current_vddc) { 564 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 565 rdev->pm.current_vddc = voltage->voltage; 566 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 567 } 568 } 569 } 570 571 bool r600_gui_idle(struct radeon_device *rdev) 572 { 573 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 574 return false; 575 else 576 return true; 577 } 578 579 /* hpd for digital panel detect/disconnect */ 580 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 581 { 582 bool connected = false; 583 584 if (ASIC_IS_DCE3(rdev)) { 585 switch (hpd) { 586 case RADEON_HPD_1: 587 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 588 connected = true; 589 break; 590 case RADEON_HPD_2: 591 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 592 connected = true; 593 break; 594 case RADEON_HPD_3: 595 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 596 connected = true; 597 break; 598 case RADEON_HPD_4: 599 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 600 connected = true; 601 break; 602 /* DCE 3.2 */ 603 case RADEON_HPD_5: 604 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 605 connected = true; 606 break; 607 case RADEON_HPD_6: 608 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 609 connected = true; 610 break; 611 default: 612 break; 613 } 614 } else { 615 switch (hpd) { 616 case RADEON_HPD_1: 617 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 618 connected = true; 619 break; 620 case RADEON_HPD_2: 621 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 622 connected = true; 623 break; 624 case RADEON_HPD_3: 625 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 626 connected = true; 627 break; 628 default: 629 break; 630 } 631 } 632 return connected; 633 } 634 635 void r600_hpd_set_polarity(struct radeon_device *rdev, 636 enum radeon_hpd_id hpd) 637 { 638 u32 tmp; 639 bool connected = r600_hpd_sense(rdev, hpd); 640 641 if (ASIC_IS_DCE3(rdev)) { 642 switch (hpd) { 643 case RADEON_HPD_1: 644 tmp = RREG32(DC_HPD1_INT_CONTROL); 645 if (connected) 646 tmp &= ~DC_HPDx_INT_POLARITY; 647 else 648 tmp |= DC_HPDx_INT_POLARITY; 649 WREG32(DC_HPD1_INT_CONTROL, tmp); 650 break; 651 case RADEON_HPD_2: 652 tmp = RREG32(DC_HPD2_INT_CONTROL); 653 if (connected) 654 tmp &= ~DC_HPDx_INT_POLARITY; 655 else 656 tmp |= DC_HPDx_INT_POLARITY; 657 WREG32(DC_HPD2_INT_CONTROL, tmp); 658 break; 659 case RADEON_HPD_3: 660 tmp = RREG32(DC_HPD3_INT_CONTROL); 661 if (connected) 662 tmp &= ~DC_HPDx_INT_POLARITY; 663 else 664 tmp |= DC_HPDx_INT_POLARITY; 665 WREG32(DC_HPD3_INT_CONTROL, tmp); 666 break; 667 case RADEON_HPD_4: 668 tmp = RREG32(DC_HPD4_INT_CONTROL); 669 if (connected) 670 tmp &= ~DC_HPDx_INT_POLARITY; 671 else 672 tmp |= DC_HPDx_INT_POLARITY; 673 WREG32(DC_HPD4_INT_CONTROL, tmp); 674 break; 675 case RADEON_HPD_5: 676 tmp = RREG32(DC_HPD5_INT_CONTROL); 677 if (connected) 678 tmp &= ~DC_HPDx_INT_POLARITY; 679 else 680 tmp |= DC_HPDx_INT_POLARITY; 681 WREG32(DC_HPD5_INT_CONTROL, tmp); 682 break; 683 /* DCE 3.2 */ 684 case RADEON_HPD_6: 685 tmp = RREG32(DC_HPD6_INT_CONTROL); 686 if (connected) 687 tmp &= ~DC_HPDx_INT_POLARITY; 688 else 689 tmp |= DC_HPDx_INT_POLARITY; 690 WREG32(DC_HPD6_INT_CONTROL, tmp); 691 break; 692 default: 693 break; 694 } 695 } else { 696 switch (hpd) { 697 case RADEON_HPD_1: 698 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 699 if (connected) 700 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 701 else 702 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 703 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 704 break; 705 case RADEON_HPD_2: 706 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 707 if (connected) 708 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 709 else 710 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 711 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 712 break; 713 case RADEON_HPD_3: 714 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 715 if (connected) 716 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 717 else 718 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 719 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 720 break; 721 default: 722 break; 723 } 724 } 725 } 726 727 void r600_hpd_init(struct radeon_device *rdev) 728 { 729 struct drm_device *dev = rdev->ddev; 730 struct drm_connector *connector; 731 unsigned enable = 0; 732 733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 734 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 735 736 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 737 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 738 /* don't try to enable hpd on eDP or LVDS avoid breaking the 739 * aux dp channel on imac and help (but not completely fix) 740 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 741 */ 742 continue; 743 } 744 if (ASIC_IS_DCE3(rdev)) { 745 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 746 if (ASIC_IS_DCE32(rdev)) 747 tmp |= DC_HPDx_EN; 748 749 switch (radeon_connector->hpd.hpd) { 750 case RADEON_HPD_1: 751 WREG32(DC_HPD1_CONTROL, tmp); 752 break; 753 case RADEON_HPD_2: 754 WREG32(DC_HPD2_CONTROL, tmp); 755 break; 756 case RADEON_HPD_3: 757 WREG32(DC_HPD3_CONTROL, tmp); 758 break; 759 case RADEON_HPD_4: 760 WREG32(DC_HPD4_CONTROL, tmp); 761 break; 762 /* DCE 3.2 */ 763 case RADEON_HPD_5: 764 WREG32(DC_HPD5_CONTROL, tmp); 765 break; 766 case RADEON_HPD_6: 767 WREG32(DC_HPD6_CONTROL, tmp); 768 break; 769 default: 770 break; 771 } 772 } else { 773 switch (radeon_connector->hpd.hpd) { 774 case RADEON_HPD_1: 775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 776 break; 777 case RADEON_HPD_2: 778 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 779 break; 780 case RADEON_HPD_3: 781 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 782 break; 783 default: 784 break; 785 } 786 } 787 enable |= 1 << radeon_connector->hpd.hpd; 788 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 789 } 790 radeon_irq_kms_enable_hpd(rdev, enable); 791 } 792 793 void r600_hpd_fini(struct radeon_device *rdev) 794 { 795 struct drm_device *dev = rdev->ddev; 796 struct drm_connector *connector; 797 unsigned disable = 0; 798 799 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 800 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 801 if (ASIC_IS_DCE3(rdev)) { 802 switch (radeon_connector->hpd.hpd) { 803 case RADEON_HPD_1: 804 WREG32(DC_HPD1_CONTROL, 0); 805 break; 806 case RADEON_HPD_2: 807 WREG32(DC_HPD2_CONTROL, 0); 808 break; 809 case RADEON_HPD_3: 810 WREG32(DC_HPD3_CONTROL, 0); 811 break; 812 case RADEON_HPD_4: 813 WREG32(DC_HPD4_CONTROL, 0); 814 break; 815 /* DCE 3.2 */ 816 case RADEON_HPD_5: 817 WREG32(DC_HPD5_CONTROL, 0); 818 break; 819 case RADEON_HPD_6: 820 WREG32(DC_HPD6_CONTROL, 0); 821 break; 822 default: 823 break; 824 } 825 } else { 826 switch (radeon_connector->hpd.hpd) { 827 case RADEON_HPD_1: 828 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 829 break; 830 case RADEON_HPD_2: 831 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 832 break; 833 case RADEON_HPD_3: 834 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 835 break; 836 default: 837 break; 838 } 839 } 840 disable |= 1 << radeon_connector->hpd.hpd; 841 } 842 radeon_irq_kms_disable_hpd(rdev, disable); 843 } 844 845 /* 846 * R600 PCIE GART 847 */ 848 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 849 { 850 unsigned i; 851 u32 tmp; 852 853 /* flush hdp cache so updates hit vram */ 854 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 855 !(rdev->flags & RADEON_IS_AGP)) { 856 volatile uint32_t *ptr = rdev->gart.ptr; 857 u32 tmp; 858 859 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 860 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 861 * This seems to cause problems on some AGP cards. Just use the old 862 * method for them. 863 */ 864 WREG32(HDP_DEBUG1, 0); 865 tmp = *ptr; 866 } else 867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 868 869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 872 for (i = 0; i < rdev->usec_timeout; i++) { 873 /* read MC_STATUS */ 874 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 875 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 876 if (tmp == 2) { 877 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 878 return; 879 } 880 if (tmp) { 881 return; 882 } 883 udelay(1); 884 } 885 } 886 887 int r600_pcie_gart_init(struct radeon_device *rdev) 888 { 889 int r; 890 891 if (rdev->gart.robj) { 892 WARN(1, "R600 PCIE GART already initialized\n"); 893 return 0; 894 } 895 /* Initialize common gart structure */ 896 r = radeon_gart_init(rdev); 897 if (r) 898 return r; 899 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 900 return radeon_gart_table_vram_alloc(rdev); 901 } 902 903 static int r600_pcie_gart_enable(struct radeon_device *rdev) 904 { 905 u32 tmp; 906 int r, i; 907 908 if (rdev->gart.robj == NULL) { 909 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 910 return -EINVAL; 911 } 912 r = radeon_gart_table_vram_pin(rdev); 913 if (r) 914 return r; 915 radeon_gart_restore(rdev); 916 917 /* Setup L2 cache */ 918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 920 EFFECTIVE_L2_QUEUE_SIZE(7)); 921 WREG32(VM_L2_CNTL2, 0); 922 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 923 /* Setup TLB control */ 924 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 925 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 927 ENABLE_WAIT_L2_QUERY; 928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 945 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 948 (u32)(rdev->dummy_page.addr >> 12)); 949 for (i = 1; i < 7; i++) 950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 951 952 r600_pcie_gart_tlb_flush(rdev); 953 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 954 (unsigned)(rdev->mc.gtt_size >> 20), 955 (unsigned long long)rdev->gart.table_addr); 956 rdev->gart.ready = true; 957 return 0; 958 } 959 960 static void r600_pcie_gart_disable(struct radeon_device *rdev) 961 { 962 u32 tmp; 963 int i; 964 965 /* Disable all tables */ 966 for (i = 0; i < 7; i++) 967 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 968 969 /* Disable L2 cache */ 970 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 971 EFFECTIVE_L2_QUEUE_SIZE(7)); 972 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 973 /* Setup L1 TLB control */ 974 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 975 ENABLE_WAIT_L2_QUERY; 976 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 977 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 978 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 979 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 980 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 981 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 982 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 983 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 984 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 985 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 986 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 987 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 988 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 989 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 990 radeon_gart_table_vram_unpin(rdev); 991 } 992 993 static void r600_pcie_gart_fini(struct radeon_device *rdev) 994 { 995 radeon_gart_fini(rdev); 996 r600_pcie_gart_disable(rdev); 997 radeon_gart_table_vram_free(rdev); 998 } 999 1000 static void r600_agp_enable(struct radeon_device *rdev) 1001 { 1002 u32 tmp; 1003 int i; 1004 1005 /* Setup L2 cache */ 1006 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1008 EFFECTIVE_L2_QUEUE_SIZE(7)); 1009 WREG32(VM_L2_CNTL2, 0); 1010 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1011 /* Setup TLB control */ 1012 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1014 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1015 ENABLE_WAIT_L2_QUERY; 1016 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1017 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1018 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1019 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1020 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1021 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1022 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1023 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1024 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1025 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1026 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1027 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1028 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1029 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1030 for (i = 0; i < 7; i++) 1031 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1032 } 1033 1034 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1035 { 1036 unsigned i; 1037 u32 tmp; 1038 1039 for (i = 0; i < rdev->usec_timeout; i++) { 1040 /* read MC_STATUS */ 1041 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1042 if (!tmp) 1043 return 0; 1044 udelay(1); 1045 } 1046 return -1; 1047 } 1048 1049 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1050 { 1051 uint32_t r; 1052 1053 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1054 r = RREG32(R_0028FC_MC_DATA); 1055 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1056 return r; 1057 } 1058 1059 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1060 { 1061 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1062 S_0028F8_MC_IND_WR_EN(1)); 1063 WREG32(R_0028FC_MC_DATA, v); 1064 WREG32(R_0028F8_MC_INDEX, 0x7F); 1065 } 1066 1067 static void r600_mc_program(struct radeon_device *rdev) 1068 { 1069 struct rv515_mc_save save; 1070 u32 tmp; 1071 int i, j; 1072 1073 /* Initialize HDP */ 1074 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1075 WREG32((0x2c14 + j), 0x00000000); 1076 WREG32((0x2c18 + j), 0x00000000); 1077 WREG32((0x2c1c + j), 0x00000000); 1078 WREG32((0x2c20 + j), 0x00000000); 1079 WREG32((0x2c24 + j), 0x00000000); 1080 } 1081 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1082 1083 rv515_mc_stop(rdev, &save); 1084 if (r600_mc_wait_for_idle(rdev)) { 1085 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1086 } 1087 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1088 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1089 /* Update configuration */ 1090 if (rdev->flags & RADEON_IS_AGP) { 1091 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1092 /* VRAM before AGP */ 1093 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1094 rdev->mc.vram_start >> 12); 1095 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1096 rdev->mc.gtt_end >> 12); 1097 } else { 1098 /* VRAM after AGP */ 1099 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1100 rdev->mc.gtt_start >> 12); 1101 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1102 rdev->mc.vram_end >> 12); 1103 } 1104 } else { 1105 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1106 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1107 } 1108 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1109 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1110 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1111 WREG32(MC_VM_FB_LOCATION, tmp); 1112 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1113 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1114 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1115 if (rdev->flags & RADEON_IS_AGP) { 1116 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1117 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1118 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1119 } else { 1120 WREG32(MC_VM_AGP_BASE, 0); 1121 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1122 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1123 } 1124 if (r600_mc_wait_for_idle(rdev)) { 1125 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1126 } 1127 rv515_mc_resume(rdev, &save); 1128 /* we need to own VRAM, so turn off the VGA renderer here 1129 * to stop it overwriting our objects */ 1130 rv515_vga_render_disable(rdev); 1131 } 1132 1133 /** 1134 * r600_vram_gtt_location - try to find VRAM & GTT location 1135 * @rdev: radeon device structure holding all necessary informations 1136 * @mc: memory controller structure holding memory informations 1137 * 1138 * Function will place try to place VRAM at same place as in CPU (PCI) 1139 * address space as some GPU seems to have issue when we reprogram at 1140 * different address space. 1141 * 1142 * If there is not enough space to fit the unvisible VRAM after the 1143 * aperture then we limit the VRAM size to the aperture. 1144 * 1145 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1146 * them to be in one from GPU point of view so that we can program GPU to 1147 * catch access outside them (weird GPU policy see ??). 1148 * 1149 * This function will never fails, worst case are limiting VRAM or GTT. 1150 * 1151 * Note: GTT start, end, size should be initialized before calling this 1152 * function on AGP platform. 1153 */ 1154 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1155 { 1156 u64 size_bf, size_af; 1157 1158 if (mc->mc_vram_size > 0xE0000000) { 1159 /* leave room for at least 512M GTT */ 1160 dev_warn(rdev->dev, "limiting VRAM\n"); 1161 mc->real_vram_size = 0xE0000000; 1162 mc->mc_vram_size = 0xE0000000; 1163 } 1164 if (rdev->flags & RADEON_IS_AGP) { 1165 size_bf = mc->gtt_start; 1166 size_af = mc->mc_mask - mc->gtt_end; 1167 if (size_bf > size_af) { 1168 if (mc->mc_vram_size > size_bf) { 1169 dev_warn(rdev->dev, "limiting VRAM\n"); 1170 mc->real_vram_size = size_bf; 1171 mc->mc_vram_size = size_bf; 1172 } 1173 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1174 } else { 1175 if (mc->mc_vram_size > size_af) { 1176 dev_warn(rdev->dev, "limiting VRAM\n"); 1177 mc->real_vram_size = size_af; 1178 mc->mc_vram_size = size_af; 1179 } 1180 mc->vram_start = mc->gtt_end + 1; 1181 } 1182 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1183 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1184 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, 1185 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); 1186 } else { 1187 u64 base = 0; 1188 if (rdev->flags & RADEON_IS_IGP) { 1189 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1190 base <<= 24; 1191 } 1192 radeon_vram_location(rdev, &rdev->mc, base); 1193 rdev->mc.gtt_base_align = 0; 1194 radeon_gtt_location(rdev, mc); 1195 } 1196 } 1197 1198 static int r600_mc_init(struct radeon_device *rdev) 1199 { 1200 u32 tmp; 1201 int chansize, numchan; 1202 uint32_t h_addr, l_addr; 1203 unsigned long long k8_addr; 1204 1205 /* Get VRAM informations */ 1206 rdev->mc.vram_is_ddr = true; 1207 tmp = RREG32(RAMCFG); 1208 if (tmp & CHANSIZE_OVERRIDE) { 1209 chansize = 16; 1210 } else if (tmp & CHANSIZE_MASK) { 1211 chansize = 64; 1212 } else { 1213 chansize = 32; 1214 } 1215 tmp = RREG32(CHMAP); 1216 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1217 case 0: 1218 default: 1219 numchan = 1; 1220 break; 1221 case 1: 1222 numchan = 2; 1223 break; 1224 case 2: 1225 numchan = 4; 1226 break; 1227 case 3: 1228 numchan = 8; 1229 break; 1230 } 1231 rdev->mc.vram_width = numchan * chansize; 1232 /* Could aper size report 0 ? */ 1233 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1234 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1235 /* Setup GPU memory space */ 1236 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1237 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1238 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1239 r600_vram_gtt_location(rdev, &rdev->mc); 1240 1241 if (rdev->flags & RADEON_IS_IGP) { 1242 rs690_pm_info(rdev); 1243 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1244 1245 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1246 /* Use K8 direct mapping for fast fb access. */ 1247 rdev->fastfb_working = false; 1248 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1249 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1250 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1251 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1252 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1253 #endif 1254 { 1255 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1256 * memory is present. 1257 */ 1258 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1259 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1260 (unsigned long long)rdev->mc.aper_base, k8_addr); 1261 rdev->mc.aper_base = (resource_size_t)k8_addr; 1262 rdev->fastfb_working = true; 1263 } 1264 } 1265 } 1266 } 1267 1268 radeon_update_bandwidth_info(rdev); 1269 return 0; 1270 } 1271 1272 int r600_vram_scratch_init(struct radeon_device *rdev) 1273 { 1274 int r; 1275 void *vram_scratch_ptr_ptr; 1276 1277 if (rdev->vram_scratch.robj == NULL) { 1278 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1279 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1280 NULL, &rdev->vram_scratch.robj); 1281 if (r) { 1282 return r; 1283 } 1284 } 1285 1286 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1287 if (unlikely(r != 0)) { 1288 radeon_bo_unref(&rdev->vram_scratch.robj); 1289 return r; 1290 } 1291 r = radeon_bo_pin(rdev->vram_scratch.robj, 1292 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1293 if (r) { 1294 radeon_bo_unreserve(rdev->vram_scratch.robj); 1295 radeon_bo_unref(&rdev->vram_scratch.robj); 1296 return r; 1297 } 1298 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1299 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1300 vram_scratch_ptr_ptr); 1301 if (r) 1302 radeon_bo_unpin(rdev->vram_scratch.robj); 1303 radeon_bo_unreserve(rdev->vram_scratch.robj); 1304 if (r) 1305 radeon_bo_unref(&rdev->vram_scratch.robj); 1306 1307 return r; 1308 } 1309 1310 void r600_vram_scratch_fini(struct radeon_device *rdev) 1311 { 1312 int r; 1313 1314 if (rdev->vram_scratch.robj == NULL) { 1315 return; 1316 } 1317 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1318 if (likely(r == 0)) { 1319 radeon_bo_kunmap(rdev->vram_scratch.robj); 1320 radeon_bo_unpin(rdev->vram_scratch.robj); 1321 radeon_bo_unreserve(rdev->vram_scratch.robj); 1322 } 1323 radeon_bo_unref(&rdev->vram_scratch.robj); 1324 } 1325 1326 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1327 { 1328 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1329 1330 if (hung) 1331 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1332 else 1333 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1334 1335 WREG32(R600_BIOS_3_SCRATCH, tmp); 1336 } 1337 1338 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1339 { 1340 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1341 RREG32(R_008010_GRBM_STATUS)); 1342 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1343 RREG32(R_008014_GRBM_STATUS2)); 1344 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1345 RREG32(R_000E50_SRBM_STATUS)); 1346 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1347 RREG32(CP_STALLED_STAT1)); 1348 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1349 RREG32(CP_STALLED_STAT2)); 1350 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1351 RREG32(CP_BUSY_STAT)); 1352 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1353 RREG32(CP_STAT)); 1354 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1355 RREG32(DMA_STATUS_REG)); 1356 } 1357 1358 static bool r600_is_display_hung(struct radeon_device *rdev) 1359 { 1360 u32 crtc_hung = 0; 1361 u32 crtc_status[2]; 1362 u32 i, j, tmp; 1363 1364 for (i = 0; i < rdev->num_crtc; i++) { 1365 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1366 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1367 crtc_hung |= (1 << i); 1368 } 1369 } 1370 1371 for (j = 0; j < 10; j++) { 1372 for (i = 0; i < rdev->num_crtc; i++) { 1373 if (crtc_hung & (1 << i)) { 1374 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1375 if (tmp != crtc_status[i]) 1376 crtc_hung &= ~(1 << i); 1377 } 1378 } 1379 if (crtc_hung == 0) 1380 return false; 1381 udelay(100); 1382 } 1383 1384 return true; 1385 } 1386 1387 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1388 { 1389 u32 reset_mask = 0; 1390 u32 tmp; 1391 1392 /* GRBM_STATUS */ 1393 tmp = RREG32(R_008010_GRBM_STATUS); 1394 if (rdev->family >= CHIP_RV770) { 1395 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1396 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1397 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1398 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1399 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1400 reset_mask |= RADEON_RESET_GFX; 1401 } else { 1402 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1403 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1404 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1405 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1406 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1407 reset_mask |= RADEON_RESET_GFX; 1408 } 1409 1410 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1411 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1412 reset_mask |= RADEON_RESET_CP; 1413 1414 if (G_008010_GRBM_EE_BUSY(tmp)) 1415 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1416 1417 /* DMA_STATUS_REG */ 1418 tmp = RREG32(DMA_STATUS_REG); 1419 if (!(tmp & DMA_IDLE)) 1420 reset_mask |= RADEON_RESET_DMA; 1421 1422 /* SRBM_STATUS */ 1423 tmp = RREG32(R_000E50_SRBM_STATUS); 1424 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1425 reset_mask |= RADEON_RESET_RLC; 1426 1427 if (G_000E50_IH_BUSY(tmp)) 1428 reset_mask |= RADEON_RESET_IH; 1429 1430 if (G_000E50_SEM_BUSY(tmp)) 1431 reset_mask |= RADEON_RESET_SEM; 1432 1433 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1434 reset_mask |= RADEON_RESET_GRBM; 1435 1436 if (G_000E50_VMC_BUSY(tmp)) 1437 reset_mask |= RADEON_RESET_VMC; 1438 1439 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1440 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1441 G_000E50_MCDW_BUSY(tmp)) 1442 reset_mask |= RADEON_RESET_MC; 1443 1444 if (r600_is_display_hung(rdev)) 1445 reset_mask |= RADEON_RESET_DISPLAY; 1446 1447 /* Skip MC reset as it's mostly likely not hung, just busy */ 1448 if (reset_mask & RADEON_RESET_MC) { 1449 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1450 reset_mask &= ~RADEON_RESET_MC; 1451 } 1452 1453 return reset_mask; 1454 } 1455 1456 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1457 { 1458 struct rv515_mc_save save; 1459 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1460 u32 tmp; 1461 1462 if (reset_mask == 0) 1463 return; 1464 1465 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1466 1467 r600_print_gpu_status_regs(rdev); 1468 1469 /* Disable CP parsing/prefetching */ 1470 if (rdev->family >= CHIP_RV770) 1471 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1472 else 1473 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1474 1475 /* disable the RLC */ 1476 WREG32(RLC_CNTL, 0); 1477 1478 if (reset_mask & RADEON_RESET_DMA) { 1479 /* Disable DMA */ 1480 tmp = RREG32(DMA_RB_CNTL); 1481 tmp &= ~DMA_RB_ENABLE; 1482 WREG32(DMA_RB_CNTL, tmp); 1483 } 1484 1485 mdelay(50); 1486 1487 rv515_mc_stop(rdev, &save); 1488 if (r600_mc_wait_for_idle(rdev)) { 1489 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1490 } 1491 1492 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1493 if (rdev->family >= CHIP_RV770) 1494 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1495 S_008020_SOFT_RESET_CB(1) | 1496 S_008020_SOFT_RESET_PA(1) | 1497 S_008020_SOFT_RESET_SC(1) | 1498 S_008020_SOFT_RESET_SPI(1) | 1499 S_008020_SOFT_RESET_SX(1) | 1500 S_008020_SOFT_RESET_SH(1) | 1501 S_008020_SOFT_RESET_TC(1) | 1502 S_008020_SOFT_RESET_TA(1) | 1503 S_008020_SOFT_RESET_VC(1) | 1504 S_008020_SOFT_RESET_VGT(1); 1505 else 1506 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1507 S_008020_SOFT_RESET_DB(1) | 1508 S_008020_SOFT_RESET_CB(1) | 1509 S_008020_SOFT_RESET_PA(1) | 1510 S_008020_SOFT_RESET_SC(1) | 1511 S_008020_SOFT_RESET_SMX(1) | 1512 S_008020_SOFT_RESET_SPI(1) | 1513 S_008020_SOFT_RESET_SX(1) | 1514 S_008020_SOFT_RESET_SH(1) | 1515 S_008020_SOFT_RESET_TC(1) | 1516 S_008020_SOFT_RESET_TA(1) | 1517 S_008020_SOFT_RESET_VC(1) | 1518 S_008020_SOFT_RESET_VGT(1); 1519 } 1520 1521 if (reset_mask & RADEON_RESET_CP) { 1522 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1523 S_008020_SOFT_RESET_VGT(1); 1524 1525 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1526 } 1527 1528 if (reset_mask & RADEON_RESET_DMA) { 1529 if (rdev->family >= CHIP_RV770) 1530 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1531 else 1532 srbm_soft_reset |= SOFT_RESET_DMA; 1533 } 1534 1535 if (reset_mask & RADEON_RESET_RLC) 1536 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1537 1538 if (reset_mask & RADEON_RESET_SEM) 1539 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1540 1541 if (reset_mask & RADEON_RESET_IH) 1542 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1543 1544 if (reset_mask & RADEON_RESET_GRBM) 1545 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1546 1547 if (!(rdev->flags & RADEON_IS_IGP)) { 1548 if (reset_mask & RADEON_RESET_MC) 1549 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1550 } 1551 1552 if (reset_mask & RADEON_RESET_VMC) 1553 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1554 1555 if (grbm_soft_reset) { 1556 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1557 tmp |= grbm_soft_reset; 1558 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1559 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1560 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1561 1562 udelay(50); 1563 1564 tmp &= ~grbm_soft_reset; 1565 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1566 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1567 } 1568 1569 if (srbm_soft_reset) { 1570 tmp = RREG32(SRBM_SOFT_RESET); 1571 tmp |= srbm_soft_reset; 1572 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1573 WREG32(SRBM_SOFT_RESET, tmp); 1574 tmp = RREG32(SRBM_SOFT_RESET); 1575 1576 udelay(50); 1577 1578 tmp &= ~srbm_soft_reset; 1579 WREG32(SRBM_SOFT_RESET, tmp); 1580 tmp = RREG32(SRBM_SOFT_RESET); 1581 } 1582 1583 /* Wait a little for things to settle down */ 1584 mdelay(1); 1585 1586 rv515_mc_resume(rdev, &save); 1587 udelay(50); 1588 1589 r600_print_gpu_status_regs(rdev); 1590 } 1591 1592 int r600_asic_reset(struct radeon_device *rdev) 1593 { 1594 u32 reset_mask; 1595 1596 reset_mask = r600_gpu_check_soft_reset(rdev); 1597 1598 if (reset_mask) 1599 r600_set_bios_scratch_engine_hung(rdev, true); 1600 1601 r600_gpu_soft_reset(rdev, reset_mask); 1602 1603 reset_mask = r600_gpu_check_soft_reset(rdev); 1604 1605 if (!reset_mask) 1606 r600_set_bios_scratch_engine_hung(rdev, false); 1607 1608 return 0; 1609 } 1610 1611 /** 1612 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1613 * 1614 * @rdev: radeon_device pointer 1615 * @ring: radeon_ring structure holding ring information 1616 * 1617 * Check if the GFX engine is locked up. 1618 * Returns true if the engine appears to be locked up, false if not. 1619 */ 1620 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1621 { 1622 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1623 1624 if (!(reset_mask & (RADEON_RESET_GFX | 1625 RADEON_RESET_COMPUTE | 1626 RADEON_RESET_CP))) { 1627 radeon_ring_lockup_update(ring); 1628 return false; 1629 } 1630 /* force CP activities */ 1631 radeon_ring_force_activity(rdev, ring); 1632 return radeon_ring_test_lockup(rdev, ring); 1633 } 1634 1635 /** 1636 * r600_dma_is_lockup - Check if the DMA engine is locked up 1637 * 1638 * @rdev: radeon_device pointer 1639 * @ring: radeon_ring structure holding ring information 1640 * 1641 * Check if the async DMA engine is locked up. 1642 * Returns true if the engine appears to be locked up, false if not. 1643 */ 1644 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1645 { 1646 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1647 1648 if (!(reset_mask & RADEON_RESET_DMA)) { 1649 radeon_ring_lockup_update(ring); 1650 return false; 1651 } 1652 /* force ring activities */ 1653 radeon_ring_force_activity(rdev, ring); 1654 return radeon_ring_test_lockup(rdev, ring); 1655 } 1656 1657 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1658 u32 tiling_pipe_num, 1659 u32 max_rb_num, 1660 u32 total_max_rb_num, 1661 u32 disabled_rb_mask) 1662 { 1663 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1664 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1665 u32 data = 0, mask = 1 << (max_rb_num - 1); 1666 unsigned i, j; 1667 1668 /* mask out the RBs that don't exist on that asic */ 1669 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1670 /* make sure at least one RB is available */ 1671 if ((tmp & 0xff) != 0xff) 1672 disabled_rb_mask = tmp; 1673 1674 rendering_pipe_num = 1 << tiling_pipe_num; 1675 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1676 BUG_ON(rendering_pipe_num < req_rb_num); 1677 1678 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1679 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1680 1681 if (rdev->family <= CHIP_RV740) { 1682 /* r6xx/r7xx */ 1683 rb_num_width = 2; 1684 } else { 1685 /* eg+ */ 1686 rb_num_width = 4; 1687 } 1688 1689 for (i = 0; i < max_rb_num; i++) { 1690 if (!(mask & disabled_rb_mask)) { 1691 for (j = 0; j < pipe_rb_ratio; j++) { 1692 data <<= rb_num_width; 1693 data |= max_rb_num - i - 1; 1694 } 1695 if (pipe_rb_remain) { 1696 data <<= rb_num_width; 1697 data |= max_rb_num - i - 1; 1698 pipe_rb_remain--; 1699 } 1700 } 1701 mask >>= 1; 1702 } 1703 1704 return data; 1705 } 1706 1707 int r600_count_pipe_bits(uint32_t val) 1708 { 1709 return hweight32(val); 1710 } 1711 1712 static void r600_gpu_init(struct radeon_device *rdev) 1713 { 1714 u32 tiling_config; 1715 u32 ramcfg; 1716 u32 cc_rb_backend_disable; 1717 u32 cc_gc_shader_pipe_config; 1718 u32 tmp; 1719 int i, j; 1720 u32 sq_config; 1721 u32 sq_gpr_resource_mgmt_1 = 0; 1722 u32 sq_gpr_resource_mgmt_2 = 0; 1723 u32 sq_thread_resource_mgmt = 0; 1724 u32 sq_stack_resource_mgmt_1 = 0; 1725 u32 sq_stack_resource_mgmt_2 = 0; 1726 u32 disabled_rb_mask; 1727 1728 rdev->config.r600.tiling_group_size = 256; 1729 switch (rdev->family) { 1730 case CHIP_R600: 1731 rdev->config.r600.max_pipes = 4; 1732 rdev->config.r600.max_tile_pipes = 8; 1733 rdev->config.r600.max_simds = 4; 1734 rdev->config.r600.max_backends = 4; 1735 rdev->config.r600.max_gprs = 256; 1736 rdev->config.r600.max_threads = 192; 1737 rdev->config.r600.max_stack_entries = 256; 1738 rdev->config.r600.max_hw_contexts = 8; 1739 rdev->config.r600.max_gs_threads = 16; 1740 rdev->config.r600.sx_max_export_size = 128; 1741 rdev->config.r600.sx_max_export_pos_size = 16; 1742 rdev->config.r600.sx_max_export_smx_size = 128; 1743 rdev->config.r600.sq_num_cf_insts = 2; 1744 break; 1745 case CHIP_RV630: 1746 case CHIP_RV635: 1747 rdev->config.r600.max_pipes = 2; 1748 rdev->config.r600.max_tile_pipes = 2; 1749 rdev->config.r600.max_simds = 3; 1750 rdev->config.r600.max_backends = 1; 1751 rdev->config.r600.max_gprs = 128; 1752 rdev->config.r600.max_threads = 192; 1753 rdev->config.r600.max_stack_entries = 128; 1754 rdev->config.r600.max_hw_contexts = 8; 1755 rdev->config.r600.max_gs_threads = 4; 1756 rdev->config.r600.sx_max_export_size = 128; 1757 rdev->config.r600.sx_max_export_pos_size = 16; 1758 rdev->config.r600.sx_max_export_smx_size = 128; 1759 rdev->config.r600.sq_num_cf_insts = 2; 1760 break; 1761 case CHIP_RV610: 1762 case CHIP_RV620: 1763 case CHIP_RS780: 1764 case CHIP_RS880: 1765 rdev->config.r600.max_pipes = 1; 1766 rdev->config.r600.max_tile_pipes = 1; 1767 rdev->config.r600.max_simds = 2; 1768 rdev->config.r600.max_backends = 1; 1769 rdev->config.r600.max_gprs = 128; 1770 rdev->config.r600.max_threads = 192; 1771 rdev->config.r600.max_stack_entries = 128; 1772 rdev->config.r600.max_hw_contexts = 4; 1773 rdev->config.r600.max_gs_threads = 4; 1774 rdev->config.r600.sx_max_export_size = 128; 1775 rdev->config.r600.sx_max_export_pos_size = 16; 1776 rdev->config.r600.sx_max_export_smx_size = 128; 1777 rdev->config.r600.sq_num_cf_insts = 1; 1778 break; 1779 case CHIP_RV670: 1780 rdev->config.r600.max_pipes = 4; 1781 rdev->config.r600.max_tile_pipes = 4; 1782 rdev->config.r600.max_simds = 4; 1783 rdev->config.r600.max_backends = 4; 1784 rdev->config.r600.max_gprs = 192; 1785 rdev->config.r600.max_threads = 192; 1786 rdev->config.r600.max_stack_entries = 256; 1787 rdev->config.r600.max_hw_contexts = 8; 1788 rdev->config.r600.max_gs_threads = 16; 1789 rdev->config.r600.sx_max_export_size = 128; 1790 rdev->config.r600.sx_max_export_pos_size = 16; 1791 rdev->config.r600.sx_max_export_smx_size = 128; 1792 rdev->config.r600.sq_num_cf_insts = 2; 1793 break; 1794 default: 1795 break; 1796 } 1797 1798 /* Initialize HDP */ 1799 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1800 WREG32((0x2c14 + j), 0x00000000); 1801 WREG32((0x2c18 + j), 0x00000000); 1802 WREG32((0x2c1c + j), 0x00000000); 1803 WREG32((0x2c20 + j), 0x00000000); 1804 WREG32((0x2c24 + j), 0x00000000); 1805 } 1806 1807 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1808 1809 /* Setup tiling */ 1810 tiling_config = 0; 1811 ramcfg = RREG32(RAMCFG); 1812 switch (rdev->config.r600.max_tile_pipes) { 1813 case 1: 1814 tiling_config |= PIPE_TILING(0); 1815 break; 1816 case 2: 1817 tiling_config |= PIPE_TILING(1); 1818 break; 1819 case 4: 1820 tiling_config |= PIPE_TILING(2); 1821 break; 1822 case 8: 1823 tiling_config |= PIPE_TILING(3); 1824 break; 1825 default: 1826 break; 1827 } 1828 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1829 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1830 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1831 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1832 1833 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1834 if (tmp > 3) { 1835 tiling_config |= ROW_TILING(3); 1836 tiling_config |= SAMPLE_SPLIT(3); 1837 } else { 1838 tiling_config |= ROW_TILING(tmp); 1839 tiling_config |= SAMPLE_SPLIT(tmp); 1840 } 1841 tiling_config |= BANK_SWAPS(1); 1842 1843 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1844 tmp = R6XX_MAX_BACKENDS - 1845 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1846 if (tmp < rdev->config.r600.max_backends) { 1847 rdev->config.r600.max_backends = tmp; 1848 } 1849 1850 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1851 tmp = R6XX_MAX_PIPES - 1852 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1853 if (tmp < rdev->config.r600.max_pipes) { 1854 rdev->config.r600.max_pipes = tmp; 1855 } 1856 tmp = R6XX_MAX_SIMDS - 1857 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1858 if (tmp < rdev->config.r600.max_simds) { 1859 rdev->config.r600.max_simds = tmp; 1860 } 1861 1862 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1863 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1864 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1865 R6XX_MAX_BACKENDS, disabled_rb_mask); 1866 tiling_config |= tmp << 16; 1867 rdev->config.r600.backend_map = tmp; 1868 1869 rdev->config.r600.tile_config = tiling_config; 1870 WREG32(GB_TILING_CONFIG, tiling_config); 1871 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1872 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1873 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1874 1875 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1876 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1877 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1878 1879 /* Setup some CP states */ 1880 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1881 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1882 1883 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1884 SYNC_WALKER | SYNC_ALIGNER)); 1885 /* Setup various GPU states */ 1886 if (rdev->family == CHIP_RV670) 1887 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1888 1889 tmp = RREG32(SX_DEBUG_1); 1890 tmp |= SMX_EVENT_RELEASE; 1891 if ((rdev->family > CHIP_R600)) 1892 tmp |= ENABLE_NEW_SMX_ADDRESS; 1893 WREG32(SX_DEBUG_1, tmp); 1894 1895 if (((rdev->family) == CHIP_R600) || 1896 ((rdev->family) == CHIP_RV630) || 1897 ((rdev->family) == CHIP_RV610) || 1898 ((rdev->family) == CHIP_RV620) || 1899 ((rdev->family) == CHIP_RS780) || 1900 ((rdev->family) == CHIP_RS880)) { 1901 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1902 } else { 1903 WREG32(DB_DEBUG, 0); 1904 } 1905 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1906 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1907 1908 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1909 WREG32(VGT_NUM_INSTANCES, 0); 1910 1911 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1912 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1913 1914 tmp = RREG32(SQ_MS_FIFO_SIZES); 1915 if (((rdev->family) == CHIP_RV610) || 1916 ((rdev->family) == CHIP_RV620) || 1917 ((rdev->family) == CHIP_RS780) || 1918 ((rdev->family) == CHIP_RS880)) { 1919 tmp = (CACHE_FIFO_SIZE(0xa) | 1920 FETCH_FIFO_HIWATER(0xa) | 1921 DONE_FIFO_HIWATER(0xe0) | 1922 ALU_UPDATE_FIFO_HIWATER(0x8)); 1923 } else if (((rdev->family) == CHIP_R600) || 1924 ((rdev->family) == CHIP_RV630)) { 1925 tmp &= ~DONE_FIFO_HIWATER(0xff); 1926 tmp |= DONE_FIFO_HIWATER(0x4); 1927 } 1928 WREG32(SQ_MS_FIFO_SIZES, tmp); 1929 1930 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1931 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1932 */ 1933 sq_config = RREG32(SQ_CONFIG); 1934 sq_config &= ~(PS_PRIO(3) | 1935 VS_PRIO(3) | 1936 GS_PRIO(3) | 1937 ES_PRIO(3)); 1938 sq_config |= (DX9_CONSTS | 1939 VC_ENABLE | 1940 PS_PRIO(0) | 1941 VS_PRIO(1) | 1942 GS_PRIO(2) | 1943 ES_PRIO(3)); 1944 1945 if ((rdev->family) == CHIP_R600) { 1946 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1947 NUM_VS_GPRS(124) | 1948 NUM_CLAUSE_TEMP_GPRS(4)); 1949 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1950 NUM_ES_GPRS(0)); 1951 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1952 NUM_VS_THREADS(48) | 1953 NUM_GS_THREADS(4) | 1954 NUM_ES_THREADS(4)); 1955 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1956 NUM_VS_STACK_ENTRIES(128)); 1957 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1958 NUM_ES_STACK_ENTRIES(0)); 1959 } else if (((rdev->family) == CHIP_RV610) || 1960 ((rdev->family) == CHIP_RV620) || 1961 ((rdev->family) == CHIP_RS780) || 1962 ((rdev->family) == CHIP_RS880)) { 1963 /* no vertex cache */ 1964 sq_config &= ~VC_ENABLE; 1965 1966 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1967 NUM_VS_GPRS(44) | 1968 NUM_CLAUSE_TEMP_GPRS(2)); 1969 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1970 NUM_ES_GPRS(17)); 1971 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1972 NUM_VS_THREADS(78) | 1973 NUM_GS_THREADS(4) | 1974 NUM_ES_THREADS(31)); 1975 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1976 NUM_VS_STACK_ENTRIES(40)); 1977 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1978 NUM_ES_STACK_ENTRIES(16)); 1979 } else if (((rdev->family) == CHIP_RV630) || 1980 ((rdev->family) == CHIP_RV635)) { 1981 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1982 NUM_VS_GPRS(44) | 1983 NUM_CLAUSE_TEMP_GPRS(2)); 1984 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1985 NUM_ES_GPRS(18)); 1986 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1987 NUM_VS_THREADS(78) | 1988 NUM_GS_THREADS(4) | 1989 NUM_ES_THREADS(31)); 1990 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1991 NUM_VS_STACK_ENTRIES(40)); 1992 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1993 NUM_ES_STACK_ENTRIES(16)); 1994 } else if ((rdev->family) == CHIP_RV670) { 1995 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1996 NUM_VS_GPRS(44) | 1997 NUM_CLAUSE_TEMP_GPRS(2)); 1998 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1999 NUM_ES_GPRS(17)); 2000 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2001 NUM_VS_THREADS(78) | 2002 NUM_GS_THREADS(4) | 2003 NUM_ES_THREADS(31)); 2004 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2005 NUM_VS_STACK_ENTRIES(64)); 2006 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2007 NUM_ES_STACK_ENTRIES(64)); 2008 } 2009 2010 WREG32(SQ_CONFIG, sq_config); 2011 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2012 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2013 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2014 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2015 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2016 2017 if (((rdev->family) == CHIP_RV610) || 2018 ((rdev->family) == CHIP_RV620) || 2019 ((rdev->family) == CHIP_RS780) || 2020 ((rdev->family) == CHIP_RS880)) { 2021 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2022 } else { 2023 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2024 } 2025 2026 /* More default values. 2D/3D driver should adjust as needed */ 2027 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2028 S1_X(0x4) | S1_Y(0xc))); 2029 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2030 S1_X(0x2) | S1_Y(0x2) | 2031 S2_X(0xa) | S2_Y(0x6) | 2032 S3_X(0x6) | S3_Y(0xa))); 2033 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2034 S1_X(0x4) | S1_Y(0xc) | 2035 S2_X(0x1) | S2_Y(0x6) | 2036 S3_X(0xa) | S3_Y(0xe))); 2037 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2038 S5_X(0x0) | S5_Y(0x0) | 2039 S6_X(0xb) | S6_Y(0x4) | 2040 S7_X(0x7) | S7_Y(0x8))); 2041 2042 WREG32(VGT_STRMOUT_EN, 0); 2043 tmp = rdev->config.r600.max_pipes * 16; 2044 switch (rdev->family) { 2045 case CHIP_RV610: 2046 case CHIP_RV620: 2047 case CHIP_RS780: 2048 case CHIP_RS880: 2049 tmp += 32; 2050 break; 2051 case CHIP_RV670: 2052 tmp += 128; 2053 break; 2054 default: 2055 break; 2056 } 2057 if (tmp > 256) { 2058 tmp = 256; 2059 } 2060 WREG32(VGT_ES_PER_GS, 128); 2061 WREG32(VGT_GS_PER_ES, tmp); 2062 WREG32(VGT_GS_PER_VS, 2); 2063 WREG32(VGT_GS_VERTEX_REUSE, 16); 2064 2065 /* more default values. 2D/3D driver should adjust as needed */ 2066 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2067 WREG32(VGT_STRMOUT_EN, 0); 2068 WREG32(SX_MISC, 0); 2069 WREG32(PA_SC_MODE_CNTL, 0); 2070 WREG32(PA_SC_AA_CONFIG, 0); 2071 WREG32(PA_SC_LINE_STIPPLE, 0); 2072 WREG32(SPI_INPUT_Z, 0); 2073 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2074 WREG32(CB_COLOR7_FRAG, 0); 2075 2076 /* Clear render buffer base addresses */ 2077 WREG32(CB_COLOR0_BASE, 0); 2078 WREG32(CB_COLOR1_BASE, 0); 2079 WREG32(CB_COLOR2_BASE, 0); 2080 WREG32(CB_COLOR3_BASE, 0); 2081 WREG32(CB_COLOR4_BASE, 0); 2082 WREG32(CB_COLOR5_BASE, 0); 2083 WREG32(CB_COLOR6_BASE, 0); 2084 WREG32(CB_COLOR7_BASE, 0); 2085 WREG32(CB_COLOR7_FRAG, 0); 2086 2087 switch (rdev->family) { 2088 case CHIP_RV610: 2089 case CHIP_RV620: 2090 case CHIP_RS780: 2091 case CHIP_RS880: 2092 tmp = TC_L2_SIZE(8); 2093 break; 2094 case CHIP_RV630: 2095 case CHIP_RV635: 2096 tmp = TC_L2_SIZE(4); 2097 break; 2098 case CHIP_R600: 2099 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2100 break; 2101 default: 2102 tmp = TC_L2_SIZE(0); 2103 break; 2104 } 2105 WREG32(TC_CNTL, tmp); 2106 2107 tmp = RREG32(HDP_HOST_PATH_CNTL); 2108 WREG32(HDP_HOST_PATH_CNTL, tmp); 2109 2110 tmp = RREG32(ARB_POP); 2111 tmp |= ENABLE_TC128; 2112 WREG32(ARB_POP, tmp); 2113 2114 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2115 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2116 NUM_CLIP_SEQ(3))); 2117 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2118 WREG32(VC_ENHANCE, 0); 2119 } 2120 2121 2122 /* 2123 * Indirect registers accessor 2124 */ 2125 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2126 { 2127 u32 r; 2128 2129 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2130 (void)RREG32(PCIE_PORT_INDEX); 2131 r = RREG32(PCIE_PORT_DATA); 2132 return r; 2133 } 2134 2135 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2136 { 2137 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2138 (void)RREG32(PCIE_PORT_INDEX); 2139 WREG32(PCIE_PORT_DATA, (v)); 2140 (void)RREG32(PCIE_PORT_DATA); 2141 } 2142 2143 /* 2144 * CP & Ring 2145 */ 2146 void r600_cp_stop(struct radeon_device *rdev) 2147 { 2148 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2149 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2150 WREG32(SCRATCH_UMSK, 0); 2151 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2152 } 2153 2154 int r600_init_microcode(struct radeon_device *rdev) 2155 { 2156 const char *chip_name; 2157 const char *rlc_chip_name; 2158 const char *smc_chip_name = "RV770"; 2159 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2160 char fw_name[30]; 2161 int err; 2162 2163 DRM_DEBUG("\n"); 2164 2165 switch (rdev->family) { 2166 case CHIP_R600: 2167 chip_name = "R600"; 2168 rlc_chip_name = "R600"; 2169 break; 2170 case CHIP_RV610: 2171 chip_name = "RV610"; 2172 rlc_chip_name = "R600"; 2173 break; 2174 case CHIP_RV630: 2175 chip_name = "RV630"; 2176 rlc_chip_name = "R600"; 2177 break; 2178 case CHIP_RV620: 2179 chip_name = "RV620"; 2180 rlc_chip_name = "R600"; 2181 break; 2182 case CHIP_RV635: 2183 chip_name = "RV635"; 2184 rlc_chip_name = "R600"; 2185 break; 2186 case CHIP_RV670: 2187 chip_name = "RV670"; 2188 rlc_chip_name = "R600"; 2189 break; 2190 case CHIP_RS780: 2191 case CHIP_RS880: 2192 chip_name = "RS780"; 2193 rlc_chip_name = "R600"; 2194 break; 2195 case CHIP_RV770: 2196 chip_name = "RV770"; 2197 rlc_chip_name = "R700"; 2198 smc_chip_name = "RV770"; 2199 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2200 break; 2201 case CHIP_RV730: 2202 chip_name = "RV730"; 2203 rlc_chip_name = "R700"; 2204 smc_chip_name = "RV730"; 2205 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2206 break; 2207 case CHIP_RV710: 2208 chip_name = "RV710"; 2209 rlc_chip_name = "R700"; 2210 smc_chip_name = "RV710"; 2211 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2212 break; 2213 case CHIP_RV740: 2214 chip_name = "RV730"; 2215 rlc_chip_name = "R700"; 2216 smc_chip_name = "RV740"; 2217 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2218 break; 2219 case CHIP_CEDAR: 2220 chip_name = "CEDAR"; 2221 rlc_chip_name = "CEDAR"; 2222 smc_chip_name = "CEDAR"; 2223 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2224 break; 2225 case CHIP_REDWOOD: 2226 chip_name = "REDWOOD"; 2227 rlc_chip_name = "REDWOOD"; 2228 smc_chip_name = "REDWOOD"; 2229 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2230 break; 2231 case CHIP_JUNIPER: 2232 chip_name = "JUNIPER"; 2233 rlc_chip_name = "JUNIPER"; 2234 smc_chip_name = "JUNIPER"; 2235 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2236 break; 2237 case CHIP_CYPRESS: 2238 case CHIP_HEMLOCK: 2239 chip_name = "CYPRESS"; 2240 rlc_chip_name = "CYPRESS"; 2241 smc_chip_name = "CYPRESS"; 2242 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2243 break; 2244 case CHIP_PALM: 2245 chip_name = "PALM"; 2246 rlc_chip_name = "SUMO"; 2247 break; 2248 case CHIP_SUMO: 2249 chip_name = "SUMO"; 2250 rlc_chip_name = "SUMO"; 2251 break; 2252 case CHIP_SUMO2: 2253 chip_name = "SUMO2"; 2254 rlc_chip_name = "SUMO"; 2255 break; 2256 default: BUG(); 2257 } 2258 2259 if (rdev->family >= CHIP_CEDAR) { 2260 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2261 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2262 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2263 } else if (rdev->family >= CHIP_RV770) { 2264 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2265 me_req_size = R700_PM4_UCODE_SIZE * 4; 2266 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2267 } else { 2268 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2269 me_req_size = R600_PM4_UCODE_SIZE * 12; 2270 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2271 } 2272 2273 DRM_INFO("Loading %s Microcode\n", chip_name); 2274 2275 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2276 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2277 if (err) 2278 goto out; 2279 if (rdev->pfp_fw->datasize != pfp_req_size) { 2280 printk(KERN_ERR 2281 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2282 rdev->pfp_fw->datasize, fw_name); 2283 err = -EINVAL; 2284 goto out; 2285 } 2286 2287 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2288 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2289 if (err) 2290 goto out; 2291 if (rdev->me_fw->datasize != me_req_size) { 2292 printk(KERN_ERR 2293 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2294 rdev->me_fw->datasize, fw_name); 2295 err = -EINVAL; 2296 } 2297 2298 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 2299 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2300 if (err) 2301 goto out; 2302 if (rdev->rlc_fw->datasize != rlc_req_size) { 2303 printk(KERN_ERR 2304 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2305 rdev->rlc_fw->datasize, fw_name); 2306 err = -EINVAL; 2307 } 2308 2309 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2310 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name); 2311 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2312 if (err) { 2313 printk(KERN_ERR 2314 "smc: error loading firmware \"%s\"\n", 2315 fw_name); 2316 release_firmware(rdev->smc_fw); 2317 rdev->smc_fw = NULL; 2318 } else if (rdev->smc_fw->datasize != smc_req_size) { 2319 printk(KERN_ERR 2320 "smc: Bogus length %zu in firmware \"%s\"\n", 2321 rdev->smc_fw->datasize, fw_name); 2322 err = -EINVAL; 2323 } 2324 } 2325 2326 out: 2327 if (err) { 2328 if (err != -EINVAL) 2329 printk(KERN_ERR 2330 "r600_cp: Failed to load firmware \"%s\"\n", 2331 fw_name); 2332 release_firmware(rdev->pfp_fw); 2333 rdev->pfp_fw = NULL; 2334 release_firmware(rdev->me_fw); 2335 rdev->me_fw = NULL; 2336 release_firmware(rdev->rlc_fw); 2337 rdev->rlc_fw = NULL; 2338 release_firmware(rdev->smc_fw); 2339 rdev->smc_fw = NULL; 2340 } 2341 return err; 2342 } 2343 2344 /** 2345 * r600_fini_microcode - drop the firmwares image references 2346 * 2347 * @rdev: radeon_device pointer 2348 * 2349 * Drop the pfp, me and rlc firmwares image references. 2350 * Called at driver shutdown. 2351 */ 2352 void r600_fini_microcode(struct radeon_device *rdev) 2353 { 2354 release_firmware(rdev->pfp_fw); 2355 rdev->pfp_fw = NULL; 2356 release_firmware(rdev->me_fw); 2357 rdev->me_fw = NULL; 2358 release_firmware(rdev->rlc_fw); 2359 rdev->rlc_fw = NULL; 2360 release_firmware(rdev->smc_fw); 2361 rdev->smc_fw = NULL; 2362 } 2363 2364 static int r600_cp_load_microcode(struct radeon_device *rdev) 2365 { 2366 const __be32 *fw_data; 2367 int i; 2368 2369 if (!rdev->me_fw || !rdev->pfp_fw) 2370 return -EINVAL; 2371 2372 r600_cp_stop(rdev); 2373 2374 WREG32(CP_RB_CNTL, 2375 #ifdef __BIG_ENDIAN 2376 BUF_SWAP_32BIT | 2377 #endif 2378 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2379 2380 /* Reset cp */ 2381 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2382 RREG32(GRBM_SOFT_RESET); 2383 mdelay(15); 2384 WREG32(GRBM_SOFT_RESET, 0); 2385 2386 WREG32(CP_ME_RAM_WADDR, 0); 2387 2388 fw_data = (const __be32 *)rdev->me_fw->data; 2389 WREG32(CP_ME_RAM_WADDR, 0); 2390 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2391 WREG32(CP_ME_RAM_DATA, 2392 be32_to_cpup(fw_data++)); 2393 2394 fw_data = (const __be32 *)rdev->pfp_fw->data; 2395 WREG32(CP_PFP_UCODE_ADDR, 0); 2396 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2397 WREG32(CP_PFP_UCODE_DATA, 2398 be32_to_cpup(fw_data++)); 2399 2400 WREG32(CP_PFP_UCODE_ADDR, 0); 2401 WREG32(CP_ME_RAM_WADDR, 0); 2402 WREG32(CP_ME_RAM_RADDR, 0); 2403 return 0; 2404 } 2405 2406 int r600_cp_start(struct radeon_device *rdev) 2407 { 2408 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2409 int r; 2410 uint32_t cp_me; 2411 2412 r = radeon_ring_lock(rdev, ring, 7); 2413 if (r) { 2414 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2415 return r; 2416 } 2417 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2418 radeon_ring_write(ring, 0x1); 2419 if (rdev->family >= CHIP_RV770) { 2420 radeon_ring_write(ring, 0x0); 2421 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2422 } else { 2423 radeon_ring_write(ring, 0x3); 2424 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2425 } 2426 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2427 radeon_ring_write(ring, 0); 2428 radeon_ring_write(ring, 0); 2429 radeon_ring_unlock_commit(rdev, ring); 2430 2431 cp_me = 0xff; 2432 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2433 return 0; 2434 } 2435 2436 int r600_cp_resume(struct radeon_device *rdev) 2437 { 2438 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2439 u32 tmp; 2440 u32 rb_bufsz; 2441 int r; 2442 2443 /* Reset cp */ 2444 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2445 RREG32(GRBM_SOFT_RESET); 2446 mdelay(15); 2447 WREG32(GRBM_SOFT_RESET, 0); 2448 2449 /* Set ring buffer size */ 2450 rb_bufsz = drm_order(ring->ring_size / 8); 2451 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2452 #ifdef __BIG_ENDIAN 2453 tmp |= BUF_SWAP_32BIT; 2454 #endif 2455 WREG32(CP_RB_CNTL, tmp); 2456 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2457 2458 /* Set the write pointer delay */ 2459 WREG32(CP_RB_WPTR_DELAY, 0); 2460 2461 /* Initialize the ring buffer's read and write pointers */ 2462 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2463 WREG32(CP_RB_RPTR_WR, 0); 2464 ring->wptr = 0; 2465 WREG32(CP_RB_WPTR, ring->wptr); 2466 2467 /* set the wb address whether it's enabled or not */ 2468 WREG32(CP_RB_RPTR_ADDR, 2469 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2470 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2471 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2472 2473 if (rdev->wb.enabled) 2474 WREG32(SCRATCH_UMSK, 0xff); 2475 else { 2476 tmp |= RB_NO_UPDATE; 2477 WREG32(SCRATCH_UMSK, 0); 2478 } 2479 2480 mdelay(1); 2481 WREG32(CP_RB_CNTL, tmp); 2482 2483 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2484 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2485 2486 ring->rptr = RREG32(CP_RB_RPTR); 2487 2488 r600_cp_start(rdev); 2489 ring->ready = true; 2490 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2491 if (r) { 2492 ring->ready = false; 2493 return r; 2494 } 2495 return 0; 2496 } 2497 2498 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2499 { 2500 u32 rb_bufsz; 2501 int r; 2502 2503 /* Align ring size */ 2504 rb_bufsz = drm_order(ring_size / 8); 2505 ring_size = (1 << (rb_bufsz + 1)) * 4; 2506 ring->ring_size = ring_size; 2507 ring->align_mask = 16 - 1; 2508 2509 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2510 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2511 if (r) { 2512 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2513 ring->rptr_save_reg = 0; 2514 } 2515 } 2516 } 2517 2518 void r600_cp_fini(struct radeon_device *rdev) 2519 { 2520 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2521 r600_cp_stop(rdev); 2522 radeon_ring_fini(rdev, ring); 2523 radeon_scratch_free(rdev, ring->rptr_save_reg); 2524 } 2525 2526 /* 2527 * DMA 2528 * Starting with R600, the GPU has an asynchronous 2529 * DMA engine. The programming model is very similar 2530 * to the 3D engine (ring buffer, IBs, etc.), but the 2531 * DMA controller has it's own packet format that is 2532 * different form the PM4 format used by the 3D engine. 2533 * It supports copying data, writing embedded data, 2534 * solid fills, and a number of other things. It also 2535 * has support for tiling/detiling of buffers. 2536 */ 2537 /** 2538 * r600_dma_stop - stop the async dma engine 2539 * 2540 * @rdev: radeon_device pointer 2541 * 2542 * Stop the async dma engine (r6xx-evergreen). 2543 */ 2544 void r600_dma_stop(struct radeon_device *rdev) 2545 { 2546 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2547 2548 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2549 2550 rb_cntl &= ~DMA_RB_ENABLE; 2551 WREG32(DMA_RB_CNTL, rb_cntl); 2552 2553 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2554 } 2555 2556 /** 2557 * r600_dma_resume - setup and start the async dma engine 2558 * 2559 * @rdev: radeon_device pointer 2560 * 2561 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2562 * Returns 0 for success, error for failure. 2563 */ 2564 int r600_dma_resume(struct radeon_device *rdev) 2565 { 2566 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2567 u32 rb_cntl, dma_cntl, ib_cntl; 2568 u32 rb_bufsz; 2569 int r; 2570 2571 /* Reset dma */ 2572 if (rdev->family >= CHIP_RV770) 2573 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2574 else 2575 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2576 RREG32(SRBM_SOFT_RESET); 2577 udelay(50); 2578 WREG32(SRBM_SOFT_RESET, 0); 2579 2580 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2581 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2582 2583 /* Set ring buffer size in dwords */ 2584 rb_bufsz = drm_order(ring->ring_size / 4); 2585 rb_cntl = rb_bufsz << 1; 2586 #ifdef __BIG_ENDIAN 2587 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2588 #endif 2589 WREG32(DMA_RB_CNTL, rb_cntl); 2590 2591 /* Initialize the ring buffer's read and write pointers */ 2592 WREG32(DMA_RB_RPTR, 0); 2593 WREG32(DMA_RB_WPTR, 0); 2594 2595 /* set the wb address whether it's enabled or not */ 2596 WREG32(DMA_RB_RPTR_ADDR_HI, 2597 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2598 WREG32(DMA_RB_RPTR_ADDR_LO, 2599 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2600 2601 if (rdev->wb.enabled) 2602 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2603 2604 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2605 2606 /* enable DMA IBs */ 2607 ib_cntl = DMA_IB_ENABLE; 2608 #ifdef __BIG_ENDIAN 2609 ib_cntl |= DMA_IB_SWAP_ENABLE; 2610 #endif 2611 WREG32(DMA_IB_CNTL, ib_cntl); 2612 2613 dma_cntl = RREG32(DMA_CNTL); 2614 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2615 WREG32(DMA_CNTL, dma_cntl); 2616 2617 if (rdev->family >= CHIP_RV770) 2618 WREG32(DMA_MODE, 1); 2619 2620 ring->wptr = 0; 2621 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2622 2623 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2624 2625 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2626 2627 ring->ready = true; 2628 2629 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2630 if (r) { 2631 ring->ready = false; 2632 return r; 2633 } 2634 2635 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2636 2637 return 0; 2638 } 2639 2640 /** 2641 * r600_dma_fini - tear down the async dma engine 2642 * 2643 * @rdev: radeon_device pointer 2644 * 2645 * Stop the async dma engine and free the ring (r6xx-evergreen). 2646 */ 2647 void r600_dma_fini(struct radeon_device *rdev) 2648 { 2649 r600_dma_stop(rdev); 2650 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2651 } 2652 2653 /* 2654 * UVD 2655 */ 2656 int r600_uvd_rbc_start(struct radeon_device *rdev) 2657 { 2658 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2659 uint64_t rptr_addr; 2660 uint32_t rb_bufsz, tmp; 2661 int r; 2662 2663 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET; 2664 2665 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) { 2666 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n"); 2667 return -EINVAL; 2668 } 2669 2670 /* force RBC into idle state */ 2671 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2672 2673 /* Set the write pointer delay */ 2674 WREG32(UVD_RBC_RB_WPTR_CNTL, 0); 2675 2676 /* set the wb address */ 2677 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2); 2678 2679 /* programm the 4GB memory segment for rptr and ring buffer */ 2680 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) | 2681 (0x7 << 16) | (0x1 << 31)); 2682 2683 /* Initialize the ring buffer's read and write pointers */ 2684 WREG32(UVD_RBC_RB_RPTR, 0x0); 2685 2686 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR); 2687 WREG32(UVD_RBC_RB_WPTR, ring->wptr); 2688 2689 /* set the ring address */ 2690 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); 2691 2692 /* Set ring buffer size */ 2693 rb_bufsz = drm_order(ring->ring_size); 2694 rb_bufsz = (0x1 << 8) | rb_bufsz; 2695 WREG32(UVD_RBC_RB_CNTL, rb_bufsz); 2696 2697 ring->ready = true; 2698 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring); 2699 if (r) { 2700 ring->ready = false; 2701 return r; 2702 } 2703 2704 r = radeon_ring_lock(rdev, ring, 10); 2705 if (r) { 2706 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r); 2707 return r; 2708 } 2709 2710 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 2711 radeon_ring_write(ring, tmp); 2712 radeon_ring_write(ring, 0xFFFFF); 2713 2714 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 2715 radeon_ring_write(ring, tmp); 2716 radeon_ring_write(ring, 0xFFFFF); 2717 2718 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 2719 radeon_ring_write(ring, tmp); 2720 radeon_ring_write(ring, 0xFFFFF); 2721 2722 /* Clear timeout status bits */ 2723 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); 2724 radeon_ring_write(ring, 0x8); 2725 2726 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); 2727 radeon_ring_write(ring, 3); 2728 2729 radeon_ring_unlock_commit(rdev, ring); 2730 2731 return 0; 2732 } 2733 2734 void r600_uvd_stop(struct radeon_device *rdev) 2735 { 2736 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2737 2738 /* force RBC into idle state */ 2739 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2740 2741 /* Stall UMC and register bus before resetting VCPU */ 2742 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2743 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2744 mdelay(1); 2745 2746 /* put VCPU into reset */ 2747 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); 2748 mdelay(5); 2749 2750 /* disable VCPU clock */ 2751 WREG32(UVD_VCPU_CNTL, 0x0); 2752 2753 /* Unstall UMC and register bus */ 2754 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 2755 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); 2756 2757 ring->ready = false; 2758 } 2759 2760 int r600_uvd_init(struct radeon_device *rdev) 2761 { 2762 int i, j, r; 2763 /* disable byte swapping */ 2764 u32 lmi_swap_cntl = 0; 2765 u32 mp_swap_cntl = 0; 2766 2767 /* raise clocks while booting up the VCPU */ 2768 radeon_set_uvd_clocks(rdev, 53300, 40000); 2769 2770 /* disable clock gating */ 2771 WREG32(UVD_CGC_GATE, 0); 2772 2773 /* disable interupt */ 2774 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); 2775 2776 /* Stall UMC and register bus before resetting VCPU */ 2777 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2778 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2779 mdelay(1); 2780 2781 /* put LMI, VCPU, RBC etc... into reset */ 2782 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | 2783 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET | 2784 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET); 2785 mdelay(5); 2786 2787 /* take UVD block out of reset */ 2788 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); 2789 mdelay(5); 2790 2791 /* initialize UVD memory controller */ 2792 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 2793 (1 << 21) | (1 << 9) | (1 << 20)); 2794 2795 #ifdef __BIG_ENDIAN 2796 /* swap (8 in 32) RB and IB */ 2797 lmi_swap_cntl = 0xa; 2798 mp_swap_cntl = 0; 2799 #endif 2800 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); 2801 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); 2802 2803 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); 2804 WREG32(UVD_MPC_SET_MUXA1, 0x0); 2805 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); 2806 WREG32(UVD_MPC_SET_MUXB1, 0x0); 2807 WREG32(UVD_MPC_SET_ALU, 0); 2808 WREG32(UVD_MPC_SET_MUX, 0x88); 2809 2810 /* take all subblocks out of reset, except VCPU */ 2811 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); 2812 mdelay(5); 2813 2814 /* enable VCPU clock */ 2815 WREG32(UVD_VCPU_CNTL, 1 << 9); 2816 2817 /* enable UMC */ 2818 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 2819 2820 /* boot up the VCPU */ 2821 WREG32(UVD_SOFT_RESET, 0); 2822 mdelay(10); 2823 2824 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); 2825 2826 for (i = 0; i < 10; ++i) { 2827 uint32_t status; 2828 for (j = 0; j < 100; ++j) { 2829 status = RREG32(UVD_STATUS); 2830 if (status & 2) 2831 break; 2832 mdelay(10); 2833 } 2834 r = 0; 2835 if (status & 2) 2836 break; 2837 2838 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 2839 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); 2840 mdelay(10); 2841 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); 2842 mdelay(10); 2843 r = -1; 2844 } 2845 2846 if (r) { 2847 DRM_ERROR("UVD not responding, giving up!!!\n"); 2848 radeon_set_uvd_clocks(rdev, 0, 0); 2849 return r; 2850 } 2851 2852 /* enable interupt */ 2853 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); 2854 2855 r = r600_uvd_rbc_start(rdev); 2856 if (!r) 2857 DRM_INFO("UVD initialized successfully.\n"); 2858 2859 /* lower clocks again */ 2860 radeon_set_uvd_clocks(rdev, 0, 0); 2861 2862 return r; 2863 } 2864 2865 /* 2866 * GPU scratch registers helpers function. 2867 */ 2868 void r600_scratch_init(struct radeon_device *rdev) 2869 { 2870 int i; 2871 2872 rdev->scratch.num_reg = 7; 2873 rdev->scratch.reg_base = SCRATCH_REG0; 2874 for (i = 0; i < rdev->scratch.num_reg; i++) { 2875 rdev->scratch.free[i] = true; 2876 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2877 } 2878 } 2879 2880 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2881 { 2882 uint32_t scratch; 2883 uint32_t tmp = 0; 2884 unsigned i; 2885 int r; 2886 2887 r = radeon_scratch_get(rdev, &scratch); 2888 if (r) { 2889 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2890 return r; 2891 } 2892 WREG32(scratch, 0xCAFEDEAD); 2893 r = radeon_ring_lock(rdev, ring, 3); 2894 if (r) { 2895 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2896 radeon_scratch_free(rdev, scratch); 2897 return r; 2898 } 2899 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2900 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2901 radeon_ring_write(ring, 0xDEADBEEF); 2902 radeon_ring_unlock_commit(rdev, ring); 2903 for (i = 0; i < rdev->usec_timeout; i++) { 2904 tmp = RREG32(scratch); 2905 if (tmp == 0xDEADBEEF) 2906 break; 2907 DRM_UDELAY(1); 2908 } 2909 if (i < rdev->usec_timeout) { 2910 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2911 } else { 2912 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2913 ring->idx, scratch, tmp); 2914 r = -EINVAL; 2915 } 2916 radeon_scratch_free(rdev, scratch); 2917 return r; 2918 } 2919 2920 /** 2921 * r600_dma_ring_test - simple async dma engine test 2922 * 2923 * @rdev: radeon_device pointer 2924 * @ring: radeon_ring structure holding ring information 2925 * 2926 * Test the DMA engine by writing using it to write an 2927 * value to memory. (r6xx-SI). 2928 * Returns 0 for success, error for failure. 2929 */ 2930 int r600_dma_ring_test(struct radeon_device *rdev, 2931 struct radeon_ring *ring) 2932 { 2933 unsigned i; 2934 int r; 2935 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 2936 u32 tmp; 2937 2938 if (!ptr) { 2939 DRM_ERROR("invalid vram scratch pointer\n"); 2940 return -EINVAL; 2941 } 2942 2943 tmp = 0xCAFEDEAD; 2944 *ptr = tmp; 2945 2946 r = radeon_ring_lock(rdev, ring, 4); 2947 if (r) { 2948 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2949 return r; 2950 } 2951 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2952 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2953 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2954 radeon_ring_write(ring, 0xDEADBEEF); 2955 radeon_ring_unlock_commit(rdev, ring); 2956 2957 for (i = 0; i < rdev->usec_timeout; i++) { 2958 tmp = *ptr; 2959 if (tmp == 0xDEADBEEF) 2960 break; 2961 DRM_UDELAY(1); 2962 } 2963 2964 if (i < rdev->usec_timeout) { 2965 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2966 } else { 2967 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2968 ring->idx, tmp); 2969 r = -EINVAL; 2970 } 2971 return r; 2972 } 2973 2974 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2975 { 2976 uint32_t tmp = 0; 2977 unsigned i; 2978 int r; 2979 2980 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); 2981 r = radeon_ring_lock(rdev, ring, 3); 2982 if (r) { 2983 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", 2984 ring->idx, r); 2985 return r; 2986 } 2987 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 2988 radeon_ring_write(ring, 0xDEADBEEF); 2989 radeon_ring_unlock_commit(rdev, ring); 2990 for (i = 0; i < rdev->usec_timeout; i++) { 2991 tmp = RREG32(UVD_CONTEXT_ID); 2992 if (tmp == 0xDEADBEEF) 2993 break; 2994 DRM_UDELAY(1); 2995 } 2996 2997 if (i < rdev->usec_timeout) { 2998 DRM_INFO("ring test on %d succeeded in %d usecs\n", 2999 ring->idx, i); 3000 } else { 3001 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 3002 ring->idx, tmp); 3003 r = -EINVAL; 3004 } 3005 return r; 3006 } 3007 3008 /* 3009 * CP fences/semaphores 3010 */ 3011 3012 void r600_fence_ring_emit(struct radeon_device *rdev, 3013 struct radeon_fence *fence) 3014 { 3015 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3016 3017 if (rdev->wb.use_event) { 3018 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3019 /* flush read cache over gart */ 3020 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3021 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 3022 PACKET3_VC_ACTION_ENA | 3023 PACKET3_SH_ACTION_ENA); 3024 radeon_ring_write(ring, 0xFFFFFFFF); 3025 radeon_ring_write(ring, 0); 3026 radeon_ring_write(ring, 10); /* poll interval */ 3027 /* EVENT_WRITE_EOP - flush caches, send int */ 3028 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3029 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 3030 radeon_ring_write(ring, addr & 0xffffffff); 3031 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 3032 radeon_ring_write(ring, fence->seq); 3033 radeon_ring_write(ring, 0); 3034 } else { 3035 /* flush read cache over gart */ 3036 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3037 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 3038 PACKET3_VC_ACTION_ENA | 3039 PACKET3_SH_ACTION_ENA); 3040 radeon_ring_write(ring, 0xFFFFFFFF); 3041 radeon_ring_write(ring, 0); 3042 radeon_ring_write(ring, 10); /* poll interval */ 3043 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 3044 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 3045 /* wait for 3D idle clean */ 3046 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3047 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3048 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 3049 /* Emit fence sequence & fire IRQ */ 3050 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3051 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3052 radeon_ring_write(ring, fence->seq); 3053 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 3054 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 3055 radeon_ring_write(ring, RB_INT_STAT); 3056 } 3057 } 3058 3059 void r600_uvd_fence_emit(struct radeon_device *rdev, 3060 struct radeon_fence *fence) 3061 { 3062 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3063 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 3064 3065 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 3066 radeon_ring_write(ring, fence->seq); 3067 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3068 radeon_ring_write(ring, addr & 0xffffffff); 3069 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3070 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3071 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3072 radeon_ring_write(ring, 0); 3073 3074 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3075 radeon_ring_write(ring, 0); 3076 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3077 radeon_ring_write(ring, 0); 3078 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3079 radeon_ring_write(ring, 2); 3080 return; 3081 } 3082 3083 void r600_semaphore_ring_emit(struct radeon_device *rdev, 3084 struct radeon_ring *ring, 3085 struct radeon_semaphore *semaphore, 3086 bool emit_wait) 3087 { 3088 uint64_t addr = semaphore->gpu_addr; 3089 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3090 3091 if (rdev->family < CHIP_CAYMAN) 3092 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 3093 3094 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3095 radeon_ring_write(ring, addr & 0xffffffff); 3096 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 3097 } 3098 3099 /* 3100 * DMA fences/semaphores 3101 */ 3102 3103 /** 3104 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 3105 * 3106 * @rdev: radeon_device pointer 3107 * @fence: radeon fence object 3108 * 3109 * Add a DMA fence packet to the ring to write 3110 * the fence seq number and DMA trap packet to generate 3111 * an interrupt if needed (r6xx-r7xx). 3112 */ 3113 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 3114 struct radeon_fence *fence) 3115 { 3116 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3117 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3118 3119 /* write the fence */ 3120 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 3121 radeon_ring_write(ring, addr & 0xfffffffc); 3122 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 3123 radeon_ring_write(ring, lower_32_bits(fence->seq)); 3124 /* generate an interrupt */ 3125 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 3126 } 3127 3128 /** 3129 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 3130 * 3131 * @rdev: radeon_device pointer 3132 * @ring: radeon_ring structure holding ring information 3133 * @semaphore: radeon semaphore object 3134 * @emit_wait: wait or signal semaphore 3135 * 3136 * Add a DMA semaphore packet to the ring wait on or signal 3137 * other rings (r6xx-SI). 3138 */ 3139 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 3140 struct radeon_ring *ring, 3141 struct radeon_semaphore *semaphore, 3142 bool emit_wait) 3143 { 3144 u64 addr = semaphore->gpu_addr; 3145 u32 s = emit_wait ? 0 : 1; 3146 3147 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 3148 radeon_ring_write(ring, addr & 0xfffffffc); 3149 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3150 } 3151 3152 void r600_uvd_semaphore_emit(struct radeon_device *rdev, 3153 struct radeon_ring *ring, 3154 struct radeon_semaphore *semaphore, 3155 bool emit_wait) 3156 { 3157 uint64_t addr = semaphore->gpu_addr; 3158 3159 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); 3160 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); 3161 3162 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); 3163 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); 3164 3165 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); 3166 radeon_ring_write(ring, emit_wait ? 1 : 0); 3167 } 3168 3169 int r600_copy_blit(struct radeon_device *rdev, 3170 uint64_t src_offset, 3171 uint64_t dst_offset, 3172 unsigned num_gpu_pages, 3173 struct radeon_fence **fence) 3174 { 3175 struct radeon_semaphore *sem = NULL; 3176 struct radeon_sa_bo *vb = NULL; 3177 int r; 3178 3179 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 3180 if (r) { 3181 return r; 3182 } 3183 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 3184 r600_blit_done_copy(rdev, fence, vb, sem); 3185 return 0; 3186 } 3187 3188 /** 3189 * r600_copy_cpdma - copy pages using the CP DMA engine 3190 * 3191 * @rdev: radeon_device pointer 3192 * @src_offset: src GPU address 3193 * @dst_offset: dst GPU address 3194 * @num_gpu_pages: number of GPU pages to xfer 3195 * @fence: radeon fence object 3196 * 3197 * Copy GPU paging using the CP DMA engine (r6xx+). 3198 * Used by the radeon ttm implementation to move pages if 3199 * registered as the asic copy callback. 3200 */ 3201 int r600_copy_cpdma(struct radeon_device *rdev, 3202 uint64_t src_offset, uint64_t dst_offset, 3203 unsigned num_gpu_pages, 3204 struct radeon_fence **fence) 3205 { 3206 struct radeon_semaphore *sem = NULL; 3207 int ring_index = rdev->asic->copy.blit_ring_index; 3208 struct radeon_ring *ring = &rdev->ring[ring_index]; 3209 u32 size_in_bytes, cur_size_in_bytes, tmp; 3210 int i, num_loops; 3211 int r = 0; 3212 3213 r = radeon_semaphore_create(rdev, &sem); 3214 if (r) { 3215 DRM_ERROR("radeon: moving bo (%d).\n", r); 3216 return r; 3217 } 3218 3219 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3220 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3221 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3222 if (r) { 3223 DRM_ERROR("radeon: moving bo (%d).\n", r); 3224 radeon_semaphore_free(rdev, &sem, NULL); 3225 return r; 3226 } 3227 3228 if (radeon_fence_need_sync(*fence, ring->idx)) { 3229 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3230 ring->idx); 3231 radeon_fence_note_sync(*fence, ring->idx); 3232 } else { 3233 radeon_semaphore_free(rdev, &sem, NULL); 3234 } 3235 3236 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3237 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3238 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3239 for (i = 0; i < num_loops; i++) { 3240 cur_size_in_bytes = size_in_bytes; 3241 if (cur_size_in_bytes > 0x1fffff) 3242 cur_size_in_bytes = 0x1fffff; 3243 size_in_bytes -= cur_size_in_bytes; 3244 tmp = upper_32_bits(src_offset) & 0xff; 3245 if (size_in_bytes == 0) 3246 tmp |= PACKET3_CP_DMA_CP_SYNC; 3247 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3248 radeon_ring_write(ring, src_offset & 0xffffffff); 3249 radeon_ring_write(ring, tmp); 3250 radeon_ring_write(ring, dst_offset & 0xffffffff); 3251 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3252 radeon_ring_write(ring, cur_size_in_bytes); 3253 src_offset += cur_size_in_bytes; 3254 dst_offset += cur_size_in_bytes; 3255 } 3256 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3257 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3258 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3259 3260 r = radeon_fence_emit(rdev, fence, ring->idx); 3261 if (r) { 3262 radeon_ring_unlock_undo(rdev, ring); 3263 return r; 3264 } 3265 3266 radeon_ring_unlock_commit(rdev, ring); 3267 radeon_semaphore_free(rdev, &sem, *fence); 3268 3269 return r; 3270 } 3271 3272 /** 3273 * r600_copy_dma - copy pages using the DMA engine 3274 * 3275 * @rdev: radeon_device pointer 3276 * @src_offset: src GPU address 3277 * @dst_offset: dst GPU address 3278 * @num_gpu_pages: number of GPU pages to xfer 3279 * @fence: radeon fence object 3280 * 3281 * Copy GPU paging using the DMA engine (r6xx). 3282 * Used by the radeon ttm implementation to move pages if 3283 * registered as the asic copy callback. 3284 */ 3285 int r600_copy_dma(struct radeon_device *rdev, 3286 uint64_t src_offset, uint64_t dst_offset, 3287 unsigned num_gpu_pages, 3288 struct radeon_fence **fence) 3289 { 3290 struct radeon_semaphore *sem = NULL; 3291 int ring_index = rdev->asic->copy.dma_ring_index; 3292 struct radeon_ring *ring = &rdev->ring[ring_index]; 3293 u32 size_in_dw, cur_size_in_dw; 3294 int i, num_loops; 3295 int r = 0; 3296 3297 r = radeon_semaphore_create(rdev, &sem); 3298 if (r) { 3299 DRM_ERROR("radeon: moving bo (%d).\n", r); 3300 return r; 3301 } 3302 3303 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 3304 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 3305 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 3306 if (r) { 3307 DRM_ERROR("radeon: moving bo (%d).\n", r); 3308 radeon_semaphore_free(rdev, &sem, NULL); 3309 return r; 3310 } 3311 3312 if (radeon_fence_need_sync(*fence, ring->idx)) { 3313 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3314 ring->idx); 3315 radeon_fence_note_sync(*fence, ring->idx); 3316 } else { 3317 radeon_semaphore_free(rdev, &sem, NULL); 3318 } 3319 3320 for (i = 0; i < num_loops; i++) { 3321 cur_size_in_dw = size_in_dw; 3322 if (cur_size_in_dw > 0xFFFE) 3323 cur_size_in_dw = 0xFFFE; 3324 size_in_dw -= cur_size_in_dw; 3325 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 3326 radeon_ring_write(ring, dst_offset & 0xfffffffc); 3327 radeon_ring_write(ring, src_offset & 0xfffffffc); 3328 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 3329 (upper_32_bits(src_offset) & 0xff))); 3330 src_offset += cur_size_in_dw * 4; 3331 dst_offset += cur_size_in_dw * 4; 3332 } 3333 3334 r = radeon_fence_emit(rdev, fence, ring->idx); 3335 if (r) { 3336 radeon_ring_unlock_undo(rdev, ring); 3337 return r; 3338 } 3339 3340 radeon_ring_unlock_commit(rdev, ring); 3341 radeon_semaphore_free(rdev, &sem, *fence); 3342 3343 return r; 3344 } 3345 3346 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3347 uint32_t tiling_flags, uint32_t pitch, 3348 uint32_t offset, uint32_t obj_size) 3349 { 3350 /* FIXME: implement */ 3351 return 0; 3352 } 3353 3354 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3355 { 3356 /* FIXME: implement */ 3357 } 3358 3359 static int r600_startup(struct radeon_device *rdev) 3360 { 3361 struct radeon_ring *ring; 3362 int r; 3363 3364 /* enable pcie gen2 link */ 3365 r600_pcie_gen2_enable(rdev); 3366 3367 r600_mc_program(rdev); 3368 3369 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3370 r = r600_init_microcode(rdev); 3371 if (r) { 3372 DRM_ERROR("Failed to load firmware!\n"); 3373 return r; 3374 } 3375 } 3376 3377 r = r600_vram_scratch_init(rdev); 3378 if (r) 3379 return r; 3380 3381 if (rdev->flags & RADEON_IS_AGP) { 3382 r600_agp_enable(rdev); 3383 } else { 3384 r = r600_pcie_gart_enable(rdev); 3385 if (r) 3386 return r; 3387 } 3388 r600_gpu_init(rdev); 3389 r = r600_blit_init(rdev); 3390 if (r) { 3391 r600_blit_fini(rdev); 3392 rdev->asic->copy.copy = NULL; 3393 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3394 } 3395 3396 /* allocate wb buffer */ 3397 r = radeon_wb_init(rdev); 3398 if (r) 3399 return r; 3400 3401 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3402 if (r) { 3403 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3404 return r; 3405 } 3406 3407 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 3408 if (r) { 3409 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 3410 return r; 3411 } 3412 3413 /* Enable IRQ */ 3414 if (!rdev->irq.installed) { 3415 r = radeon_irq_kms_init(rdev); 3416 if (r) 3417 return r; 3418 } 3419 3420 r = r600_irq_init(rdev); 3421 if (r) { 3422 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3423 radeon_irq_kms_fini(rdev); 3424 return r; 3425 } 3426 r600_irq_set(rdev); 3427 3428 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3429 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3430 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3431 0, 0xfffff, RADEON_CP_PACKET2); 3432 if (r) 3433 return r; 3434 3435 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3436 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3437 DMA_RB_RPTR, DMA_RB_WPTR, 3438 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3439 if (r) 3440 return r; 3441 3442 r = r600_cp_load_microcode(rdev); 3443 if (r) 3444 return r; 3445 r = r600_cp_resume(rdev); 3446 if (r) 3447 return r; 3448 3449 r = r600_dma_resume(rdev); 3450 if (r) 3451 return r; 3452 3453 r = radeon_ib_pool_init(rdev); 3454 if (r) { 3455 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3456 return r; 3457 } 3458 3459 r = r600_audio_init(rdev); 3460 if (r) { 3461 DRM_ERROR("radeon: audio init failed\n"); 3462 return r; 3463 } 3464 3465 return 0; 3466 } 3467 3468 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3469 { 3470 uint32_t temp; 3471 3472 temp = RREG32(CONFIG_CNTL); 3473 if (state == false) { 3474 temp &= ~(1<<0); 3475 temp |= (1<<1); 3476 } else { 3477 temp &= ~(1<<1); 3478 } 3479 WREG32(CONFIG_CNTL, temp); 3480 } 3481 3482 int r600_resume(struct radeon_device *rdev) 3483 { 3484 int r; 3485 3486 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3487 * posting will perform necessary task to bring back GPU into good 3488 * shape. 3489 */ 3490 /* post card */ 3491 atom_asic_init(rdev->mode_info.atom_context); 3492 3493 rdev->accel_working = true; 3494 r = r600_startup(rdev); 3495 if (r) { 3496 DRM_ERROR("r600 startup failed on resume\n"); 3497 rdev->accel_working = false; 3498 return r; 3499 } 3500 3501 return r; 3502 } 3503 3504 int r600_suspend(struct radeon_device *rdev) 3505 { 3506 r600_audio_fini(rdev); 3507 r600_cp_stop(rdev); 3508 r600_dma_stop(rdev); 3509 r600_irq_suspend(rdev); 3510 radeon_wb_disable(rdev); 3511 r600_pcie_gart_disable(rdev); 3512 3513 return 0; 3514 } 3515 3516 /* Plan is to move initialization in that function and use 3517 * helper function so that radeon_device_init pretty much 3518 * do nothing more than calling asic specific function. This 3519 * should also allow to remove a bunch of callback function 3520 * like vram_info. 3521 */ 3522 int r600_init(struct radeon_device *rdev) 3523 { 3524 int r; 3525 3526 if (r600_debugfs_mc_info_init(rdev)) { 3527 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3528 } 3529 /* Read BIOS */ 3530 if (!radeon_get_bios(rdev)) { 3531 if (ASIC_IS_AVIVO(rdev)) 3532 return -EINVAL; 3533 } 3534 /* Must be an ATOMBIOS */ 3535 if (!rdev->is_atom_bios) { 3536 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3537 return -EINVAL; 3538 } 3539 r = radeon_atombios_init(rdev); 3540 if (r) 3541 return r; 3542 /* Post card if necessary */ 3543 if (!radeon_card_posted(rdev)) { 3544 if (!rdev->bios) { 3545 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3546 return -EINVAL; 3547 } 3548 DRM_INFO("GPU not posted. posting now...\n"); 3549 atom_asic_init(rdev->mode_info.atom_context); 3550 } 3551 /* Initialize scratch registers */ 3552 r600_scratch_init(rdev); 3553 /* Initialize surface registers */ 3554 radeon_surface_init(rdev); 3555 /* Initialize clocks */ 3556 radeon_get_clock_info(rdev->ddev); 3557 /* Fence driver */ 3558 r = radeon_fence_driver_init(rdev); 3559 if (r) 3560 return r; 3561 if (rdev->flags & RADEON_IS_AGP) { 3562 r = radeon_agp_init(rdev); 3563 if (r) 3564 radeon_agp_disable(rdev); 3565 } 3566 r = r600_mc_init(rdev); 3567 if (r) 3568 return r; 3569 /* Memory manager */ 3570 r = radeon_bo_init(rdev); 3571 if (r) 3572 return r; 3573 3574 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3575 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3576 3577 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 3578 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 3579 3580 rdev->ih.ring_obj = NULL; 3581 r600_ih_ring_init(rdev, 64 * 1024); 3582 3583 r = r600_pcie_gart_init(rdev); 3584 if (r) 3585 return r; 3586 3587 rdev->accel_working = true; 3588 r = r600_startup(rdev); 3589 if (r) { 3590 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3591 r600_cp_fini(rdev); 3592 r600_dma_fini(rdev); 3593 r600_irq_fini(rdev); 3594 radeon_wb_fini(rdev); 3595 radeon_ib_pool_fini(rdev); 3596 radeon_irq_kms_fini(rdev); 3597 r600_pcie_gart_fini(rdev); 3598 rdev->accel_working = false; 3599 } 3600 3601 return 0; 3602 } 3603 3604 void r600_fini(struct radeon_device *rdev) 3605 { 3606 r600_audio_fini(rdev); 3607 r600_blit_fini(rdev); 3608 r600_cp_fini(rdev); 3609 r600_dma_fini(rdev); 3610 r600_irq_fini(rdev); 3611 radeon_wb_fini(rdev); 3612 radeon_ib_pool_fini(rdev); 3613 radeon_irq_kms_fini(rdev); 3614 r600_pcie_gart_fini(rdev); 3615 r600_vram_scratch_fini(rdev); 3616 radeon_agp_fini(rdev); 3617 radeon_gem_fini(rdev); 3618 radeon_fence_driver_fini(rdev); 3619 radeon_bo_fini(rdev); 3620 radeon_atombios_fini(rdev); 3621 r600_fini_microcode(rdev); 3622 kfree(rdev->bios); 3623 rdev->bios = NULL; 3624 } 3625 3626 3627 /* 3628 * CS stuff 3629 */ 3630 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3631 { 3632 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3633 u32 next_rptr; 3634 3635 if (ring->rptr_save_reg) { 3636 next_rptr = ring->wptr + 3 + 4; 3637 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3638 radeon_ring_write(ring, ((ring->rptr_save_reg - 3639 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3640 radeon_ring_write(ring, next_rptr); 3641 } else if (rdev->wb.enabled) { 3642 next_rptr = ring->wptr + 5 + 4; 3643 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3644 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3645 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3646 radeon_ring_write(ring, next_rptr); 3647 radeon_ring_write(ring, 0); 3648 } 3649 3650 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3651 radeon_ring_write(ring, 3652 #ifdef __BIG_ENDIAN 3653 (2 << 0) | 3654 #endif 3655 (ib->gpu_addr & 0xFFFFFFFC)); 3656 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3657 radeon_ring_write(ring, ib->length_dw); 3658 } 3659 3660 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3661 { 3662 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3663 3664 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); 3665 radeon_ring_write(ring, ib->gpu_addr); 3666 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); 3667 radeon_ring_write(ring, ib->length_dw); 3668 } 3669 3670 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3671 { 3672 struct radeon_ib ib; 3673 uint32_t scratch; 3674 uint32_t tmp = 0; 3675 unsigned i; 3676 int r; 3677 3678 r = radeon_scratch_get(rdev, &scratch); 3679 if (r) { 3680 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3681 return r; 3682 } 3683 WREG32(scratch, 0xCAFEDEAD); 3684 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3685 if (r) { 3686 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3687 goto free_scratch; 3688 } 3689 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3690 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3691 ib.ptr[2] = 0xDEADBEEF; 3692 ib.length_dw = 3; 3693 r = radeon_ib_schedule(rdev, &ib, NULL); 3694 if (r) { 3695 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3696 goto free_ib; 3697 } 3698 r = radeon_fence_wait(ib.fence, false); 3699 if (r) { 3700 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3701 goto free_ib; 3702 } 3703 for (i = 0; i < rdev->usec_timeout; i++) { 3704 tmp = RREG32(scratch); 3705 if (tmp == 0xDEADBEEF) 3706 break; 3707 DRM_UDELAY(1); 3708 } 3709 if (i < rdev->usec_timeout) { 3710 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3711 } else { 3712 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3713 scratch, tmp); 3714 r = -EINVAL; 3715 } 3716 free_ib: 3717 radeon_ib_free(rdev, &ib); 3718 free_scratch: 3719 radeon_scratch_free(rdev, scratch); 3720 return r; 3721 } 3722 3723 /** 3724 * r600_dma_ib_test - test an IB on the DMA engine 3725 * 3726 * @rdev: radeon_device pointer 3727 * @ring: radeon_ring structure holding ring information 3728 * 3729 * Test a simple IB in the DMA ring (r6xx-SI). 3730 * Returns 0 on success, error on failure. 3731 */ 3732 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3733 { 3734 struct radeon_ib ib; 3735 unsigned i; 3736 int r; 3737 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 3738 u32 tmp = 0; 3739 3740 if (!ptr) { 3741 DRM_ERROR("invalid vram scratch pointer\n"); 3742 return -EINVAL; 3743 } 3744 3745 tmp = 0xCAFEDEAD; 3746 *ptr = tmp; 3747 3748 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3749 if (r) { 3750 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3751 return r; 3752 } 3753 3754 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3755 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3756 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3757 ib.ptr[3] = 0xDEADBEEF; 3758 ib.length_dw = 4; 3759 3760 r = radeon_ib_schedule(rdev, &ib, NULL); 3761 if (r) { 3762 radeon_ib_free(rdev, &ib); 3763 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3764 return r; 3765 } 3766 r = radeon_fence_wait(ib.fence, false); 3767 if (r) { 3768 radeon_ib_free(rdev, &ib); 3769 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3770 return r; 3771 } 3772 for (i = 0; i < rdev->usec_timeout; i++) { 3773 tmp = *ptr; 3774 if (tmp == 0xDEADBEEF) 3775 break; 3776 DRM_UDELAY(1); 3777 } 3778 if (i < rdev->usec_timeout) { 3779 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3780 } else { 3781 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3782 r = -EINVAL; 3783 } 3784 radeon_ib_free(rdev, &ib); 3785 return r; 3786 } 3787 3788 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3789 { 3790 struct radeon_fence *fence = NULL; 3791 int r; 3792 3793 r = radeon_set_uvd_clocks(rdev, 53300, 40000); 3794 if (r) { 3795 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 3796 return r; 3797 } 3798 3799 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); 3800 if (r) { 3801 DRM_ERROR("radeon: failed to get create msg (%d).\n", r); 3802 goto error; 3803 } 3804 3805 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); 3806 if (r) { 3807 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); 3808 goto error; 3809 } 3810 3811 r = radeon_fence_wait(fence, false); 3812 if (r) { 3813 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3814 goto error; 3815 } 3816 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 3817 error: 3818 radeon_fence_unref(&fence); 3819 radeon_set_uvd_clocks(rdev, 0, 0); 3820 return r; 3821 } 3822 3823 /** 3824 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3825 * 3826 * @rdev: radeon_device pointer 3827 * @ib: IB object to schedule 3828 * 3829 * Schedule an IB in the DMA ring (r6xx-r7xx). 3830 */ 3831 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3832 { 3833 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3834 3835 if (rdev->wb.enabled) { 3836 u32 next_rptr = ring->wptr + 4; 3837 while ((next_rptr & 7) != 5) 3838 next_rptr++; 3839 next_rptr += 3; 3840 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3841 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3842 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3843 radeon_ring_write(ring, next_rptr); 3844 } 3845 3846 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3847 * Pad as necessary with NOPs. 3848 */ 3849 while ((ring->wptr & 7) != 5) 3850 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3851 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3852 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3853 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3854 3855 } 3856 3857 /* 3858 * Interrupts 3859 * 3860 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3861 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3862 * writing to the ring and the GPU consuming, the GPU writes to the ring 3863 * and host consumes. As the host irq handler processes interrupts, it 3864 * increments the rptr. When the rptr catches up with the wptr, all the 3865 * current interrupts have been processed. 3866 */ 3867 3868 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3869 { 3870 u32 rb_bufsz; 3871 3872 /* Align ring size */ 3873 rb_bufsz = drm_order(ring_size / 4); 3874 ring_size = (1 << rb_bufsz) * 4; 3875 rdev->ih.ring_size = ring_size; 3876 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3877 rdev->ih.rptr = 0; 3878 } 3879 3880 int r600_ih_ring_alloc(struct radeon_device *rdev) 3881 { 3882 int r; 3883 void *ring_ptr; 3884 3885 /* Allocate ring buffer */ 3886 if (rdev->ih.ring_obj == NULL) { 3887 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3888 PAGE_SIZE, true, 3889 RADEON_GEM_DOMAIN_GTT, 3890 NULL, &rdev->ih.ring_obj); 3891 if (r) { 3892 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3893 return r; 3894 } 3895 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3896 if (unlikely(r != 0)) { 3897 radeon_bo_unref(&rdev->ih.ring_obj); 3898 return r; 3899 } 3900 r = radeon_bo_pin(rdev->ih.ring_obj, 3901 RADEON_GEM_DOMAIN_GTT, 3902 &rdev->ih.gpu_addr); 3903 if (r) { 3904 radeon_bo_unreserve(rdev->ih.ring_obj); 3905 radeon_bo_unref(&rdev->ih.ring_obj); 3906 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3907 return r; 3908 } 3909 ring_ptr = &rdev->ih.ring; 3910 r = radeon_bo_kmap(rdev->ih.ring_obj, 3911 ring_ptr); 3912 if (r) 3913 radeon_bo_unpin(rdev->ih.ring_obj); 3914 radeon_bo_unreserve(rdev->ih.ring_obj); 3915 if (r) { 3916 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3917 radeon_bo_unref(&rdev->ih.ring_obj); 3918 return r; 3919 } 3920 } 3921 return 0; 3922 } 3923 3924 void r600_ih_ring_fini(struct radeon_device *rdev) 3925 { 3926 int r; 3927 if (rdev->ih.ring_obj) { 3928 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3929 if (likely(r == 0)) { 3930 radeon_bo_kunmap(rdev->ih.ring_obj); 3931 radeon_bo_unpin(rdev->ih.ring_obj); 3932 radeon_bo_unreserve(rdev->ih.ring_obj); 3933 } 3934 radeon_bo_unref(&rdev->ih.ring_obj); 3935 rdev->ih.ring = NULL; 3936 rdev->ih.ring_obj = NULL; 3937 } 3938 } 3939 3940 void r600_rlc_stop(struct radeon_device *rdev) 3941 { 3942 3943 if ((rdev->family >= CHIP_RV770) && 3944 (rdev->family <= CHIP_RV740)) { 3945 /* r7xx asics need to soft reset RLC before halting */ 3946 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3947 RREG32(SRBM_SOFT_RESET); 3948 mdelay(15); 3949 WREG32(SRBM_SOFT_RESET, 0); 3950 RREG32(SRBM_SOFT_RESET); 3951 } 3952 3953 WREG32(RLC_CNTL, 0); 3954 } 3955 3956 static void r600_rlc_start(struct radeon_device *rdev) 3957 { 3958 WREG32(RLC_CNTL, RLC_ENABLE); 3959 } 3960 3961 static int r600_rlc_resume(struct radeon_device *rdev) 3962 { 3963 u32 i; 3964 const __be32 *fw_data; 3965 3966 if (!rdev->rlc_fw) 3967 return -EINVAL; 3968 3969 r600_rlc_stop(rdev); 3970 3971 WREG32(RLC_HB_CNTL, 0); 3972 3973 WREG32(RLC_HB_BASE, 0); 3974 WREG32(RLC_HB_RPTR, 0); 3975 WREG32(RLC_HB_WPTR, 0); 3976 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3977 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3978 WREG32(RLC_MC_CNTL, 0); 3979 WREG32(RLC_UCODE_CNTL, 0); 3980 3981 fw_data = (const __be32 *)rdev->rlc_fw->data; 3982 if (rdev->family >= CHIP_RV770) { 3983 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3984 WREG32(RLC_UCODE_ADDR, i); 3985 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3986 } 3987 } else { 3988 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3989 WREG32(RLC_UCODE_ADDR, i); 3990 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3991 } 3992 } 3993 WREG32(RLC_UCODE_ADDR, 0); 3994 3995 r600_rlc_start(rdev); 3996 3997 return 0; 3998 } 3999 4000 static void r600_enable_interrupts(struct radeon_device *rdev) 4001 { 4002 u32 ih_cntl = RREG32(IH_CNTL); 4003 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 4004 4005 ih_cntl |= ENABLE_INTR; 4006 ih_rb_cntl |= IH_RB_ENABLE; 4007 WREG32(IH_CNTL, ih_cntl); 4008 WREG32(IH_RB_CNTL, ih_rb_cntl); 4009 rdev->ih.enabled = true; 4010 } 4011 4012 void r600_disable_interrupts(struct radeon_device *rdev) 4013 { 4014 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 4015 u32 ih_cntl = RREG32(IH_CNTL); 4016 4017 ih_rb_cntl &= ~IH_RB_ENABLE; 4018 ih_cntl &= ~ENABLE_INTR; 4019 WREG32(IH_RB_CNTL, ih_rb_cntl); 4020 WREG32(IH_CNTL, ih_cntl); 4021 /* set rptr, wptr to 0 */ 4022 WREG32(IH_RB_RPTR, 0); 4023 WREG32(IH_RB_WPTR, 0); 4024 rdev->ih.enabled = false; 4025 rdev->ih.rptr = 0; 4026 } 4027 4028 static void r600_disable_interrupt_state(struct radeon_device *rdev) 4029 { 4030 u32 tmp; 4031 4032 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 4033 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4034 WREG32(DMA_CNTL, tmp); 4035 WREG32(GRBM_INT_CNTL, 0); 4036 WREG32(DxMODE_INT_MASK, 0); 4037 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 4038 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 4039 if (ASIC_IS_DCE3(rdev)) { 4040 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 4041 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 4042 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4043 WREG32(DC_HPD1_INT_CONTROL, tmp); 4044 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4045 WREG32(DC_HPD2_INT_CONTROL, tmp); 4046 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4047 WREG32(DC_HPD3_INT_CONTROL, tmp); 4048 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4049 WREG32(DC_HPD4_INT_CONTROL, tmp); 4050 if (ASIC_IS_DCE32(rdev)) { 4051 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4052 WREG32(DC_HPD5_INT_CONTROL, tmp); 4053 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 4054 WREG32(DC_HPD6_INT_CONTROL, tmp); 4055 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4056 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4057 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4058 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4059 } else { 4060 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4061 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4062 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4063 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4064 } 4065 } else { 4066 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4067 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 4068 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4069 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 4070 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4071 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 4072 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4073 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 4074 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4075 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4076 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4077 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4078 } 4079 } 4080 4081 int r600_irq_init(struct radeon_device *rdev) 4082 { 4083 int ret = 0; 4084 int rb_bufsz; 4085 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 4086 4087 /* allocate ring */ 4088 ret = r600_ih_ring_alloc(rdev); 4089 if (ret) 4090 return ret; 4091 4092 /* disable irqs */ 4093 r600_disable_interrupts(rdev); 4094 4095 /* init rlc */ 4096 if (rdev->family >= CHIP_CEDAR) 4097 ret = evergreen_rlc_resume(rdev); 4098 else 4099 ret = r600_rlc_resume(rdev); 4100 if (ret) { 4101 r600_ih_ring_fini(rdev); 4102 return ret; 4103 } 4104 4105 /* setup interrupt control */ 4106 /* set dummy read address to ring address */ 4107 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 4108 interrupt_cntl = RREG32(INTERRUPT_CNTL); 4109 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 4110 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 4111 */ 4112 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 4113 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 4114 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 4115 WREG32(INTERRUPT_CNTL, interrupt_cntl); 4116 4117 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 4118 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 4119 4120 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 4121 IH_WPTR_OVERFLOW_CLEAR | 4122 (rb_bufsz << 1)); 4123 4124 if (rdev->wb.enabled) 4125 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 4126 4127 /* set the writeback address whether it's enabled or not */ 4128 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 4129 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 4130 4131 WREG32(IH_RB_CNTL, ih_rb_cntl); 4132 4133 /* set rptr, wptr to 0 */ 4134 WREG32(IH_RB_RPTR, 0); 4135 WREG32(IH_RB_WPTR, 0); 4136 4137 /* Default settings for IH_CNTL (disabled at first) */ 4138 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 4139 /* RPTR_REARM only works if msi's are enabled */ 4140 if (rdev->msi_enabled) 4141 ih_cntl |= RPTR_REARM; 4142 WREG32(IH_CNTL, ih_cntl); 4143 4144 /* force the active interrupt state to all disabled */ 4145 if (rdev->family >= CHIP_CEDAR) 4146 evergreen_disable_interrupt_state(rdev); 4147 else 4148 r600_disable_interrupt_state(rdev); 4149 4150 /* at this point everything should be setup correctly to enable master */ 4151 pci_enable_busmaster(rdev->dev); 4152 4153 /* enable irqs */ 4154 r600_enable_interrupts(rdev); 4155 4156 return ret; 4157 } 4158 4159 void r600_irq_suspend(struct radeon_device *rdev) 4160 { 4161 r600_irq_disable(rdev); 4162 r600_rlc_stop(rdev); 4163 } 4164 4165 void r600_irq_fini(struct radeon_device *rdev) 4166 { 4167 r600_irq_suspend(rdev); 4168 r600_ih_ring_fini(rdev); 4169 } 4170 4171 int r600_irq_set(struct radeon_device *rdev) 4172 { 4173 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 4174 u32 mode_int = 0; 4175 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 4176 u32 grbm_int_cntl = 0; 4177 u32 hdmi0, hdmi1; 4178 u32 d1grph = 0, d2grph = 0; 4179 u32 dma_cntl; 4180 u32 thermal_int = 0; 4181 4182 if (!rdev->irq.installed) { 4183 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 4184 return -EINVAL; 4185 } 4186 /* don't enable anything if the ih is disabled */ 4187 if (!rdev->ih.enabled) { 4188 r600_disable_interrupts(rdev); 4189 /* force the active interrupt state to all disabled */ 4190 r600_disable_interrupt_state(rdev); 4191 return 0; 4192 } 4193 4194 if (ASIC_IS_DCE3(rdev)) { 4195 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4196 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4197 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4198 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 4199 if (ASIC_IS_DCE32(rdev)) { 4200 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 4201 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 4202 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4203 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4204 } else { 4205 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4206 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4207 } 4208 } else { 4209 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4210 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4211 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4212 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4213 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4214 } 4215 4216 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4217 4218 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4219 thermal_int = RREG32(CG_THERMAL_INT) & 4220 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4221 } else if (rdev->family >= CHIP_RV770) { 4222 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 4223 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4224 } 4225 if (rdev->irq.dpm_thermal) { 4226 DRM_DEBUG("dpm thermal\n"); 4227 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 4228 } 4229 4230 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 4231 DRM_DEBUG("r600_irq_set: sw int\n"); 4232 cp_int_cntl |= RB_INT_ENABLE; 4233 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 4234 } 4235 4236 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 4237 DRM_DEBUG("r600_irq_set: sw int dma\n"); 4238 dma_cntl |= TRAP_ENABLE; 4239 } 4240 4241 if (rdev->irq.crtc_vblank_int[0] || 4242 atomic_read(&rdev->irq.pflip[0])) { 4243 DRM_DEBUG("r600_irq_set: vblank 0\n"); 4244 mode_int |= D1MODE_VBLANK_INT_MASK; 4245 } 4246 if (rdev->irq.crtc_vblank_int[1] || 4247 atomic_read(&rdev->irq.pflip[1])) { 4248 DRM_DEBUG("r600_irq_set: vblank 1\n"); 4249 mode_int |= D2MODE_VBLANK_INT_MASK; 4250 } 4251 if (rdev->irq.hpd[0]) { 4252 DRM_DEBUG("r600_irq_set: hpd 1\n"); 4253 hpd1 |= DC_HPDx_INT_EN; 4254 } 4255 if (rdev->irq.hpd[1]) { 4256 DRM_DEBUG("r600_irq_set: hpd 2\n"); 4257 hpd2 |= DC_HPDx_INT_EN; 4258 } 4259 if (rdev->irq.hpd[2]) { 4260 DRM_DEBUG("r600_irq_set: hpd 3\n"); 4261 hpd3 |= DC_HPDx_INT_EN; 4262 } 4263 if (rdev->irq.hpd[3]) { 4264 DRM_DEBUG("r600_irq_set: hpd 4\n"); 4265 hpd4 |= DC_HPDx_INT_EN; 4266 } 4267 if (rdev->irq.hpd[4]) { 4268 DRM_DEBUG("r600_irq_set: hpd 5\n"); 4269 hpd5 |= DC_HPDx_INT_EN; 4270 } 4271 if (rdev->irq.hpd[5]) { 4272 DRM_DEBUG("r600_irq_set: hpd 6\n"); 4273 hpd6 |= DC_HPDx_INT_EN; 4274 } 4275 if (rdev->irq.afmt[0]) { 4276 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4277 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4278 } 4279 if (rdev->irq.afmt[1]) { 4280 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4281 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4282 } 4283 4284 WREG32(CP_INT_CNTL, cp_int_cntl); 4285 WREG32(DMA_CNTL, dma_cntl); 4286 WREG32(DxMODE_INT_MASK, mode_int); 4287 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 4288 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 4289 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 4290 if (ASIC_IS_DCE3(rdev)) { 4291 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4292 WREG32(DC_HPD2_INT_CONTROL, hpd2); 4293 WREG32(DC_HPD3_INT_CONTROL, hpd3); 4294 WREG32(DC_HPD4_INT_CONTROL, hpd4); 4295 if (ASIC_IS_DCE32(rdev)) { 4296 WREG32(DC_HPD5_INT_CONTROL, hpd5); 4297 WREG32(DC_HPD6_INT_CONTROL, hpd6); 4298 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 4299 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 4300 } else { 4301 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4302 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4303 } 4304 } else { 4305 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 4306 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 4307 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 4308 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4309 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4310 } 4311 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4312 WREG32(CG_THERMAL_INT, thermal_int); 4313 } else if (rdev->family >= CHIP_RV770) { 4314 WREG32(RV770_CG_THERMAL_INT, thermal_int); 4315 } 4316 4317 return 0; 4318 } 4319 4320 static void r600_irq_ack(struct radeon_device *rdev) 4321 { 4322 u32 tmp; 4323 4324 if (ASIC_IS_DCE3(rdev)) { 4325 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 4326 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 4327 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 4328 if (ASIC_IS_DCE32(rdev)) { 4329 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 4330 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 4331 } else { 4332 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4333 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 4334 } 4335 } else { 4336 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 4337 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 4338 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 4339 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4340 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 4341 } 4342 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 4343 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 4344 4345 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4346 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4347 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4348 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4349 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 4350 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4351 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 4352 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4353 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 4354 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4355 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 4356 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4357 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4358 if (ASIC_IS_DCE3(rdev)) { 4359 tmp = RREG32(DC_HPD1_INT_CONTROL); 4360 tmp |= DC_HPDx_INT_ACK; 4361 WREG32(DC_HPD1_INT_CONTROL, tmp); 4362 } else { 4363 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 4364 tmp |= DC_HPDx_INT_ACK; 4365 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 4366 } 4367 } 4368 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4369 if (ASIC_IS_DCE3(rdev)) { 4370 tmp = RREG32(DC_HPD2_INT_CONTROL); 4371 tmp |= DC_HPDx_INT_ACK; 4372 WREG32(DC_HPD2_INT_CONTROL, tmp); 4373 } else { 4374 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 4375 tmp |= DC_HPDx_INT_ACK; 4376 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 4377 } 4378 } 4379 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4380 if (ASIC_IS_DCE3(rdev)) { 4381 tmp = RREG32(DC_HPD3_INT_CONTROL); 4382 tmp |= DC_HPDx_INT_ACK; 4383 WREG32(DC_HPD3_INT_CONTROL, tmp); 4384 } else { 4385 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 4386 tmp |= DC_HPDx_INT_ACK; 4387 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 4388 } 4389 } 4390 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4391 tmp = RREG32(DC_HPD4_INT_CONTROL); 4392 tmp |= DC_HPDx_INT_ACK; 4393 WREG32(DC_HPD4_INT_CONTROL, tmp); 4394 } 4395 if (ASIC_IS_DCE32(rdev)) { 4396 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4397 tmp = RREG32(DC_HPD5_INT_CONTROL); 4398 tmp |= DC_HPDx_INT_ACK; 4399 WREG32(DC_HPD5_INT_CONTROL, tmp); 4400 } 4401 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4402 tmp = RREG32(DC_HPD5_INT_CONTROL); 4403 tmp |= DC_HPDx_INT_ACK; 4404 WREG32(DC_HPD6_INT_CONTROL, tmp); 4405 } 4406 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 4407 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 4408 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4409 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4410 } 4411 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4412 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4413 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4414 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4415 } 4416 } else { 4417 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4418 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4419 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4420 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4421 } 4422 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4423 if (ASIC_IS_DCE3(rdev)) { 4424 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4425 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4426 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4427 } else { 4428 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4429 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4430 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4431 } 4432 } 4433 } 4434 } 4435 4436 void r600_irq_disable(struct radeon_device *rdev) 4437 { 4438 r600_disable_interrupts(rdev); 4439 /* Wait and acknowledge irq */ 4440 mdelay(1); 4441 r600_irq_ack(rdev); 4442 r600_disable_interrupt_state(rdev); 4443 } 4444 4445 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4446 { 4447 u32 wptr, tmp; 4448 4449 if (rdev->wb.enabled) 4450 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4451 else 4452 wptr = RREG32(IH_RB_WPTR); 4453 4454 if (wptr & RB_OVERFLOW) { 4455 /* When a ring buffer overflow happen start parsing interrupt 4456 * from the last not overwritten vector (wptr + 16). Hopefully 4457 * this should allow us to catchup. 4458 */ 4459 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 4460 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 4461 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4462 tmp = RREG32(IH_RB_CNTL); 4463 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4464 WREG32(IH_RB_CNTL, tmp); 4465 } 4466 return (wptr & rdev->ih.ptr_mask); 4467 } 4468 4469 /* r600 IV Ring 4470 * Each IV ring entry is 128 bits: 4471 * [7:0] - interrupt source id 4472 * [31:8] - reserved 4473 * [59:32] - interrupt source data 4474 * [127:60] - reserved 4475 * 4476 * The basic interrupt vector entries 4477 * are decoded as follows: 4478 * src_id src_data description 4479 * 1 0 D1 Vblank 4480 * 1 1 D1 Vline 4481 * 5 0 D2 Vblank 4482 * 5 1 D2 Vline 4483 * 19 0 FP Hot plug detection A 4484 * 19 1 FP Hot plug detection B 4485 * 19 2 DAC A auto-detection 4486 * 19 3 DAC B auto-detection 4487 * 21 4 HDMI block A 4488 * 21 5 HDMI block B 4489 * 176 - CP_INT RB 4490 * 177 - CP_INT IB1 4491 * 178 - CP_INT IB2 4492 * 181 - EOP Interrupt 4493 * 233 - GUI Idle 4494 * 4495 * Note, these are based on r600 and may need to be 4496 * adjusted or added to on newer asics 4497 */ 4498 4499 irqreturn_t r600_irq_process(struct radeon_device *rdev) 4500 { 4501 u32 wptr; 4502 u32 rptr; 4503 u32 src_id, src_data; 4504 u32 ring_index; 4505 bool queue_hotplug = false; 4506 bool queue_hdmi = false; 4507 bool queue_thermal = false; 4508 4509 if (!rdev->ih.enabled || rdev->shutdown) 4510 return IRQ_NONE; 4511 4512 /* No MSIs, need a dummy read to flush PCI DMAs */ 4513 if (!rdev->msi_enabled) 4514 RREG32(IH_RB_WPTR); 4515 4516 wptr = r600_get_ih_wptr(rdev); 4517 4518 restart_ih: 4519 /* is somebody else already processing irqs? */ 4520 if (atomic_xchg(&rdev->ih.lock, 1)) 4521 return IRQ_NONE; 4522 4523 rptr = rdev->ih.rptr; 4524 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4525 4526 /* Order reading of wptr vs. reading of IH ring data */ 4527 rmb(); 4528 4529 /* display interrupts */ 4530 r600_irq_ack(rdev); 4531 4532 while (rptr != wptr) { 4533 /* wptr/rptr are in bytes! */ 4534 ring_index = rptr / 4; 4535 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4536 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4537 4538 switch (src_id) { 4539 case 1: /* D1 vblank/vline */ 4540 switch (src_data) { 4541 case 0: /* D1 vblank */ 4542 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4543 if (rdev->irq.crtc_vblank_int[0]) { 4544 drm_handle_vblank(rdev->ddev, 0); 4545 rdev->pm.vblank_sync = true; 4546 wake_up(&rdev->irq.vblank_queue); 4547 } 4548 if (atomic_read(&rdev->irq.pflip[0])) 4549 radeon_crtc_handle_flip(rdev, 0); 4550 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4551 DRM_DEBUG("IH: D1 vblank\n"); 4552 } 4553 break; 4554 case 1: /* D1 vline */ 4555 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4556 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4557 DRM_DEBUG("IH: D1 vline\n"); 4558 } 4559 break; 4560 default: 4561 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4562 break; 4563 } 4564 break; 4565 case 5: /* D2 vblank/vline */ 4566 switch (src_data) { 4567 case 0: /* D2 vblank */ 4568 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4569 if (rdev->irq.crtc_vblank_int[1]) { 4570 drm_handle_vblank(rdev->ddev, 1); 4571 rdev->pm.vblank_sync = true; 4572 wake_up(&rdev->irq.vblank_queue); 4573 } 4574 if (atomic_read(&rdev->irq.pflip[1])) 4575 radeon_crtc_handle_flip(rdev, 1); 4576 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4577 DRM_DEBUG("IH: D2 vblank\n"); 4578 } 4579 break; 4580 case 1: /* D1 vline */ 4581 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4582 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4583 DRM_DEBUG("IH: D2 vline\n"); 4584 } 4585 break; 4586 default: 4587 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4588 break; 4589 } 4590 break; 4591 case 19: /* HPD/DAC hotplug */ 4592 switch (src_data) { 4593 case 0: 4594 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4595 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4596 queue_hotplug = true; 4597 DRM_DEBUG("IH: HPD1\n"); 4598 } 4599 break; 4600 case 1: 4601 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4602 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4603 queue_hotplug = true; 4604 DRM_DEBUG("IH: HPD2\n"); 4605 } 4606 break; 4607 case 4: 4608 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4609 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4610 queue_hotplug = true; 4611 DRM_DEBUG("IH: HPD3\n"); 4612 } 4613 break; 4614 case 5: 4615 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4616 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4617 queue_hotplug = true; 4618 DRM_DEBUG("IH: HPD4\n"); 4619 } 4620 break; 4621 case 10: 4622 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4623 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4624 queue_hotplug = true; 4625 DRM_DEBUG("IH: HPD5\n"); 4626 } 4627 break; 4628 case 12: 4629 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4630 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4631 queue_hotplug = true; 4632 DRM_DEBUG("IH: HPD6\n"); 4633 } 4634 break; 4635 default: 4636 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4637 break; 4638 } 4639 break; 4640 case 21: /* hdmi */ 4641 switch (src_data) { 4642 case 4: 4643 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4644 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4645 queue_hdmi = true; 4646 DRM_DEBUG("IH: HDMI0\n"); 4647 } 4648 break; 4649 case 5: 4650 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4651 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4652 queue_hdmi = true; 4653 DRM_DEBUG("IH: HDMI1\n"); 4654 } 4655 break; 4656 default: 4657 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4658 break; 4659 } 4660 break; 4661 case 176: /* CP_INT in ring buffer */ 4662 case 177: /* CP_INT in IB1 */ 4663 case 178: /* CP_INT in IB2 */ 4664 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4665 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4666 break; 4667 case 181: /* CP EOP event */ 4668 DRM_DEBUG("IH: CP EOP\n"); 4669 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4670 break; 4671 case 224: /* DMA trap event */ 4672 DRM_DEBUG("IH: DMA trap\n"); 4673 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4674 break; 4675 case 230: /* thermal low to high */ 4676 DRM_DEBUG("IH: thermal low to high\n"); 4677 rdev->pm.dpm.thermal.high_to_low = false; 4678 queue_thermal = true; 4679 break; 4680 case 231: /* thermal high to low */ 4681 DRM_DEBUG("IH: thermal high to low\n"); 4682 rdev->pm.dpm.thermal.high_to_low = true; 4683 queue_thermal = true; 4684 break; 4685 case 233: /* GUI IDLE */ 4686 DRM_DEBUG("IH: GUI idle\n"); 4687 break; 4688 default: 4689 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4690 break; 4691 } 4692 4693 /* wptr/rptr are in bytes! */ 4694 rptr += 16; 4695 rptr &= rdev->ih.ptr_mask; 4696 } 4697 if (queue_hotplug) 4698 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 4699 if (queue_hdmi) 4700 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 4701 if (queue_thermal && rdev->pm.dpm_enabled) 4702 taskqueue_enqueue(rdev->tq, &rdev->pm.dpm.thermal.work); 4703 rdev->ih.rptr = rptr; 4704 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4705 atomic_set(&rdev->ih.lock, 0); 4706 4707 /* make sure wptr hasn't changed while processing */ 4708 wptr = r600_get_ih_wptr(rdev); 4709 if (wptr != rptr) 4710 goto restart_ih; 4711 4712 return IRQ_HANDLED; 4713 } 4714 4715 /* 4716 * Debugfs info 4717 */ 4718 #if defined(CONFIG_DEBUG_FS) 4719 4720 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4721 { 4722 struct drm_info_node *node = (struct drm_info_node *) m->private; 4723 struct drm_device *dev = node->minor->dev; 4724 struct radeon_device *rdev = dev->dev_private; 4725 4726 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4727 DREG32_SYS(m, rdev, VM_L2_STATUS); 4728 return 0; 4729 } 4730 4731 static struct drm_info_list r600_mc_info_list[] = { 4732 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4733 }; 4734 #endif 4735 4736 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4737 { 4738 #if defined(CONFIG_DEBUG_FS) 4739 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4740 #else 4741 return 0; 4742 #endif 4743 } 4744 4745 /** 4746 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4747 * rdev: radeon device structure 4748 * bo: buffer object struct which userspace is waiting for idle 4749 * 4750 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4751 * through ring buffer, this leads to corruption in rendering, see 4752 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4753 * directly perform HDP flush by writing register through MMIO. 4754 */ 4755 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4756 { 4757 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4758 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4759 * This seems to cause problems on some AGP cards. Just use the old 4760 * method for them. 4761 */ 4762 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4763 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4764 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4765 u32 tmp; 4766 4767 WREG32(HDP_DEBUG1, 0); 4768 tmp = *ptr; 4769 } else 4770 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4771 } 4772 4773 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4774 { 4775 u32 link_width_cntl, mask; 4776 4777 if (rdev->flags & RADEON_IS_IGP) 4778 return; 4779 4780 if (!(rdev->flags & RADEON_IS_PCIE)) 4781 return; 4782 4783 /* x2 cards have a special sequence */ 4784 if (ASIC_IS_X2(rdev)) 4785 return; 4786 4787 radeon_gui_idle(rdev); 4788 4789 switch (lanes) { 4790 case 0: 4791 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4792 break; 4793 case 1: 4794 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4795 break; 4796 case 2: 4797 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4798 break; 4799 case 4: 4800 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4801 break; 4802 case 8: 4803 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4804 break; 4805 case 12: 4806 /* not actually supported */ 4807 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4808 break; 4809 case 16: 4810 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4811 break; 4812 default: 4813 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4814 return; 4815 } 4816 4817 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4818 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4819 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4820 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4821 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4822 4823 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4824 } 4825 4826 int r600_get_pcie_lanes(struct radeon_device *rdev) 4827 { 4828 u32 link_width_cntl; 4829 4830 if (rdev->flags & RADEON_IS_IGP) 4831 return 0; 4832 4833 if (!(rdev->flags & RADEON_IS_PCIE)) 4834 return 0; 4835 4836 /* x2 cards have a special sequence */ 4837 if (ASIC_IS_X2(rdev)) 4838 return 0; 4839 4840 radeon_gui_idle(rdev); 4841 4842 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4843 4844 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4845 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4846 return 1; 4847 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4848 return 2; 4849 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4850 return 4; 4851 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4852 return 8; 4853 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4854 /* not actually supported */ 4855 return 12; 4856 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4857 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4858 default: 4859 return 16; 4860 } 4861 } 4862 4863 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4864 { 4865 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4866 u16 link_cntl2; 4867 u32 mask; 4868 int ret; 4869 4870 if (radeon_pcie_gen2 == 0) 4871 return; 4872 4873 if (rdev->flags & RADEON_IS_IGP) 4874 return; 4875 4876 if (!(rdev->flags & RADEON_IS_PCIE)) 4877 return; 4878 4879 /* x2 cards have a special sequence */ 4880 if (ASIC_IS_X2(rdev)) 4881 return; 4882 4883 /* only RV6xx+ chips are supported */ 4884 if (rdev->family <= CHIP_R600) 4885 return; 4886 4887 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4888 if (ret != 0) 4889 return; 4890 4891 if (!(mask & DRM_PCIE_SPEED_50)) 4892 return; 4893 4894 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4895 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4896 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4897 return; 4898 } 4899 4900 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4901 4902 /* 55 nm r6xx asics */ 4903 if ((rdev->family == CHIP_RV670) || 4904 (rdev->family == CHIP_RV620) || 4905 (rdev->family == CHIP_RV635)) { 4906 /* advertise upconfig capability */ 4907 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4908 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4909 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4910 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4911 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4912 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4913 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4914 LC_RECONFIG_ARC_MISSING_ESCAPE); 4915 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4916 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4917 } else { 4918 link_width_cntl |= LC_UPCONFIGURE_DIS; 4919 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4920 } 4921 } 4922 4923 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4924 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4925 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4926 4927 /* 55 nm r6xx asics */ 4928 if ((rdev->family == CHIP_RV670) || 4929 (rdev->family == CHIP_RV620) || 4930 (rdev->family == CHIP_RV635)) { 4931 WREG32(MM_CFGREGS_CNTL, 0x8); 4932 link_cntl2 = RREG32(0x4088); 4933 WREG32(MM_CFGREGS_CNTL, 0); 4934 /* not supported yet */ 4935 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4936 return; 4937 } 4938 4939 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4940 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4941 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4942 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4943 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4944 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4945 4946 tmp = RREG32(0x541c); 4947 WREG32(0x541c, tmp | 0x8); 4948 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4949 link_cntl2 = RREG16(0x4088); 4950 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4951 link_cntl2 |= 0x2; 4952 WREG16(0x4088, link_cntl2); 4953 WREG32(MM_CFGREGS_CNTL, 0); 4954 4955 if ((rdev->family == CHIP_RV670) || 4956 (rdev->family == CHIP_RV620) || 4957 (rdev->family == CHIP_RV635)) { 4958 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4959 training_cntl &= ~LC_POINT_7_PLUS_EN; 4960 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4961 } else { 4962 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4963 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4964 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4965 } 4966 4967 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4968 speed_cntl |= LC_GEN2_EN_STRAP; 4969 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4970 4971 } else { 4972 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4973 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4974 if (1) 4975 link_width_cntl |= LC_UPCONFIGURE_DIS; 4976 else 4977 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4978 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4979 } 4980 } 4981 4982 /** 4983 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4984 * 4985 * @rdev: radeon_device pointer 4986 * 4987 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4988 * Returns the 64 bit clock counter snapshot. 4989 */ 4990 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4991 { 4992 uint64_t clock; 4993 4994 spin_lock(&rdev->gpu_clock_mutex); 4995 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4996 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4997 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4998 spin_unlock(&rdev->gpu_clock_mutex); 4999 return clock; 5000 } 5001