1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <drm/drmP.h> 32 #include <uapi_drm/radeon_drm.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_mode.h" 36 #include "r600d.h" 37 #include "atom.h" 38 #include "avivod.h" 39 #include "radeon_ucode.h" 40 41 /* Firmware Names */ 42 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 43 MODULE_FIRMWARE("radeon/R600_me.bin"); 44 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 45 MODULE_FIRMWARE("radeon/RV610_me.bin"); 46 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 47 MODULE_FIRMWARE("radeon/RV630_me.bin"); 48 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 49 MODULE_FIRMWARE("radeon/RV620_me.bin"); 50 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV635_me.bin"); 52 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV670_me.bin"); 54 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RS780_me.bin"); 56 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV770_me.bin"); 58 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 59 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV730_me.bin"); 61 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 62 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 63 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RV710_me.bin"); 65 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 66 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 67 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 68 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 69 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 72 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 73 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 76 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 77 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 80 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 81 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 84 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 85 MODULE_FIRMWARE("radeon/PALM_me.bin"); 86 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 87 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 89 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 90 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 91 MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 92 MODULE_FIRMWARE("radeon/OLAND_me.bin"); 93 MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 94 MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 95 MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 96 97 static const u32 crtc_offsets[2] = 98 { 99 0, 100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 101 }; 102 103 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 104 105 /* r600,rv610,rv630,rv620,rv635,rv670 */ 106 static void r600_gpu_init(struct radeon_device *rdev); 107 void r600_irq_disable(struct radeon_device *rdev); 108 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 109 110 /** 111 * r600_get_xclk - get the xclk 112 * 113 * @rdev: radeon_device pointer 114 * 115 * Returns the reference clock used by the gfx engine 116 * (r6xx, IGPs, APUs). 117 */ 118 u32 r600_get_xclk(struct radeon_device *rdev) 119 { 120 return rdev->clock.spll.reference_freq; 121 } 122 123 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 124 { 125 return 0; 126 } 127 128 void dce3_program_fmt(struct drm_encoder *encoder) 129 { 130 struct drm_device *dev = encoder->dev; 131 struct radeon_device *rdev = dev->dev_private; 132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 133 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 134 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 135 int bpc = 0; 136 u32 tmp = 0; 137 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 138 139 if (connector) { 140 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 141 bpc = radeon_get_monitor_bpc(connector); 142 dither = radeon_connector->dither; 143 } 144 145 /* LVDS FMT is set up by atom */ 146 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 147 return; 148 149 /* not needed for analog */ 150 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 151 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 152 return; 153 154 if (bpc == 0) 155 return; 156 157 switch (bpc) { 158 case 6: 159 if (dither == RADEON_FMT_DITHER_ENABLE) 160 /* XXX sort out optimal dither settings */ 161 tmp |= FMT_SPATIAL_DITHER_EN; 162 else 163 tmp |= FMT_TRUNCATE_EN; 164 break; 165 case 8: 166 if (dither == RADEON_FMT_DITHER_ENABLE) 167 /* XXX sort out optimal dither settings */ 168 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 169 else 170 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 171 break; 172 case 10: 173 default: 174 /* not needed */ 175 break; 176 } 177 178 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 179 } 180 181 /* get temperature in millidegrees */ 182 int rv6xx_get_temp(struct radeon_device *rdev) 183 { 184 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 185 ASIC_T_SHIFT; 186 int actual_temp = temp & 0xff; 187 188 if (temp & 0x100) 189 actual_temp -= 256; 190 191 return actual_temp * 1000; 192 } 193 194 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 195 { 196 int i; 197 198 rdev->pm.dynpm_can_upclock = true; 199 rdev->pm.dynpm_can_downclock = true; 200 201 /* power state array is low to high, default is first */ 202 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 203 int min_power_state_index = 0; 204 205 if (rdev->pm.num_power_states > 2) 206 min_power_state_index = 1; 207 208 switch (rdev->pm.dynpm_planned_action) { 209 case DYNPM_ACTION_MINIMUM: 210 rdev->pm.requested_power_state_index = min_power_state_index; 211 rdev->pm.requested_clock_mode_index = 0; 212 rdev->pm.dynpm_can_downclock = false; 213 break; 214 case DYNPM_ACTION_DOWNCLOCK: 215 if (rdev->pm.current_power_state_index == min_power_state_index) { 216 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 217 rdev->pm.dynpm_can_downclock = false; 218 } else { 219 if (rdev->pm.active_crtc_count > 1) { 220 for (i = 0; i < rdev->pm.num_power_states; i++) { 221 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 222 continue; 223 else if (i >= rdev->pm.current_power_state_index) { 224 rdev->pm.requested_power_state_index = 225 rdev->pm.current_power_state_index; 226 break; 227 } else { 228 rdev->pm.requested_power_state_index = i; 229 break; 230 } 231 } 232 } else { 233 if (rdev->pm.current_power_state_index == 0) 234 rdev->pm.requested_power_state_index = 235 rdev->pm.num_power_states - 1; 236 else 237 rdev->pm.requested_power_state_index = 238 rdev->pm.current_power_state_index - 1; 239 } 240 } 241 rdev->pm.requested_clock_mode_index = 0; 242 /* don't use the power state if crtcs are active and no display flag is set */ 243 if ((rdev->pm.active_crtc_count > 0) && 244 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 245 clock_info[rdev->pm.requested_clock_mode_index].flags & 246 RADEON_PM_MODE_NO_DISPLAY)) { 247 rdev->pm.requested_power_state_index++; 248 } 249 break; 250 case DYNPM_ACTION_UPCLOCK: 251 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 252 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 253 rdev->pm.dynpm_can_upclock = false; 254 } else { 255 if (rdev->pm.active_crtc_count > 1) { 256 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 257 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 258 continue; 259 else if (i <= rdev->pm.current_power_state_index) { 260 rdev->pm.requested_power_state_index = 261 rdev->pm.current_power_state_index; 262 break; 263 } else { 264 rdev->pm.requested_power_state_index = i; 265 break; 266 } 267 } 268 } else 269 rdev->pm.requested_power_state_index = 270 rdev->pm.current_power_state_index + 1; 271 } 272 rdev->pm.requested_clock_mode_index = 0; 273 break; 274 case DYNPM_ACTION_DEFAULT: 275 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 276 rdev->pm.requested_clock_mode_index = 0; 277 rdev->pm.dynpm_can_upclock = false; 278 break; 279 case DYNPM_ACTION_NONE: 280 default: 281 DRM_ERROR("Requested mode for not defined action\n"); 282 return; 283 } 284 } else { 285 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 286 /* for now just select the first power state and switch between clock modes */ 287 /* power state array is low to high, default is first (0) */ 288 if (rdev->pm.active_crtc_count > 1) { 289 rdev->pm.requested_power_state_index = -1; 290 /* start at 1 as we don't want the default mode */ 291 for (i = 1; i < rdev->pm.num_power_states; i++) { 292 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 293 continue; 294 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 295 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 296 rdev->pm.requested_power_state_index = i; 297 break; 298 } 299 } 300 /* if nothing selected, grab the default state. */ 301 if (rdev->pm.requested_power_state_index == -1) 302 rdev->pm.requested_power_state_index = 0; 303 } else 304 rdev->pm.requested_power_state_index = 1; 305 306 switch (rdev->pm.dynpm_planned_action) { 307 case DYNPM_ACTION_MINIMUM: 308 rdev->pm.requested_clock_mode_index = 0; 309 rdev->pm.dynpm_can_downclock = false; 310 break; 311 case DYNPM_ACTION_DOWNCLOCK: 312 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 313 if (rdev->pm.current_clock_mode_index == 0) { 314 rdev->pm.requested_clock_mode_index = 0; 315 rdev->pm.dynpm_can_downclock = false; 316 } else 317 rdev->pm.requested_clock_mode_index = 318 rdev->pm.current_clock_mode_index - 1; 319 } else { 320 rdev->pm.requested_clock_mode_index = 0; 321 rdev->pm.dynpm_can_downclock = false; 322 } 323 /* don't use the power state if crtcs are active and no display flag is set */ 324 if ((rdev->pm.active_crtc_count > 0) && 325 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 326 clock_info[rdev->pm.requested_clock_mode_index].flags & 327 RADEON_PM_MODE_NO_DISPLAY)) { 328 rdev->pm.requested_clock_mode_index++; 329 } 330 break; 331 case DYNPM_ACTION_UPCLOCK: 332 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 333 if (rdev->pm.current_clock_mode_index == 334 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 335 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 336 rdev->pm.dynpm_can_upclock = false; 337 } else 338 rdev->pm.requested_clock_mode_index = 339 rdev->pm.current_clock_mode_index + 1; 340 } else { 341 rdev->pm.requested_clock_mode_index = 342 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 343 rdev->pm.dynpm_can_upclock = false; 344 } 345 break; 346 case DYNPM_ACTION_DEFAULT: 347 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 348 rdev->pm.requested_clock_mode_index = 0; 349 rdev->pm.dynpm_can_upclock = false; 350 break; 351 case DYNPM_ACTION_NONE: 352 default: 353 DRM_ERROR("Requested mode for not defined action\n"); 354 return; 355 } 356 } 357 358 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 359 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 360 clock_info[rdev->pm.requested_clock_mode_index].sclk, 361 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 362 clock_info[rdev->pm.requested_clock_mode_index].mclk, 363 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 364 pcie_lanes); 365 } 366 367 void rs780_pm_init_profile(struct radeon_device *rdev) 368 { 369 if (rdev->pm.num_power_states == 2) { 370 /* default */ 371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 372 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 373 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 375 /* low sh */ 376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 377 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 378 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 380 /* mid sh */ 381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 382 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 383 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 385 /* high sh */ 386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 387 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 388 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 390 /* low mh */ 391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 392 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 393 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 395 /* mid mh */ 396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 397 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 398 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 400 /* high mh */ 401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 402 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 403 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 405 } else if (rdev->pm.num_power_states == 3) { 406 /* default */ 407 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 408 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 409 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 410 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 411 /* low sh */ 412 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 413 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 414 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 415 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 416 /* mid sh */ 417 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 418 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 419 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 420 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 421 /* high sh */ 422 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 423 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 424 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 425 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 426 /* low mh */ 427 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 428 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 429 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 430 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 431 /* mid mh */ 432 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 433 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 434 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 435 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 436 /* high mh */ 437 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 438 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 439 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 440 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 441 } else { 442 /* default */ 443 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 444 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 445 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 446 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 447 /* low sh */ 448 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 449 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 450 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 451 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 452 /* mid sh */ 453 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 454 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 455 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 456 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 457 /* high sh */ 458 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 459 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 460 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 461 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 462 /* low mh */ 463 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 464 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 465 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 466 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 467 /* mid mh */ 468 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 469 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 470 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 471 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 472 /* high mh */ 473 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 474 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 475 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 476 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 477 } 478 } 479 480 void r600_pm_init_profile(struct radeon_device *rdev) 481 { 482 int idx; 483 484 if (rdev->family == CHIP_R600) { 485 /* XXX */ 486 /* default */ 487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 490 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 491 /* low sh */ 492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 496 /* mid sh */ 497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 501 /* high sh */ 502 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 506 /* low mh */ 507 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 508 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 509 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 510 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 511 /* mid mh */ 512 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 513 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 514 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 515 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 516 /* high mh */ 517 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 518 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 519 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 520 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 521 } else { 522 if (rdev->pm.num_power_states < 4) { 523 /* default */ 524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 526 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 527 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 528 /* low sh */ 529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 531 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 532 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 533 /* mid sh */ 534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 538 /* high sh */ 539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 543 /* low mh */ 544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 548 /* low mh */ 549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 553 /* high mh */ 554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 558 } else { 559 /* default */ 560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 562 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 563 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 564 /* low sh */ 565 if (rdev->flags & RADEON_IS_MOBILITY) 566 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 567 else 568 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 569 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 570 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 571 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 572 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 573 /* mid sh */ 574 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 575 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 576 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 577 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 578 /* high sh */ 579 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 580 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 581 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 582 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 583 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 584 /* low mh */ 585 if (rdev->flags & RADEON_IS_MOBILITY) 586 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 587 else 588 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 589 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 590 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 591 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 592 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 593 /* mid mh */ 594 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 595 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 596 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 597 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 598 /* high mh */ 599 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 600 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 601 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 602 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 603 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 604 } 605 } 606 } 607 608 void r600_pm_misc(struct radeon_device *rdev) 609 { 610 int req_ps_idx = rdev->pm.requested_power_state_index; 611 int req_cm_idx = rdev->pm.requested_clock_mode_index; 612 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 613 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 614 615 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 616 /* 0xff01 is a flag rather then an actual voltage */ 617 if (voltage->voltage == 0xff01) 618 return; 619 if (voltage->voltage != rdev->pm.current_vddc) { 620 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 621 rdev->pm.current_vddc = voltage->voltage; 622 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 623 } 624 } 625 } 626 627 bool r600_gui_idle(struct radeon_device *rdev) 628 { 629 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 630 return false; 631 else 632 return true; 633 } 634 635 /* hpd for digital panel detect/disconnect */ 636 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 637 { 638 bool connected = false; 639 640 if (ASIC_IS_DCE3(rdev)) { 641 switch (hpd) { 642 case RADEON_HPD_1: 643 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 644 connected = true; 645 break; 646 case RADEON_HPD_2: 647 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 648 connected = true; 649 break; 650 case RADEON_HPD_3: 651 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 652 connected = true; 653 break; 654 case RADEON_HPD_4: 655 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 656 connected = true; 657 break; 658 /* DCE 3.2 */ 659 case RADEON_HPD_5: 660 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 661 connected = true; 662 break; 663 case RADEON_HPD_6: 664 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 665 connected = true; 666 break; 667 default: 668 break; 669 } 670 } else { 671 switch (hpd) { 672 case RADEON_HPD_1: 673 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 674 connected = true; 675 break; 676 case RADEON_HPD_2: 677 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 678 connected = true; 679 break; 680 case RADEON_HPD_3: 681 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 682 connected = true; 683 break; 684 default: 685 break; 686 } 687 } 688 return connected; 689 } 690 691 void r600_hpd_set_polarity(struct radeon_device *rdev, 692 enum radeon_hpd_id hpd) 693 { 694 u32 tmp; 695 bool connected = r600_hpd_sense(rdev, hpd); 696 697 if (ASIC_IS_DCE3(rdev)) { 698 switch (hpd) { 699 case RADEON_HPD_1: 700 tmp = RREG32(DC_HPD1_INT_CONTROL); 701 if (connected) 702 tmp &= ~DC_HPDx_INT_POLARITY; 703 else 704 tmp |= DC_HPDx_INT_POLARITY; 705 WREG32(DC_HPD1_INT_CONTROL, tmp); 706 break; 707 case RADEON_HPD_2: 708 tmp = RREG32(DC_HPD2_INT_CONTROL); 709 if (connected) 710 tmp &= ~DC_HPDx_INT_POLARITY; 711 else 712 tmp |= DC_HPDx_INT_POLARITY; 713 WREG32(DC_HPD2_INT_CONTROL, tmp); 714 break; 715 case RADEON_HPD_3: 716 tmp = RREG32(DC_HPD3_INT_CONTROL); 717 if (connected) 718 tmp &= ~DC_HPDx_INT_POLARITY; 719 else 720 tmp |= DC_HPDx_INT_POLARITY; 721 WREG32(DC_HPD3_INT_CONTROL, tmp); 722 break; 723 case RADEON_HPD_4: 724 tmp = RREG32(DC_HPD4_INT_CONTROL); 725 if (connected) 726 tmp &= ~DC_HPDx_INT_POLARITY; 727 else 728 tmp |= DC_HPDx_INT_POLARITY; 729 WREG32(DC_HPD4_INT_CONTROL, tmp); 730 break; 731 case RADEON_HPD_5: 732 tmp = RREG32(DC_HPD5_INT_CONTROL); 733 if (connected) 734 tmp &= ~DC_HPDx_INT_POLARITY; 735 else 736 tmp |= DC_HPDx_INT_POLARITY; 737 WREG32(DC_HPD5_INT_CONTROL, tmp); 738 break; 739 /* DCE 3.2 */ 740 case RADEON_HPD_6: 741 tmp = RREG32(DC_HPD6_INT_CONTROL); 742 if (connected) 743 tmp &= ~DC_HPDx_INT_POLARITY; 744 else 745 tmp |= DC_HPDx_INT_POLARITY; 746 WREG32(DC_HPD6_INT_CONTROL, tmp); 747 break; 748 default: 749 break; 750 } 751 } else { 752 switch (hpd) { 753 case RADEON_HPD_1: 754 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 755 if (connected) 756 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 757 else 758 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 759 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 760 break; 761 case RADEON_HPD_2: 762 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 763 if (connected) 764 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 765 else 766 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 767 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 768 break; 769 case RADEON_HPD_3: 770 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 771 if (connected) 772 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 773 else 774 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 775 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 776 break; 777 default: 778 break; 779 } 780 } 781 } 782 783 void r600_hpd_init(struct radeon_device *rdev) 784 { 785 struct drm_device *dev = rdev->ddev; 786 struct drm_connector *connector; 787 unsigned enable = 0; 788 789 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 790 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 791 792 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 793 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 794 /* don't try to enable hpd on eDP or LVDS avoid breaking the 795 * aux dp channel on imac and help (but not completely fix) 796 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 797 */ 798 continue; 799 } 800 if (ASIC_IS_DCE3(rdev)) { 801 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 802 if (ASIC_IS_DCE32(rdev)) 803 tmp |= DC_HPDx_EN; 804 805 switch (radeon_connector->hpd.hpd) { 806 case RADEON_HPD_1: 807 WREG32(DC_HPD1_CONTROL, tmp); 808 break; 809 case RADEON_HPD_2: 810 WREG32(DC_HPD2_CONTROL, tmp); 811 break; 812 case RADEON_HPD_3: 813 WREG32(DC_HPD3_CONTROL, tmp); 814 break; 815 case RADEON_HPD_4: 816 WREG32(DC_HPD4_CONTROL, tmp); 817 break; 818 /* DCE 3.2 */ 819 case RADEON_HPD_5: 820 WREG32(DC_HPD5_CONTROL, tmp); 821 break; 822 case RADEON_HPD_6: 823 WREG32(DC_HPD6_CONTROL, tmp); 824 break; 825 default: 826 break; 827 } 828 } else { 829 switch (radeon_connector->hpd.hpd) { 830 case RADEON_HPD_1: 831 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 832 break; 833 case RADEON_HPD_2: 834 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 835 break; 836 case RADEON_HPD_3: 837 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 838 break; 839 default: 840 break; 841 } 842 } 843 enable |= 1 << radeon_connector->hpd.hpd; 844 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 845 } 846 radeon_irq_kms_enable_hpd(rdev, enable); 847 } 848 849 void r600_hpd_fini(struct radeon_device *rdev) 850 { 851 struct drm_device *dev = rdev->ddev; 852 struct drm_connector *connector; 853 unsigned disable = 0; 854 855 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 856 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 857 if (ASIC_IS_DCE3(rdev)) { 858 switch (radeon_connector->hpd.hpd) { 859 case RADEON_HPD_1: 860 WREG32(DC_HPD1_CONTROL, 0); 861 break; 862 case RADEON_HPD_2: 863 WREG32(DC_HPD2_CONTROL, 0); 864 break; 865 case RADEON_HPD_3: 866 WREG32(DC_HPD3_CONTROL, 0); 867 break; 868 case RADEON_HPD_4: 869 WREG32(DC_HPD4_CONTROL, 0); 870 break; 871 /* DCE 3.2 */ 872 case RADEON_HPD_5: 873 WREG32(DC_HPD5_CONTROL, 0); 874 break; 875 case RADEON_HPD_6: 876 WREG32(DC_HPD6_CONTROL, 0); 877 break; 878 default: 879 break; 880 } 881 } else { 882 switch (radeon_connector->hpd.hpd) { 883 case RADEON_HPD_1: 884 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 885 break; 886 case RADEON_HPD_2: 887 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 888 break; 889 case RADEON_HPD_3: 890 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 891 break; 892 default: 893 break; 894 } 895 } 896 disable |= 1 << radeon_connector->hpd.hpd; 897 } 898 radeon_irq_kms_disable_hpd(rdev, disable); 899 } 900 901 /* 902 * R600 PCIE GART 903 */ 904 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 905 { 906 unsigned i; 907 u32 tmp; 908 909 /* flush hdp cache so updates hit vram */ 910 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 911 !(rdev->flags & RADEON_IS_AGP)) { 912 volatile uint32_t *ptr = rdev->gart.ptr; 913 u32 tmp; 914 915 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 916 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 917 * This seems to cause problems on some AGP cards. Just use the old 918 * method for them. 919 */ 920 WREG32(HDP_DEBUG1, 0); 921 tmp = *ptr; 922 } else 923 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 924 925 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 926 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 927 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 928 for (i = 0; i < rdev->usec_timeout; i++) { 929 /* read MC_STATUS */ 930 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 931 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 932 if (tmp == 2) { 933 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 934 return; 935 } 936 if (tmp) { 937 return; 938 } 939 udelay(1); 940 } 941 } 942 943 int r600_pcie_gart_init(struct radeon_device *rdev) 944 { 945 int r; 946 947 if (rdev->gart.robj) { 948 WARN(1, "R600 PCIE GART already initialized\n"); 949 return 0; 950 } 951 /* Initialize common gart structure */ 952 r = radeon_gart_init(rdev); 953 if (r) 954 return r; 955 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 956 return radeon_gart_table_vram_alloc(rdev); 957 } 958 959 static int r600_pcie_gart_enable(struct radeon_device *rdev) 960 { 961 u32 tmp; 962 int r, i; 963 964 if (rdev->gart.robj == NULL) { 965 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 966 return -EINVAL; 967 } 968 r = radeon_gart_table_vram_pin(rdev); 969 if (r) 970 return r; 971 972 /* Setup L2 cache */ 973 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 974 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 975 EFFECTIVE_L2_QUEUE_SIZE(7)); 976 WREG32(VM_L2_CNTL2, 0); 977 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 978 /* Setup TLB control */ 979 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 980 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 981 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 982 ENABLE_WAIT_L2_QUERY; 983 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 984 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 985 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 986 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 987 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 988 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 989 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 990 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 991 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 992 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 993 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 994 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 995 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 996 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 997 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 998 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 999 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1000 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1001 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1002 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1003 (u32)(rdev->dummy_page.addr >> 12)); 1004 for (i = 1; i < 7; i++) 1005 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1006 1007 r600_pcie_gart_tlb_flush(rdev); 1008 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1009 (unsigned)(rdev->mc.gtt_size >> 20), 1010 (unsigned long long)rdev->gart.table_addr); 1011 rdev->gart.ready = true; 1012 return 0; 1013 } 1014 1015 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1016 { 1017 u32 tmp; 1018 int i; 1019 1020 /* Disable all tables */ 1021 for (i = 0; i < 7; i++) 1022 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1023 1024 /* Disable L2 cache */ 1025 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1026 EFFECTIVE_L2_QUEUE_SIZE(7)); 1027 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1028 /* Setup L1 TLB control */ 1029 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1030 ENABLE_WAIT_L2_QUERY; 1031 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1032 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1033 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1034 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1035 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1036 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1037 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1038 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1039 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1040 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1041 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1042 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1043 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1044 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1045 radeon_gart_table_vram_unpin(rdev); 1046 } 1047 1048 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1049 { 1050 radeon_gart_fini(rdev); 1051 r600_pcie_gart_disable(rdev); 1052 radeon_gart_table_vram_free(rdev); 1053 } 1054 1055 static void r600_agp_enable(struct radeon_device *rdev) 1056 { 1057 u32 tmp; 1058 int i; 1059 1060 /* Setup L2 cache */ 1061 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1062 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1063 EFFECTIVE_L2_QUEUE_SIZE(7)); 1064 WREG32(VM_L2_CNTL2, 0); 1065 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1066 /* Setup TLB control */ 1067 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1068 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1069 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1070 ENABLE_WAIT_L2_QUERY; 1071 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1072 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1073 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1074 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1075 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1076 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1077 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1078 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1079 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1080 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1081 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1082 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1083 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1084 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1085 for (i = 0; i < 7; i++) 1086 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1087 } 1088 1089 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1090 { 1091 unsigned i; 1092 u32 tmp; 1093 1094 for (i = 0; i < rdev->usec_timeout; i++) { 1095 /* read MC_STATUS */ 1096 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1097 if (!tmp) 1098 return 0; 1099 udelay(1); 1100 } 1101 return -1; 1102 } 1103 1104 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1105 { 1106 uint32_t r; 1107 1108 spin_lock(&rdev->mc_idx_lock); 1109 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1110 r = RREG32(R_0028FC_MC_DATA); 1111 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1112 spin_unlock(&rdev->mc_idx_lock); 1113 return r; 1114 } 1115 1116 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1117 { 1118 spin_lock(&rdev->mc_idx_lock); 1119 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1120 S_0028F8_MC_IND_WR_EN(1)); 1121 WREG32(R_0028FC_MC_DATA, v); 1122 WREG32(R_0028F8_MC_INDEX, 0x7F); 1123 spin_unlock(&rdev->mc_idx_lock); 1124 } 1125 1126 static void r600_mc_program(struct radeon_device *rdev) 1127 { 1128 struct rv515_mc_save save; 1129 u32 tmp; 1130 int i, j; 1131 1132 /* Initialize HDP */ 1133 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1134 WREG32((0x2c14 + j), 0x00000000); 1135 WREG32((0x2c18 + j), 0x00000000); 1136 WREG32((0x2c1c + j), 0x00000000); 1137 WREG32((0x2c20 + j), 0x00000000); 1138 WREG32((0x2c24 + j), 0x00000000); 1139 } 1140 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1141 1142 rv515_mc_stop(rdev, &save); 1143 if (r600_mc_wait_for_idle(rdev)) { 1144 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1145 } 1146 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1147 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1148 /* Update configuration */ 1149 if (rdev->flags & RADEON_IS_AGP) { 1150 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1151 /* VRAM before AGP */ 1152 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1153 rdev->mc.vram_start >> 12); 1154 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1155 rdev->mc.gtt_end >> 12); 1156 } else { 1157 /* VRAM after AGP */ 1158 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1159 rdev->mc.gtt_start >> 12); 1160 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1161 rdev->mc.vram_end >> 12); 1162 } 1163 } else { 1164 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1165 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1166 } 1167 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1168 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1169 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1170 WREG32(MC_VM_FB_LOCATION, tmp); 1171 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1172 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1173 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1174 if (rdev->flags & RADEON_IS_AGP) { 1175 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1176 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1177 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1178 } else { 1179 WREG32(MC_VM_AGP_BASE, 0); 1180 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1181 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1182 } 1183 if (r600_mc_wait_for_idle(rdev)) { 1184 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1185 } 1186 rv515_mc_resume(rdev, &save); 1187 /* we need to own VRAM, so turn off the VGA renderer here 1188 * to stop it overwriting our objects */ 1189 rv515_vga_render_disable(rdev); 1190 } 1191 1192 /** 1193 * r600_vram_gtt_location - try to find VRAM & GTT location 1194 * @rdev: radeon device structure holding all necessary informations 1195 * @mc: memory controller structure holding memory informations 1196 * 1197 * Function will place try to place VRAM at same place as in CPU (PCI) 1198 * address space as some GPU seems to have issue when we reprogram at 1199 * different address space. 1200 * 1201 * If there is not enough space to fit the unvisible VRAM after the 1202 * aperture then we limit the VRAM size to the aperture. 1203 * 1204 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1205 * them to be in one from GPU point of view so that we can program GPU to 1206 * catch access outside them (weird GPU policy see ??). 1207 * 1208 * This function will never fails, worst case are limiting VRAM or GTT. 1209 * 1210 * Note: GTT start, end, size should be initialized before calling this 1211 * function on AGP platform. 1212 */ 1213 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1214 { 1215 u64 size_bf, size_af; 1216 1217 if (mc->mc_vram_size > 0xE0000000) { 1218 /* leave room for at least 512M GTT */ 1219 dev_warn(rdev->dev, "limiting VRAM\n"); 1220 mc->real_vram_size = 0xE0000000; 1221 mc->mc_vram_size = 0xE0000000; 1222 } 1223 if (rdev->flags & RADEON_IS_AGP) { 1224 size_bf = mc->gtt_start; 1225 size_af = mc->mc_mask - mc->gtt_end; 1226 if (size_bf > size_af) { 1227 if (mc->mc_vram_size > size_bf) { 1228 dev_warn(rdev->dev, "limiting VRAM\n"); 1229 mc->real_vram_size = size_bf; 1230 mc->mc_vram_size = size_bf; 1231 } 1232 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1233 } else { 1234 if (mc->mc_vram_size > size_af) { 1235 dev_warn(rdev->dev, "limiting VRAM\n"); 1236 mc->real_vram_size = size_af; 1237 mc->mc_vram_size = size_af; 1238 } 1239 mc->vram_start = mc->gtt_end + 1; 1240 } 1241 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1242 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1243 mc->mc_vram_size >> 20, mc->vram_start, 1244 mc->vram_end, mc->real_vram_size >> 20); 1245 } else { 1246 u64 base = 0; 1247 if (rdev->flags & RADEON_IS_IGP) { 1248 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1249 base <<= 24; 1250 } 1251 radeon_vram_location(rdev, &rdev->mc, base); 1252 rdev->mc.gtt_base_align = 0; 1253 radeon_gtt_location(rdev, mc); 1254 } 1255 } 1256 1257 static int r600_mc_init(struct radeon_device *rdev) 1258 { 1259 u32 tmp; 1260 int chansize, numchan; 1261 uint32_t h_addr, l_addr; 1262 unsigned long long k8_addr; 1263 1264 /* Get VRAM informations */ 1265 rdev->mc.vram_is_ddr = true; 1266 tmp = RREG32(RAMCFG); 1267 if (tmp & CHANSIZE_OVERRIDE) { 1268 chansize = 16; 1269 } else if (tmp & CHANSIZE_MASK) { 1270 chansize = 64; 1271 } else { 1272 chansize = 32; 1273 } 1274 tmp = RREG32(CHMAP); 1275 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1276 case 0: 1277 default: 1278 numchan = 1; 1279 break; 1280 case 1: 1281 numchan = 2; 1282 break; 1283 case 2: 1284 numchan = 4; 1285 break; 1286 case 3: 1287 numchan = 8; 1288 break; 1289 } 1290 rdev->mc.vram_width = numchan * chansize; 1291 /* Could aper size report 0 ? */ 1292 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1293 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1294 /* Setup GPU memory space */ 1295 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1296 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1297 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1298 r600_vram_gtt_location(rdev, &rdev->mc); 1299 1300 if (rdev->flags & RADEON_IS_IGP) { 1301 rs690_pm_info(rdev); 1302 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1303 1304 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1305 /* Use K8 direct mapping for fast fb access. */ 1306 rdev->fastfb_working = false; 1307 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1308 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1309 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1310 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1311 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1312 #endif 1313 { 1314 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1315 * memory is present. 1316 */ 1317 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1318 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1319 (unsigned long long)rdev->mc.aper_base, k8_addr); 1320 rdev->mc.aper_base = (resource_size_t)k8_addr; 1321 rdev->fastfb_working = true; 1322 } 1323 } 1324 } 1325 } 1326 1327 radeon_update_bandwidth_info(rdev); 1328 return 0; 1329 } 1330 1331 int r600_vram_scratch_init(struct radeon_device *rdev) 1332 { 1333 int r; 1334 void *vram_scratch_ptr_ptr; 1335 1336 if (rdev->vram_scratch.robj == NULL) { 1337 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1338 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1339 0, NULL, &rdev->vram_scratch.robj); 1340 if (r) { 1341 return r; 1342 } 1343 } 1344 1345 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1346 if (unlikely(r != 0)) { 1347 radeon_bo_unref(&rdev->vram_scratch.robj); 1348 return r; 1349 } 1350 r = radeon_bo_pin(rdev->vram_scratch.robj, 1351 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1352 if (r) { 1353 radeon_bo_unreserve(rdev->vram_scratch.robj); 1354 radeon_bo_unref(&rdev->vram_scratch.robj); 1355 return r; 1356 } 1357 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1358 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1359 vram_scratch_ptr_ptr); 1360 if (r) 1361 radeon_bo_unpin(rdev->vram_scratch.robj); 1362 radeon_bo_unreserve(rdev->vram_scratch.robj); 1363 if (r) 1364 radeon_bo_unref(&rdev->vram_scratch.robj); 1365 1366 return r; 1367 } 1368 1369 void r600_vram_scratch_fini(struct radeon_device *rdev) 1370 { 1371 int r; 1372 1373 if (rdev->vram_scratch.robj == NULL) { 1374 return; 1375 } 1376 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1377 if (likely(r == 0)) { 1378 radeon_bo_kunmap(rdev->vram_scratch.robj); 1379 radeon_bo_unpin(rdev->vram_scratch.robj); 1380 radeon_bo_unreserve(rdev->vram_scratch.robj); 1381 } 1382 radeon_bo_unref(&rdev->vram_scratch.robj); 1383 } 1384 1385 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1386 { 1387 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1388 1389 if (hung) 1390 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1391 else 1392 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1393 1394 WREG32(R600_BIOS_3_SCRATCH, tmp); 1395 } 1396 1397 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1398 { 1399 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1400 RREG32(R_008010_GRBM_STATUS)); 1401 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1402 RREG32(R_008014_GRBM_STATUS2)); 1403 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1404 RREG32(R_000E50_SRBM_STATUS)); 1405 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1406 RREG32(CP_STALLED_STAT1)); 1407 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1408 RREG32(CP_STALLED_STAT2)); 1409 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1410 RREG32(CP_BUSY_STAT)); 1411 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1412 RREG32(CP_STAT)); 1413 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1414 RREG32(DMA_STATUS_REG)); 1415 } 1416 1417 static bool r600_is_display_hung(struct radeon_device *rdev) 1418 { 1419 u32 crtc_hung = 0; 1420 u32 crtc_status[2]; 1421 u32 i, j, tmp; 1422 1423 for (i = 0; i < rdev->num_crtc; i++) { 1424 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1425 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1426 crtc_hung |= (1 << i); 1427 } 1428 } 1429 1430 for (j = 0; j < 10; j++) { 1431 for (i = 0; i < rdev->num_crtc; i++) { 1432 if (crtc_hung & (1 << i)) { 1433 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1434 if (tmp != crtc_status[i]) 1435 crtc_hung &= ~(1 << i); 1436 } 1437 } 1438 if (crtc_hung == 0) 1439 return false; 1440 udelay(100); 1441 } 1442 1443 return true; 1444 } 1445 1446 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1447 { 1448 u32 reset_mask = 0; 1449 u32 tmp; 1450 1451 /* GRBM_STATUS */ 1452 tmp = RREG32(R_008010_GRBM_STATUS); 1453 if (rdev->family >= CHIP_RV770) { 1454 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1455 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1456 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1457 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1458 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1459 reset_mask |= RADEON_RESET_GFX; 1460 } else { 1461 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1462 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1463 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1464 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1465 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1466 reset_mask |= RADEON_RESET_GFX; 1467 } 1468 1469 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1470 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1471 reset_mask |= RADEON_RESET_CP; 1472 1473 if (G_008010_GRBM_EE_BUSY(tmp)) 1474 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1475 1476 /* DMA_STATUS_REG */ 1477 tmp = RREG32(DMA_STATUS_REG); 1478 if (!(tmp & DMA_IDLE)) 1479 reset_mask |= RADEON_RESET_DMA; 1480 1481 /* SRBM_STATUS */ 1482 tmp = RREG32(R_000E50_SRBM_STATUS); 1483 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1484 reset_mask |= RADEON_RESET_RLC; 1485 1486 if (G_000E50_IH_BUSY(tmp)) 1487 reset_mask |= RADEON_RESET_IH; 1488 1489 if (G_000E50_SEM_BUSY(tmp)) 1490 reset_mask |= RADEON_RESET_SEM; 1491 1492 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1493 reset_mask |= RADEON_RESET_GRBM; 1494 1495 if (G_000E50_VMC_BUSY(tmp)) 1496 reset_mask |= RADEON_RESET_VMC; 1497 1498 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1499 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1500 G_000E50_MCDW_BUSY(tmp)) 1501 reset_mask |= RADEON_RESET_MC; 1502 1503 if (r600_is_display_hung(rdev)) 1504 reset_mask |= RADEON_RESET_DISPLAY; 1505 1506 /* Skip MC reset as it's mostly likely not hung, just busy */ 1507 if (reset_mask & RADEON_RESET_MC) { 1508 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1509 reset_mask &= ~RADEON_RESET_MC; 1510 } 1511 1512 return reset_mask; 1513 } 1514 1515 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1516 { 1517 struct rv515_mc_save save; 1518 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1519 u32 tmp; 1520 1521 if (reset_mask == 0) 1522 return; 1523 1524 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1525 1526 r600_print_gpu_status_regs(rdev); 1527 1528 /* Disable CP parsing/prefetching */ 1529 if (rdev->family >= CHIP_RV770) 1530 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1531 else 1532 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1533 1534 /* disable the RLC */ 1535 WREG32(RLC_CNTL, 0); 1536 1537 if (reset_mask & RADEON_RESET_DMA) { 1538 /* Disable DMA */ 1539 tmp = RREG32(DMA_RB_CNTL); 1540 tmp &= ~DMA_RB_ENABLE; 1541 WREG32(DMA_RB_CNTL, tmp); 1542 } 1543 1544 mdelay(50); 1545 1546 rv515_mc_stop(rdev, &save); 1547 if (r600_mc_wait_for_idle(rdev)) { 1548 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1549 } 1550 1551 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1552 if (rdev->family >= CHIP_RV770) 1553 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1554 S_008020_SOFT_RESET_CB(1) | 1555 S_008020_SOFT_RESET_PA(1) | 1556 S_008020_SOFT_RESET_SC(1) | 1557 S_008020_SOFT_RESET_SPI(1) | 1558 S_008020_SOFT_RESET_SX(1) | 1559 S_008020_SOFT_RESET_SH(1) | 1560 S_008020_SOFT_RESET_TC(1) | 1561 S_008020_SOFT_RESET_TA(1) | 1562 S_008020_SOFT_RESET_VC(1) | 1563 S_008020_SOFT_RESET_VGT(1); 1564 else 1565 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1566 S_008020_SOFT_RESET_DB(1) | 1567 S_008020_SOFT_RESET_CB(1) | 1568 S_008020_SOFT_RESET_PA(1) | 1569 S_008020_SOFT_RESET_SC(1) | 1570 S_008020_SOFT_RESET_SMX(1) | 1571 S_008020_SOFT_RESET_SPI(1) | 1572 S_008020_SOFT_RESET_SX(1) | 1573 S_008020_SOFT_RESET_SH(1) | 1574 S_008020_SOFT_RESET_TC(1) | 1575 S_008020_SOFT_RESET_TA(1) | 1576 S_008020_SOFT_RESET_VC(1) | 1577 S_008020_SOFT_RESET_VGT(1); 1578 } 1579 1580 if (reset_mask & RADEON_RESET_CP) { 1581 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1582 S_008020_SOFT_RESET_VGT(1); 1583 1584 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1585 } 1586 1587 if (reset_mask & RADEON_RESET_DMA) { 1588 if (rdev->family >= CHIP_RV770) 1589 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1590 else 1591 srbm_soft_reset |= SOFT_RESET_DMA; 1592 } 1593 1594 if (reset_mask & RADEON_RESET_RLC) 1595 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1596 1597 if (reset_mask & RADEON_RESET_SEM) 1598 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1599 1600 if (reset_mask & RADEON_RESET_IH) 1601 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1602 1603 if (reset_mask & RADEON_RESET_GRBM) 1604 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1605 1606 if (!(rdev->flags & RADEON_IS_IGP)) { 1607 if (reset_mask & RADEON_RESET_MC) 1608 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1609 } 1610 1611 if (reset_mask & RADEON_RESET_VMC) 1612 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1613 1614 if (grbm_soft_reset) { 1615 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1616 tmp |= grbm_soft_reset; 1617 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1618 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1619 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1620 1621 udelay(50); 1622 1623 tmp &= ~grbm_soft_reset; 1624 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1625 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1626 } 1627 1628 if (srbm_soft_reset) { 1629 tmp = RREG32(SRBM_SOFT_RESET); 1630 tmp |= srbm_soft_reset; 1631 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1632 WREG32(SRBM_SOFT_RESET, tmp); 1633 tmp = RREG32(SRBM_SOFT_RESET); 1634 1635 udelay(50); 1636 1637 tmp &= ~srbm_soft_reset; 1638 WREG32(SRBM_SOFT_RESET, tmp); 1639 tmp = RREG32(SRBM_SOFT_RESET); 1640 } 1641 1642 /* Wait a little for things to settle down */ 1643 mdelay(1); 1644 1645 rv515_mc_resume(rdev, &save); 1646 udelay(50); 1647 1648 r600_print_gpu_status_regs(rdev); 1649 } 1650 1651 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1652 { 1653 struct rv515_mc_save save; 1654 u32 tmp, i; 1655 1656 dev_info(rdev->dev, "GPU pci config reset\n"); 1657 1658 /* disable dpm? */ 1659 1660 /* Disable CP parsing/prefetching */ 1661 if (rdev->family >= CHIP_RV770) 1662 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1663 else 1664 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1665 1666 /* disable the RLC */ 1667 WREG32(RLC_CNTL, 0); 1668 1669 /* Disable DMA */ 1670 tmp = RREG32(DMA_RB_CNTL); 1671 tmp &= ~DMA_RB_ENABLE; 1672 WREG32(DMA_RB_CNTL, tmp); 1673 1674 mdelay(50); 1675 1676 /* set mclk/sclk to bypass */ 1677 if (rdev->family >= CHIP_RV770) 1678 rv770_set_clk_bypass_mode(rdev); 1679 /* disable BM */ 1680 pci_disable_busmaster(rdev->pdev->dev); 1681 /* disable mem access */ 1682 rv515_mc_stop(rdev, &save); 1683 if (r600_mc_wait_for_idle(rdev)) { 1684 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1685 } 1686 1687 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1688 tmp = RREG32(BUS_CNTL); 1689 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1690 WREG32(BUS_CNTL, tmp); 1691 1692 tmp = RREG32(BIF_SCRATCH0); 1693 1694 /* reset */ 1695 radeon_pci_config_reset(rdev); 1696 mdelay(1); 1697 1698 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1699 tmp = SOFT_RESET_BIF; 1700 WREG32(SRBM_SOFT_RESET, tmp); 1701 mdelay(1); 1702 WREG32(SRBM_SOFT_RESET, 0); 1703 1704 /* wait for asic to come out of reset */ 1705 for (i = 0; i < rdev->usec_timeout; i++) { 1706 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1707 break; 1708 udelay(1); 1709 } 1710 } 1711 1712 int r600_asic_reset(struct radeon_device *rdev) 1713 { 1714 u32 reset_mask; 1715 1716 reset_mask = r600_gpu_check_soft_reset(rdev); 1717 1718 if (reset_mask) 1719 r600_set_bios_scratch_engine_hung(rdev, true); 1720 1721 /* try soft reset */ 1722 r600_gpu_soft_reset(rdev, reset_mask); 1723 1724 reset_mask = r600_gpu_check_soft_reset(rdev); 1725 1726 /* try pci config reset */ 1727 if (reset_mask && radeon_hard_reset) 1728 r600_gpu_pci_config_reset(rdev); 1729 1730 reset_mask = r600_gpu_check_soft_reset(rdev); 1731 1732 if (!reset_mask) 1733 r600_set_bios_scratch_engine_hung(rdev, false); 1734 1735 return 0; 1736 } 1737 1738 /** 1739 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1740 * 1741 * @rdev: radeon_device pointer 1742 * @ring: radeon_ring structure holding ring information 1743 * 1744 * Check if the GFX engine is locked up. 1745 * Returns true if the engine appears to be locked up, false if not. 1746 */ 1747 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1748 { 1749 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1750 1751 if (!(reset_mask & (RADEON_RESET_GFX | 1752 RADEON_RESET_COMPUTE | 1753 RADEON_RESET_CP))) { 1754 radeon_ring_lockup_update(rdev, ring); 1755 return false; 1756 } 1757 return radeon_ring_test_lockup(rdev, ring); 1758 } 1759 1760 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1761 u32 tiling_pipe_num, 1762 u32 max_rb_num, 1763 u32 total_max_rb_num, 1764 u32 disabled_rb_mask) 1765 { 1766 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1767 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1768 u32 data = 0, mask = 1 << (max_rb_num - 1); 1769 unsigned i, j; 1770 1771 /* mask out the RBs that don't exist on that asic */ 1772 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1773 /* make sure at least one RB is available */ 1774 if ((tmp & 0xff) != 0xff) 1775 disabled_rb_mask = tmp; 1776 1777 rendering_pipe_num = 1 << tiling_pipe_num; 1778 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1779 BUG_ON(rendering_pipe_num < req_rb_num); 1780 1781 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1782 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1783 1784 if (rdev->family <= CHIP_RV740) { 1785 /* r6xx/r7xx */ 1786 rb_num_width = 2; 1787 } else { 1788 /* eg+ */ 1789 rb_num_width = 4; 1790 } 1791 1792 for (i = 0; i < max_rb_num; i++) { 1793 if (!(mask & disabled_rb_mask)) { 1794 for (j = 0; j < pipe_rb_ratio; j++) { 1795 data <<= rb_num_width; 1796 data |= max_rb_num - i - 1; 1797 } 1798 if (pipe_rb_remain) { 1799 data <<= rb_num_width; 1800 data |= max_rb_num - i - 1; 1801 pipe_rb_remain--; 1802 } 1803 } 1804 mask >>= 1; 1805 } 1806 1807 return data; 1808 } 1809 1810 int r600_count_pipe_bits(uint32_t val) 1811 { 1812 return hweight32(val); 1813 } 1814 1815 static void r600_gpu_init(struct radeon_device *rdev) 1816 { 1817 u32 tiling_config; 1818 u32 ramcfg; 1819 u32 cc_gc_shader_pipe_config; 1820 u32 tmp; 1821 int i, j; 1822 u32 sq_config; 1823 u32 sq_gpr_resource_mgmt_1 = 0; 1824 u32 sq_gpr_resource_mgmt_2 = 0; 1825 u32 sq_thread_resource_mgmt = 0; 1826 u32 sq_stack_resource_mgmt_1 = 0; 1827 u32 sq_stack_resource_mgmt_2 = 0; 1828 u32 disabled_rb_mask; 1829 1830 rdev->config.r600.tiling_group_size = 256; 1831 switch (rdev->family) { 1832 case CHIP_R600: 1833 rdev->config.r600.max_pipes = 4; 1834 rdev->config.r600.max_tile_pipes = 8; 1835 rdev->config.r600.max_simds = 4; 1836 rdev->config.r600.max_backends = 4; 1837 rdev->config.r600.max_gprs = 256; 1838 rdev->config.r600.max_threads = 192; 1839 rdev->config.r600.max_stack_entries = 256; 1840 rdev->config.r600.max_hw_contexts = 8; 1841 rdev->config.r600.max_gs_threads = 16; 1842 rdev->config.r600.sx_max_export_size = 128; 1843 rdev->config.r600.sx_max_export_pos_size = 16; 1844 rdev->config.r600.sx_max_export_smx_size = 128; 1845 rdev->config.r600.sq_num_cf_insts = 2; 1846 break; 1847 case CHIP_RV630: 1848 case CHIP_RV635: 1849 rdev->config.r600.max_pipes = 2; 1850 rdev->config.r600.max_tile_pipes = 2; 1851 rdev->config.r600.max_simds = 3; 1852 rdev->config.r600.max_backends = 1; 1853 rdev->config.r600.max_gprs = 128; 1854 rdev->config.r600.max_threads = 192; 1855 rdev->config.r600.max_stack_entries = 128; 1856 rdev->config.r600.max_hw_contexts = 8; 1857 rdev->config.r600.max_gs_threads = 4; 1858 rdev->config.r600.sx_max_export_size = 128; 1859 rdev->config.r600.sx_max_export_pos_size = 16; 1860 rdev->config.r600.sx_max_export_smx_size = 128; 1861 rdev->config.r600.sq_num_cf_insts = 2; 1862 break; 1863 case CHIP_RV610: 1864 case CHIP_RV620: 1865 case CHIP_RS780: 1866 case CHIP_RS880: 1867 rdev->config.r600.max_pipes = 1; 1868 rdev->config.r600.max_tile_pipes = 1; 1869 rdev->config.r600.max_simds = 2; 1870 rdev->config.r600.max_backends = 1; 1871 rdev->config.r600.max_gprs = 128; 1872 rdev->config.r600.max_threads = 192; 1873 rdev->config.r600.max_stack_entries = 128; 1874 rdev->config.r600.max_hw_contexts = 4; 1875 rdev->config.r600.max_gs_threads = 4; 1876 rdev->config.r600.sx_max_export_size = 128; 1877 rdev->config.r600.sx_max_export_pos_size = 16; 1878 rdev->config.r600.sx_max_export_smx_size = 128; 1879 rdev->config.r600.sq_num_cf_insts = 1; 1880 break; 1881 case CHIP_RV670: 1882 rdev->config.r600.max_pipes = 4; 1883 rdev->config.r600.max_tile_pipes = 4; 1884 rdev->config.r600.max_simds = 4; 1885 rdev->config.r600.max_backends = 4; 1886 rdev->config.r600.max_gprs = 192; 1887 rdev->config.r600.max_threads = 192; 1888 rdev->config.r600.max_stack_entries = 256; 1889 rdev->config.r600.max_hw_contexts = 8; 1890 rdev->config.r600.max_gs_threads = 16; 1891 rdev->config.r600.sx_max_export_size = 128; 1892 rdev->config.r600.sx_max_export_pos_size = 16; 1893 rdev->config.r600.sx_max_export_smx_size = 128; 1894 rdev->config.r600.sq_num_cf_insts = 2; 1895 break; 1896 default: 1897 break; 1898 } 1899 1900 /* Initialize HDP */ 1901 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1902 WREG32((0x2c14 + j), 0x00000000); 1903 WREG32((0x2c18 + j), 0x00000000); 1904 WREG32((0x2c1c + j), 0x00000000); 1905 WREG32((0x2c20 + j), 0x00000000); 1906 WREG32((0x2c24 + j), 0x00000000); 1907 } 1908 1909 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1910 1911 /* Setup tiling */ 1912 tiling_config = 0; 1913 ramcfg = RREG32(RAMCFG); 1914 switch (rdev->config.r600.max_tile_pipes) { 1915 case 1: 1916 tiling_config |= PIPE_TILING(0); 1917 break; 1918 case 2: 1919 tiling_config |= PIPE_TILING(1); 1920 break; 1921 case 4: 1922 tiling_config |= PIPE_TILING(2); 1923 break; 1924 case 8: 1925 tiling_config |= PIPE_TILING(3); 1926 break; 1927 default: 1928 break; 1929 } 1930 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1931 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1932 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1933 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1934 1935 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1936 if (tmp > 3) { 1937 tiling_config |= ROW_TILING(3); 1938 tiling_config |= SAMPLE_SPLIT(3); 1939 } else { 1940 tiling_config |= ROW_TILING(tmp); 1941 tiling_config |= SAMPLE_SPLIT(tmp); 1942 } 1943 tiling_config |= BANK_SWAPS(1); 1944 1945 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1946 tmp = rdev->config.r600.max_simds - 1947 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1948 rdev->config.r600.active_simds = tmp; 1949 1950 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1951 tmp = 0; 1952 for (i = 0; i < rdev->config.r600.max_backends; i++) 1953 tmp |= (1 << i); 1954 /* if all the backends are disabled, fix it up here */ 1955 if ((disabled_rb_mask & tmp) == tmp) { 1956 for (i = 0; i < rdev->config.r600.max_backends; i++) 1957 disabled_rb_mask &= ~(1 << i); 1958 } 1959 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1960 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1961 R6XX_MAX_BACKENDS, disabled_rb_mask); 1962 tiling_config |= tmp << 16; 1963 rdev->config.r600.backend_map = tmp; 1964 1965 rdev->config.r600.tile_config = tiling_config; 1966 WREG32(GB_TILING_CONFIG, tiling_config); 1967 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1968 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1969 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1970 1971 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1972 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1973 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1974 1975 /* Setup some CP states */ 1976 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1977 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1978 1979 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1980 SYNC_WALKER | SYNC_ALIGNER)); 1981 /* Setup various GPU states */ 1982 if (rdev->family == CHIP_RV670) 1983 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1984 1985 tmp = RREG32(SX_DEBUG_1); 1986 tmp |= SMX_EVENT_RELEASE; 1987 if ((rdev->family > CHIP_R600)) 1988 tmp |= ENABLE_NEW_SMX_ADDRESS; 1989 WREG32(SX_DEBUG_1, tmp); 1990 1991 if (((rdev->family) == CHIP_R600) || 1992 ((rdev->family) == CHIP_RV630) || 1993 ((rdev->family) == CHIP_RV610) || 1994 ((rdev->family) == CHIP_RV620) || 1995 ((rdev->family) == CHIP_RS780) || 1996 ((rdev->family) == CHIP_RS880)) { 1997 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1998 } else { 1999 WREG32(DB_DEBUG, 0); 2000 } 2001 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2002 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2003 2004 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2005 WREG32(VGT_NUM_INSTANCES, 0); 2006 2007 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2008 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2009 2010 tmp = RREG32(SQ_MS_FIFO_SIZES); 2011 if (((rdev->family) == CHIP_RV610) || 2012 ((rdev->family) == CHIP_RV620) || 2013 ((rdev->family) == CHIP_RS780) || 2014 ((rdev->family) == CHIP_RS880)) { 2015 tmp = (CACHE_FIFO_SIZE(0xa) | 2016 FETCH_FIFO_HIWATER(0xa) | 2017 DONE_FIFO_HIWATER(0xe0) | 2018 ALU_UPDATE_FIFO_HIWATER(0x8)); 2019 } else if (((rdev->family) == CHIP_R600) || 2020 ((rdev->family) == CHIP_RV630)) { 2021 tmp &= ~DONE_FIFO_HIWATER(0xff); 2022 tmp |= DONE_FIFO_HIWATER(0x4); 2023 } 2024 WREG32(SQ_MS_FIFO_SIZES, tmp); 2025 2026 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2027 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2028 */ 2029 sq_config = RREG32(SQ_CONFIG); 2030 sq_config &= ~(PS_PRIO(3) | 2031 VS_PRIO(3) | 2032 GS_PRIO(3) | 2033 ES_PRIO(3)); 2034 sq_config |= (DX9_CONSTS | 2035 VC_ENABLE | 2036 PS_PRIO(0) | 2037 VS_PRIO(1) | 2038 GS_PRIO(2) | 2039 ES_PRIO(3)); 2040 2041 if ((rdev->family) == CHIP_R600) { 2042 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2043 NUM_VS_GPRS(124) | 2044 NUM_CLAUSE_TEMP_GPRS(4)); 2045 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2046 NUM_ES_GPRS(0)); 2047 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2048 NUM_VS_THREADS(48) | 2049 NUM_GS_THREADS(4) | 2050 NUM_ES_THREADS(4)); 2051 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2052 NUM_VS_STACK_ENTRIES(128)); 2053 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2054 NUM_ES_STACK_ENTRIES(0)); 2055 } else if (((rdev->family) == CHIP_RV610) || 2056 ((rdev->family) == CHIP_RV620) || 2057 ((rdev->family) == CHIP_RS780) || 2058 ((rdev->family) == CHIP_RS880)) { 2059 /* no vertex cache */ 2060 sq_config &= ~VC_ENABLE; 2061 2062 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2063 NUM_VS_GPRS(44) | 2064 NUM_CLAUSE_TEMP_GPRS(2)); 2065 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2066 NUM_ES_GPRS(17)); 2067 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2068 NUM_VS_THREADS(78) | 2069 NUM_GS_THREADS(4) | 2070 NUM_ES_THREADS(31)); 2071 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2072 NUM_VS_STACK_ENTRIES(40)); 2073 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2074 NUM_ES_STACK_ENTRIES(16)); 2075 } else if (((rdev->family) == CHIP_RV630) || 2076 ((rdev->family) == CHIP_RV635)) { 2077 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2078 NUM_VS_GPRS(44) | 2079 NUM_CLAUSE_TEMP_GPRS(2)); 2080 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2081 NUM_ES_GPRS(18)); 2082 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2083 NUM_VS_THREADS(78) | 2084 NUM_GS_THREADS(4) | 2085 NUM_ES_THREADS(31)); 2086 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2087 NUM_VS_STACK_ENTRIES(40)); 2088 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2089 NUM_ES_STACK_ENTRIES(16)); 2090 } else if ((rdev->family) == CHIP_RV670) { 2091 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2092 NUM_VS_GPRS(44) | 2093 NUM_CLAUSE_TEMP_GPRS(2)); 2094 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2095 NUM_ES_GPRS(17)); 2096 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2097 NUM_VS_THREADS(78) | 2098 NUM_GS_THREADS(4) | 2099 NUM_ES_THREADS(31)); 2100 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2101 NUM_VS_STACK_ENTRIES(64)); 2102 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2103 NUM_ES_STACK_ENTRIES(64)); 2104 } 2105 2106 WREG32(SQ_CONFIG, sq_config); 2107 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2108 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2109 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2110 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2111 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2112 2113 if (((rdev->family) == CHIP_RV610) || 2114 ((rdev->family) == CHIP_RV620) || 2115 ((rdev->family) == CHIP_RS780) || 2116 ((rdev->family) == CHIP_RS880)) { 2117 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2118 } else { 2119 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2120 } 2121 2122 /* More default values. 2D/3D driver should adjust as needed */ 2123 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2124 S1_X(0x4) | S1_Y(0xc))); 2125 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2126 S1_X(0x2) | S1_Y(0x2) | 2127 S2_X(0xa) | S2_Y(0x6) | 2128 S3_X(0x6) | S3_Y(0xa))); 2129 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2130 S1_X(0x4) | S1_Y(0xc) | 2131 S2_X(0x1) | S2_Y(0x6) | 2132 S3_X(0xa) | S3_Y(0xe))); 2133 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2134 S5_X(0x0) | S5_Y(0x0) | 2135 S6_X(0xb) | S6_Y(0x4) | 2136 S7_X(0x7) | S7_Y(0x8))); 2137 2138 WREG32(VGT_STRMOUT_EN, 0); 2139 tmp = rdev->config.r600.max_pipes * 16; 2140 switch (rdev->family) { 2141 case CHIP_RV610: 2142 case CHIP_RV620: 2143 case CHIP_RS780: 2144 case CHIP_RS880: 2145 tmp += 32; 2146 break; 2147 case CHIP_RV670: 2148 tmp += 128; 2149 break; 2150 default: 2151 break; 2152 } 2153 if (tmp > 256) { 2154 tmp = 256; 2155 } 2156 WREG32(VGT_ES_PER_GS, 128); 2157 WREG32(VGT_GS_PER_ES, tmp); 2158 WREG32(VGT_GS_PER_VS, 2); 2159 WREG32(VGT_GS_VERTEX_REUSE, 16); 2160 2161 /* more default values. 2D/3D driver should adjust as needed */ 2162 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2163 WREG32(VGT_STRMOUT_EN, 0); 2164 WREG32(SX_MISC, 0); 2165 WREG32(PA_SC_MODE_CNTL, 0); 2166 WREG32(PA_SC_AA_CONFIG, 0); 2167 WREG32(PA_SC_LINE_STIPPLE, 0); 2168 WREG32(SPI_INPUT_Z, 0); 2169 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2170 WREG32(CB_COLOR7_FRAG, 0); 2171 2172 /* Clear render buffer base addresses */ 2173 WREG32(CB_COLOR0_BASE, 0); 2174 WREG32(CB_COLOR1_BASE, 0); 2175 WREG32(CB_COLOR2_BASE, 0); 2176 WREG32(CB_COLOR3_BASE, 0); 2177 WREG32(CB_COLOR4_BASE, 0); 2178 WREG32(CB_COLOR5_BASE, 0); 2179 WREG32(CB_COLOR6_BASE, 0); 2180 WREG32(CB_COLOR7_BASE, 0); 2181 WREG32(CB_COLOR7_FRAG, 0); 2182 2183 switch (rdev->family) { 2184 case CHIP_RV610: 2185 case CHIP_RV620: 2186 case CHIP_RS780: 2187 case CHIP_RS880: 2188 tmp = TC_L2_SIZE(8); 2189 break; 2190 case CHIP_RV630: 2191 case CHIP_RV635: 2192 tmp = TC_L2_SIZE(4); 2193 break; 2194 case CHIP_R600: 2195 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2196 break; 2197 default: 2198 tmp = TC_L2_SIZE(0); 2199 break; 2200 } 2201 WREG32(TC_CNTL, tmp); 2202 2203 tmp = RREG32(HDP_HOST_PATH_CNTL); 2204 WREG32(HDP_HOST_PATH_CNTL, tmp); 2205 2206 tmp = RREG32(ARB_POP); 2207 tmp |= ENABLE_TC128; 2208 WREG32(ARB_POP, tmp); 2209 2210 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2211 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2212 NUM_CLIP_SEQ(3))); 2213 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2214 WREG32(VC_ENHANCE, 0); 2215 } 2216 2217 2218 /* 2219 * Indirect registers accessor 2220 */ 2221 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2222 { 2223 u32 r; 2224 2225 spin_lock(&rdev->pciep_idx_lock); 2226 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2227 (void)RREG32(PCIE_PORT_INDEX); 2228 r = RREG32(PCIE_PORT_DATA); 2229 spin_unlock(&rdev->pciep_idx_lock); 2230 return r; 2231 } 2232 2233 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2234 { 2235 spin_lock(&rdev->pciep_idx_lock); 2236 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2237 (void)RREG32(PCIE_PORT_INDEX); 2238 WREG32(PCIE_PORT_DATA, (v)); 2239 (void)RREG32(PCIE_PORT_DATA); 2240 spin_unlock(&rdev->pciep_idx_lock); 2241 } 2242 2243 /* 2244 * CP & Ring 2245 */ 2246 void r600_cp_stop(struct radeon_device *rdev) 2247 { 2248 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2249 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2250 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2251 WREG32(SCRATCH_UMSK, 0); 2252 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2253 } 2254 2255 int r600_init_microcode(struct radeon_device *rdev) 2256 { 2257 const char *chip_name; 2258 const char *rlc_chip_name; 2259 const char *smc_chip_name = "RV770"; 2260 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2261 char fw_name[30]; 2262 int err; 2263 2264 DRM_DEBUG("\n"); 2265 2266 switch (rdev->family) { 2267 case CHIP_R600: 2268 chip_name = "R600"; 2269 rlc_chip_name = "R600"; 2270 break; 2271 case CHIP_RV610: 2272 chip_name = "RV610"; 2273 rlc_chip_name = "R600"; 2274 break; 2275 case CHIP_RV630: 2276 chip_name = "RV630"; 2277 rlc_chip_name = "R600"; 2278 break; 2279 case CHIP_RV620: 2280 chip_name = "RV620"; 2281 rlc_chip_name = "R600"; 2282 break; 2283 case CHIP_RV635: 2284 chip_name = "RV635"; 2285 rlc_chip_name = "R600"; 2286 break; 2287 case CHIP_RV670: 2288 chip_name = "RV670"; 2289 rlc_chip_name = "R600"; 2290 break; 2291 case CHIP_RS780: 2292 case CHIP_RS880: 2293 chip_name = "RS780"; 2294 rlc_chip_name = "R600"; 2295 break; 2296 case CHIP_RV770: 2297 chip_name = "RV770"; 2298 rlc_chip_name = "R700"; 2299 smc_chip_name = "RV770"; 2300 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2301 break; 2302 case CHIP_RV730: 2303 chip_name = "RV730"; 2304 rlc_chip_name = "R700"; 2305 smc_chip_name = "RV730"; 2306 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2307 break; 2308 case CHIP_RV710: 2309 chip_name = "RV710"; 2310 rlc_chip_name = "R700"; 2311 smc_chip_name = "RV710"; 2312 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2313 break; 2314 case CHIP_RV740: 2315 chip_name = "RV730"; 2316 rlc_chip_name = "R700"; 2317 smc_chip_name = "RV740"; 2318 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2319 break; 2320 case CHIP_CEDAR: 2321 chip_name = "CEDAR"; 2322 rlc_chip_name = "CEDAR"; 2323 smc_chip_name = "CEDAR"; 2324 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2325 break; 2326 case CHIP_REDWOOD: 2327 chip_name = "REDWOOD"; 2328 rlc_chip_name = "REDWOOD"; 2329 smc_chip_name = "REDWOOD"; 2330 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2331 break; 2332 case CHIP_JUNIPER: 2333 chip_name = "JUNIPER"; 2334 rlc_chip_name = "JUNIPER"; 2335 smc_chip_name = "JUNIPER"; 2336 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2337 break; 2338 case CHIP_CYPRESS: 2339 case CHIP_HEMLOCK: 2340 chip_name = "CYPRESS"; 2341 rlc_chip_name = "CYPRESS"; 2342 smc_chip_name = "CYPRESS"; 2343 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2344 break; 2345 case CHIP_PALM: 2346 chip_name = "PALM"; 2347 rlc_chip_name = "SUMO"; 2348 break; 2349 case CHIP_SUMO: 2350 chip_name = "SUMO"; 2351 rlc_chip_name = "SUMO"; 2352 break; 2353 case CHIP_SUMO2: 2354 chip_name = "SUMO2"; 2355 rlc_chip_name = "SUMO"; 2356 break; 2357 default: BUG(); 2358 } 2359 2360 if (rdev->family >= CHIP_CEDAR) { 2361 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2362 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2363 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2364 } else if (rdev->family >= CHIP_RV770) { 2365 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2366 me_req_size = R700_PM4_UCODE_SIZE * 4; 2367 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2368 } else { 2369 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2370 me_req_size = R600_PM4_UCODE_SIZE * 12; 2371 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2372 } 2373 2374 DRM_INFO("Loading %s Microcode\n", chip_name); 2375 2376 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2377 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2378 if (err) 2379 goto out; 2380 if (rdev->pfp_fw->datasize != pfp_req_size) { 2381 printk(KERN_ERR 2382 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2383 rdev->pfp_fw->datasize, fw_name); 2384 err = -EINVAL; 2385 goto out; 2386 } 2387 2388 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2389 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2390 if (err) 2391 goto out; 2392 if (rdev->me_fw->datasize != me_req_size) { 2393 printk(KERN_ERR 2394 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2395 rdev->me_fw->datasize, fw_name); 2396 err = -EINVAL; 2397 } 2398 2399 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 2400 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2401 if (err) 2402 goto out; 2403 if (rdev->rlc_fw->datasize != rlc_req_size) { 2404 printk(KERN_ERR 2405 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2406 rdev->rlc_fw->datasize, fw_name); 2407 err = -EINVAL; 2408 } 2409 2410 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2411 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name); 2412 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2413 if (err) { 2414 printk(KERN_ERR 2415 "smc: error loading firmware \"%s\"\n", 2416 fw_name); 2417 release_firmware(rdev->smc_fw); 2418 rdev->smc_fw = NULL; 2419 err = 0; 2420 } else if (rdev->smc_fw->datasize != smc_req_size) { 2421 printk(KERN_ERR 2422 "smc: Bogus length %zu in firmware \"%s\"\n", 2423 rdev->smc_fw->datasize, fw_name); 2424 err = -EINVAL; 2425 } 2426 } 2427 2428 out: 2429 if (err) { 2430 if (err != -EINVAL) 2431 printk(KERN_ERR 2432 "r600_cp: Failed to load firmware \"%s\"\n", 2433 fw_name); 2434 release_firmware(rdev->pfp_fw); 2435 rdev->pfp_fw = NULL; 2436 release_firmware(rdev->me_fw); 2437 rdev->me_fw = NULL; 2438 release_firmware(rdev->rlc_fw); 2439 rdev->rlc_fw = NULL; 2440 release_firmware(rdev->smc_fw); 2441 rdev->smc_fw = NULL; 2442 } 2443 return err; 2444 } 2445 2446 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2447 struct radeon_ring *ring) 2448 { 2449 u32 rptr; 2450 2451 if (rdev->wb.enabled) 2452 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2453 else 2454 rptr = RREG32(R600_CP_RB_RPTR); 2455 2456 return rptr; 2457 } 2458 2459 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2460 struct radeon_ring *ring) 2461 { 2462 u32 wptr; 2463 2464 wptr = RREG32(R600_CP_RB_WPTR); 2465 2466 return wptr; 2467 } 2468 2469 void r600_gfx_set_wptr(struct radeon_device *rdev, 2470 struct radeon_ring *ring) 2471 { 2472 WREG32(R600_CP_RB_WPTR, ring->wptr); 2473 (void)RREG32(R600_CP_RB_WPTR); 2474 } 2475 2476 /** 2477 * r600_fini_microcode - drop the firmwares image references 2478 * 2479 * @rdev: radeon_device pointer 2480 * 2481 * Drop the pfp, me and rlc firmwares image references. 2482 * Called at driver shutdown. 2483 */ 2484 void r600_fini_microcode(struct radeon_device *rdev) 2485 { 2486 release_firmware(rdev->pfp_fw); 2487 rdev->pfp_fw = NULL; 2488 release_firmware(rdev->me_fw); 2489 rdev->me_fw = NULL; 2490 release_firmware(rdev->rlc_fw); 2491 rdev->rlc_fw = NULL; 2492 release_firmware(rdev->smc_fw); 2493 rdev->smc_fw = NULL; 2494 } 2495 2496 static int r600_cp_load_microcode(struct radeon_device *rdev) 2497 { 2498 const __be32 *fw_data; 2499 int i; 2500 2501 if (!rdev->me_fw || !rdev->pfp_fw) 2502 return -EINVAL; 2503 2504 r600_cp_stop(rdev); 2505 2506 WREG32(CP_RB_CNTL, 2507 #ifdef __BIG_ENDIAN 2508 BUF_SWAP_32BIT | 2509 #endif 2510 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2511 2512 /* Reset cp */ 2513 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2514 RREG32(GRBM_SOFT_RESET); 2515 mdelay(15); 2516 WREG32(GRBM_SOFT_RESET, 0); 2517 2518 WREG32(CP_ME_RAM_WADDR, 0); 2519 2520 fw_data = (const __be32 *)rdev->me_fw->data; 2521 WREG32(CP_ME_RAM_WADDR, 0); 2522 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2523 WREG32(CP_ME_RAM_DATA, 2524 be32_to_cpup(fw_data++)); 2525 2526 fw_data = (const __be32 *)rdev->pfp_fw->data; 2527 WREG32(CP_PFP_UCODE_ADDR, 0); 2528 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2529 WREG32(CP_PFP_UCODE_DATA, 2530 be32_to_cpup(fw_data++)); 2531 2532 WREG32(CP_PFP_UCODE_ADDR, 0); 2533 WREG32(CP_ME_RAM_WADDR, 0); 2534 WREG32(CP_ME_RAM_RADDR, 0); 2535 return 0; 2536 } 2537 2538 int r600_cp_start(struct radeon_device *rdev) 2539 { 2540 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2541 int r; 2542 uint32_t cp_me; 2543 2544 r = radeon_ring_lock(rdev, ring, 7); 2545 if (r) { 2546 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2547 return r; 2548 } 2549 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2550 radeon_ring_write(ring, 0x1); 2551 if (rdev->family >= CHIP_RV770) { 2552 radeon_ring_write(ring, 0x0); 2553 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2554 } else { 2555 radeon_ring_write(ring, 0x3); 2556 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2557 } 2558 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2559 radeon_ring_write(ring, 0); 2560 radeon_ring_write(ring, 0); 2561 radeon_ring_unlock_commit(rdev, ring, false); 2562 2563 cp_me = 0xff; 2564 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2565 return 0; 2566 } 2567 2568 int r600_cp_resume(struct radeon_device *rdev) 2569 { 2570 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2571 u32 tmp; 2572 u32 rb_bufsz; 2573 int r; 2574 2575 /* Reset cp */ 2576 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2577 RREG32(GRBM_SOFT_RESET); 2578 mdelay(15); 2579 WREG32(GRBM_SOFT_RESET, 0); 2580 2581 /* Set ring buffer size */ 2582 rb_bufsz = order_base_2(ring->ring_size / 8); 2583 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2584 #ifdef __BIG_ENDIAN 2585 tmp |= BUF_SWAP_32BIT; 2586 #endif 2587 WREG32(CP_RB_CNTL, tmp); 2588 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2589 2590 /* Set the write pointer delay */ 2591 WREG32(CP_RB_WPTR_DELAY, 0); 2592 2593 /* Initialize the ring buffer's read and write pointers */ 2594 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2595 WREG32(CP_RB_RPTR_WR, 0); 2596 ring->wptr = 0; 2597 WREG32(CP_RB_WPTR, ring->wptr); 2598 2599 /* set the wb address whether it's enabled or not */ 2600 WREG32(CP_RB_RPTR_ADDR, 2601 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2602 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2603 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2604 2605 if (rdev->wb.enabled) 2606 WREG32(SCRATCH_UMSK, 0xff); 2607 else { 2608 tmp |= RB_NO_UPDATE; 2609 WREG32(SCRATCH_UMSK, 0); 2610 } 2611 2612 mdelay(1); 2613 WREG32(CP_RB_CNTL, tmp); 2614 2615 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2616 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2617 2618 r600_cp_start(rdev); 2619 ring->ready = true; 2620 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2621 if (r) { 2622 ring->ready = false; 2623 return r; 2624 } 2625 2626 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2627 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2628 2629 return 0; 2630 } 2631 2632 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2633 { 2634 u32 rb_bufsz; 2635 int r; 2636 2637 /* Align ring size */ 2638 rb_bufsz = order_base_2(ring_size / 8); 2639 ring_size = (1 << (rb_bufsz + 1)) * 4; 2640 ring->ring_size = ring_size; 2641 ring->align_mask = 16 - 1; 2642 2643 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2644 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2645 if (r) { 2646 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2647 ring->rptr_save_reg = 0; 2648 } 2649 } 2650 } 2651 2652 void r600_cp_fini(struct radeon_device *rdev) 2653 { 2654 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2655 r600_cp_stop(rdev); 2656 radeon_ring_fini(rdev, ring); 2657 radeon_scratch_free(rdev, ring->rptr_save_reg); 2658 } 2659 2660 /* 2661 * GPU scratch registers helpers function. 2662 */ 2663 void r600_scratch_init(struct radeon_device *rdev) 2664 { 2665 int i; 2666 2667 rdev->scratch.num_reg = 7; 2668 rdev->scratch.reg_base = SCRATCH_REG0; 2669 for (i = 0; i < rdev->scratch.num_reg; i++) { 2670 rdev->scratch.free[i] = true; 2671 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2672 } 2673 } 2674 2675 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2676 { 2677 uint32_t scratch; 2678 uint32_t tmp = 0; 2679 unsigned i; 2680 int r; 2681 2682 r = radeon_scratch_get(rdev, &scratch); 2683 if (r) { 2684 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2685 return r; 2686 } 2687 WREG32(scratch, 0xCAFEDEAD); 2688 r = radeon_ring_lock(rdev, ring, 3); 2689 if (r) { 2690 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2691 radeon_scratch_free(rdev, scratch); 2692 return r; 2693 } 2694 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2695 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2696 radeon_ring_write(ring, 0xDEADBEEF); 2697 radeon_ring_unlock_commit(rdev, ring, false); 2698 for (i = 0; i < rdev->usec_timeout; i++) { 2699 tmp = RREG32(scratch); 2700 if (tmp == 0xDEADBEEF) 2701 break; 2702 DRM_UDELAY(1); 2703 } 2704 if (i < rdev->usec_timeout) { 2705 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2706 } else { 2707 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2708 ring->idx, scratch, tmp); 2709 r = -EINVAL; 2710 } 2711 radeon_scratch_free(rdev, scratch); 2712 return r; 2713 } 2714 2715 /* 2716 * CP fences/semaphores 2717 */ 2718 2719 void r600_fence_ring_emit(struct radeon_device *rdev, 2720 struct radeon_fence *fence) 2721 { 2722 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2723 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2724 PACKET3_SH_ACTION_ENA; 2725 2726 if (rdev->family >= CHIP_RV770) 2727 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2728 2729 if (rdev->wb.use_event) { 2730 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2731 /* flush read cache over gart */ 2732 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2733 radeon_ring_write(ring, cp_coher_cntl); 2734 radeon_ring_write(ring, 0xFFFFFFFF); 2735 radeon_ring_write(ring, 0); 2736 radeon_ring_write(ring, 10); /* poll interval */ 2737 /* EVENT_WRITE_EOP - flush caches, send int */ 2738 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2739 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2740 radeon_ring_write(ring, lower_32_bits(addr)); 2741 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2742 radeon_ring_write(ring, fence->seq); 2743 radeon_ring_write(ring, 0); 2744 } else { 2745 /* flush read cache over gart */ 2746 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2747 radeon_ring_write(ring, cp_coher_cntl); 2748 radeon_ring_write(ring, 0xFFFFFFFF); 2749 radeon_ring_write(ring, 0); 2750 radeon_ring_write(ring, 10); /* poll interval */ 2751 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2752 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2753 /* wait for 3D idle clean */ 2754 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2755 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2756 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2757 /* Emit fence sequence & fire IRQ */ 2758 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2759 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2760 radeon_ring_write(ring, fence->seq); 2761 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2762 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2763 radeon_ring_write(ring, RB_INT_STAT); 2764 } 2765 } 2766 2767 /** 2768 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2769 * 2770 * @rdev: radeon_device pointer 2771 * @ring: radeon ring buffer object 2772 * @semaphore: radeon semaphore object 2773 * @emit_wait: Is this a sempahore wait? 2774 * 2775 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2776 * from running ahead of semaphore waits. 2777 */ 2778 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2779 struct radeon_ring *ring, 2780 struct radeon_semaphore *semaphore, 2781 bool emit_wait) 2782 { 2783 uint64_t addr = semaphore->gpu_addr; 2784 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2785 2786 if (rdev->family < CHIP_CAYMAN) 2787 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2788 2789 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2790 radeon_ring_write(ring, lower_32_bits(addr)); 2791 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2792 2793 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2794 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2795 /* Prevent the PFP from running ahead of the semaphore wait */ 2796 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2797 radeon_ring_write(ring, 0x0); 2798 } 2799 2800 return true; 2801 } 2802 2803 /** 2804 * r600_copy_cpdma - copy pages using the CP DMA engine 2805 * 2806 * @rdev: radeon_device pointer 2807 * @src_offset: src GPU address 2808 * @dst_offset: dst GPU address 2809 * @num_gpu_pages: number of GPU pages to xfer 2810 * @fence: radeon fence object 2811 * 2812 * Copy GPU paging using the CP DMA engine (r6xx+). 2813 * Used by the radeon ttm implementation to move pages if 2814 * registered as the asic copy callback. 2815 */ 2816 int r600_copy_cpdma(struct radeon_device *rdev, 2817 uint64_t src_offset, uint64_t dst_offset, 2818 unsigned num_gpu_pages, 2819 struct radeon_fence **fence) 2820 { 2821 struct radeon_semaphore *sem = NULL; 2822 int ring_index = rdev->asic->copy.blit_ring_index; 2823 struct radeon_ring *ring = &rdev->ring[ring_index]; 2824 u32 size_in_bytes, cur_size_in_bytes, tmp; 2825 int i, num_loops; 2826 int r = 0; 2827 2828 r = radeon_semaphore_create(rdev, &sem); 2829 if (r) { 2830 DRM_ERROR("radeon: moving bo (%d).\n", r); 2831 return r; 2832 } 2833 2834 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 2835 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 2836 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 2837 if (r) { 2838 DRM_ERROR("radeon: moving bo (%d).\n", r); 2839 radeon_semaphore_free(rdev, &sem, NULL); 2840 return r; 2841 } 2842 2843 radeon_semaphore_sync_to(sem, *fence); 2844 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 2845 2846 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2847 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2848 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 2849 for (i = 0; i < num_loops; i++) { 2850 cur_size_in_bytes = size_in_bytes; 2851 if (cur_size_in_bytes > 0x1fffff) 2852 cur_size_in_bytes = 0x1fffff; 2853 size_in_bytes -= cur_size_in_bytes; 2854 tmp = upper_32_bits(src_offset) & 0xff; 2855 if (size_in_bytes == 0) 2856 tmp |= PACKET3_CP_DMA_CP_SYNC; 2857 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 2858 radeon_ring_write(ring, lower_32_bits(src_offset)); 2859 radeon_ring_write(ring, tmp); 2860 radeon_ring_write(ring, lower_32_bits(dst_offset)); 2861 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 2862 radeon_ring_write(ring, cur_size_in_bytes); 2863 src_offset += cur_size_in_bytes; 2864 dst_offset += cur_size_in_bytes; 2865 } 2866 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2867 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2868 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 2869 2870 r = radeon_fence_emit(rdev, fence, ring->idx); 2871 if (r) { 2872 radeon_ring_unlock_undo(rdev, ring); 2873 radeon_semaphore_free(rdev, &sem, NULL); 2874 return r; 2875 } 2876 2877 radeon_ring_unlock_commit(rdev, ring, false); 2878 radeon_semaphore_free(rdev, &sem, *fence); 2879 2880 return r; 2881 } 2882 2883 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2884 uint32_t tiling_flags, uint32_t pitch, 2885 uint32_t offset, uint32_t obj_size) 2886 { 2887 /* FIXME: implement */ 2888 return 0; 2889 } 2890 2891 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2892 { 2893 /* FIXME: implement */ 2894 } 2895 2896 static int r600_startup(struct radeon_device *rdev) 2897 { 2898 struct radeon_ring *ring; 2899 int r; 2900 2901 /* enable pcie gen2 link */ 2902 r600_pcie_gen2_enable(rdev); 2903 2904 /* scratch needs to be initialized before MC */ 2905 r = r600_vram_scratch_init(rdev); 2906 if (r) 2907 return r; 2908 2909 r600_mc_program(rdev); 2910 2911 if (rdev->flags & RADEON_IS_AGP) { 2912 r600_agp_enable(rdev); 2913 } else { 2914 r = r600_pcie_gart_enable(rdev); 2915 if (r) 2916 return r; 2917 } 2918 r600_gpu_init(rdev); 2919 2920 /* allocate wb buffer */ 2921 r = radeon_wb_init(rdev); 2922 if (r) 2923 return r; 2924 2925 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2926 if (r) { 2927 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2928 return r; 2929 } 2930 2931 /* Enable IRQ */ 2932 if (!rdev->irq.installed) { 2933 r = radeon_irq_kms_init(rdev); 2934 if (r) 2935 return r; 2936 } 2937 2938 r = r600_irq_init(rdev); 2939 if (r) { 2940 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2941 radeon_irq_kms_fini(rdev); 2942 return r; 2943 } 2944 r600_irq_set(rdev); 2945 2946 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2947 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2948 RADEON_CP_PACKET2); 2949 if (r) 2950 return r; 2951 2952 r = r600_cp_load_microcode(rdev); 2953 if (r) 2954 return r; 2955 r = r600_cp_resume(rdev); 2956 if (r) 2957 return r; 2958 2959 r = radeon_ib_pool_init(rdev); 2960 if (r) { 2961 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2962 return r; 2963 } 2964 2965 r = r600_audio_init(rdev); 2966 if (r) { 2967 DRM_ERROR("radeon: audio init failed\n"); 2968 return r; 2969 } 2970 2971 return 0; 2972 } 2973 2974 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2975 { 2976 uint32_t temp; 2977 2978 temp = RREG32(CONFIG_CNTL); 2979 if (state == false) { 2980 temp &= ~(1<<0); 2981 temp |= (1<<1); 2982 } else { 2983 temp &= ~(1<<1); 2984 } 2985 WREG32(CONFIG_CNTL, temp); 2986 } 2987 2988 int r600_resume(struct radeon_device *rdev) 2989 { 2990 int r; 2991 2992 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2993 * posting will perform necessary task to bring back GPU into good 2994 * shape. 2995 */ 2996 /* post card */ 2997 atom_asic_init(rdev->mode_info.atom_context); 2998 2999 if (rdev->pm.pm_method == PM_METHOD_DPM) 3000 radeon_pm_resume(rdev); 3001 3002 rdev->accel_working = true; 3003 r = r600_startup(rdev); 3004 if (r) { 3005 DRM_ERROR("r600 startup failed on resume\n"); 3006 rdev->accel_working = false; 3007 return r; 3008 } 3009 3010 return r; 3011 } 3012 3013 int r600_suspend(struct radeon_device *rdev) 3014 { 3015 radeon_pm_suspend(rdev); 3016 r600_audio_fini(rdev); 3017 r600_cp_stop(rdev); 3018 r600_irq_suspend(rdev); 3019 radeon_wb_disable(rdev); 3020 r600_pcie_gart_disable(rdev); 3021 3022 return 0; 3023 } 3024 3025 /* Plan is to move initialization in that function and use 3026 * helper function so that radeon_device_init pretty much 3027 * do nothing more than calling asic specific function. This 3028 * should also allow to remove a bunch of callback function 3029 * like vram_info. 3030 */ 3031 int r600_init(struct radeon_device *rdev) 3032 { 3033 int r; 3034 3035 if (r600_debugfs_mc_info_init(rdev)) { 3036 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3037 } 3038 /* Read BIOS */ 3039 if (!radeon_get_bios(rdev)) { 3040 if (ASIC_IS_AVIVO(rdev)) 3041 return -EINVAL; 3042 } 3043 /* Must be an ATOMBIOS */ 3044 if (!rdev->is_atom_bios) { 3045 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3046 return -EINVAL; 3047 } 3048 r = radeon_atombios_init(rdev); 3049 if (r) 3050 return r; 3051 /* Post card if necessary */ 3052 if (!radeon_card_posted(rdev)) { 3053 if (!rdev->bios) { 3054 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3055 return -EINVAL; 3056 } 3057 DRM_INFO("GPU not posted. posting now...\n"); 3058 atom_asic_init(rdev->mode_info.atom_context); 3059 } 3060 /* Initialize scratch registers */ 3061 r600_scratch_init(rdev); 3062 /* Initialize surface registers */ 3063 radeon_surface_init(rdev); 3064 /* Initialize clocks */ 3065 radeon_get_clock_info(rdev->ddev); 3066 /* Fence driver */ 3067 r = radeon_fence_driver_init(rdev); 3068 if (r) 3069 return r; 3070 if (rdev->flags & RADEON_IS_AGP) { 3071 r = radeon_agp_init(rdev); 3072 if (r) 3073 radeon_agp_disable(rdev); 3074 } 3075 r = r600_mc_init(rdev); 3076 if (r) 3077 return r; 3078 /* Memory manager */ 3079 r = radeon_bo_init(rdev); 3080 if (r) 3081 return r; 3082 3083 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3084 r = r600_init_microcode(rdev); 3085 if (r) { 3086 DRM_ERROR("Failed to load firmware!\n"); 3087 return r; 3088 } 3089 } 3090 3091 /* Initialize power management */ 3092 radeon_pm_init(rdev); 3093 3094 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3095 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3096 3097 rdev->ih.ring_obj = NULL; 3098 r600_ih_ring_init(rdev, 64 * 1024); 3099 3100 r = r600_pcie_gart_init(rdev); 3101 if (r) 3102 return r; 3103 3104 rdev->accel_working = true; 3105 r = r600_startup(rdev); 3106 if (r) { 3107 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3108 r600_cp_fini(rdev); 3109 r600_irq_fini(rdev); 3110 radeon_wb_fini(rdev); 3111 radeon_ib_pool_fini(rdev); 3112 radeon_irq_kms_fini(rdev); 3113 r600_pcie_gart_fini(rdev); 3114 rdev->accel_working = false; 3115 } 3116 3117 return 0; 3118 } 3119 3120 void r600_fini(struct radeon_device *rdev) 3121 { 3122 radeon_pm_fini(rdev); 3123 r600_audio_fini(rdev); 3124 r600_cp_fini(rdev); 3125 r600_irq_fini(rdev); 3126 radeon_wb_fini(rdev); 3127 radeon_ib_pool_fini(rdev); 3128 radeon_irq_kms_fini(rdev); 3129 r600_pcie_gart_fini(rdev); 3130 r600_vram_scratch_fini(rdev); 3131 radeon_agp_fini(rdev); 3132 radeon_gem_fini(rdev); 3133 radeon_fence_driver_fini(rdev); 3134 radeon_bo_fini(rdev); 3135 radeon_atombios_fini(rdev); 3136 r600_fini_microcode(rdev); 3137 kfree(rdev->bios); 3138 rdev->bios = NULL; 3139 } 3140 3141 3142 /* 3143 * CS stuff 3144 */ 3145 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3146 { 3147 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3148 u32 next_rptr; 3149 3150 if (ring->rptr_save_reg) { 3151 next_rptr = ring->wptr + 3 + 4; 3152 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3153 radeon_ring_write(ring, ((ring->rptr_save_reg - 3154 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3155 radeon_ring_write(ring, next_rptr); 3156 } else if (rdev->wb.enabled) { 3157 next_rptr = ring->wptr + 5 + 4; 3158 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3159 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3160 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3161 radeon_ring_write(ring, next_rptr); 3162 radeon_ring_write(ring, 0); 3163 } 3164 3165 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3166 radeon_ring_write(ring, 3167 #ifdef __BIG_ENDIAN 3168 (2 << 0) | 3169 #endif 3170 (ib->gpu_addr & 0xFFFFFFFC)); 3171 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3172 radeon_ring_write(ring, ib->length_dw); 3173 } 3174 3175 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3176 { 3177 struct radeon_ib ib; 3178 uint32_t scratch; 3179 uint32_t tmp = 0; 3180 unsigned i; 3181 int r; 3182 3183 r = radeon_scratch_get(rdev, &scratch); 3184 if (r) { 3185 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3186 return r; 3187 } 3188 WREG32(scratch, 0xCAFEDEAD); 3189 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3190 if (r) { 3191 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3192 goto free_scratch; 3193 } 3194 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3195 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3196 ib.ptr[2] = 0xDEADBEEF; 3197 ib.length_dw = 3; 3198 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3199 if (r) { 3200 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3201 goto free_ib; 3202 } 3203 r = radeon_fence_wait(ib.fence, false); 3204 if (r) { 3205 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3206 goto free_ib; 3207 } 3208 for (i = 0; i < rdev->usec_timeout; i++) { 3209 tmp = RREG32(scratch); 3210 if (tmp == 0xDEADBEEF) 3211 break; 3212 DRM_UDELAY(1); 3213 } 3214 if (i < rdev->usec_timeout) { 3215 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3216 } else { 3217 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3218 scratch, tmp); 3219 r = -EINVAL; 3220 } 3221 free_ib: 3222 radeon_ib_free(rdev, &ib); 3223 free_scratch: 3224 radeon_scratch_free(rdev, scratch); 3225 return r; 3226 } 3227 3228 /* 3229 * Interrupts 3230 * 3231 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3232 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3233 * writing to the ring and the GPU consuming, the GPU writes to the ring 3234 * and host consumes. As the host irq handler processes interrupts, it 3235 * increments the rptr. When the rptr catches up with the wptr, all the 3236 * current interrupts have been processed. 3237 */ 3238 3239 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3240 { 3241 u32 rb_bufsz; 3242 3243 /* Align ring size */ 3244 rb_bufsz = order_base_2(ring_size / 4); 3245 ring_size = (1 << rb_bufsz) * 4; 3246 rdev->ih.ring_size = ring_size; 3247 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3248 rdev->ih.rptr = 0; 3249 } 3250 3251 int r600_ih_ring_alloc(struct radeon_device *rdev) 3252 { 3253 int r; 3254 void *ring_ptr; 3255 3256 /* Allocate ring buffer */ 3257 if (rdev->ih.ring_obj == NULL) { 3258 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3259 PAGE_SIZE, true, 3260 RADEON_GEM_DOMAIN_GTT, 0, 3261 NULL, &rdev->ih.ring_obj); 3262 if (r) { 3263 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3264 return r; 3265 } 3266 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3267 if (unlikely(r != 0)) { 3268 radeon_bo_unref(&rdev->ih.ring_obj); 3269 return r; 3270 } 3271 r = radeon_bo_pin(rdev->ih.ring_obj, 3272 RADEON_GEM_DOMAIN_GTT, 3273 &rdev->ih.gpu_addr); 3274 if (r) { 3275 radeon_bo_unreserve(rdev->ih.ring_obj); 3276 radeon_bo_unref(&rdev->ih.ring_obj); 3277 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3278 return r; 3279 } 3280 ring_ptr = &rdev->ih.ring; 3281 r = radeon_bo_kmap(rdev->ih.ring_obj, 3282 ring_ptr); 3283 if (r) 3284 radeon_bo_unpin(rdev->ih.ring_obj); 3285 radeon_bo_unreserve(rdev->ih.ring_obj); 3286 if (r) { 3287 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3288 radeon_bo_unref(&rdev->ih.ring_obj); 3289 return r; 3290 } 3291 } 3292 return 0; 3293 } 3294 3295 void r600_ih_ring_fini(struct radeon_device *rdev) 3296 { 3297 int r; 3298 if (rdev->ih.ring_obj) { 3299 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3300 if (likely(r == 0)) { 3301 radeon_bo_kunmap(rdev->ih.ring_obj); 3302 radeon_bo_unpin(rdev->ih.ring_obj); 3303 radeon_bo_unreserve(rdev->ih.ring_obj); 3304 } 3305 radeon_bo_unref(&rdev->ih.ring_obj); 3306 rdev->ih.ring = NULL; 3307 rdev->ih.ring_obj = NULL; 3308 } 3309 } 3310 3311 void r600_rlc_stop(struct radeon_device *rdev) 3312 { 3313 3314 if ((rdev->family >= CHIP_RV770) && 3315 (rdev->family <= CHIP_RV740)) { 3316 /* r7xx asics need to soft reset RLC before halting */ 3317 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3318 RREG32(SRBM_SOFT_RESET); 3319 mdelay(15); 3320 WREG32(SRBM_SOFT_RESET, 0); 3321 RREG32(SRBM_SOFT_RESET); 3322 } 3323 3324 WREG32(RLC_CNTL, 0); 3325 } 3326 3327 static void r600_rlc_start(struct radeon_device *rdev) 3328 { 3329 WREG32(RLC_CNTL, RLC_ENABLE); 3330 } 3331 3332 static int r600_rlc_resume(struct radeon_device *rdev) 3333 { 3334 u32 i; 3335 const __be32 *fw_data; 3336 3337 if (!rdev->rlc_fw) 3338 return -EINVAL; 3339 3340 r600_rlc_stop(rdev); 3341 3342 WREG32(RLC_HB_CNTL, 0); 3343 3344 WREG32(RLC_HB_BASE, 0); 3345 WREG32(RLC_HB_RPTR, 0); 3346 WREG32(RLC_HB_WPTR, 0); 3347 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3348 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3349 WREG32(RLC_MC_CNTL, 0); 3350 WREG32(RLC_UCODE_CNTL, 0); 3351 3352 fw_data = (const __be32 *)rdev->rlc_fw->data; 3353 if (rdev->family >= CHIP_RV770) { 3354 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3355 WREG32(RLC_UCODE_ADDR, i); 3356 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3357 } 3358 } else { 3359 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3360 WREG32(RLC_UCODE_ADDR, i); 3361 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3362 } 3363 } 3364 WREG32(RLC_UCODE_ADDR, 0); 3365 3366 r600_rlc_start(rdev); 3367 3368 return 0; 3369 } 3370 3371 static void r600_enable_interrupts(struct radeon_device *rdev) 3372 { 3373 u32 ih_cntl = RREG32(IH_CNTL); 3374 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3375 3376 ih_cntl |= ENABLE_INTR; 3377 ih_rb_cntl |= IH_RB_ENABLE; 3378 WREG32(IH_CNTL, ih_cntl); 3379 WREG32(IH_RB_CNTL, ih_rb_cntl); 3380 rdev->ih.enabled = true; 3381 } 3382 3383 void r600_disable_interrupts(struct radeon_device *rdev) 3384 { 3385 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3386 u32 ih_cntl = RREG32(IH_CNTL); 3387 3388 ih_rb_cntl &= ~IH_RB_ENABLE; 3389 ih_cntl &= ~ENABLE_INTR; 3390 WREG32(IH_RB_CNTL, ih_rb_cntl); 3391 WREG32(IH_CNTL, ih_cntl); 3392 /* set rptr, wptr to 0 */ 3393 WREG32(IH_RB_RPTR, 0); 3394 WREG32(IH_RB_WPTR, 0); 3395 rdev->ih.enabled = false; 3396 rdev->ih.rptr = 0; 3397 } 3398 3399 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3400 { 3401 u32 tmp; 3402 3403 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3404 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3405 WREG32(DMA_CNTL, tmp); 3406 WREG32(GRBM_INT_CNTL, 0); 3407 WREG32(DxMODE_INT_MASK, 0); 3408 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3409 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3410 if (ASIC_IS_DCE3(rdev)) { 3411 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3412 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3413 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3414 WREG32(DC_HPD1_INT_CONTROL, tmp); 3415 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3416 WREG32(DC_HPD2_INT_CONTROL, tmp); 3417 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3418 WREG32(DC_HPD3_INT_CONTROL, tmp); 3419 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3420 WREG32(DC_HPD4_INT_CONTROL, tmp); 3421 if (ASIC_IS_DCE32(rdev)) { 3422 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3423 WREG32(DC_HPD5_INT_CONTROL, tmp); 3424 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3425 WREG32(DC_HPD6_INT_CONTROL, tmp); 3426 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3427 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3428 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3429 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3430 } else { 3431 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3432 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3433 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3434 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3435 } 3436 } else { 3437 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3438 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3439 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3440 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3441 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3442 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3443 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3444 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3445 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3446 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3447 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3448 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3449 } 3450 } 3451 3452 int r600_irq_init(struct radeon_device *rdev) 3453 { 3454 int ret = 0; 3455 int rb_bufsz; 3456 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3457 3458 /* allocate ring */ 3459 ret = r600_ih_ring_alloc(rdev); 3460 if (ret) 3461 return ret; 3462 3463 /* disable irqs */ 3464 r600_disable_interrupts(rdev); 3465 3466 /* init rlc */ 3467 if (rdev->family >= CHIP_CEDAR) 3468 ret = evergreen_rlc_resume(rdev); 3469 else 3470 ret = r600_rlc_resume(rdev); 3471 if (ret) { 3472 r600_ih_ring_fini(rdev); 3473 return ret; 3474 } 3475 3476 /* setup interrupt control */ 3477 /* set dummy read address to ring address */ 3478 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3479 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3480 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3481 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3482 */ 3483 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3484 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3485 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3486 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3487 3488 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3489 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3490 3491 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3492 IH_WPTR_OVERFLOW_CLEAR | 3493 (rb_bufsz << 1)); 3494 3495 if (rdev->wb.enabled) 3496 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3497 3498 /* set the writeback address whether it's enabled or not */ 3499 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3500 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3501 3502 WREG32(IH_RB_CNTL, ih_rb_cntl); 3503 3504 /* set rptr, wptr to 0 */ 3505 WREG32(IH_RB_RPTR, 0); 3506 WREG32(IH_RB_WPTR, 0); 3507 3508 /* Default settings for IH_CNTL (disabled at first) */ 3509 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3510 /* RPTR_REARM only works if msi's are enabled */ 3511 if (rdev->msi_enabled) 3512 ih_cntl |= RPTR_REARM; 3513 WREG32(IH_CNTL, ih_cntl); 3514 3515 /* force the active interrupt state to all disabled */ 3516 if (rdev->family >= CHIP_CEDAR) 3517 evergreen_disable_interrupt_state(rdev); 3518 else 3519 r600_disable_interrupt_state(rdev); 3520 3521 /* at this point everything should be setup correctly to enable master */ 3522 pci_enable_busmaster(rdev->dev); 3523 3524 /* enable irqs */ 3525 r600_enable_interrupts(rdev); 3526 3527 return ret; 3528 } 3529 3530 void r600_irq_suspend(struct radeon_device *rdev) 3531 { 3532 r600_irq_disable(rdev); 3533 r600_rlc_stop(rdev); 3534 } 3535 3536 void r600_irq_fini(struct radeon_device *rdev) 3537 { 3538 r600_irq_suspend(rdev); 3539 r600_ih_ring_fini(rdev); 3540 } 3541 3542 int r600_irq_set(struct radeon_device *rdev) 3543 { 3544 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3545 u32 mode_int = 0; 3546 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3547 u32 grbm_int_cntl = 0; 3548 u32 hdmi0, hdmi1; 3549 u32 dma_cntl; 3550 u32 thermal_int = 0; 3551 3552 if (!rdev->irq.installed) { 3553 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3554 return -EINVAL; 3555 } 3556 /* don't enable anything if the ih is disabled */ 3557 if (!rdev->ih.enabled) { 3558 r600_disable_interrupts(rdev); 3559 /* force the active interrupt state to all disabled */ 3560 r600_disable_interrupt_state(rdev); 3561 return 0; 3562 } 3563 3564 if (ASIC_IS_DCE3(rdev)) { 3565 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3566 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3567 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3568 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3569 if (ASIC_IS_DCE32(rdev)) { 3570 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3571 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3572 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3573 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3574 } else { 3575 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3576 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3577 } 3578 } else { 3579 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3580 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3581 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3582 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3583 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3584 } 3585 3586 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3587 3588 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3589 thermal_int = RREG32(CG_THERMAL_INT) & 3590 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3591 } else if (rdev->family >= CHIP_RV770) { 3592 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3593 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3594 } 3595 if (rdev->irq.dpm_thermal) { 3596 DRM_DEBUG("dpm thermal\n"); 3597 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3598 } 3599 3600 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3601 DRM_DEBUG("r600_irq_set: sw int\n"); 3602 cp_int_cntl |= RB_INT_ENABLE; 3603 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3604 } 3605 3606 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3607 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3608 dma_cntl |= TRAP_ENABLE; 3609 } 3610 3611 if (rdev->irq.crtc_vblank_int[0] || 3612 atomic_read(&rdev->irq.pflip[0])) { 3613 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3614 mode_int |= D1MODE_VBLANK_INT_MASK; 3615 } 3616 if (rdev->irq.crtc_vblank_int[1] || 3617 atomic_read(&rdev->irq.pflip[1])) { 3618 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3619 mode_int |= D2MODE_VBLANK_INT_MASK; 3620 } 3621 if (rdev->irq.hpd[0]) { 3622 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3623 hpd1 |= DC_HPDx_INT_EN; 3624 } 3625 if (rdev->irq.hpd[1]) { 3626 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3627 hpd2 |= DC_HPDx_INT_EN; 3628 } 3629 if (rdev->irq.hpd[2]) { 3630 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3631 hpd3 |= DC_HPDx_INT_EN; 3632 } 3633 if (rdev->irq.hpd[3]) { 3634 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3635 hpd4 |= DC_HPDx_INT_EN; 3636 } 3637 if (rdev->irq.hpd[4]) { 3638 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3639 hpd5 |= DC_HPDx_INT_EN; 3640 } 3641 if (rdev->irq.hpd[5]) { 3642 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3643 hpd6 |= DC_HPDx_INT_EN; 3644 } 3645 if (rdev->irq.afmt[0]) { 3646 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3647 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3648 } 3649 if (rdev->irq.afmt[1]) { 3650 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3651 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3652 } 3653 3654 WREG32(CP_INT_CNTL, cp_int_cntl); 3655 WREG32(DMA_CNTL, dma_cntl); 3656 WREG32(DxMODE_INT_MASK, mode_int); 3657 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3658 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3659 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3660 if (ASIC_IS_DCE3(rdev)) { 3661 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3662 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3663 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3664 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3665 if (ASIC_IS_DCE32(rdev)) { 3666 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3667 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3668 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3669 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3670 } else { 3671 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3672 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3673 } 3674 } else { 3675 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3676 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3677 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3678 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3679 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3680 } 3681 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3682 WREG32(CG_THERMAL_INT, thermal_int); 3683 } else if (rdev->family >= CHIP_RV770) { 3684 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3685 } 3686 3687 return 0; 3688 } 3689 3690 static void r600_irq_ack(struct radeon_device *rdev) 3691 { 3692 u32 tmp; 3693 3694 if (ASIC_IS_DCE3(rdev)) { 3695 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3696 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3697 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3698 if (ASIC_IS_DCE32(rdev)) { 3699 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3700 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3701 } else { 3702 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3703 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3704 } 3705 } else { 3706 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3707 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3708 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3709 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3710 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3711 } 3712 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3713 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3714 3715 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3716 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3717 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3718 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3719 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3720 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3721 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3722 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3723 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3724 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3725 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3726 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3727 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3728 if (ASIC_IS_DCE3(rdev)) { 3729 tmp = RREG32(DC_HPD1_INT_CONTROL); 3730 tmp |= DC_HPDx_INT_ACK; 3731 WREG32(DC_HPD1_INT_CONTROL, tmp); 3732 } else { 3733 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3734 tmp |= DC_HPDx_INT_ACK; 3735 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3736 } 3737 } 3738 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3739 if (ASIC_IS_DCE3(rdev)) { 3740 tmp = RREG32(DC_HPD2_INT_CONTROL); 3741 tmp |= DC_HPDx_INT_ACK; 3742 WREG32(DC_HPD2_INT_CONTROL, tmp); 3743 } else { 3744 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3745 tmp |= DC_HPDx_INT_ACK; 3746 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3747 } 3748 } 3749 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3750 if (ASIC_IS_DCE3(rdev)) { 3751 tmp = RREG32(DC_HPD3_INT_CONTROL); 3752 tmp |= DC_HPDx_INT_ACK; 3753 WREG32(DC_HPD3_INT_CONTROL, tmp); 3754 } else { 3755 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3756 tmp |= DC_HPDx_INT_ACK; 3757 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3758 } 3759 } 3760 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3761 tmp = RREG32(DC_HPD4_INT_CONTROL); 3762 tmp |= DC_HPDx_INT_ACK; 3763 WREG32(DC_HPD4_INT_CONTROL, tmp); 3764 } 3765 if (ASIC_IS_DCE32(rdev)) { 3766 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3767 tmp = RREG32(DC_HPD5_INT_CONTROL); 3768 tmp |= DC_HPDx_INT_ACK; 3769 WREG32(DC_HPD5_INT_CONTROL, tmp); 3770 } 3771 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3772 tmp = RREG32(DC_HPD5_INT_CONTROL); 3773 tmp |= DC_HPDx_INT_ACK; 3774 WREG32(DC_HPD6_INT_CONTROL, tmp); 3775 } 3776 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3777 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3778 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3779 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3780 } 3781 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3782 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3783 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3784 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3785 } 3786 } else { 3787 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3788 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3789 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3790 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3791 } 3792 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3793 if (ASIC_IS_DCE3(rdev)) { 3794 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3795 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3796 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3797 } else { 3798 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3799 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3800 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3801 } 3802 } 3803 } 3804 } 3805 3806 void r600_irq_disable(struct radeon_device *rdev) 3807 { 3808 r600_disable_interrupts(rdev); 3809 /* Wait and acknowledge irq */ 3810 mdelay(1); 3811 r600_irq_ack(rdev); 3812 r600_disable_interrupt_state(rdev); 3813 } 3814 3815 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3816 { 3817 u32 wptr, tmp; 3818 3819 if (rdev->wb.enabled) 3820 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3821 else 3822 wptr = RREG32(IH_RB_WPTR); 3823 3824 if (wptr & RB_OVERFLOW) { 3825 wptr &= ~RB_OVERFLOW; 3826 /* When a ring buffer overflow happen start parsing interrupt 3827 * from the last not overwritten vector (wptr + 16). Hopefully 3828 * this should allow us to catchup. 3829 */ 3830 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 3831 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 3832 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3833 tmp = RREG32(IH_RB_CNTL); 3834 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3835 WREG32(IH_RB_CNTL, tmp); 3836 } 3837 return (wptr & rdev->ih.ptr_mask); 3838 } 3839 3840 /* r600 IV Ring 3841 * Each IV ring entry is 128 bits: 3842 * [7:0] - interrupt source id 3843 * [31:8] - reserved 3844 * [59:32] - interrupt source data 3845 * [127:60] - reserved 3846 * 3847 * The basic interrupt vector entries 3848 * are decoded as follows: 3849 * src_id src_data description 3850 * 1 0 D1 Vblank 3851 * 1 1 D1 Vline 3852 * 5 0 D2 Vblank 3853 * 5 1 D2 Vline 3854 * 19 0 FP Hot plug detection A 3855 * 19 1 FP Hot plug detection B 3856 * 19 2 DAC A auto-detection 3857 * 19 3 DAC B auto-detection 3858 * 21 4 HDMI block A 3859 * 21 5 HDMI block B 3860 * 176 - CP_INT RB 3861 * 177 - CP_INT IB1 3862 * 178 - CP_INT IB2 3863 * 181 - EOP Interrupt 3864 * 233 - GUI Idle 3865 * 3866 * Note, these are based on r600 and may need to be 3867 * adjusted or added to on newer asics 3868 */ 3869 3870 irqreturn_t r600_irq_process(struct radeon_device *rdev) 3871 { 3872 u32 wptr; 3873 u32 rptr; 3874 u32 src_id, src_data; 3875 u32 ring_index; 3876 bool queue_hotplug = false; 3877 bool queue_hdmi = false; 3878 bool queue_thermal = false; 3879 3880 if (!rdev->ih.enabled || rdev->shutdown) 3881 return IRQ_NONE; 3882 3883 /* No MSIs, need a dummy read to flush PCI DMAs */ 3884 if (!rdev->msi_enabled) 3885 RREG32(IH_RB_WPTR); 3886 3887 wptr = r600_get_ih_wptr(rdev); 3888 3889 restart_ih: 3890 /* is somebody else already processing irqs? */ 3891 if (atomic_xchg(&rdev->ih.lock, 1)) 3892 return IRQ_NONE; 3893 3894 rptr = rdev->ih.rptr; 3895 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3896 3897 /* Order reading of wptr vs. reading of IH ring data */ 3898 rmb(); 3899 3900 /* display interrupts */ 3901 r600_irq_ack(rdev); 3902 3903 while (rptr != wptr) { 3904 /* wptr/rptr are in bytes! */ 3905 ring_index = rptr / 4; 3906 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3907 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3908 3909 switch (src_id) { 3910 case 1: /* D1 vblank/vline */ 3911 switch (src_data) { 3912 case 0: /* D1 vblank */ 3913 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3914 if (rdev->irq.crtc_vblank_int[0]) { 3915 drm_handle_vblank(rdev->ddev, 0); 3916 rdev->pm.vblank_sync = true; 3917 wake_up(&rdev->irq.vblank_queue); 3918 } 3919 if (atomic_read(&rdev->irq.pflip[0])) 3920 radeon_crtc_handle_vblank(rdev, 0); 3921 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3922 DRM_DEBUG("IH: D1 vblank\n"); 3923 } 3924 break; 3925 case 1: /* D1 vline */ 3926 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3927 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3928 DRM_DEBUG("IH: D1 vline\n"); 3929 } 3930 break; 3931 default: 3932 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3933 break; 3934 } 3935 break; 3936 case 5: /* D2 vblank/vline */ 3937 switch (src_data) { 3938 case 0: /* D2 vblank */ 3939 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3940 if (rdev->irq.crtc_vblank_int[1]) { 3941 drm_handle_vblank(rdev->ddev, 1); 3942 rdev->pm.vblank_sync = true; 3943 wake_up(&rdev->irq.vblank_queue); 3944 } 3945 if (atomic_read(&rdev->irq.pflip[1])) 3946 radeon_crtc_handle_vblank(rdev, 1); 3947 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3948 DRM_DEBUG("IH: D2 vblank\n"); 3949 } 3950 break; 3951 case 1: /* D1 vline */ 3952 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3953 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3954 DRM_DEBUG("IH: D2 vline\n"); 3955 } 3956 break; 3957 default: 3958 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3959 break; 3960 } 3961 break; 3962 case 9: /* D1 pflip */ 3963 DRM_DEBUG("IH: D1 flip\n"); 3964 if (radeon_use_pflipirq > 0) 3965 radeon_crtc_handle_flip(rdev, 0); 3966 break; 3967 case 11: /* D2 pflip */ 3968 DRM_DEBUG("IH: D2 flip\n"); 3969 if (radeon_use_pflipirq > 0) 3970 radeon_crtc_handle_flip(rdev, 1); 3971 break; 3972 case 19: /* HPD/DAC hotplug */ 3973 switch (src_data) { 3974 case 0: 3975 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3976 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3977 queue_hotplug = true; 3978 DRM_DEBUG("IH: HPD1\n"); 3979 } 3980 break; 3981 case 1: 3982 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3983 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3984 queue_hotplug = true; 3985 DRM_DEBUG("IH: HPD2\n"); 3986 } 3987 break; 3988 case 4: 3989 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3990 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3991 queue_hotplug = true; 3992 DRM_DEBUG("IH: HPD3\n"); 3993 } 3994 break; 3995 case 5: 3996 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3997 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3998 queue_hotplug = true; 3999 DRM_DEBUG("IH: HPD4\n"); 4000 } 4001 break; 4002 case 10: 4003 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4004 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4005 queue_hotplug = true; 4006 DRM_DEBUG("IH: HPD5\n"); 4007 } 4008 break; 4009 case 12: 4010 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4011 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4012 queue_hotplug = true; 4013 DRM_DEBUG("IH: HPD6\n"); 4014 } 4015 break; 4016 default: 4017 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4018 break; 4019 } 4020 break; 4021 case 21: /* hdmi */ 4022 switch (src_data) { 4023 case 4: 4024 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4025 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4026 queue_hdmi = true; 4027 DRM_DEBUG("IH: HDMI0\n"); 4028 } 4029 break; 4030 case 5: 4031 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4032 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4033 queue_hdmi = true; 4034 DRM_DEBUG("IH: HDMI1\n"); 4035 } 4036 break; 4037 default: 4038 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4039 break; 4040 } 4041 break; 4042 case 124: /* UVD */ 4043 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4044 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4045 break; 4046 case 176: /* CP_INT in ring buffer */ 4047 case 177: /* CP_INT in IB1 */ 4048 case 178: /* CP_INT in IB2 */ 4049 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4050 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4051 break; 4052 case 181: /* CP EOP event */ 4053 DRM_DEBUG("IH: CP EOP\n"); 4054 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4055 break; 4056 case 224: /* DMA trap event */ 4057 DRM_DEBUG("IH: DMA trap\n"); 4058 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4059 break; 4060 case 230: /* thermal low to high */ 4061 DRM_DEBUG("IH: thermal low to high\n"); 4062 rdev->pm.dpm.thermal.high_to_low = false; 4063 queue_thermal = true; 4064 break; 4065 case 231: /* thermal high to low */ 4066 DRM_DEBUG("IH: thermal high to low\n"); 4067 rdev->pm.dpm.thermal.high_to_low = true; 4068 queue_thermal = true; 4069 break; 4070 case 233: /* GUI IDLE */ 4071 DRM_DEBUG("IH: GUI idle\n"); 4072 break; 4073 default: 4074 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4075 break; 4076 } 4077 4078 /* wptr/rptr are in bytes! */ 4079 rptr += 16; 4080 rptr &= rdev->ih.ptr_mask; 4081 WREG32(IH_RB_RPTR, rptr); 4082 } 4083 if (queue_hotplug) 4084 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 4085 if (queue_hdmi) 4086 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 4087 if (queue_thermal && rdev->pm.dpm_enabled) 4088 taskqueue_enqueue(rdev->tq, &rdev->pm.dpm.thermal.work); 4089 rdev->ih.rptr = rptr; 4090 atomic_set(&rdev->ih.lock, 0); 4091 4092 /* make sure wptr hasn't changed while processing */ 4093 wptr = r600_get_ih_wptr(rdev); 4094 if (wptr != rptr) 4095 goto restart_ih; 4096 4097 return IRQ_HANDLED; 4098 } 4099 4100 /* 4101 * Debugfs info 4102 */ 4103 #if defined(CONFIG_DEBUG_FS) 4104 4105 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4106 { 4107 struct drm_info_node *node = (struct drm_info_node *) m->private; 4108 struct drm_device *dev = node->minor->dev; 4109 struct radeon_device *rdev = dev->dev_private; 4110 4111 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4112 DREG32_SYS(m, rdev, VM_L2_STATUS); 4113 return 0; 4114 } 4115 4116 static struct drm_info_list r600_mc_info_list[] = { 4117 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4118 }; 4119 #endif 4120 4121 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4122 { 4123 #if defined(CONFIG_DEBUG_FS) 4124 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4125 #else 4126 return 0; 4127 #endif 4128 } 4129 4130 /** 4131 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4132 * rdev: radeon device structure 4133 * 4134 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4135 * through the ring buffer. This leads to corruption in rendering, see 4136 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4137 * directly perform the HDP flush by writing the register through MMIO. 4138 */ 4139 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4140 { 4141 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4142 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4143 * This seems to cause problems on some AGP cards. Just use the old 4144 * method for them. 4145 */ 4146 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4147 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4148 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4149 u32 tmp; 4150 4151 WREG32(HDP_DEBUG1, 0); 4152 tmp = *ptr; 4153 } else 4154 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4155 } 4156 4157 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4158 { 4159 u32 link_width_cntl, mask; 4160 4161 if (rdev->flags & RADEON_IS_IGP) 4162 return; 4163 4164 if (!(rdev->flags & RADEON_IS_PCIE)) 4165 return; 4166 4167 /* x2 cards have a special sequence */ 4168 if (ASIC_IS_X2(rdev)) 4169 return; 4170 4171 radeon_gui_idle(rdev); 4172 4173 switch (lanes) { 4174 case 0: 4175 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4176 break; 4177 case 1: 4178 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4179 break; 4180 case 2: 4181 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4182 break; 4183 case 4: 4184 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4185 break; 4186 case 8: 4187 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4188 break; 4189 case 12: 4190 /* not actually supported */ 4191 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4192 break; 4193 case 16: 4194 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4195 break; 4196 default: 4197 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4198 return; 4199 } 4200 4201 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4202 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4203 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4204 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4205 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4206 4207 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4208 } 4209 4210 int r600_get_pcie_lanes(struct radeon_device *rdev) 4211 { 4212 u32 link_width_cntl; 4213 4214 if (rdev->flags & RADEON_IS_IGP) 4215 return 0; 4216 4217 if (!(rdev->flags & RADEON_IS_PCIE)) 4218 return 0; 4219 4220 /* x2 cards have a special sequence */ 4221 if (ASIC_IS_X2(rdev)) 4222 return 0; 4223 4224 radeon_gui_idle(rdev); 4225 4226 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4227 4228 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4229 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4230 return 1; 4231 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4232 return 2; 4233 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4234 return 4; 4235 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4236 return 8; 4237 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4238 /* not actually supported */ 4239 return 12; 4240 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4241 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4242 default: 4243 return 16; 4244 } 4245 } 4246 4247 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4248 { 4249 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4250 u16 link_cntl2; 4251 u32 mask; 4252 int ret; 4253 4254 if (radeon_pcie_gen2 == 0) 4255 return; 4256 4257 if (rdev->flags & RADEON_IS_IGP) 4258 return; 4259 4260 if (!(rdev->flags & RADEON_IS_PCIE)) 4261 return; 4262 4263 /* x2 cards have a special sequence */ 4264 if (ASIC_IS_X2(rdev)) 4265 return; 4266 4267 /* only RV6xx+ chips are supported */ 4268 if (rdev->family <= CHIP_R600) 4269 return; 4270 4271 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4272 if (ret != 0) 4273 return; 4274 4275 if (!(mask & DRM_PCIE_SPEED_50)) 4276 return; 4277 4278 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4279 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4280 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4281 return; 4282 } 4283 4284 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4285 4286 /* 55 nm r6xx asics */ 4287 if ((rdev->family == CHIP_RV670) || 4288 (rdev->family == CHIP_RV620) || 4289 (rdev->family == CHIP_RV635)) { 4290 /* advertise upconfig capability */ 4291 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4292 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4293 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4294 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4295 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4296 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4297 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4298 LC_RECONFIG_ARC_MISSING_ESCAPE); 4299 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4300 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4301 } else { 4302 link_width_cntl |= LC_UPCONFIGURE_DIS; 4303 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4304 } 4305 } 4306 4307 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4308 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4309 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4310 4311 /* 55 nm r6xx asics */ 4312 if ((rdev->family == CHIP_RV670) || 4313 (rdev->family == CHIP_RV620) || 4314 (rdev->family == CHIP_RV635)) { 4315 WREG32(MM_CFGREGS_CNTL, 0x8); 4316 link_cntl2 = RREG32(0x4088); 4317 WREG32(MM_CFGREGS_CNTL, 0); 4318 /* not supported yet */ 4319 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4320 return; 4321 } 4322 4323 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4324 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4325 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4326 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4327 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4328 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4329 4330 tmp = RREG32(0x541c); 4331 WREG32(0x541c, tmp | 0x8); 4332 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4333 link_cntl2 = RREG16(0x4088); 4334 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4335 link_cntl2 |= 0x2; 4336 WREG16(0x4088, link_cntl2); 4337 WREG32(MM_CFGREGS_CNTL, 0); 4338 4339 if ((rdev->family == CHIP_RV670) || 4340 (rdev->family == CHIP_RV620) || 4341 (rdev->family == CHIP_RV635)) { 4342 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4343 training_cntl &= ~LC_POINT_7_PLUS_EN; 4344 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4345 } else { 4346 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4347 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4348 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4349 } 4350 4351 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4352 speed_cntl |= LC_GEN2_EN_STRAP; 4353 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4354 4355 } else { 4356 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4357 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4358 if (1) 4359 link_width_cntl |= LC_UPCONFIGURE_DIS; 4360 else 4361 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4362 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4363 } 4364 } 4365 4366 /** 4367 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4368 * 4369 * @rdev: radeon_device pointer 4370 * 4371 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4372 * Returns the 64 bit clock counter snapshot. 4373 */ 4374 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4375 { 4376 uint64_t clock; 4377 4378 spin_lock(&rdev->gpu_clock_mutex); 4379 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4380 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4381 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4382 spin_unlock(&rdev->gpu_clock_mutex); 4383 return clock; 4384 } 4385