1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <drm/drmP.h> 32 #include <drm/radeon_drm.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_mode.h" 36 #include "r600d.h" 37 #include "atom.h" 38 #include "avivod.h" 39 #include "radeon_ucode.h" 40 41 /* Firmware Names */ 42 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 43 MODULE_FIRMWARE("radeon/R600_me.bin"); 44 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 45 MODULE_FIRMWARE("radeon/RV610_me.bin"); 46 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 47 MODULE_FIRMWARE("radeon/RV630_me.bin"); 48 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 49 MODULE_FIRMWARE("radeon/RV620_me.bin"); 50 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV635_me.bin"); 52 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV670_me.bin"); 54 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RS780_me.bin"); 56 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV770_me.bin"); 58 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 59 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV730_me.bin"); 61 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 62 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 63 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RV710_me.bin"); 65 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 66 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 67 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 68 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 69 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 72 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 73 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 76 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 77 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 80 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 81 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 84 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 85 MODULE_FIRMWARE("radeon/PALM_me.bin"); 86 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 87 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 89 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 90 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 91 MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 92 MODULE_FIRMWARE("radeon/OLAND_me.bin"); 93 MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 94 MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 95 MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 96 97 static const u32 crtc_offsets[2] = 98 { 99 0, 100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 101 }; 102 103 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 104 105 /* r600,rv610,rv630,rv620,rv635,rv670 */ 106 static void r600_gpu_init(struct radeon_device *rdev); 107 void r600_irq_disable(struct radeon_device *rdev); 108 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 109 110 /** 111 * r600_get_xclk - get the xclk 112 * 113 * @rdev: radeon_device pointer 114 * 115 * Returns the reference clock used by the gfx engine 116 * (r6xx, IGPs, APUs). 117 */ 118 u32 r600_get_xclk(struct radeon_device *rdev) 119 { 120 return rdev->clock.spll.reference_freq; 121 } 122 123 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 124 { 125 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 126 int r; 127 128 /* bypass vclk and dclk with bclk */ 129 WREG32_P(CG_UPLL_FUNC_CNTL_2, 130 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 131 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 132 133 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 134 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 135 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 136 137 if (rdev->family >= CHIP_RS780) 138 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 139 ~UPLL_BYPASS_CNTL); 140 141 if (!vclk || !dclk) { 142 /* keep the Bypass mode, put PLL to sleep */ 143 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 144 return 0; 145 } 146 147 if (rdev->clock.spll.reference_freq == 10000) 148 ref_div = 34; 149 else 150 ref_div = 4; 151 152 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 153 ref_div + 1, 0xFFF, 2, 30, ~0, 154 &fb_div, &vclk_div, &dclk_div); 155 if (r) 156 return r; 157 158 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 159 fb_div >>= 1; 160 else 161 fb_div |= 1; 162 163 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 164 if (r) 165 return r; 166 167 /* assert PLL_RESET */ 168 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 169 170 /* For RS780 we have to choose ref clk */ 171 if (rdev->family >= CHIP_RS780) 172 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 173 ~UPLL_REFCLK_SRC_SEL_MASK); 174 175 /* set the required fb, ref and post divder values */ 176 WREG32_P(CG_UPLL_FUNC_CNTL, 177 UPLL_FB_DIV(fb_div) | 178 UPLL_REF_DIV(ref_div), 179 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 180 WREG32_P(CG_UPLL_FUNC_CNTL_2, 181 UPLL_SW_HILEN(vclk_div >> 1) | 182 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 183 UPLL_SW_HILEN2(dclk_div >> 1) | 184 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 185 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 186 ~UPLL_SW_MASK); 187 188 /* give the PLL some time to settle */ 189 mdelay(15); 190 191 /* deassert PLL_RESET */ 192 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 193 194 mdelay(15); 195 196 /* deassert BYPASS EN */ 197 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 198 199 if (rdev->family >= CHIP_RS780) 200 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 201 202 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 203 if (r) 204 return r; 205 206 /* switch VCLK and DCLK selection */ 207 WREG32_P(CG_UPLL_FUNC_CNTL_2, 208 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 209 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 210 211 mdelay(100); 212 213 return 0; 214 } 215 216 void dce3_program_fmt(struct drm_encoder *encoder) 217 { 218 struct drm_device *dev = encoder->dev; 219 struct radeon_device *rdev = dev->dev_private; 220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 222 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 223 int bpc = 0; 224 u32 tmp = 0; 225 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 226 227 if (connector) { 228 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 229 bpc = radeon_get_monitor_bpc(connector); 230 dither = radeon_connector->dither; 231 } 232 233 /* LVDS FMT is set up by atom */ 234 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 235 return; 236 237 /* not needed for analog */ 238 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 239 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 240 return; 241 242 if (bpc == 0) 243 return; 244 245 switch (bpc) { 246 case 6: 247 if (dither == RADEON_FMT_DITHER_ENABLE) 248 /* XXX sort out optimal dither settings */ 249 tmp |= FMT_SPATIAL_DITHER_EN; 250 else 251 tmp |= FMT_TRUNCATE_EN; 252 break; 253 case 8: 254 if (dither == RADEON_FMT_DITHER_ENABLE) 255 /* XXX sort out optimal dither settings */ 256 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 257 else 258 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 259 break; 260 case 10: 261 default: 262 /* not needed */ 263 break; 264 } 265 266 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 267 } 268 269 /* get temperature in millidegrees */ 270 int rv6xx_get_temp(struct radeon_device *rdev) 271 { 272 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 273 ASIC_T_SHIFT; 274 int actual_temp = temp & 0xff; 275 276 if (temp & 0x100) 277 actual_temp -= 256; 278 279 return actual_temp * 1000; 280 } 281 282 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 283 { 284 int i; 285 286 rdev->pm.dynpm_can_upclock = true; 287 rdev->pm.dynpm_can_downclock = true; 288 289 /* power state array is low to high, default is first */ 290 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 291 int min_power_state_index = 0; 292 293 if (rdev->pm.num_power_states > 2) 294 min_power_state_index = 1; 295 296 switch (rdev->pm.dynpm_planned_action) { 297 case DYNPM_ACTION_MINIMUM: 298 rdev->pm.requested_power_state_index = min_power_state_index; 299 rdev->pm.requested_clock_mode_index = 0; 300 rdev->pm.dynpm_can_downclock = false; 301 break; 302 case DYNPM_ACTION_DOWNCLOCK: 303 if (rdev->pm.current_power_state_index == min_power_state_index) { 304 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 305 rdev->pm.dynpm_can_downclock = false; 306 } else { 307 if (rdev->pm.active_crtc_count > 1) { 308 for (i = 0; i < rdev->pm.num_power_states; i++) { 309 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 310 continue; 311 else if (i >= rdev->pm.current_power_state_index) { 312 rdev->pm.requested_power_state_index = 313 rdev->pm.current_power_state_index; 314 break; 315 } else { 316 rdev->pm.requested_power_state_index = i; 317 break; 318 } 319 } 320 } else { 321 if (rdev->pm.current_power_state_index == 0) 322 rdev->pm.requested_power_state_index = 323 rdev->pm.num_power_states - 1; 324 else 325 rdev->pm.requested_power_state_index = 326 rdev->pm.current_power_state_index - 1; 327 } 328 } 329 rdev->pm.requested_clock_mode_index = 0; 330 /* don't use the power state if crtcs are active and no display flag is set */ 331 if ((rdev->pm.active_crtc_count > 0) && 332 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 333 clock_info[rdev->pm.requested_clock_mode_index].flags & 334 RADEON_PM_MODE_NO_DISPLAY)) { 335 rdev->pm.requested_power_state_index++; 336 } 337 break; 338 case DYNPM_ACTION_UPCLOCK: 339 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 340 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 341 rdev->pm.dynpm_can_upclock = false; 342 } else { 343 if (rdev->pm.active_crtc_count > 1) { 344 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 345 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 346 continue; 347 else if (i <= rdev->pm.current_power_state_index) { 348 rdev->pm.requested_power_state_index = 349 rdev->pm.current_power_state_index; 350 break; 351 } else { 352 rdev->pm.requested_power_state_index = i; 353 break; 354 } 355 } 356 } else 357 rdev->pm.requested_power_state_index = 358 rdev->pm.current_power_state_index + 1; 359 } 360 rdev->pm.requested_clock_mode_index = 0; 361 break; 362 case DYNPM_ACTION_DEFAULT: 363 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 364 rdev->pm.requested_clock_mode_index = 0; 365 rdev->pm.dynpm_can_upclock = false; 366 break; 367 case DYNPM_ACTION_NONE: 368 default: 369 DRM_ERROR("Requested mode for not defined action\n"); 370 return; 371 } 372 } else { 373 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 374 /* for now just select the first power state and switch between clock modes */ 375 /* power state array is low to high, default is first (0) */ 376 if (rdev->pm.active_crtc_count > 1) { 377 rdev->pm.requested_power_state_index = -1; 378 /* start at 1 as we don't want the default mode */ 379 for (i = 1; i < rdev->pm.num_power_states; i++) { 380 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 381 continue; 382 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 383 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 384 rdev->pm.requested_power_state_index = i; 385 break; 386 } 387 } 388 /* if nothing selected, grab the default state. */ 389 if (rdev->pm.requested_power_state_index == -1) 390 rdev->pm.requested_power_state_index = 0; 391 } else 392 rdev->pm.requested_power_state_index = 1; 393 394 switch (rdev->pm.dynpm_planned_action) { 395 case DYNPM_ACTION_MINIMUM: 396 rdev->pm.requested_clock_mode_index = 0; 397 rdev->pm.dynpm_can_downclock = false; 398 break; 399 case DYNPM_ACTION_DOWNCLOCK: 400 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 401 if (rdev->pm.current_clock_mode_index == 0) { 402 rdev->pm.requested_clock_mode_index = 0; 403 rdev->pm.dynpm_can_downclock = false; 404 } else 405 rdev->pm.requested_clock_mode_index = 406 rdev->pm.current_clock_mode_index - 1; 407 } else { 408 rdev->pm.requested_clock_mode_index = 0; 409 rdev->pm.dynpm_can_downclock = false; 410 } 411 /* don't use the power state if crtcs are active and no display flag is set */ 412 if ((rdev->pm.active_crtc_count > 0) && 413 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 414 clock_info[rdev->pm.requested_clock_mode_index].flags & 415 RADEON_PM_MODE_NO_DISPLAY)) { 416 rdev->pm.requested_clock_mode_index++; 417 } 418 break; 419 case DYNPM_ACTION_UPCLOCK: 420 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 421 if (rdev->pm.current_clock_mode_index == 422 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 423 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 424 rdev->pm.dynpm_can_upclock = false; 425 } else 426 rdev->pm.requested_clock_mode_index = 427 rdev->pm.current_clock_mode_index + 1; 428 } else { 429 rdev->pm.requested_clock_mode_index = 430 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 431 rdev->pm.dynpm_can_upclock = false; 432 } 433 break; 434 case DYNPM_ACTION_DEFAULT: 435 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 436 rdev->pm.requested_clock_mode_index = 0; 437 rdev->pm.dynpm_can_upclock = false; 438 break; 439 case DYNPM_ACTION_NONE: 440 default: 441 DRM_ERROR("Requested mode for not defined action\n"); 442 return; 443 } 444 } 445 446 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 447 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 448 clock_info[rdev->pm.requested_clock_mode_index].sclk, 449 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 450 clock_info[rdev->pm.requested_clock_mode_index].mclk, 451 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 452 pcie_lanes); 453 } 454 455 void rs780_pm_init_profile(struct radeon_device *rdev) 456 { 457 if (rdev->pm.num_power_states == 2) { 458 /* default */ 459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 460 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 461 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 462 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 463 /* low sh */ 464 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 465 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 466 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 467 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 468 /* mid sh */ 469 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 470 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 471 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 472 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 473 /* high sh */ 474 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 475 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 476 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 477 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 478 /* low mh */ 479 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 480 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 481 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 482 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 483 /* mid mh */ 484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 485 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 486 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 487 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 488 /* high mh */ 489 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 490 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 491 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 492 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 493 } else if (rdev->pm.num_power_states == 3) { 494 /* default */ 495 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 496 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 497 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 498 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 499 /* low sh */ 500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 504 /* mid sh */ 505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 507 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 509 /* high sh */ 510 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 512 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 514 /* low mh */ 515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 518 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 519 /* mid mh */ 520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 523 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 524 /* high mh */ 525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 529 } else { 530 /* default */ 531 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 532 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 533 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 534 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 535 /* low sh */ 536 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 537 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 538 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 539 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 540 /* mid sh */ 541 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 542 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 543 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 544 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 545 /* high sh */ 546 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 547 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 550 /* low mh */ 551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 552 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 554 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 555 /* mid mh */ 556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 557 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 560 /* high mh */ 561 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 562 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 563 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 565 } 566 } 567 568 void r600_pm_init_profile(struct radeon_device *rdev) 569 { 570 int idx; 571 572 if (rdev->family == CHIP_R600) { 573 /* XXX */ 574 /* default */ 575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 579 /* low sh */ 580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 584 /* mid sh */ 585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 589 /* high sh */ 590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 594 /* low mh */ 595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 599 /* mid mh */ 600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 604 /* high mh */ 605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 609 } else { 610 if (rdev->pm.num_power_states < 4) { 611 /* default */ 612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 615 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 616 /* low sh */ 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 620 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 621 /* mid sh */ 622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 625 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 626 /* high sh */ 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 630 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 631 /* low mh */ 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 635 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 636 /* low mh */ 637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 640 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 641 /* high mh */ 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 645 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 646 } else { 647 /* default */ 648 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 649 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 650 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 651 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 652 /* low sh */ 653 if (rdev->flags & RADEON_IS_MOBILITY) 654 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 655 else 656 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 657 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 658 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 659 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 661 /* mid sh */ 662 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 663 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 664 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 666 /* high sh */ 667 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 668 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 669 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 672 /* low mh */ 673 if (rdev->flags & RADEON_IS_MOBILITY) 674 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 675 else 676 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 679 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 680 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 681 /* mid mh */ 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 684 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 685 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 686 /* high mh */ 687 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 689 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 690 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 691 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 692 } 693 } 694 } 695 696 void r600_pm_misc(struct radeon_device *rdev) 697 { 698 int req_ps_idx = rdev->pm.requested_power_state_index; 699 int req_cm_idx = rdev->pm.requested_clock_mode_index; 700 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 701 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 702 703 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 704 /* 0xff01 is a flag rather then an actual voltage */ 705 if (voltage->voltage == 0xff01) 706 return; 707 if (voltage->voltage != rdev->pm.current_vddc) { 708 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 709 rdev->pm.current_vddc = voltage->voltage; 710 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 711 } 712 } 713 } 714 715 bool r600_gui_idle(struct radeon_device *rdev) 716 { 717 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 718 return false; 719 else 720 return true; 721 } 722 723 /* hpd for digital panel detect/disconnect */ 724 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 725 { 726 bool connected = false; 727 728 if (ASIC_IS_DCE3(rdev)) { 729 switch (hpd) { 730 case RADEON_HPD_1: 731 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 732 connected = true; 733 break; 734 case RADEON_HPD_2: 735 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 736 connected = true; 737 break; 738 case RADEON_HPD_3: 739 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 740 connected = true; 741 break; 742 case RADEON_HPD_4: 743 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 744 connected = true; 745 break; 746 /* DCE 3.2 */ 747 case RADEON_HPD_5: 748 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 749 connected = true; 750 break; 751 case RADEON_HPD_6: 752 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 753 connected = true; 754 break; 755 default: 756 break; 757 } 758 } else { 759 switch (hpd) { 760 case RADEON_HPD_1: 761 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 762 connected = true; 763 break; 764 case RADEON_HPD_2: 765 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 766 connected = true; 767 break; 768 case RADEON_HPD_3: 769 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 770 connected = true; 771 break; 772 default: 773 break; 774 } 775 } 776 return connected; 777 } 778 779 void r600_hpd_set_polarity(struct radeon_device *rdev, 780 enum radeon_hpd_id hpd) 781 { 782 u32 tmp; 783 bool connected = r600_hpd_sense(rdev, hpd); 784 785 if (ASIC_IS_DCE3(rdev)) { 786 switch (hpd) { 787 case RADEON_HPD_1: 788 tmp = RREG32(DC_HPD1_INT_CONTROL); 789 if (connected) 790 tmp &= ~DC_HPDx_INT_POLARITY; 791 else 792 tmp |= DC_HPDx_INT_POLARITY; 793 WREG32(DC_HPD1_INT_CONTROL, tmp); 794 break; 795 case RADEON_HPD_2: 796 tmp = RREG32(DC_HPD2_INT_CONTROL); 797 if (connected) 798 tmp &= ~DC_HPDx_INT_POLARITY; 799 else 800 tmp |= DC_HPDx_INT_POLARITY; 801 WREG32(DC_HPD2_INT_CONTROL, tmp); 802 break; 803 case RADEON_HPD_3: 804 tmp = RREG32(DC_HPD3_INT_CONTROL); 805 if (connected) 806 tmp &= ~DC_HPDx_INT_POLARITY; 807 else 808 tmp |= DC_HPDx_INT_POLARITY; 809 WREG32(DC_HPD3_INT_CONTROL, tmp); 810 break; 811 case RADEON_HPD_4: 812 tmp = RREG32(DC_HPD4_INT_CONTROL); 813 if (connected) 814 tmp &= ~DC_HPDx_INT_POLARITY; 815 else 816 tmp |= DC_HPDx_INT_POLARITY; 817 WREG32(DC_HPD4_INT_CONTROL, tmp); 818 break; 819 case RADEON_HPD_5: 820 tmp = RREG32(DC_HPD5_INT_CONTROL); 821 if (connected) 822 tmp &= ~DC_HPDx_INT_POLARITY; 823 else 824 tmp |= DC_HPDx_INT_POLARITY; 825 WREG32(DC_HPD5_INT_CONTROL, tmp); 826 break; 827 /* DCE 3.2 */ 828 case RADEON_HPD_6: 829 tmp = RREG32(DC_HPD6_INT_CONTROL); 830 if (connected) 831 tmp &= ~DC_HPDx_INT_POLARITY; 832 else 833 tmp |= DC_HPDx_INT_POLARITY; 834 WREG32(DC_HPD6_INT_CONTROL, tmp); 835 break; 836 default: 837 break; 838 } 839 } else { 840 switch (hpd) { 841 case RADEON_HPD_1: 842 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 843 if (connected) 844 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 845 else 846 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 847 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 848 break; 849 case RADEON_HPD_2: 850 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 851 if (connected) 852 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 853 else 854 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 855 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 856 break; 857 case RADEON_HPD_3: 858 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 859 if (connected) 860 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 861 else 862 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 863 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 864 break; 865 default: 866 break; 867 } 868 } 869 } 870 871 void r600_hpd_init(struct radeon_device *rdev) 872 { 873 struct drm_device *dev = rdev->ddev; 874 struct drm_connector *connector; 875 unsigned enable = 0; 876 877 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 878 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 879 880 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 881 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 882 /* don't try to enable hpd on eDP or LVDS avoid breaking the 883 * aux dp channel on imac and help (but not completely fix) 884 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 885 */ 886 continue; 887 } 888 if (ASIC_IS_DCE3(rdev)) { 889 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 890 if (ASIC_IS_DCE32(rdev)) 891 tmp |= DC_HPDx_EN; 892 893 switch (radeon_connector->hpd.hpd) { 894 case RADEON_HPD_1: 895 WREG32(DC_HPD1_CONTROL, tmp); 896 break; 897 case RADEON_HPD_2: 898 WREG32(DC_HPD2_CONTROL, tmp); 899 break; 900 case RADEON_HPD_3: 901 WREG32(DC_HPD3_CONTROL, tmp); 902 break; 903 case RADEON_HPD_4: 904 WREG32(DC_HPD4_CONTROL, tmp); 905 break; 906 /* DCE 3.2 */ 907 case RADEON_HPD_5: 908 WREG32(DC_HPD5_CONTROL, tmp); 909 break; 910 case RADEON_HPD_6: 911 WREG32(DC_HPD6_CONTROL, tmp); 912 break; 913 default: 914 break; 915 } 916 } else { 917 switch (radeon_connector->hpd.hpd) { 918 case RADEON_HPD_1: 919 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 920 break; 921 case RADEON_HPD_2: 922 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 923 break; 924 case RADEON_HPD_3: 925 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 926 break; 927 default: 928 break; 929 } 930 } 931 enable |= 1 << radeon_connector->hpd.hpd; 932 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 933 } 934 radeon_irq_kms_enable_hpd(rdev, enable); 935 } 936 937 void r600_hpd_fini(struct radeon_device *rdev) 938 { 939 struct drm_device *dev = rdev->ddev; 940 struct drm_connector *connector; 941 unsigned disable = 0; 942 943 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 944 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 945 if (ASIC_IS_DCE3(rdev)) { 946 switch (radeon_connector->hpd.hpd) { 947 case RADEON_HPD_1: 948 WREG32(DC_HPD1_CONTROL, 0); 949 break; 950 case RADEON_HPD_2: 951 WREG32(DC_HPD2_CONTROL, 0); 952 break; 953 case RADEON_HPD_3: 954 WREG32(DC_HPD3_CONTROL, 0); 955 break; 956 case RADEON_HPD_4: 957 WREG32(DC_HPD4_CONTROL, 0); 958 break; 959 /* DCE 3.2 */ 960 case RADEON_HPD_5: 961 WREG32(DC_HPD5_CONTROL, 0); 962 break; 963 case RADEON_HPD_6: 964 WREG32(DC_HPD6_CONTROL, 0); 965 break; 966 default: 967 break; 968 } 969 } else { 970 switch (radeon_connector->hpd.hpd) { 971 case RADEON_HPD_1: 972 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 973 break; 974 case RADEON_HPD_2: 975 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 976 break; 977 case RADEON_HPD_3: 978 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 979 break; 980 default: 981 break; 982 } 983 } 984 disable |= 1 << radeon_connector->hpd.hpd; 985 } 986 radeon_irq_kms_disable_hpd(rdev, disable); 987 } 988 989 /* 990 * R600 PCIE GART 991 */ 992 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 993 { 994 unsigned i; 995 u32 tmp; 996 997 /* flush hdp cache so updates hit vram */ 998 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 999 !(rdev->flags & RADEON_IS_AGP)) { 1000 volatile uint32_t *ptr = rdev->gart.ptr; 1001 u32 tmp; 1002 1003 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1004 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1005 * This seems to cause problems on some AGP cards. Just use the old 1006 * method for them. 1007 */ 1008 WREG32(HDP_DEBUG1, 0); 1009 tmp = *ptr; 1010 } else 1011 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1012 1013 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1014 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1015 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1016 for (i = 0; i < rdev->usec_timeout; i++) { 1017 /* read MC_STATUS */ 1018 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1019 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1020 if (tmp == 2) { 1021 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1022 return; 1023 } 1024 if (tmp) { 1025 return; 1026 } 1027 udelay(1); 1028 } 1029 } 1030 1031 int r600_pcie_gart_init(struct radeon_device *rdev) 1032 { 1033 int r; 1034 1035 if (rdev->gart.robj) { 1036 WARN(1, "R600 PCIE GART already initialized\n"); 1037 return 0; 1038 } 1039 /* Initialize common gart structure */ 1040 r = radeon_gart_init(rdev); 1041 if (r) 1042 return r; 1043 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1044 return radeon_gart_table_vram_alloc(rdev); 1045 } 1046 1047 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1048 { 1049 u32 tmp; 1050 int r, i; 1051 1052 if (rdev->gart.robj == NULL) { 1053 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1054 return -EINVAL; 1055 } 1056 r = radeon_gart_table_vram_pin(rdev); 1057 if (r) 1058 return r; 1059 1060 /* Setup L2 cache */ 1061 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1062 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1063 EFFECTIVE_L2_QUEUE_SIZE(7)); 1064 WREG32(VM_L2_CNTL2, 0); 1065 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1066 /* Setup TLB control */ 1067 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1068 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1069 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1070 ENABLE_WAIT_L2_QUERY; 1071 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1072 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1073 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1074 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1075 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1076 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1077 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1078 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1079 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1080 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1081 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1082 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1083 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1084 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1085 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1086 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1087 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1088 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1089 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1090 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1091 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1092 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1093 (u32)(rdev->dummy_page.addr >> 12)); 1094 for (i = 1; i < 7; i++) 1095 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1096 1097 r600_pcie_gart_tlb_flush(rdev); 1098 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1099 (unsigned)(rdev->mc.gtt_size >> 20), 1100 (unsigned long long)rdev->gart.table_addr); 1101 rdev->gart.ready = true; 1102 return 0; 1103 } 1104 1105 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1106 { 1107 u32 tmp; 1108 int i; 1109 1110 /* Disable all tables */ 1111 for (i = 0; i < 7; i++) 1112 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1113 1114 /* Disable L2 cache */ 1115 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1116 EFFECTIVE_L2_QUEUE_SIZE(7)); 1117 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1118 /* Setup L1 TLB control */ 1119 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1120 ENABLE_WAIT_L2_QUERY; 1121 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1122 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1123 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1124 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1125 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1126 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1127 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1128 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1129 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1130 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1131 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1132 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1133 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1134 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1135 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1136 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1137 radeon_gart_table_vram_unpin(rdev); 1138 } 1139 1140 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1141 { 1142 radeon_gart_fini(rdev); 1143 r600_pcie_gart_disable(rdev); 1144 radeon_gart_table_vram_free(rdev); 1145 } 1146 1147 static void r600_agp_enable(struct radeon_device *rdev) 1148 { 1149 u32 tmp; 1150 int i; 1151 1152 /* Setup L2 cache */ 1153 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1154 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1155 EFFECTIVE_L2_QUEUE_SIZE(7)); 1156 WREG32(VM_L2_CNTL2, 0); 1157 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1158 /* Setup TLB control */ 1159 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1160 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1161 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1162 ENABLE_WAIT_L2_QUERY; 1163 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1164 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1165 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1166 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1167 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1168 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1169 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1170 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1171 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1172 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1173 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1174 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1175 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1176 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1177 for (i = 0; i < 7; i++) 1178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1179 } 1180 1181 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1182 { 1183 unsigned i; 1184 u32 tmp; 1185 1186 for (i = 0; i < rdev->usec_timeout; i++) { 1187 /* read MC_STATUS */ 1188 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1189 if (!tmp) 1190 return 0; 1191 udelay(1); 1192 } 1193 return -1; 1194 } 1195 1196 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1197 { 1198 uint32_t r; 1199 1200 spin_lock(&rdev->mc_idx_lock); 1201 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1202 r = RREG32(R_0028FC_MC_DATA); 1203 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1204 spin_unlock(&rdev->mc_idx_lock); 1205 return r; 1206 } 1207 1208 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1209 { 1210 spin_lock(&rdev->mc_idx_lock); 1211 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1212 S_0028F8_MC_IND_WR_EN(1)); 1213 WREG32(R_0028FC_MC_DATA, v); 1214 WREG32(R_0028F8_MC_INDEX, 0x7F); 1215 spin_unlock(&rdev->mc_idx_lock); 1216 } 1217 1218 static void r600_mc_program(struct radeon_device *rdev) 1219 { 1220 struct rv515_mc_save save; 1221 u32 tmp; 1222 int i, j; 1223 1224 /* Initialize HDP */ 1225 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1226 WREG32((0x2c14 + j), 0x00000000); 1227 WREG32((0x2c18 + j), 0x00000000); 1228 WREG32((0x2c1c + j), 0x00000000); 1229 WREG32((0x2c20 + j), 0x00000000); 1230 WREG32((0x2c24 + j), 0x00000000); 1231 } 1232 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1233 1234 rv515_mc_stop(rdev, &save); 1235 if (r600_mc_wait_for_idle(rdev)) { 1236 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1237 } 1238 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1239 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1240 /* Update configuration */ 1241 if (rdev->flags & RADEON_IS_AGP) { 1242 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1243 /* VRAM before AGP */ 1244 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1245 rdev->mc.vram_start >> 12); 1246 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1247 rdev->mc.gtt_end >> 12); 1248 } else { 1249 /* VRAM after AGP */ 1250 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1251 rdev->mc.gtt_start >> 12); 1252 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1253 rdev->mc.vram_end >> 12); 1254 } 1255 } else { 1256 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1257 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1258 } 1259 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1260 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1261 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1262 WREG32(MC_VM_FB_LOCATION, tmp); 1263 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1264 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1265 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1266 if (rdev->flags & RADEON_IS_AGP) { 1267 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1268 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1269 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1270 } else { 1271 WREG32(MC_VM_AGP_BASE, 0); 1272 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1273 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1274 } 1275 if (r600_mc_wait_for_idle(rdev)) { 1276 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1277 } 1278 rv515_mc_resume(rdev, &save); 1279 /* we need to own VRAM, so turn off the VGA renderer here 1280 * to stop it overwriting our objects */ 1281 rv515_vga_render_disable(rdev); 1282 } 1283 1284 /** 1285 * r600_vram_gtt_location - try to find VRAM & GTT location 1286 * @rdev: radeon device structure holding all necessary informations 1287 * @mc: memory controller structure holding memory informations 1288 * 1289 * Function will place try to place VRAM at same place as in CPU (PCI) 1290 * address space as some GPU seems to have issue when we reprogram at 1291 * different address space. 1292 * 1293 * If there is not enough space to fit the unvisible VRAM after the 1294 * aperture then we limit the VRAM size to the aperture. 1295 * 1296 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1297 * them to be in one from GPU point of view so that we can program GPU to 1298 * catch access outside them (weird GPU policy see ??). 1299 * 1300 * This function will never fails, worst case are limiting VRAM or GTT. 1301 * 1302 * Note: GTT start, end, size should be initialized before calling this 1303 * function on AGP platform. 1304 */ 1305 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1306 { 1307 u64 size_bf, size_af; 1308 1309 if (mc->mc_vram_size > 0xE0000000) { 1310 /* leave room for at least 512M GTT */ 1311 dev_warn(rdev->dev, "limiting VRAM\n"); 1312 mc->real_vram_size = 0xE0000000; 1313 mc->mc_vram_size = 0xE0000000; 1314 } 1315 if (rdev->flags & RADEON_IS_AGP) { 1316 size_bf = mc->gtt_start; 1317 size_af = mc->mc_mask - mc->gtt_end; 1318 if (size_bf > size_af) { 1319 if (mc->mc_vram_size > size_bf) { 1320 dev_warn(rdev->dev, "limiting VRAM\n"); 1321 mc->real_vram_size = size_bf; 1322 mc->mc_vram_size = size_bf; 1323 } 1324 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1325 } else { 1326 if (mc->mc_vram_size > size_af) { 1327 dev_warn(rdev->dev, "limiting VRAM\n"); 1328 mc->real_vram_size = size_af; 1329 mc->mc_vram_size = size_af; 1330 } 1331 mc->vram_start = mc->gtt_end + 1; 1332 } 1333 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1334 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1335 mc->mc_vram_size >> 20, mc->vram_start, 1336 mc->vram_end, mc->real_vram_size >> 20); 1337 } else { 1338 u64 base = 0; 1339 if (rdev->flags & RADEON_IS_IGP) { 1340 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1341 base <<= 24; 1342 } 1343 radeon_vram_location(rdev, &rdev->mc, base); 1344 rdev->mc.gtt_base_align = 0; 1345 radeon_gtt_location(rdev, mc); 1346 } 1347 } 1348 1349 static int r600_mc_init(struct radeon_device *rdev) 1350 { 1351 u32 tmp; 1352 int chansize, numchan; 1353 uint32_t h_addr, l_addr; 1354 unsigned long long k8_addr; 1355 1356 /* Get VRAM informations */ 1357 rdev->mc.vram_is_ddr = true; 1358 tmp = RREG32(RAMCFG); 1359 if (tmp & CHANSIZE_OVERRIDE) { 1360 chansize = 16; 1361 } else if (tmp & CHANSIZE_MASK) { 1362 chansize = 64; 1363 } else { 1364 chansize = 32; 1365 } 1366 tmp = RREG32(CHMAP); 1367 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1368 case 0: 1369 default: 1370 numchan = 1; 1371 break; 1372 case 1: 1373 numchan = 2; 1374 break; 1375 case 2: 1376 numchan = 4; 1377 break; 1378 case 3: 1379 numchan = 8; 1380 break; 1381 } 1382 rdev->mc.vram_width = numchan * chansize; 1383 /* Could aper size report 0 ? */ 1384 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1385 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1386 /* Setup GPU memory space */ 1387 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1388 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1389 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1390 r600_vram_gtt_location(rdev, &rdev->mc); 1391 1392 if (rdev->flags & RADEON_IS_IGP) { 1393 rs690_pm_info(rdev); 1394 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1395 1396 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1397 /* Use K8 direct mapping for fast fb access. */ 1398 rdev->fastfb_working = false; 1399 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1400 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1401 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1402 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1403 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1404 #endif 1405 { 1406 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1407 * memory is present. 1408 */ 1409 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1410 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1411 (unsigned long long)rdev->mc.aper_base, k8_addr); 1412 rdev->mc.aper_base = (resource_size_t)k8_addr; 1413 rdev->fastfb_working = true; 1414 } 1415 } 1416 } 1417 } 1418 1419 radeon_update_bandwidth_info(rdev); 1420 return 0; 1421 } 1422 1423 int r600_vram_scratch_init(struct radeon_device *rdev) 1424 { 1425 int r; 1426 void *vram_scratch_ptr_ptr; 1427 1428 if (rdev->vram_scratch.robj == NULL) { 1429 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1430 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1431 0, NULL, &rdev->vram_scratch.robj); 1432 if (r) { 1433 return r; 1434 } 1435 } 1436 1437 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1438 if (unlikely(r != 0)) { 1439 radeon_bo_unref(&rdev->vram_scratch.robj); 1440 return r; 1441 } 1442 r = radeon_bo_pin(rdev->vram_scratch.robj, 1443 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1444 if (r) { 1445 radeon_bo_unreserve(rdev->vram_scratch.robj); 1446 radeon_bo_unref(&rdev->vram_scratch.robj); 1447 return r; 1448 } 1449 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1450 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1451 vram_scratch_ptr_ptr); 1452 if (r) 1453 radeon_bo_unpin(rdev->vram_scratch.robj); 1454 radeon_bo_unreserve(rdev->vram_scratch.robj); 1455 if (r) 1456 radeon_bo_unref(&rdev->vram_scratch.robj); 1457 1458 return r; 1459 } 1460 1461 void r600_vram_scratch_fini(struct radeon_device *rdev) 1462 { 1463 int r; 1464 1465 if (rdev->vram_scratch.robj == NULL) { 1466 return; 1467 } 1468 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1469 if (likely(r == 0)) { 1470 radeon_bo_kunmap(rdev->vram_scratch.robj); 1471 radeon_bo_unpin(rdev->vram_scratch.robj); 1472 radeon_bo_unreserve(rdev->vram_scratch.robj); 1473 } 1474 radeon_bo_unref(&rdev->vram_scratch.robj); 1475 } 1476 1477 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1478 { 1479 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1480 1481 if (hung) 1482 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1483 else 1484 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1485 1486 WREG32(R600_BIOS_3_SCRATCH, tmp); 1487 } 1488 1489 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1490 { 1491 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1492 RREG32(R_008010_GRBM_STATUS)); 1493 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1494 RREG32(R_008014_GRBM_STATUS2)); 1495 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1496 RREG32(R_000E50_SRBM_STATUS)); 1497 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1498 RREG32(CP_STALLED_STAT1)); 1499 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1500 RREG32(CP_STALLED_STAT2)); 1501 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1502 RREG32(CP_BUSY_STAT)); 1503 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1504 RREG32(CP_STAT)); 1505 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1506 RREG32(DMA_STATUS_REG)); 1507 } 1508 1509 static bool r600_is_display_hung(struct radeon_device *rdev) 1510 { 1511 u32 crtc_hung = 0; 1512 u32 crtc_status[2]; 1513 u32 i, j, tmp; 1514 1515 for (i = 0; i < rdev->num_crtc; i++) { 1516 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1517 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1518 crtc_hung |= (1 << i); 1519 } 1520 } 1521 1522 for (j = 0; j < 10; j++) { 1523 for (i = 0; i < rdev->num_crtc; i++) { 1524 if (crtc_hung & (1 << i)) { 1525 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1526 if (tmp != crtc_status[i]) 1527 crtc_hung &= ~(1 << i); 1528 } 1529 } 1530 if (crtc_hung == 0) 1531 return false; 1532 udelay(100); 1533 } 1534 1535 return true; 1536 } 1537 1538 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1539 { 1540 u32 reset_mask = 0; 1541 u32 tmp; 1542 1543 /* GRBM_STATUS */ 1544 tmp = RREG32(R_008010_GRBM_STATUS); 1545 if (rdev->family >= CHIP_RV770) { 1546 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1547 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1548 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1549 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1550 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1551 reset_mask |= RADEON_RESET_GFX; 1552 } else { 1553 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1554 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1555 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1556 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1557 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1558 reset_mask |= RADEON_RESET_GFX; 1559 } 1560 1561 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1562 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1563 reset_mask |= RADEON_RESET_CP; 1564 1565 if (G_008010_GRBM_EE_BUSY(tmp)) 1566 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1567 1568 /* DMA_STATUS_REG */ 1569 tmp = RREG32(DMA_STATUS_REG); 1570 if (!(tmp & DMA_IDLE)) 1571 reset_mask |= RADEON_RESET_DMA; 1572 1573 /* SRBM_STATUS */ 1574 tmp = RREG32(R_000E50_SRBM_STATUS); 1575 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1576 reset_mask |= RADEON_RESET_RLC; 1577 1578 if (G_000E50_IH_BUSY(tmp)) 1579 reset_mask |= RADEON_RESET_IH; 1580 1581 if (G_000E50_SEM_BUSY(tmp)) 1582 reset_mask |= RADEON_RESET_SEM; 1583 1584 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1585 reset_mask |= RADEON_RESET_GRBM; 1586 1587 if (G_000E50_VMC_BUSY(tmp)) 1588 reset_mask |= RADEON_RESET_VMC; 1589 1590 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1591 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1592 G_000E50_MCDW_BUSY(tmp)) 1593 reset_mask |= RADEON_RESET_MC; 1594 1595 if (r600_is_display_hung(rdev)) 1596 reset_mask |= RADEON_RESET_DISPLAY; 1597 1598 /* Skip MC reset as it's mostly likely not hung, just busy */ 1599 if (reset_mask & RADEON_RESET_MC) { 1600 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1601 reset_mask &= ~RADEON_RESET_MC; 1602 } 1603 1604 return reset_mask; 1605 } 1606 1607 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1608 { 1609 struct rv515_mc_save save; 1610 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1611 u32 tmp; 1612 1613 if (reset_mask == 0) 1614 return; 1615 1616 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1617 1618 r600_print_gpu_status_regs(rdev); 1619 1620 /* Disable CP parsing/prefetching */ 1621 if (rdev->family >= CHIP_RV770) 1622 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1623 else 1624 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1625 1626 /* disable the RLC */ 1627 WREG32(RLC_CNTL, 0); 1628 1629 if (reset_mask & RADEON_RESET_DMA) { 1630 /* Disable DMA */ 1631 tmp = RREG32(DMA_RB_CNTL); 1632 tmp &= ~DMA_RB_ENABLE; 1633 WREG32(DMA_RB_CNTL, tmp); 1634 } 1635 1636 mdelay(50); 1637 1638 rv515_mc_stop(rdev, &save); 1639 if (r600_mc_wait_for_idle(rdev)) { 1640 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1641 } 1642 1643 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1644 if (rdev->family >= CHIP_RV770) 1645 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1646 S_008020_SOFT_RESET_CB(1) | 1647 S_008020_SOFT_RESET_PA(1) | 1648 S_008020_SOFT_RESET_SC(1) | 1649 S_008020_SOFT_RESET_SPI(1) | 1650 S_008020_SOFT_RESET_SX(1) | 1651 S_008020_SOFT_RESET_SH(1) | 1652 S_008020_SOFT_RESET_TC(1) | 1653 S_008020_SOFT_RESET_TA(1) | 1654 S_008020_SOFT_RESET_VC(1) | 1655 S_008020_SOFT_RESET_VGT(1); 1656 else 1657 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1658 S_008020_SOFT_RESET_DB(1) | 1659 S_008020_SOFT_RESET_CB(1) | 1660 S_008020_SOFT_RESET_PA(1) | 1661 S_008020_SOFT_RESET_SC(1) | 1662 S_008020_SOFT_RESET_SMX(1) | 1663 S_008020_SOFT_RESET_SPI(1) | 1664 S_008020_SOFT_RESET_SX(1) | 1665 S_008020_SOFT_RESET_SH(1) | 1666 S_008020_SOFT_RESET_TC(1) | 1667 S_008020_SOFT_RESET_TA(1) | 1668 S_008020_SOFT_RESET_VC(1) | 1669 S_008020_SOFT_RESET_VGT(1); 1670 } 1671 1672 if (reset_mask & RADEON_RESET_CP) { 1673 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1674 S_008020_SOFT_RESET_VGT(1); 1675 1676 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1677 } 1678 1679 if (reset_mask & RADEON_RESET_DMA) { 1680 if (rdev->family >= CHIP_RV770) 1681 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1682 else 1683 srbm_soft_reset |= SOFT_RESET_DMA; 1684 } 1685 1686 if (reset_mask & RADEON_RESET_RLC) 1687 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1688 1689 if (reset_mask & RADEON_RESET_SEM) 1690 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1691 1692 if (reset_mask & RADEON_RESET_IH) 1693 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1694 1695 if (reset_mask & RADEON_RESET_GRBM) 1696 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1697 1698 if (!(rdev->flags & RADEON_IS_IGP)) { 1699 if (reset_mask & RADEON_RESET_MC) 1700 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1701 } 1702 1703 if (reset_mask & RADEON_RESET_VMC) 1704 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1705 1706 if (grbm_soft_reset) { 1707 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1708 tmp |= grbm_soft_reset; 1709 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1710 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1711 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1712 1713 udelay(50); 1714 1715 tmp &= ~grbm_soft_reset; 1716 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1717 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1718 } 1719 1720 if (srbm_soft_reset) { 1721 tmp = RREG32(SRBM_SOFT_RESET); 1722 tmp |= srbm_soft_reset; 1723 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1724 WREG32(SRBM_SOFT_RESET, tmp); 1725 tmp = RREG32(SRBM_SOFT_RESET); 1726 1727 udelay(50); 1728 1729 tmp &= ~srbm_soft_reset; 1730 WREG32(SRBM_SOFT_RESET, tmp); 1731 tmp = RREG32(SRBM_SOFT_RESET); 1732 } 1733 1734 /* Wait a little for things to settle down */ 1735 mdelay(1); 1736 1737 rv515_mc_resume(rdev, &save); 1738 udelay(50); 1739 1740 r600_print_gpu_status_regs(rdev); 1741 } 1742 1743 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1744 { 1745 struct rv515_mc_save save; 1746 u32 tmp, i; 1747 1748 dev_info(rdev->dev, "GPU pci config reset\n"); 1749 1750 /* disable dpm? */ 1751 1752 /* Disable CP parsing/prefetching */ 1753 if (rdev->family >= CHIP_RV770) 1754 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1755 else 1756 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1757 1758 /* disable the RLC */ 1759 WREG32(RLC_CNTL, 0); 1760 1761 /* Disable DMA */ 1762 tmp = RREG32(DMA_RB_CNTL); 1763 tmp &= ~DMA_RB_ENABLE; 1764 WREG32(DMA_RB_CNTL, tmp); 1765 1766 mdelay(50); 1767 1768 /* set mclk/sclk to bypass */ 1769 if (rdev->family >= CHIP_RV770) 1770 rv770_set_clk_bypass_mode(rdev); 1771 /* disable BM */ 1772 pci_disable_busmaster(rdev->pdev->dev.bsddev); 1773 /* disable mem access */ 1774 rv515_mc_stop(rdev, &save); 1775 if (r600_mc_wait_for_idle(rdev)) { 1776 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1777 } 1778 1779 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1780 tmp = RREG32(BUS_CNTL); 1781 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1782 WREG32(BUS_CNTL, tmp); 1783 1784 tmp = RREG32(BIF_SCRATCH0); 1785 1786 /* reset */ 1787 radeon_pci_config_reset(rdev); 1788 mdelay(1); 1789 1790 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1791 tmp = SOFT_RESET_BIF; 1792 WREG32(SRBM_SOFT_RESET, tmp); 1793 mdelay(1); 1794 WREG32(SRBM_SOFT_RESET, 0); 1795 1796 /* wait for asic to come out of reset */ 1797 for (i = 0; i < rdev->usec_timeout; i++) { 1798 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1799 break; 1800 udelay(1); 1801 } 1802 } 1803 1804 int r600_asic_reset(struct radeon_device *rdev) 1805 { 1806 u32 reset_mask; 1807 1808 reset_mask = r600_gpu_check_soft_reset(rdev); 1809 1810 if (reset_mask) 1811 r600_set_bios_scratch_engine_hung(rdev, true); 1812 1813 /* try soft reset */ 1814 r600_gpu_soft_reset(rdev, reset_mask); 1815 1816 reset_mask = r600_gpu_check_soft_reset(rdev); 1817 1818 /* try pci config reset */ 1819 if (reset_mask && radeon_hard_reset) 1820 r600_gpu_pci_config_reset(rdev); 1821 1822 reset_mask = r600_gpu_check_soft_reset(rdev); 1823 1824 if (!reset_mask) 1825 r600_set_bios_scratch_engine_hung(rdev, false); 1826 1827 return 0; 1828 } 1829 1830 /** 1831 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1832 * 1833 * @rdev: radeon_device pointer 1834 * @ring: radeon_ring structure holding ring information 1835 * 1836 * Check if the GFX engine is locked up. 1837 * Returns true if the engine appears to be locked up, false if not. 1838 */ 1839 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1840 { 1841 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1842 1843 if (!(reset_mask & (RADEON_RESET_GFX | 1844 RADEON_RESET_COMPUTE | 1845 RADEON_RESET_CP))) { 1846 radeon_ring_lockup_update(rdev, ring); 1847 return false; 1848 } 1849 return radeon_ring_test_lockup(rdev, ring); 1850 } 1851 1852 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1853 u32 tiling_pipe_num, 1854 u32 max_rb_num, 1855 u32 total_max_rb_num, 1856 u32 disabled_rb_mask) 1857 { 1858 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1859 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1860 u32 data = 0, mask = 1 << (max_rb_num - 1); 1861 unsigned i, j; 1862 1863 /* mask out the RBs that don't exist on that asic */ 1864 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1865 /* make sure at least one RB is available */ 1866 if ((tmp & 0xff) != 0xff) 1867 disabled_rb_mask = tmp; 1868 1869 rendering_pipe_num = 1 << tiling_pipe_num; 1870 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1871 BUG_ON(rendering_pipe_num < req_rb_num); 1872 1873 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1874 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1875 1876 if (rdev->family <= CHIP_RV740) { 1877 /* r6xx/r7xx */ 1878 rb_num_width = 2; 1879 } else { 1880 /* eg+ */ 1881 rb_num_width = 4; 1882 } 1883 1884 for (i = 0; i < max_rb_num; i++) { 1885 if (!(mask & disabled_rb_mask)) { 1886 for (j = 0; j < pipe_rb_ratio; j++) { 1887 data <<= rb_num_width; 1888 data |= max_rb_num - i - 1; 1889 } 1890 if (pipe_rb_remain) { 1891 data <<= rb_num_width; 1892 data |= max_rb_num - i - 1; 1893 pipe_rb_remain--; 1894 } 1895 } 1896 mask >>= 1; 1897 } 1898 1899 return data; 1900 } 1901 1902 int r600_count_pipe_bits(uint32_t val) 1903 { 1904 return hweight32(val); 1905 } 1906 1907 static void r600_gpu_init(struct radeon_device *rdev) 1908 { 1909 u32 tiling_config; 1910 u32 ramcfg; 1911 u32 cc_gc_shader_pipe_config; 1912 u32 tmp; 1913 int i, j; 1914 u32 sq_config; 1915 u32 sq_gpr_resource_mgmt_1 = 0; 1916 u32 sq_gpr_resource_mgmt_2 = 0; 1917 u32 sq_thread_resource_mgmt = 0; 1918 u32 sq_stack_resource_mgmt_1 = 0; 1919 u32 sq_stack_resource_mgmt_2 = 0; 1920 u32 disabled_rb_mask; 1921 1922 rdev->config.r600.tiling_group_size = 256; 1923 switch (rdev->family) { 1924 case CHIP_R600: 1925 rdev->config.r600.max_pipes = 4; 1926 rdev->config.r600.max_tile_pipes = 8; 1927 rdev->config.r600.max_simds = 4; 1928 rdev->config.r600.max_backends = 4; 1929 rdev->config.r600.max_gprs = 256; 1930 rdev->config.r600.max_threads = 192; 1931 rdev->config.r600.max_stack_entries = 256; 1932 rdev->config.r600.max_hw_contexts = 8; 1933 rdev->config.r600.max_gs_threads = 16; 1934 rdev->config.r600.sx_max_export_size = 128; 1935 rdev->config.r600.sx_max_export_pos_size = 16; 1936 rdev->config.r600.sx_max_export_smx_size = 128; 1937 rdev->config.r600.sq_num_cf_insts = 2; 1938 break; 1939 case CHIP_RV630: 1940 case CHIP_RV635: 1941 rdev->config.r600.max_pipes = 2; 1942 rdev->config.r600.max_tile_pipes = 2; 1943 rdev->config.r600.max_simds = 3; 1944 rdev->config.r600.max_backends = 1; 1945 rdev->config.r600.max_gprs = 128; 1946 rdev->config.r600.max_threads = 192; 1947 rdev->config.r600.max_stack_entries = 128; 1948 rdev->config.r600.max_hw_contexts = 8; 1949 rdev->config.r600.max_gs_threads = 4; 1950 rdev->config.r600.sx_max_export_size = 128; 1951 rdev->config.r600.sx_max_export_pos_size = 16; 1952 rdev->config.r600.sx_max_export_smx_size = 128; 1953 rdev->config.r600.sq_num_cf_insts = 2; 1954 break; 1955 case CHIP_RV610: 1956 case CHIP_RV620: 1957 case CHIP_RS780: 1958 case CHIP_RS880: 1959 rdev->config.r600.max_pipes = 1; 1960 rdev->config.r600.max_tile_pipes = 1; 1961 rdev->config.r600.max_simds = 2; 1962 rdev->config.r600.max_backends = 1; 1963 rdev->config.r600.max_gprs = 128; 1964 rdev->config.r600.max_threads = 192; 1965 rdev->config.r600.max_stack_entries = 128; 1966 rdev->config.r600.max_hw_contexts = 4; 1967 rdev->config.r600.max_gs_threads = 4; 1968 rdev->config.r600.sx_max_export_size = 128; 1969 rdev->config.r600.sx_max_export_pos_size = 16; 1970 rdev->config.r600.sx_max_export_smx_size = 128; 1971 rdev->config.r600.sq_num_cf_insts = 1; 1972 break; 1973 case CHIP_RV670: 1974 rdev->config.r600.max_pipes = 4; 1975 rdev->config.r600.max_tile_pipes = 4; 1976 rdev->config.r600.max_simds = 4; 1977 rdev->config.r600.max_backends = 4; 1978 rdev->config.r600.max_gprs = 192; 1979 rdev->config.r600.max_threads = 192; 1980 rdev->config.r600.max_stack_entries = 256; 1981 rdev->config.r600.max_hw_contexts = 8; 1982 rdev->config.r600.max_gs_threads = 16; 1983 rdev->config.r600.sx_max_export_size = 128; 1984 rdev->config.r600.sx_max_export_pos_size = 16; 1985 rdev->config.r600.sx_max_export_smx_size = 128; 1986 rdev->config.r600.sq_num_cf_insts = 2; 1987 break; 1988 default: 1989 break; 1990 } 1991 1992 /* Initialize HDP */ 1993 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1994 WREG32((0x2c14 + j), 0x00000000); 1995 WREG32((0x2c18 + j), 0x00000000); 1996 WREG32((0x2c1c + j), 0x00000000); 1997 WREG32((0x2c20 + j), 0x00000000); 1998 WREG32((0x2c24 + j), 0x00000000); 1999 } 2000 2001 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2002 2003 /* Setup tiling */ 2004 tiling_config = 0; 2005 ramcfg = RREG32(RAMCFG); 2006 switch (rdev->config.r600.max_tile_pipes) { 2007 case 1: 2008 tiling_config |= PIPE_TILING(0); 2009 break; 2010 case 2: 2011 tiling_config |= PIPE_TILING(1); 2012 break; 2013 case 4: 2014 tiling_config |= PIPE_TILING(2); 2015 break; 2016 case 8: 2017 tiling_config |= PIPE_TILING(3); 2018 break; 2019 default: 2020 break; 2021 } 2022 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2023 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2024 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2025 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2026 2027 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2028 if (tmp > 3) { 2029 tiling_config |= ROW_TILING(3); 2030 tiling_config |= SAMPLE_SPLIT(3); 2031 } else { 2032 tiling_config |= ROW_TILING(tmp); 2033 tiling_config |= SAMPLE_SPLIT(tmp); 2034 } 2035 tiling_config |= BANK_SWAPS(1); 2036 2037 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2038 tmp = rdev->config.r600.max_simds - 2039 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2040 rdev->config.r600.active_simds = tmp; 2041 2042 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2043 tmp = 0; 2044 for (i = 0; i < rdev->config.r600.max_backends; i++) 2045 tmp |= (1 << i); 2046 /* if all the backends are disabled, fix it up here */ 2047 if ((disabled_rb_mask & tmp) == tmp) { 2048 for (i = 0; i < rdev->config.r600.max_backends; i++) 2049 disabled_rb_mask &= ~(1 << i); 2050 } 2051 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2052 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2053 R6XX_MAX_BACKENDS, disabled_rb_mask); 2054 tiling_config |= tmp << 16; 2055 rdev->config.r600.backend_map = tmp; 2056 2057 rdev->config.r600.tile_config = tiling_config; 2058 WREG32(GB_TILING_CONFIG, tiling_config); 2059 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2060 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2061 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2062 2063 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2064 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2065 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2066 2067 /* Setup some CP states */ 2068 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2069 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2070 2071 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2072 SYNC_WALKER | SYNC_ALIGNER)); 2073 /* Setup various GPU states */ 2074 if (rdev->family == CHIP_RV670) 2075 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2076 2077 tmp = RREG32(SX_DEBUG_1); 2078 tmp |= SMX_EVENT_RELEASE; 2079 if ((rdev->family > CHIP_R600)) 2080 tmp |= ENABLE_NEW_SMX_ADDRESS; 2081 WREG32(SX_DEBUG_1, tmp); 2082 2083 if (((rdev->family) == CHIP_R600) || 2084 ((rdev->family) == CHIP_RV630) || 2085 ((rdev->family) == CHIP_RV610) || 2086 ((rdev->family) == CHIP_RV620) || 2087 ((rdev->family) == CHIP_RS780) || 2088 ((rdev->family) == CHIP_RS880)) { 2089 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2090 } else { 2091 WREG32(DB_DEBUG, 0); 2092 } 2093 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2094 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2095 2096 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2097 WREG32(VGT_NUM_INSTANCES, 0); 2098 2099 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2100 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2101 2102 tmp = RREG32(SQ_MS_FIFO_SIZES); 2103 if (((rdev->family) == CHIP_RV610) || 2104 ((rdev->family) == CHIP_RV620) || 2105 ((rdev->family) == CHIP_RS780) || 2106 ((rdev->family) == CHIP_RS880)) { 2107 tmp = (CACHE_FIFO_SIZE(0xa) | 2108 FETCH_FIFO_HIWATER(0xa) | 2109 DONE_FIFO_HIWATER(0xe0) | 2110 ALU_UPDATE_FIFO_HIWATER(0x8)); 2111 } else if (((rdev->family) == CHIP_R600) || 2112 ((rdev->family) == CHIP_RV630)) { 2113 tmp &= ~DONE_FIFO_HIWATER(0xff); 2114 tmp |= DONE_FIFO_HIWATER(0x4); 2115 } 2116 WREG32(SQ_MS_FIFO_SIZES, tmp); 2117 2118 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2119 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2120 */ 2121 sq_config = RREG32(SQ_CONFIG); 2122 sq_config &= ~(PS_PRIO(3) | 2123 VS_PRIO(3) | 2124 GS_PRIO(3) | 2125 ES_PRIO(3)); 2126 sq_config |= (DX9_CONSTS | 2127 VC_ENABLE | 2128 PS_PRIO(0) | 2129 VS_PRIO(1) | 2130 GS_PRIO(2) | 2131 ES_PRIO(3)); 2132 2133 if ((rdev->family) == CHIP_R600) { 2134 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2135 NUM_VS_GPRS(124) | 2136 NUM_CLAUSE_TEMP_GPRS(4)); 2137 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2138 NUM_ES_GPRS(0)); 2139 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2140 NUM_VS_THREADS(48) | 2141 NUM_GS_THREADS(4) | 2142 NUM_ES_THREADS(4)); 2143 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2144 NUM_VS_STACK_ENTRIES(128)); 2145 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2146 NUM_ES_STACK_ENTRIES(0)); 2147 } else if (((rdev->family) == CHIP_RV610) || 2148 ((rdev->family) == CHIP_RV620) || 2149 ((rdev->family) == CHIP_RS780) || 2150 ((rdev->family) == CHIP_RS880)) { 2151 /* no vertex cache */ 2152 sq_config &= ~VC_ENABLE; 2153 2154 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2155 NUM_VS_GPRS(44) | 2156 NUM_CLAUSE_TEMP_GPRS(2)); 2157 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2158 NUM_ES_GPRS(17)); 2159 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2160 NUM_VS_THREADS(78) | 2161 NUM_GS_THREADS(4) | 2162 NUM_ES_THREADS(31)); 2163 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2164 NUM_VS_STACK_ENTRIES(40)); 2165 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2166 NUM_ES_STACK_ENTRIES(16)); 2167 } else if (((rdev->family) == CHIP_RV630) || 2168 ((rdev->family) == CHIP_RV635)) { 2169 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2170 NUM_VS_GPRS(44) | 2171 NUM_CLAUSE_TEMP_GPRS(2)); 2172 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2173 NUM_ES_GPRS(18)); 2174 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2175 NUM_VS_THREADS(78) | 2176 NUM_GS_THREADS(4) | 2177 NUM_ES_THREADS(31)); 2178 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2179 NUM_VS_STACK_ENTRIES(40)); 2180 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2181 NUM_ES_STACK_ENTRIES(16)); 2182 } else if ((rdev->family) == CHIP_RV670) { 2183 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2184 NUM_VS_GPRS(44) | 2185 NUM_CLAUSE_TEMP_GPRS(2)); 2186 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2187 NUM_ES_GPRS(17)); 2188 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2189 NUM_VS_THREADS(78) | 2190 NUM_GS_THREADS(4) | 2191 NUM_ES_THREADS(31)); 2192 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2193 NUM_VS_STACK_ENTRIES(64)); 2194 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2195 NUM_ES_STACK_ENTRIES(64)); 2196 } 2197 2198 WREG32(SQ_CONFIG, sq_config); 2199 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2200 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2201 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2202 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2203 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2204 2205 if (((rdev->family) == CHIP_RV610) || 2206 ((rdev->family) == CHIP_RV620) || 2207 ((rdev->family) == CHIP_RS780) || 2208 ((rdev->family) == CHIP_RS880)) { 2209 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2210 } else { 2211 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2212 } 2213 2214 /* More default values. 2D/3D driver should adjust as needed */ 2215 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2216 S1_X(0x4) | S1_Y(0xc))); 2217 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2218 S1_X(0x2) | S1_Y(0x2) | 2219 S2_X(0xa) | S2_Y(0x6) | 2220 S3_X(0x6) | S3_Y(0xa))); 2221 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2222 S1_X(0x4) | S1_Y(0xc) | 2223 S2_X(0x1) | S2_Y(0x6) | 2224 S3_X(0xa) | S3_Y(0xe))); 2225 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2226 S5_X(0x0) | S5_Y(0x0) | 2227 S6_X(0xb) | S6_Y(0x4) | 2228 S7_X(0x7) | S7_Y(0x8))); 2229 2230 WREG32(VGT_STRMOUT_EN, 0); 2231 tmp = rdev->config.r600.max_pipes * 16; 2232 switch (rdev->family) { 2233 case CHIP_RV610: 2234 case CHIP_RV620: 2235 case CHIP_RS780: 2236 case CHIP_RS880: 2237 tmp += 32; 2238 break; 2239 case CHIP_RV670: 2240 tmp += 128; 2241 break; 2242 default: 2243 break; 2244 } 2245 if (tmp > 256) { 2246 tmp = 256; 2247 } 2248 WREG32(VGT_ES_PER_GS, 128); 2249 WREG32(VGT_GS_PER_ES, tmp); 2250 WREG32(VGT_GS_PER_VS, 2); 2251 WREG32(VGT_GS_VERTEX_REUSE, 16); 2252 2253 /* more default values. 2D/3D driver should adjust as needed */ 2254 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2255 WREG32(VGT_STRMOUT_EN, 0); 2256 WREG32(SX_MISC, 0); 2257 WREG32(PA_SC_MODE_CNTL, 0); 2258 WREG32(PA_SC_AA_CONFIG, 0); 2259 WREG32(PA_SC_LINE_STIPPLE, 0); 2260 WREG32(SPI_INPUT_Z, 0); 2261 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2262 WREG32(CB_COLOR7_FRAG, 0); 2263 2264 /* Clear render buffer base addresses */ 2265 WREG32(CB_COLOR0_BASE, 0); 2266 WREG32(CB_COLOR1_BASE, 0); 2267 WREG32(CB_COLOR2_BASE, 0); 2268 WREG32(CB_COLOR3_BASE, 0); 2269 WREG32(CB_COLOR4_BASE, 0); 2270 WREG32(CB_COLOR5_BASE, 0); 2271 WREG32(CB_COLOR6_BASE, 0); 2272 WREG32(CB_COLOR7_BASE, 0); 2273 WREG32(CB_COLOR7_FRAG, 0); 2274 2275 switch (rdev->family) { 2276 case CHIP_RV610: 2277 case CHIP_RV620: 2278 case CHIP_RS780: 2279 case CHIP_RS880: 2280 tmp = TC_L2_SIZE(8); 2281 break; 2282 case CHIP_RV630: 2283 case CHIP_RV635: 2284 tmp = TC_L2_SIZE(4); 2285 break; 2286 case CHIP_R600: 2287 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2288 break; 2289 default: 2290 tmp = TC_L2_SIZE(0); 2291 break; 2292 } 2293 WREG32(TC_CNTL, tmp); 2294 2295 tmp = RREG32(HDP_HOST_PATH_CNTL); 2296 WREG32(HDP_HOST_PATH_CNTL, tmp); 2297 2298 tmp = RREG32(ARB_POP); 2299 tmp |= ENABLE_TC128; 2300 WREG32(ARB_POP, tmp); 2301 2302 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2303 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2304 NUM_CLIP_SEQ(3))); 2305 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2306 WREG32(VC_ENHANCE, 0); 2307 } 2308 2309 2310 /* 2311 * Indirect registers accessor 2312 */ 2313 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2314 { 2315 u32 r; 2316 2317 spin_lock(&rdev->pciep_idx_lock); 2318 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2319 (void)RREG32(PCIE_PORT_INDEX); 2320 r = RREG32(PCIE_PORT_DATA); 2321 spin_unlock(&rdev->pciep_idx_lock); 2322 return r; 2323 } 2324 2325 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2326 { 2327 spin_lock(&rdev->pciep_idx_lock); 2328 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2329 (void)RREG32(PCIE_PORT_INDEX); 2330 WREG32(PCIE_PORT_DATA, (v)); 2331 (void)RREG32(PCIE_PORT_DATA); 2332 spin_unlock(&rdev->pciep_idx_lock); 2333 } 2334 2335 /* 2336 * CP & Ring 2337 */ 2338 void r600_cp_stop(struct radeon_device *rdev) 2339 { 2340 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2341 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2342 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2343 WREG32(SCRATCH_UMSK, 0); 2344 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2345 } 2346 2347 int r600_init_microcode(struct radeon_device *rdev) 2348 { 2349 const char *chip_name; 2350 const char *rlc_chip_name; 2351 const char *smc_chip_name = "RV770"; 2352 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2353 char fw_name[30]; 2354 int err; 2355 2356 DRM_DEBUG("\n"); 2357 2358 switch (rdev->family) { 2359 case CHIP_R600: 2360 chip_name = "R600"; 2361 rlc_chip_name = "R600"; 2362 break; 2363 case CHIP_RV610: 2364 chip_name = "RV610"; 2365 rlc_chip_name = "R600"; 2366 break; 2367 case CHIP_RV630: 2368 chip_name = "RV630"; 2369 rlc_chip_name = "R600"; 2370 break; 2371 case CHIP_RV620: 2372 chip_name = "RV620"; 2373 rlc_chip_name = "R600"; 2374 break; 2375 case CHIP_RV635: 2376 chip_name = "RV635"; 2377 rlc_chip_name = "R600"; 2378 break; 2379 case CHIP_RV670: 2380 chip_name = "RV670"; 2381 rlc_chip_name = "R600"; 2382 break; 2383 case CHIP_RS780: 2384 case CHIP_RS880: 2385 chip_name = "RS780"; 2386 rlc_chip_name = "R600"; 2387 break; 2388 case CHIP_RV770: 2389 chip_name = "RV770"; 2390 rlc_chip_name = "R700"; 2391 smc_chip_name = "RV770"; 2392 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2393 break; 2394 case CHIP_RV730: 2395 chip_name = "RV730"; 2396 rlc_chip_name = "R700"; 2397 smc_chip_name = "RV730"; 2398 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2399 break; 2400 case CHIP_RV710: 2401 chip_name = "RV710"; 2402 rlc_chip_name = "R700"; 2403 smc_chip_name = "RV710"; 2404 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2405 break; 2406 case CHIP_RV740: 2407 chip_name = "RV730"; 2408 rlc_chip_name = "R700"; 2409 smc_chip_name = "RV740"; 2410 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2411 break; 2412 case CHIP_CEDAR: 2413 chip_name = "CEDAR"; 2414 rlc_chip_name = "CEDAR"; 2415 smc_chip_name = "CEDAR"; 2416 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2417 break; 2418 case CHIP_REDWOOD: 2419 chip_name = "REDWOOD"; 2420 rlc_chip_name = "REDWOOD"; 2421 smc_chip_name = "REDWOOD"; 2422 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2423 break; 2424 case CHIP_JUNIPER: 2425 chip_name = "JUNIPER"; 2426 rlc_chip_name = "JUNIPER"; 2427 smc_chip_name = "JUNIPER"; 2428 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2429 break; 2430 case CHIP_CYPRESS: 2431 case CHIP_HEMLOCK: 2432 chip_name = "CYPRESS"; 2433 rlc_chip_name = "CYPRESS"; 2434 smc_chip_name = "CYPRESS"; 2435 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2436 break; 2437 case CHIP_PALM: 2438 chip_name = "PALM"; 2439 rlc_chip_name = "SUMO"; 2440 break; 2441 case CHIP_SUMO: 2442 chip_name = "SUMO"; 2443 rlc_chip_name = "SUMO"; 2444 break; 2445 case CHIP_SUMO2: 2446 chip_name = "SUMO2"; 2447 rlc_chip_name = "SUMO"; 2448 break; 2449 default: BUG(); 2450 } 2451 2452 if (rdev->family >= CHIP_CEDAR) { 2453 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2454 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2455 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2456 } else if (rdev->family >= CHIP_RV770) { 2457 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2458 me_req_size = R700_PM4_UCODE_SIZE * 4; 2459 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2460 } else { 2461 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2462 me_req_size = R600_PM4_UCODE_SIZE * 12; 2463 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2464 } 2465 2466 DRM_INFO("Loading %s Microcode\n", chip_name); 2467 2468 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2469 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2470 if (err) 2471 goto out; 2472 if (rdev->pfp_fw->datasize != pfp_req_size) { 2473 printk(KERN_ERR 2474 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2475 rdev->pfp_fw->datasize, fw_name); 2476 err = -EINVAL; 2477 goto out; 2478 } 2479 2480 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2481 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2482 if (err) 2483 goto out; 2484 if (rdev->me_fw->datasize != me_req_size) { 2485 printk(KERN_ERR 2486 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2487 rdev->me_fw->datasize, fw_name); 2488 err = -EINVAL; 2489 } 2490 2491 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 2492 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2493 if (err) 2494 goto out; 2495 if (rdev->rlc_fw->datasize != rlc_req_size) { 2496 printk(KERN_ERR 2497 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2498 rdev->rlc_fw->datasize, fw_name); 2499 err = -EINVAL; 2500 } 2501 2502 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2503 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name); 2504 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2505 if (err) { 2506 printk(KERN_ERR 2507 "smc: error loading firmware \"%s\"\n", 2508 fw_name); 2509 release_firmware(rdev->smc_fw); 2510 rdev->smc_fw = NULL; 2511 err = 0; 2512 } else if (rdev->smc_fw->datasize != smc_req_size) { 2513 printk(KERN_ERR 2514 "smc: Bogus length %zu in firmware \"%s\"\n", 2515 rdev->smc_fw->datasize, fw_name); 2516 err = -EINVAL; 2517 } 2518 } 2519 2520 out: 2521 if (err) { 2522 if (err != -EINVAL) 2523 printk(KERN_ERR 2524 "r600_cp: Failed to load firmware \"%s\"\n", 2525 fw_name); 2526 release_firmware(rdev->pfp_fw); 2527 rdev->pfp_fw = NULL; 2528 release_firmware(rdev->me_fw); 2529 rdev->me_fw = NULL; 2530 release_firmware(rdev->rlc_fw); 2531 rdev->rlc_fw = NULL; 2532 release_firmware(rdev->smc_fw); 2533 rdev->smc_fw = NULL; 2534 } 2535 return err; 2536 } 2537 2538 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2539 struct radeon_ring *ring) 2540 { 2541 u32 rptr; 2542 2543 if (rdev->wb.enabled) 2544 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2545 else 2546 rptr = RREG32(R600_CP_RB_RPTR); 2547 2548 return rptr; 2549 } 2550 2551 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2552 struct radeon_ring *ring) 2553 { 2554 u32 wptr; 2555 2556 wptr = RREG32(R600_CP_RB_WPTR); 2557 2558 return wptr; 2559 } 2560 2561 void r600_gfx_set_wptr(struct radeon_device *rdev, 2562 struct radeon_ring *ring) 2563 { 2564 WREG32(R600_CP_RB_WPTR, ring->wptr); 2565 (void)RREG32(R600_CP_RB_WPTR); 2566 } 2567 2568 /** 2569 * r600_fini_microcode - drop the firmwares image references 2570 * 2571 * @rdev: radeon_device pointer 2572 * 2573 * Drop the pfp, me and rlc firmwares image references. 2574 * Called at driver shutdown. 2575 */ 2576 void r600_fini_microcode(struct radeon_device *rdev) 2577 { 2578 release_firmware(rdev->pfp_fw); 2579 rdev->pfp_fw = NULL; 2580 release_firmware(rdev->me_fw); 2581 rdev->me_fw = NULL; 2582 release_firmware(rdev->rlc_fw); 2583 rdev->rlc_fw = NULL; 2584 release_firmware(rdev->smc_fw); 2585 rdev->smc_fw = NULL; 2586 } 2587 2588 static int r600_cp_load_microcode(struct radeon_device *rdev) 2589 { 2590 const __be32 *fw_data; 2591 int i; 2592 2593 if (!rdev->me_fw || !rdev->pfp_fw) 2594 return -EINVAL; 2595 2596 r600_cp_stop(rdev); 2597 2598 WREG32(CP_RB_CNTL, 2599 #ifdef __BIG_ENDIAN 2600 BUF_SWAP_32BIT | 2601 #endif 2602 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2603 2604 /* Reset cp */ 2605 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2606 RREG32(GRBM_SOFT_RESET); 2607 mdelay(15); 2608 WREG32(GRBM_SOFT_RESET, 0); 2609 2610 WREG32(CP_ME_RAM_WADDR, 0); 2611 2612 fw_data = (const __be32 *)rdev->me_fw->data; 2613 WREG32(CP_ME_RAM_WADDR, 0); 2614 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2615 WREG32(CP_ME_RAM_DATA, 2616 be32_to_cpup(fw_data++)); 2617 2618 fw_data = (const __be32 *)rdev->pfp_fw->data; 2619 WREG32(CP_PFP_UCODE_ADDR, 0); 2620 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2621 WREG32(CP_PFP_UCODE_DATA, 2622 be32_to_cpup(fw_data++)); 2623 2624 WREG32(CP_PFP_UCODE_ADDR, 0); 2625 WREG32(CP_ME_RAM_WADDR, 0); 2626 WREG32(CP_ME_RAM_RADDR, 0); 2627 return 0; 2628 } 2629 2630 int r600_cp_start(struct radeon_device *rdev) 2631 { 2632 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2633 int r; 2634 uint32_t cp_me; 2635 2636 r = radeon_ring_lock(rdev, ring, 7); 2637 if (r) { 2638 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2639 return r; 2640 } 2641 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2642 radeon_ring_write(ring, 0x1); 2643 if (rdev->family >= CHIP_RV770) { 2644 radeon_ring_write(ring, 0x0); 2645 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2646 } else { 2647 radeon_ring_write(ring, 0x3); 2648 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2649 } 2650 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2651 radeon_ring_write(ring, 0); 2652 radeon_ring_write(ring, 0); 2653 radeon_ring_unlock_commit(rdev, ring, false); 2654 2655 cp_me = 0xff; 2656 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2657 return 0; 2658 } 2659 2660 int r600_cp_resume(struct radeon_device *rdev) 2661 { 2662 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2663 u32 tmp; 2664 u32 rb_bufsz; 2665 int r; 2666 2667 /* Reset cp */ 2668 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2669 RREG32(GRBM_SOFT_RESET); 2670 mdelay(15); 2671 WREG32(GRBM_SOFT_RESET, 0); 2672 2673 /* Set ring buffer size */ 2674 rb_bufsz = order_base_2(ring->ring_size / 8); 2675 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2676 #ifdef __BIG_ENDIAN 2677 tmp |= BUF_SWAP_32BIT; 2678 #endif 2679 WREG32(CP_RB_CNTL, tmp); 2680 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2681 2682 /* Set the write pointer delay */ 2683 WREG32(CP_RB_WPTR_DELAY, 0); 2684 2685 /* Initialize the ring buffer's read and write pointers */ 2686 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2687 WREG32(CP_RB_RPTR_WR, 0); 2688 ring->wptr = 0; 2689 WREG32(CP_RB_WPTR, ring->wptr); 2690 2691 /* set the wb address whether it's enabled or not */ 2692 WREG32(CP_RB_RPTR_ADDR, 2693 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2694 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2695 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2696 2697 if (rdev->wb.enabled) 2698 WREG32(SCRATCH_UMSK, 0xff); 2699 else { 2700 tmp |= RB_NO_UPDATE; 2701 WREG32(SCRATCH_UMSK, 0); 2702 } 2703 2704 mdelay(1); 2705 WREG32(CP_RB_CNTL, tmp); 2706 2707 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2708 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2709 2710 r600_cp_start(rdev); 2711 ring->ready = true; 2712 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2713 if (r) { 2714 ring->ready = false; 2715 return r; 2716 } 2717 2718 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2719 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2720 2721 return 0; 2722 } 2723 2724 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2725 { 2726 u32 rb_bufsz; 2727 int r; 2728 2729 /* Align ring size */ 2730 rb_bufsz = order_base_2(ring_size / 8); 2731 ring_size = (1 << (rb_bufsz + 1)) * 4; 2732 ring->ring_size = ring_size; 2733 ring->align_mask = 16 - 1; 2734 2735 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2736 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2737 if (r) { 2738 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2739 ring->rptr_save_reg = 0; 2740 } 2741 } 2742 } 2743 2744 void r600_cp_fini(struct radeon_device *rdev) 2745 { 2746 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2747 r600_cp_stop(rdev); 2748 radeon_ring_fini(rdev, ring); 2749 radeon_scratch_free(rdev, ring->rptr_save_reg); 2750 } 2751 2752 /* 2753 * GPU scratch registers helpers function. 2754 */ 2755 void r600_scratch_init(struct radeon_device *rdev) 2756 { 2757 int i; 2758 2759 rdev->scratch.num_reg = 7; 2760 rdev->scratch.reg_base = SCRATCH_REG0; 2761 for (i = 0; i < rdev->scratch.num_reg; i++) { 2762 rdev->scratch.free[i] = true; 2763 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2764 } 2765 } 2766 2767 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2768 { 2769 uint32_t scratch; 2770 uint32_t tmp = 0; 2771 unsigned i; 2772 int r; 2773 2774 r = radeon_scratch_get(rdev, &scratch); 2775 if (r) { 2776 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2777 return r; 2778 } 2779 WREG32(scratch, 0xCAFEDEAD); 2780 r = radeon_ring_lock(rdev, ring, 3); 2781 if (r) { 2782 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2783 radeon_scratch_free(rdev, scratch); 2784 return r; 2785 } 2786 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2787 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2788 radeon_ring_write(ring, 0xDEADBEEF); 2789 radeon_ring_unlock_commit(rdev, ring, false); 2790 for (i = 0; i < rdev->usec_timeout; i++) { 2791 tmp = RREG32(scratch); 2792 if (tmp == 0xDEADBEEF) 2793 break; 2794 DRM_UDELAY(1); 2795 } 2796 if (i < rdev->usec_timeout) { 2797 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2798 } else { 2799 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2800 ring->idx, scratch, tmp); 2801 r = -EINVAL; 2802 } 2803 radeon_scratch_free(rdev, scratch); 2804 return r; 2805 } 2806 2807 /* 2808 * CP fences/semaphores 2809 */ 2810 2811 void r600_fence_ring_emit(struct radeon_device *rdev, 2812 struct radeon_fence *fence) 2813 { 2814 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2815 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2816 PACKET3_SH_ACTION_ENA; 2817 2818 if (rdev->family >= CHIP_RV770) 2819 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2820 2821 if (rdev->wb.use_event) { 2822 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2823 /* flush read cache over gart */ 2824 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2825 radeon_ring_write(ring, cp_coher_cntl); 2826 radeon_ring_write(ring, 0xFFFFFFFF); 2827 radeon_ring_write(ring, 0); 2828 radeon_ring_write(ring, 10); /* poll interval */ 2829 /* EVENT_WRITE_EOP - flush caches, send int */ 2830 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2831 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2832 radeon_ring_write(ring, lower_32_bits(addr)); 2833 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2834 radeon_ring_write(ring, fence->seq); 2835 radeon_ring_write(ring, 0); 2836 } else { 2837 /* flush read cache over gart */ 2838 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2839 radeon_ring_write(ring, cp_coher_cntl); 2840 radeon_ring_write(ring, 0xFFFFFFFF); 2841 radeon_ring_write(ring, 0); 2842 radeon_ring_write(ring, 10); /* poll interval */ 2843 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2844 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2845 /* wait for 3D idle clean */ 2846 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2847 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2848 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2849 /* Emit fence sequence & fire IRQ */ 2850 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2851 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2852 radeon_ring_write(ring, fence->seq); 2853 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2854 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2855 radeon_ring_write(ring, RB_INT_STAT); 2856 } 2857 } 2858 2859 /** 2860 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2861 * 2862 * @rdev: radeon_device pointer 2863 * @ring: radeon ring buffer object 2864 * @semaphore: radeon semaphore object 2865 * @emit_wait: Is this a sempahore wait? 2866 * 2867 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2868 * from running ahead of semaphore waits. 2869 */ 2870 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2871 struct radeon_ring *ring, 2872 struct radeon_semaphore *semaphore, 2873 bool emit_wait) 2874 { 2875 uint64_t addr = semaphore->gpu_addr; 2876 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2877 2878 if (rdev->family < CHIP_CAYMAN) 2879 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2880 2881 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2882 radeon_ring_write(ring, lower_32_bits(addr)); 2883 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2884 2885 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2886 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2887 /* Prevent the PFP from running ahead of the semaphore wait */ 2888 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2889 radeon_ring_write(ring, 0x0); 2890 } 2891 2892 return true; 2893 } 2894 2895 /** 2896 * r600_copy_cpdma - copy pages using the CP DMA engine 2897 * 2898 * @rdev: radeon_device pointer 2899 * @src_offset: src GPU address 2900 * @dst_offset: dst GPU address 2901 * @num_gpu_pages: number of GPU pages to xfer 2902 * @fence: radeon fence object 2903 * 2904 * Copy GPU paging using the CP DMA engine (r6xx+). 2905 * Used by the radeon ttm implementation to move pages if 2906 * registered as the asic copy callback. 2907 */ 2908 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2909 uint64_t src_offset, uint64_t dst_offset, 2910 unsigned num_gpu_pages, 2911 struct reservation_object *resv) 2912 { 2913 struct radeon_semaphore *sem = NULL; 2914 struct radeon_fence *fence; 2915 int ring_index = rdev->asic->copy.blit_ring_index; 2916 struct radeon_ring *ring = &rdev->ring[ring_index]; 2917 u32 size_in_bytes, cur_size_in_bytes, tmp; 2918 int i, num_loops; 2919 int r = 0; 2920 2921 r = radeon_semaphore_create(rdev, &sem); 2922 if (r) { 2923 DRM_ERROR("radeon: moving bo (%d).\n", r); 2924 return ERR_PTR(r); 2925 } 2926 2927 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 2928 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 2929 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 2930 if (r) { 2931 DRM_ERROR("radeon: moving bo (%d).\n", r); 2932 radeon_semaphore_free(rdev, &sem, NULL); 2933 return ERR_PTR(r); 2934 } 2935 2936 radeon_semaphore_sync_resv(rdev, sem, resv, false); 2937 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 2938 2939 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2940 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2941 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 2942 for (i = 0; i < num_loops; i++) { 2943 cur_size_in_bytes = size_in_bytes; 2944 if (cur_size_in_bytes > 0x1fffff) 2945 cur_size_in_bytes = 0x1fffff; 2946 size_in_bytes -= cur_size_in_bytes; 2947 tmp = upper_32_bits(src_offset) & 0xff; 2948 if (size_in_bytes == 0) 2949 tmp |= PACKET3_CP_DMA_CP_SYNC; 2950 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 2951 radeon_ring_write(ring, lower_32_bits(src_offset)); 2952 radeon_ring_write(ring, tmp); 2953 radeon_ring_write(ring, lower_32_bits(dst_offset)); 2954 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 2955 radeon_ring_write(ring, cur_size_in_bytes); 2956 src_offset += cur_size_in_bytes; 2957 dst_offset += cur_size_in_bytes; 2958 } 2959 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2960 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2961 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 2962 2963 r = radeon_fence_emit(rdev, &fence, ring->idx); 2964 if (r) { 2965 radeon_ring_unlock_undo(rdev, ring); 2966 radeon_semaphore_free(rdev, &sem, NULL); 2967 return ERR_PTR(r); 2968 } 2969 2970 radeon_ring_unlock_commit(rdev, ring, false); 2971 radeon_semaphore_free(rdev, &sem, fence); 2972 2973 return fence; 2974 } 2975 2976 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2977 uint32_t tiling_flags, uint32_t pitch, 2978 uint32_t offset, uint32_t obj_size) 2979 { 2980 /* FIXME: implement */ 2981 return 0; 2982 } 2983 2984 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2985 { 2986 /* FIXME: implement */ 2987 } 2988 2989 static int r600_startup(struct radeon_device *rdev) 2990 { 2991 struct radeon_ring *ring; 2992 int r; 2993 2994 /* enable pcie gen2 link */ 2995 r600_pcie_gen2_enable(rdev); 2996 2997 /* scratch needs to be initialized before MC */ 2998 r = r600_vram_scratch_init(rdev); 2999 if (r) 3000 return r; 3001 3002 r600_mc_program(rdev); 3003 3004 if (rdev->flags & RADEON_IS_AGP) { 3005 r600_agp_enable(rdev); 3006 } else { 3007 r = r600_pcie_gart_enable(rdev); 3008 if (r) 3009 return r; 3010 } 3011 r600_gpu_init(rdev); 3012 3013 /* allocate wb buffer */ 3014 r = radeon_wb_init(rdev); 3015 if (r) 3016 return r; 3017 3018 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3019 if (r) { 3020 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3021 return r; 3022 } 3023 3024 if (rdev->has_uvd) { 3025 r = uvd_v1_0_resume(rdev); 3026 if (!r) { 3027 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3028 if (r) { 3029 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3030 } 3031 } 3032 if (r) 3033 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3034 } 3035 3036 /* Enable IRQ */ 3037 if (!rdev->irq.installed) { 3038 r = radeon_irq_kms_init(rdev); 3039 if (r) 3040 return r; 3041 } 3042 3043 r = r600_irq_init(rdev); 3044 if (r) { 3045 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3046 radeon_irq_kms_fini(rdev); 3047 return r; 3048 } 3049 r600_irq_set(rdev); 3050 3051 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3052 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3053 RADEON_CP_PACKET2); 3054 if (r) 3055 return r; 3056 3057 r = r600_cp_load_microcode(rdev); 3058 if (r) 3059 return r; 3060 r = r600_cp_resume(rdev); 3061 if (r) 3062 return r; 3063 3064 if (rdev->has_uvd) { 3065 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3066 if (ring->ring_size) { 3067 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3068 RADEON_CP_PACKET2); 3069 if (!r) 3070 r = uvd_v1_0_init(rdev); 3071 if (r) 3072 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3073 } 3074 } 3075 3076 r = radeon_ib_pool_init(rdev); 3077 if (r) { 3078 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3079 return r; 3080 } 3081 3082 r = r600_audio_init(rdev); 3083 if (r) { 3084 DRM_ERROR("radeon: audio init failed\n"); 3085 return r; 3086 } 3087 3088 return 0; 3089 } 3090 3091 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3092 { 3093 uint32_t temp; 3094 3095 temp = RREG32(CONFIG_CNTL); 3096 if (state == false) { 3097 temp &= ~(1<<0); 3098 temp |= (1<<1); 3099 } else { 3100 temp &= ~(1<<1); 3101 } 3102 WREG32(CONFIG_CNTL, temp); 3103 } 3104 3105 int r600_resume(struct radeon_device *rdev) 3106 { 3107 int r; 3108 3109 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3110 * posting will perform necessary task to bring back GPU into good 3111 * shape. 3112 */ 3113 /* post card */ 3114 atom_asic_init(rdev->mode_info.atom_context); 3115 3116 if (rdev->pm.pm_method == PM_METHOD_DPM) 3117 radeon_pm_resume(rdev); 3118 3119 rdev->accel_working = true; 3120 r = r600_startup(rdev); 3121 if (r) { 3122 DRM_ERROR("r600 startup failed on resume\n"); 3123 rdev->accel_working = false; 3124 return r; 3125 } 3126 3127 return r; 3128 } 3129 3130 int r600_suspend(struct radeon_device *rdev) 3131 { 3132 radeon_pm_suspend(rdev); 3133 r600_audio_fini(rdev); 3134 r600_cp_stop(rdev); 3135 if (rdev->has_uvd) { 3136 uvd_v1_0_fini(rdev); 3137 radeon_uvd_suspend(rdev); 3138 } 3139 r600_irq_suspend(rdev); 3140 radeon_wb_disable(rdev); 3141 r600_pcie_gart_disable(rdev); 3142 3143 return 0; 3144 } 3145 3146 /* Plan is to move initialization in that function and use 3147 * helper function so that radeon_device_init pretty much 3148 * do nothing more than calling asic specific function. This 3149 * should also allow to remove a bunch of callback function 3150 * like vram_info. 3151 */ 3152 int r600_init(struct radeon_device *rdev) 3153 { 3154 int r; 3155 3156 if (r600_debugfs_mc_info_init(rdev)) { 3157 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3158 } 3159 /* Read BIOS */ 3160 if (!radeon_get_bios(rdev)) { 3161 if (ASIC_IS_AVIVO(rdev)) 3162 return -EINVAL; 3163 } 3164 /* Must be an ATOMBIOS */ 3165 if (!rdev->is_atom_bios) { 3166 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3167 return -EINVAL; 3168 } 3169 r = radeon_atombios_init(rdev); 3170 if (r) 3171 return r; 3172 /* Post card if necessary */ 3173 if (!radeon_card_posted(rdev)) { 3174 if (!rdev->bios) { 3175 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3176 return -EINVAL; 3177 } 3178 DRM_INFO("GPU not posted. posting now...\n"); 3179 atom_asic_init(rdev->mode_info.atom_context); 3180 } 3181 /* Initialize scratch registers */ 3182 r600_scratch_init(rdev); 3183 /* Initialize surface registers */ 3184 radeon_surface_init(rdev); 3185 /* Initialize clocks */ 3186 radeon_get_clock_info(rdev->ddev); 3187 /* Fence driver */ 3188 r = radeon_fence_driver_init(rdev); 3189 if (r) 3190 return r; 3191 if (rdev->flags & RADEON_IS_AGP) { 3192 r = radeon_agp_init(rdev); 3193 if (r) 3194 radeon_agp_disable(rdev); 3195 } 3196 r = r600_mc_init(rdev); 3197 if (r) 3198 return r; 3199 /* Memory manager */ 3200 r = radeon_bo_init(rdev); 3201 if (r) 3202 return r; 3203 3204 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3205 r = r600_init_microcode(rdev); 3206 if (r) { 3207 DRM_ERROR("Failed to load firmware!\n"); 3208 return r; 3209 } 3210 } 3211 3212 /* Initialize power management */ 3213 radeon_pm_init(rdev); 3214 3215 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3216 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3217 3218 if (rdev->has_uvd) { 3219 r = radeon_uvd_init(rdev); 3220 if (!r) { 3221 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3222 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3223 } 3224 } 3225 3226 rdev->ih.ring_obj = NULL; 3227 r600_ih_ring_init(rdev, 64 * 1024); 3228 3229 r = r600_pcie_gart_init(rdev); 3230 if (r) 3231 return r; 3232 3233 rdev->accel_working = true; 3234 r = r600_startup(rdev); 3235 if (r) { 3236 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3237 r600_cp_fini(rdev); 3238 r600_irq_fini(rdev); 3239 radeon_wb_fini(rdev); 3240 radeon_ib_pool_fini(rdev); 3241 radeon_irq_kms_fini(rdev); 3242 r600_pcie_gart_fini(rdev); 3243 rdev->accel_working = false; 3244 } 3245 3246 return 0; 3247 } 3248 3249 void r600_fini(struct radeon_device *rdev) 3250 { 3251 radeon_pm_fini(rdev); 3252 r600_audio_fini(rdev); 3253 r600_cp_fini(rdev); 3254 r600_irq_fini(rdev); 3255 if (rdev->has_uvd) { 3256 uvd_v1_0_fini(rdev); 3257 radeon_uvd_fini(rdev); 3258 } 3259 radeon_wb_fini(rdev); 3260 radeon_ib_pool_fini(rdev); 3261 radeon_irq_kms_fini(rdev); 3262 r600_pcie_gart_fini(rdev); 3263 r600_vram_scratch_fini(rdev); 3264 radeon_agp_fini(rdev); 3265 radeon_gem_fini(rdev); 3266 radeon_fence_driver_fini(rdev); 3267 radeon_bo_fini(rdev); 3268 radeon_atombios_fini(rdev); 3269 r600_fini_microcode(rdev); 3270 kfree(rdev->bios); 3271 rdev->bios = NULL; 3272 } 3273 3274 3275 /* 3276 * CS stuff 3277 */ 3278 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3279 { 3280 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3281 u32 next_rptr; 3282 3283 if (ring->rptr_save_reg) { 3284 next_rptr = ring->wptr + 3 + 4; 3285 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3286 radeon_ring_write(ring, ((ring->rptr_save_reg - 3287 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3288 radeon_ring_write(ring, next_rptr); 3289 } else if (rdev->wb.enabled) { 3290 next_rptr = ring->wptr + 5 + 4; 3291 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3292 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3293 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3294 radeon_ring_write(ring, next_rptr); 3295 radeon_ring_write(ring, 0); 3296 } 3297 3298 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3299 radeon_ring_write(ring, 3300 #ifdef __BIG_ENDIAN 3301 (2 << 0) | 3302 #endif 3303 (ib->gpu_addr & 0xFFFFFFFC)); 3304 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3305 radeon_ring_write(ring, ib->length_dw); 3306 } 3307 3308 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3309 { 3310 struct radeon_ib ib; 3311 uint32_t scratch; 3312 uint32_t tmp = 0; 3313 unsigned i; 3314 int r; 3315 3316 r = radeon_scratch_get(rdev, &scratch); 3317 if (r) { 3318 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3319 return r; 3320 } 3321 WREG32(scratch, 0xCAFEDEAD); 3322 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3323 if (r) { 3324 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3325 goto free_scratch; 3326 } 3327 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3328 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3329 ib.ptr[2] = 0xDEADBEEF; 3330 ib.length_dw = 3; 3331 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3332 if (r) { 3333 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3334 goto free_ib; 3335 } 3336 r = radeon_fence_wait(ib.fence, false); 3337 if (r) { 3338 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3339 goto free_ib; 3340 } 3341 for (i = 0; i < rdev->usec_timeout; i++) { 3342 tmp = RREG32(scratch); 3343 if (tmp == 0xDEADBEEF) 3344 break; 3345 DRM_UDELAY(1); 3346 } 3347 if (i < rdev->usec_timeout) { 3348 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3349 } else { 3350 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3351 scratch, tmp); 3352 r = -EINVAL; 3353 } 3354 free_ib: 3355 radeon_ib_free(rdev, &ib); 3356 free_scratch: 3357 radeon_scratch_free(rdev, scratch); 3358 return r; 3359 } 3360 3361 /* 3362 * Interrupts 3363 * 3364 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3365 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3366 * writing to the ring and the GPU consuming, the GPU writes to the ring 3367 * and host consumes. As the host irq handler processes interrupts, it 3368 * increments the rptr. When the rptr catches up with the wptr, all the 3369 * current interrupts have been processed. 3370 */ 3371 3372 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3373 { 3374 u32 rb_bufsz; 3375 3376 /* Align ring size */ 3377 rb_bufsz = order_base_2(ring_size / 4); 3378 ring_size = (1 << rb_bufsz) * 4; 3379 rdev->ih.ring_size = ring_size; 3380 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3381 rdev->ih.rptr = 0; 3382 } 3383 3384 int r600_ih_ring_alloc(struct radeon_device *rdev) 3385 { 3386 int r; 3387 void *ring_ptr; 3388 3389 /* Allocate ring buffer */ 3390 if (rdev->ih.ring_obj == NULL) { 3391 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3392 PAGE_SIZE, true, 3393 RADEON_GEM_DOMAIN_GTT, 0, 3394 NULL, &rdev->ih.ring_obj); 3395 if (r) { 3396 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3397 return r; 3398 } 3399 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3400 if (unlikely(r != 0)) { 3401 radeon_bo_unref(&rdev->ih.ring_obj); 3402 return r; 3403 } 3404 r = radeon_bo_pin(rdev->ih.ring_obj, 3405 RADEON_GEM_DOMAIN_GTT, 3406 (u64 *)&rdev->ih.gpu_addr); 3407 if (r) { 3408 radeon_bo_unreserve(rdev->ih.ring_obj); 3409 radeon_bo_unref(&rdev->ih.ring_obj); 3410 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3411 return r; 3412 } 3413 ring_ptr = &rdev->ih.ring; 3414 r = radeon_bo_kmap(rdev->ih.ring_obj, 3415 ring_ptr); 3416 if (r) 3417 radeon_bo_unpin(rdev->ih.ring_obj); 3418 radeon_bo_unreserve(rdev->ih.ring_obj); 3419 if (r) { 3420 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3421 radeon_bo_unref(&rdev->ih.ring_obj); 3422 return r; 3423 } 3424 } 3425 return 0; 3426 } 3427 3428 void r600_ih_ring_fini(struct radeon_device *rdev) 3429 { 3430 int r; 3431 if (rdev->ih.ring_obj) { 3432 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3433 if (likely(r == 0)) { 3434 radeon_bo_kunmap(rdev->ih.ring_obj); 3435 radeon_bo_unpin(rdev->ih.ring_obj); 3436 radeon_bo_unreserve(rdev->ih.ring_obj); 3437 } 3438 radeon_bo_unref(&rdev->ih.ring_obj); 3439 rdev->ih.ring = NULL; 3440 rdev->ih.ring_obj = NULL; 3441 } 3442 } 3443 3444 void r600_rlc_stop(struct radeon_device *rdev) 3445 { 3446 3447 if ((rdev->family >= CHIP_RV770) && 3448 (rdev->family <= CHIP_RV740)) { 3449 /* r7xx asics need to soft reset RLC before halting */ 3450 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3451 RREG32(SRBM_SOFT_RESET); 3452 mdelay(15); 3453 WREG32(SRBM_SOFT_RESET, 0); 3454 RREG32(SRBM_SOFT_RESET); 3455 } 3456 3457 WREG32(RLC_CNTL, 0); 3458 } 3459 3460 static void r600_rlc_start(struct radeon_device *rdev) 3461 { 3462 WREG32(RLC_CNTL, RLC_ENABLE); 3463 } 3464 3465 static int r600_rlc_resume(struct radeon_device *rdev) 3466 { 3467 u32 i; 3468 const __be32 *fw_data; 3469 3470 if (!rdev->rlc_fw) 3471 return -EINVAL; 3472 3473 r600_rlc_stop(rdev); 3474 3475 WREG32(RLC_HB_CNTL, 0); 3476 3477 WREG32(RLC_HB_BASE, 0); 3478 WREG32(RLC_HB_RPTR, 0); 3479 WREG32(RLC_HB_WPTR, 0); 3480 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3481 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3482 WREG32(RLC_MC_CNTL, 0); 3483 WREG32(RLC_UCODE_CNTL, 0); 3484 3485 fw_data = (const __be32 *)rdev->rlc_fw->data; 3486 if (rdev->family >= CHIP_RV770) { 3487 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3488 WREG32(RLC_UCODE_ADDR, i); 3489 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3490 } 3491 } else { 3492 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3493 WREG32(RLC_UCODE_ADDR, i); 3494 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3495 } 3496 } 3497 WREG32(RLC_UCODE_ADDR, 0); 3498 3499 r600_rlc_start(rdev); 3500 3501 return 0; 3502 } 3503 3504 static void r600_enable_interrupts(struct radeon_device *rdev) 3505 { 3506 u32 ih_cntl = RREG32(IH_CNTL); 3507 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3508 3509 ih_cntl |= ENABLE_INTR; 3510 ih_rb_cntl |= IH_RB_ENABLE; 3511 WREG32(IH_CNTL, ih_cntl); 3512 WREG32(IH_RB_CNTL, ih_rb_cntl); 3513 rdev->ih.enabled = true; 3514 } 3515 3516 void r600_disable_interrupts(struct radeon_device *rdev) 3517 { 3518 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3519 u32 ih_cntl = RREG32(IH_CNTL); 3520 3521 ih_rb_cntl &= ~IH_RB_ENABLE; 3522 ih_cntl &= ~ENABLE_INTR; 3523 WREG32(IH_RB_CNTL, ih_rb_cntl); 3524 WREG32(IH_CNTL, ih_cntl); 3525 /* set rptr, wptr to 0 */ 3526 WREG32(IH_RB_RPTR, 0); 3527 WREG32(IH_RB_WPTR, 0); 3528 rdev->ih.enabled = false; 3529 rdev->ih.rptr = 0; 3530 } 3531 3532 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3533 { 3534 u32 tmp; 3535 3536 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3537 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3538 WREG32(DMA_CNTL, tmp); 3539 WREG32(GRBM_INT_CNTL, 0); 3540 WREG32(DxMODE_INT_MASK, 0); 3541 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3542 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3543 if (ASIC_IS_DCE3(rdev)) { 3544 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3545 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3546 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3547 WREG32(DC_HPD1_INT_CONTROL, tmp); 3548 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3549 WREG32(DC_HPD2_INT_CONTROL, tmp); 3550 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3551 WREG32(DC_HPD3_INT_CONTROL, tmp); 3552 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3553 WREG32(DC_HPD4_INT_CONTROL, tmp); 3554 if (ASIC_IS_DCE32(rdev)) { 3555 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3556 WREG32(DC_HPD5_INT_CONTROL, tmp); 3557 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3558 WREG32(DC_HPD6_INT_CONTROL, tmp); 3559 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3560 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3561 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3562 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3563 } else { 3564 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3565 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3566 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3567 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3568 } 3569 } else { 3570 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3571 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3572 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3573 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3574 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3575 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3576 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3577 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3578 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3579 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3580 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3581 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3582 } 3583 } 3584 3585 int r600_irq_init(struct radeon_device *rdev) 3586 { 3587 int ret = 0; 3588 int rb_bufsz; 3589 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3590 3591 /* allocate ring */ 3592 ret = r600_ih_ring_alloc(rdev); 3593 if (ret) 3594 return ret; 3595 3596 /* disable irqs */ 3597 r600_disable_interrupts(rdev); 3598 3599 /* init rlc */ 3600 if (rdev->family >= CHIP_CEDAR) 3601 ret = evergreen_rlc_resume(rdev); 3602 else 3603 ret = r600_rlc_resume(rdev); 3604 if (ret) { 3605 r600_ih_ring_fini(rdev); 3606 return ret; 3607 } 3608 3609 /* setup interrupt control */ 3610 /* set dummy read address to ring address */ 3611 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3612 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3613 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3614 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3615 */ 3616 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3617 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3618 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3619 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3620 3621 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3622 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3623 3624 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3625 IH_WPTR_OVERFLOW_CLEAR | 3626 (rb_bufsz << 1)); 3627 3628 if (rdev->wb.enabled) 3629 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3630 3631 /* set the writeback address whether it's enabled or not */ 3632 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3633 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3634 3635 WREG32(IH_RB_CNTL, ih_rb_cntl); 3636 3637 /* set rptr, wptr to 0 */ 3638 WREG32(IH_RB_RPTR, 0); 3639 WREG32(IH_RB_WPTR, 0); 3640 3641 /* Default settings for IH_CNTL (disabled at first) */ 3642 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3643 /* RPTR_REARM only works if msi's are enabled */ 3644 if (rdev->msi_enabled) 3645 ih_cntl |= RPTR_REARM; 3646 WREG32(IH_CNTL, ih_cntl); 3647 3648 /* force the active interrupt state to all disabled */ 3649 if (rdev->family >= CHIP_CEDAR) 3650 evergreen_disable_interrupt_state(rdev); 3651 else 3652 r600_disable_interrupt_state(rdev); 3653 3654 /* at this point everything should be setup correctly to enable master */ 3655 pci_enable_busmaster(rdev->dev->bsddev); 3656 3657 /* enable irqs */ 3658 r600_enable_interrupts(rdev); 3659 3660 return ret; 3661 } 3662 3663 void r600_irq_suspend(struct radeon_device *rdev) 3664 { 3665 r600_irq_disable(rdev); 3666 r600_rlc_stop(rdev); 3667 } 3668 3669 void r600_irq_fini(struct radeon_device *rdev) 3670 { 3671 r600_irq_suspend(rdev); 3672 r600_ih_ring_fini(rdev); 3673 } 3674 3675 int r600_irq_set(struct radeon_device *rdev) 3676 { 3677 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3678 u32 mode_int = 0; 3679 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3680 u32 grbm_int_cntl = 0; 3681 u32 hdmi0, hdmi1; 3682 u32 dma_cntl; 3683 u32 thermal_int = 0; 3684 3685 if (!rdev->irq.installed) { 3686 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3687 return -EINVAL; 3688 } 3689 /* don't enable anything if the ih is disabled */ 3690 if (!rdev->ih.enabled) { 3691 r600_disable_interrupts(rdev); 3692 /* force the active interrupt state to all disabled */ 3693 r600_disable_interrupt_state(rdev); 3694 return 0; 3695 } 3696 3697 if (ASIC_IS_DCE3(rdev)) { 3698 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3699 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3700 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3701 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3702 if (ASIC_IS_DCE32(rdev)) { 3703 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3704 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3705 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3706 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3707 } else { 3708 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3709 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3710 } 3711 } else { 3712 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3713 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3714 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3715 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3716 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3717 } 3718 3719 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3720 3721 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3722 thermal_int = RREG32(CG_THERMAL_INT) & 3723 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3724 } else if (rdev->family >= CHIP_RV770) { 3725 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3726 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3727 } 3728 if (rdev->irq.dpm_thermal) { 3729 DRM_DEBUG("dpm thermal\n"); 3730 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3731 } 3732 3733 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3734 DRM_DEBUG("r600_irq_set: sw int\n"); 3735 cp_int_cntl |= RB_INT_ENABLE; 3736 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3737 } 3738 3739 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3740 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3741 dma_cntl |= TRAP_ENABLE; 3742 } 3743 3744 if (rdev->irq.crtc_vblank_int[0] || 3745 atomic_read(&rdev->irq.pflip[0])) { 3746 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3747 mode_int |= D1MODE_VBLANK_INT_MASK; 3748 } 3749 if (rdev->irq.crtc_vblank_int[1] || 3750 atomic_read(&rdev->irq.pflip[1])) { 3751 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3752 mode_int |= D2MODE_VBLANK_INT_MASK; 3753 } 3754 if (rdev->irq.hpd[0]) { 3755 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3756 hpd1 |= DC_HPDx_INT_EN; 3757 } 3758 if (rdev->irq.hpd[1]) { 3759 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3760 hpd2 |= DC_HPDx_INT_EN; 3761 } 3762 if (rdev->irq.hpd[2]) { 3763 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3764 hpd3 |= DC_HPDx_INT_EN; 3765 } 3766 if (rdev->irq.hpd[3]) { 3767 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3768 hpd4 |= DC_HPDx_INT_EN; 3769 } 3770 if (rdev->irq.hpd[4]) { 3771 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3772 hpd5 |= DC_HPDx_INT_EN; 3773 } 3774 if (rdev->irq.hpd[5]) { 3775 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3776 hpd6 |= DC_HPDx_INT_EN; 3777 } 3778 if (rdev->irq.afmt[0]) { 3779 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3780 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3781 } 3782 if (rdev->irq.afmt[1]) { 3783 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3784 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3785 } 3786 3787 WREG32(CP_INT_CNTL, cp_int_cntl); 3788 WREG32(DMA_CNTL, dma_cntl); 3789 WREG32(DxMODE_INT_MASK, mode_int); 3790 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3791 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3792 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3793 if (ASIC_IS_DCE3(rdev)) { 3794 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3795 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3796 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3797 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3798 if (ASIC_IS_DCE32(rdev)) { 3799 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3800 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3801 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3802 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3803 } else { 3804 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3805 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3806 } 3807 } else { 3808 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3809 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3810 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3811 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3812 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3813 } 3814 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3815 WREG32(CG_THERMAL_INT, thermal_int); 3816 } else if (rdev->family >= CHIP_RV770) { 3817 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3818 } 3819 3820 return 0; 3821 } 3822 3823 static void r600_irq_ack(struct radeon_device *rdev) 3824 { 3825 u32 tmp; 3826 3827 if (ASIC_IS_DCE3(rdev)) { 3828 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3829 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3830 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3831 if (ASIC_IS_DCE32(rdev)) { 3832 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3833 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3834 } else { 3835 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3836 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3837 } 3838 } else { 3839 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3840 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3841 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3842 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3843 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3844 } 3845 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3846 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3847 3848 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3849 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3850 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3851 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3852 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3853 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3854 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3855 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3856 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3857 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3858 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3859 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3860 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3861 if (ASIC_IS_DCE3(rdev)) { 3862 tmp = RREG32(DC_HPD1_INT_CONTROL); 3863 tmp |= DC_HPDx_INT_ACK; 3864 WREG32(DC_HPD1_INT_CONTROL, tmp); 3865 } else { 3866 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3867 tmp |= DC_HPDx_INT_ACK; 3868 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3869 } 3870 } 3871 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3872 if (ASIC_IS_DCE3(rdev)) { 3873 tmp = RREG32(DC_HPD2_INT_CONTROL); 3874 tmp |= DC_HPDx_INT_ACK; 3875 WREG32(DC_HPD2_INT_CONTROL, tmp); 3876 } else { 3877 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3878 tmp |= DC_HPDx_INT_ACK; 3879 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3880 } 3881 } 3882 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3883 if (ASIC_IS_DCE3(rdev)) { 3884 tmp = RREG32(DC_HPD3_INT_CONTROL); 3885 tmp |= DC_HPDx_INT_ACK; 3886 WREG32(DC_HPD3_INT_CONTROL, tmp); 3887 } else { 3888 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3889 tmp |= DC_HPDx_INT_ACK; 3890 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3891 } 3892 } 3893 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3894 tmp = RREG32(DC_HPD4_INT_CONTROL); 3895 tmp |= DC_HPDx_INT_ACK; 3896 WREG32(DC_HPD4_INT_CONTROL, tmp); 3897 } 3898 if (ASIC_IS_DCE32(rdev)) { 3899 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3900 tmp = RREG32(DC_HPD5_INT_CONTROL); 3901 tmp |= DC_HPDx_INT_ACK; 3902 WREG32(DC_HPD5_INT_CONTROL, tmp); 3903 } 3904 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3905 tmp = RREG32(DC_HPD5_INT_CONTROL); 3906 tmp |= DC_HPDx_INT_ACK; 3907 WREG32(DC_HPD6_INT_CONTROL, tmp); 3908 } 3909 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3910 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3911 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3912 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3913 } 3914 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3915 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3916 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3917 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3918 } 3919 } else { 3920 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3921 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3922 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3923 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3924 } 3925 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3926 if (ASIC_IS_DCE3(rdev)) { 3927 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3928 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3929 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3930 } else { 3931 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3932 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3933 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3934 } 3935 } 3936 } 3937 } 3938 3939 void r600_irq_disable(struct radeon_device *rdev) 3940 { 3941 r600_disable_interrupts(rdev); 3942 /* Wait and acknowledge irq */ 3943 mdelay(1); 3944 r600_irq_ack(rdev); 3945 r600_disable_interrupt_state(rdev); 3946 } 3947 3948 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3949 { 3950 u32 wptr, tmp; 3951 3952 if (rdev->wb.enabled) 3953 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3954 else 3955 wptr = RREG32(IH_RB_WPTR); 3956 3957 if (wptr & RB_OVERFLOW) { 3958 wptr &= ~RB_OVERFLOW; 3959 /* When a ring buffer overflow happen start parsing interrupt 3960 * from the last not overwritten vector (wptr + 16). Hopefully 3961 * this should allow us to catchup. 3962 */ 3963 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 3964 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 3965 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3966 tmp = RREG32(IH_RB_CNTL); 3967 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3968 WREG32(IH_RB_CNTL, tmp); 3969 } 3970 return (wptr & rdev->ih.ptr_mask); 3971 } 3972 3973 /* r600 IV Ring 3974 * Each IV ring entry is 128 bits: 3975 * [7:0] - interrupt source id 3976 * [31:8] - reserved 3977 * [59:32] - interrupt source data 3978 * [127:60] - reserved 3979 * 3980 * The basic interrupt vector entries 3981 * are decoded as follows: 3982 * src_id src_data description 3983 * 1 0 D1 Vblank 3984 * 1 1 D1 Vline 3985 * 5 0 D2 Vblank 3986 * 5 1 D2 Vline 3987 * 19 0 FP Hot plug detection A 3988 * 19 1 FP Hot plug detection B 3989 * 19 2 DAC A auto-detection 3990 * 19 3 DAC B auto-detection 3991 * 21 4 HDMI block A 3992 * 21 5 HDMI block B 3993 * 176 - CP_INT RB 3994 * 177 - CP_INT IB1 3995 * 178 - CP_INT IB2 3996 * 181 - EOP Interrupt 3997 * 233 - GUI Idle 3998 * 3999 * Note, these are based on r600 and may need to be 4000 * adjusted or added to on newer asics 4001 */ 4002 4003 irqreturn_t r600_irq_process(struct radeon_device *rdev) 4004 { 4005 u32 wptr; 4006 u32 rptr; 4007 u32 src_id, src_data; 4008 u32 ring_index; 4009 bool queue_hotplug = false; 4010 bool queue_hdmi = false; 4011 bool queue_thermal = false; 4012 4013 if (!rdev->ih.enabled || rdev->shutdown) 4014 return IRQ_NONE; 4015 4016 /* No MSIs, need a dummy read to flush PCI DMAs */ 4017 if (!rdev->msi_enabled) 4018 RREG32(IH_RB_WPTR); 4019 4020 wptr = r600_get_ih_wptr(rdev); 4021 4022 restart_ih: 4023 /* is somebody else already processing irqs? */ 4024 if (atomic_xchg(&rdev->ih.lock, 1)) 4025 return IRQ_NONE; 4026 4027 rptr = rdev->ih.rptr; 4028 DRM_DEBUG_VBLANK("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4029 4030 /* Order reading of wptr vs. reading of IH ring data */ 4031 rmb(); 4032 4033 /* display interrupts */ 4034 r600_irq_ack(rdev); 4035 4036 while (rptr != wptr) { 4037 /* wptr/rptr are in bytes! */ 4038 ring_index = rptr / 4; 4039 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4040 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4041 4042 switch (src_id) { 4043 case 1: /* D1 vblank/vline */ 4044 switch (src_data) { 4045 case 0: /* D1 vblank */ 4046 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4047 if (rdev->irq.crtc_vblank_int[0]) { 4048 drm_handle_vblank(rdev->ddev, 0); 4049 rdev->pm.vblank_sync = true; 4050 wake_up(&rdev->irq.vblank_queue); 4051 } 4052 if (atomic_read(&rdev->irq.pflip[0])) 4053 radeon_crtc_handle_vblank(rdev, 0); 4054 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4055 DRM_DEBUG_VBLANK("IH: D1 vblank\n"); 4056 } 4057 break; 4058 case 1: /* D1 vline */ 4059 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4060 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4061 DRM_DEBUG_VBLANK("IH: D1 vline\n"); 4062 } 4063 break; 4064 default: 4065 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4066 break; 4067 } 4068 break; 4069 case 5: /* D2 vblank/vline */ 4070 switch (src_data) { 4071 case 0: /* D2 vblank */ 4072 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4073 if (rdev->irq.crtc_vblank_int[1]) { 4074 drm_handle_vblank(rdev->ddev, 1); 4075 rdev->pm.vblank_sync = true; 4076 wake_up(&rdev->irq.vblank_queue); 4077 } 4078 if (atomic_read(&rdev->irq.pflip[1])) 4079 radeon_crtc_handle_vblank(rdev, 1); 4080 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4081 DRM_DEBUG_VBLANK("IH: D2 vblank\n"); 4082 } 4083 break; 4084 case 1: /* D1 vline */ 4085 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4086 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4087 DRM_DEBUG_VBLANK("IH: D2 vline\n"); 4088 } 4089 break; 4090 default: 4091 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4092 break; 4093 } 4094 break; 4095 case 9: /* D1 pflip */ 4096 DRM_DEBUG_VBLANK("IH: D1 flip\n"); 4097 if (radeon_use_pflipirq > 0) 4098 radeon_crtc_handle_flip(rdev, 0); 4099 break; 4100 case 11: /* D2 pflip */ 4101 DRM_DEBUG_VBLANK("IH: D2 flip\n"); 4102 if (radeon_use_pflipirq > 0) 4103 radeon_crtc_handle_flip(rdev, 1); 4104 break; 4105 case 19: /* HPD/DAC hotplug */ 4106 switch (src_data) { 4107 case 0: 4108 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4109 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4110 queue_hotplug = true; 4111 DRM_DEBUG("IH: HPD1\n"); 4112 } 4113 break; 4114 case 1: 4115 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4116 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4117 queue_hotplug = true; 4118 DRM_DEBUG("IH: HPD2\n"); 4119 } 4120 break; 4121 case 4: 4122 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4123 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4124 queue_hotplug = true; 4125 DRM_DEBUG("IH: HPD3\n"); 4126 } 4127 break; 4128 case 5: 4129 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4130 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4131 queue_hotplug = true; 4132 DRM_DEBUG("IH: HPD4\n"); 4133 } 4134 break; 4135 case 10: 4136 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4137 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4138 queue_hotplug = true; 4139 DRM_DEBUG("IH: HPD5\n"); 4140 } 4141 break; 4142 case 12: 4143 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4144 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4145 queue_hotplug = true; 4146 DRM_DEBUG("IH: HPD6\n"); 4147 } 4148 break; 4149 default: 4150 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4151 break; 4152 } 4153 break; 4154 case 21: /* hdmi */ 4155 switch (src_data) { 4156 case 4: 4157 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4158 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4159 queue_hdmi = true; 4160 DRM_DEBUG("IH: HDMI0\n"); 4161 } 4162 break; 4163 case 5: 4164 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4165 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4166 queue_hdmi = true; 4167 DRM_DEBUG("IH: HDMI1\n"); 4168 } 4169 break; 4170 default: 4171 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4172 break; 4173 } 4174 break; 4175 case 124: /* UVD */ 4176 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4177 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4178 break; 4179 case 176: /* CP_INT in ring buffer */ 4180 case 177: /* CP_INT in IB1 */ 4181 case 178: /* CP_INT in IB2 */ 4182 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4183 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4184 break; 4185 case 181: /* CP EOP event */ 4186 DRM_DEBUG("IH: CP EOP\n"); 4187 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4188 break; 4189 case 224: /* DMA trap event */ 4190 DRM_DEBUG("IH: DMA trap\n"); 4191 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4192 break; 4193 case 230: /* thermal low to high */ 4194 DRM_DEBUG("IH: thermal low to high\n"); 4195 rdev->pm.dpm.thermal.high_to_low = false; 4196 queue_thermal = true; 4197 break; 4198 case 231: /* thermal high to low */ 4199 DRM_DEBUG("IH: thermal high to low\n"); 4200 rdev->pm.dpm.thermal.high_to_low = true; 4201 queue_thermal = true; 4202 break; 4203 case 233: /* GUI IDLE */ 4204 DRM_DEBUG("IH: GUI idle\n"); 4205 break; 4206 default: 4207 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4208 break; 4209 } 4210 4211 /* wptr/rptr are in bytes! */ 4212 rptr += 16; 4213 rptr &= rdev->ih.ptr_mask; 4214 WREG32(IH_RB_RPTR, rptr); 4215 } 4216 if (queue_hotplug) 4217 schedule_work(&rdev->hotplug_work); 4218 if (queue_hdmi) 4219 schedule_work(&rdev->audio_work); 4220 if (queue_thermal && rdev->pm.dpm_enabled) 4221 schedule_work(&rdev->pm.dpm.thermal.work); 4222 rdev->ih.rptr = rptr; 4223 atomic_set(&rdev->ih.lock, 0); 4224 4225 /* make sure wptr hasn't changed while processing */ 4226 wptr = r600_get_ih_wptr(rdev); 4227 if (wptr != rptr) 4228 goto restart_ih; 4229 4230 return IRQ_HANDLED; 4231 } 4232 4233 /* 4234 * Debugfs info 4235 */ 4236 #if defined(CONFIG_DEBUG_FS) 4237 4238 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4239 { 4240 struct drm_info_node *node = (struct drm_info_node *) m->private; 4241 struct drm_device *dev = node->minor->dev; 4242 struct radeon_device *rdev = dev->dev_private; 4243 4244 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4245 DREG32_SYS(m, rdev, VM_L2_STATUS); 4246 return 0; 4247 } 4248 4249 static struct drm_info_list r600_mc_info_list[] = { 4250 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4251 }; 4252 #endif 4253 4254 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4255 { 4256 #if defined(CONFIG_DEBUG_FS) 4257 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4258 #else 4259 return 0; 4260 #endif 4261 } 4262 4263 /** 4264 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4265 * rdev: radeon device structure 4266 * 4267 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4268 * through the ring buffer. This leads to corruption in rendering, see 4269 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4270 * directly perform the HDP flush by writing the register through MMIO. 4271 */ 4272 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4273 { 4274 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4275 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4276 * This seems to cause problems on some AGP cards. Just use the old 4277 * method for them. 4278 */ 4279 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4280 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4281 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4282 u32 tmp; 4283 4284 WREG32(HDP_DEBUG1, 0); 4285 tmp = *ptr; 4286 } else 4287 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4288 } 4289 4290 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4291 { 4292 u32 link_width_cntl, mask; 4293 4294 if (rdev->flags & RADEON_IS_IGP) 4295 return; 4296 4297 if (!(rdev->flags & RADEON_IS_PCIE)) 4298 return; 4299 4300 /* x2 cards have a special sequence */ 4301 if (ASIC_IS_X2(rdev)) 4302 return; 4303 4304 radeon_gui_idle(rdev); 4305 4306 switch (lanes) { 4307 case 0: 4308 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4309 break; 4310 case 1: 4311 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4312 break; 4313 case 2: 4314 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4315 break; 4316 case 4: 4317 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4318 break; 4319 case 8: 4320 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4321 break; 4322 case 12: 4323 /* not actually supported */ 4324 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4325 break; 4326 case 16: 4327 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4328 break; 4329 default: 4330 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4331 return; 4332 } 4333 4334 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4335 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4336 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4337 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4338 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4339 4340 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4341 } 4342 4343 int r600_get_pcie_lanes(struct radeon_device *rdev) 4344 { 4345 u32 link_width_cntl; 4346 4347 if (rdev->flags & RADEON_IS_IGP) 4348 return 0; 4349 4350 if (!(rdev->flags & RADEON_IS_PCIE)) 4351 return 0; 4352 4353 /* x2 cards have a special sequence */ 4354 if (ASIC_IS_X2(rdev)) 4355 return 0; 4356 4357 radeon_gui_idle(rdev); 4358 4359 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4360 4361 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4362 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4363 return 1; 4364 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4365 return 2; 4366 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4367 return 4; 4368 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4369 return 8; 4370 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4371 /* not actually supported */ 4372 return 12; 4373 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4374 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4375 default: 4376 return 16; 4377 } 4378 } 4379 4380 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4381 { 4382 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4383 u16 link_cntl2; 4384 u32 mask; 4385 int ret; 4386 4387 if (radeon_pcie_gen2 == 0) 4388 return; 4389 4390 if (rdev->flags & RADEON_IS_IGP) 4391 return; 4392 4393 if (!(rdev->flags & RADEON_IS_PCIE)) 4394 return; 4395 4396 /* x2 cards have a special sequence */ 4397 if (ASIC_IS_X2(rdev)) 4398 return; 4399 4400 /* only RV6xx+ chips are supported */ 4401 if (rdev->family <= CHIP_R600) 4402 return; 4403 4404 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4405 if (ret != 0) 4406 return; 4407 4408 if (!(mask & DRM_PCIE_SPEED_50)) 4409 return; 4410 4411 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4412 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4413 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4414 return; 4415 } 4416 4417 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4418 4419 /* 55 nm r6xx asics */ 4420 if ((rdev->family == CHIP_RV670) || 4421 (rdev->family == CHIP_RV620) || 4422 (rdev->family == CHIP_RV635)) { 4423 /* advertise upconfig capability */ 4424 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4425 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4426 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4427 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4428 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4429 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4430 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4431 LC_RECONFIG_ARC_MISSING_ESCAPE); 4432 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4433 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4434 } else { 4435 link_width_cntl |= LC_UPCONFIGURE_DIS; 4436 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4437 } 4438 } 4439 4440 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4441 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4442 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4443 4444 /* 55 nm r6xx asics */ 4445 if ((rdev->family == CHIP_RV670) || 4446 (rdev->family == CHIP_RV620) || 4447 (rdev->family == CHIP_RV635)) { 4448 WREG32(MM_CFGREGS_CNTL, 0x8); 4449 link_cntl2 = RREG32(0x4088); 4450 WREG32(MM_CFGREGS_CNTL, 0); 4451 /* not supported yet */ 4452 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4453 return; 4454 } 4455 4456 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4457 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4458 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4459 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4460 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4461 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4462 4463 tmp = RREG32(0x541c); 4464 WREG32(0x541c, tmp | 0x8); 4465 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4466 link_cntl2 = RREG16(0x4088); 4467 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4468 link_cntl2 |= 0x2; 4469 WREG16(0x4088, link_cntl2); 4470 WREG32(MM_CFGREGS_CNTL, 0); 4471 4472 if ((rdev->family == CHIP_RV670) || 4473 (rdev->family == CHIP_RV620) || 4474 (rdev->family == CHIP_RV635)) { 4475 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4476 training_cntl &= ~LC_POINT_7_PLUS_EN; 4477 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4478 } else { 4479 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4480 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4481 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4482 } 4483 4484 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4485 speed_cntl |= LC_GEN2_EN_STRAP; 4486 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4487 4488 } else { 4489 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4490 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4491 if (1) 4492 link_width_cntl |= LC_UPCONFIGURE_DIS; 4493 else 4494 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4495 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4496 } 4497 } 4498 4499 /** 4500 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4501 * 4502 * @rdev: radeon_device pointer 4503 * 4504 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4505 * Returns the 64 bit clock counter snapshot. 4506 */ 4507 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4508 { 4509 uint64_t clock; 4510 4511 mutex_lock(&rdev->gpu_clock_mutex); 4512 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4513 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4514 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4515 mutex_unlock(&rdev->gpu_clock_mutex); 4516 return clock; 4517 } 4518