1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r600.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include <uapi_drm/radeon_drm.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_mode.h" 36 #include "r600d.h" 37 #include "atom.h" 38 #include "avivod.h" 39 40 #define PFP_UCODE_SIZE 576 41 #define PM4_UCODE_SIZE 1792 42 #define RLC_UCODE_SIZE 768 43 #define R700_PFP_UCODE_SIZE 848 44 #define R700_PM4_UCODE_SIZE 1360 45 #define R700_RLC_UCODE_SIZE 1024 46 #define EVERGREEN_PFP_UCODE_SIZE 1120 47 #define EVERGREEN_PM4_UCODE_SIZE 1376 48 #define EVERGREEN_RLC_UCODE_SIZE 768 49 #define CAYMAN_RLC_UCODE_SIZE 1024 50 #define ARUBA_RLC_UCODE_SIZE 1536 51 52 #ifdef DUMBBELL_WIP 53 /* Firmware Names */ 54 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 55 MODULE_FIRMWARE("radeon/R600_me.bin"); 56 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV610_me.bin"); 58 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV630_me.bin"); 60 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV620_me.bin"); 62 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RV635_me.bin"); 64 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV670_me.bin"); 66 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 67 MODULE_FIRMWARE("radeon/RS780_me.bin"); 68 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 69 MODULE_FIRMWARE("radeon/RV770_me.bin"); 70 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 71 MODULE_FIRMWARE("radeon/RV730_me.bin"); 72 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 73 MODULE_FIRMWARE("radeon/RV710_me.bin"); 74 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 75 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 79 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 80 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 82 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 83 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 84 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 85 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 86 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 87 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 88 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 89 MODULE_FIRMWARE("radeon/PALM_me.bin"); 90 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 91 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 92 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 93 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 94 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 95 #endif /* DUMBBELL_WIP */ 96 97 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 98 99 /* r600,rv610,rv630,rv620,rv635,rv670 */ 100 static void r600_gpu_init(struct radeon_device *rdev); 101 void r600_irq_disable(struct radeon_device *rdev); 102 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 103 104 /* get temperature in millidegrees */ 105 int rv6xx_get_temp(struct radeon_device *rdev) 106 { 107 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 108 ASIC_T_SHIFT; 109 int actual_temp = temp & 0xff; 110 111 if (temp & 0x100) 112 actual_temp -= 256; 113 114 return actual_temp * 1000; 115 } 116 117 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 118 { 119 int i; 120 121 rdev->pm.dynpm_can_upclock = true; 122 rdev->pm.dynpm_can_downclock = true; 123 124 /* power state array is low to high, default is first */ 125 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 126 int min_power_state_index = 0; 127 128 if (rdev->pm.num_power_states > 2) 129 min_power_state_index = 1; 130 131 switch (rdev->pm.dynpm_planned_action) { 132 case DYNPM_ACTION_MINIMUM: 133 rdev->pm.requested_power_state_index = min_power_state_index; 134 rdev->pm.requested_clock_mode_index = 0; 135 rdev->pm.dynpm_can_downclock = false; 136 break; 137 case DYNPM_ACTION_DOWNCLOCK: 138 if (rdev->pm.current_power_state_index == min_power_state_index) { 139 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 140 rdev->pm.dynpm_can_downclock = false; 141 } else { 142 if (rdev->pm.active_crtc_count > 1) { 143 for (i = 0; i < rdev->pm.num_power_states; i++) { 144 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 145 continue; 146 else if (i >= rdev->pm.current_power_state_index) { 147 rdev->pm.requested_power_state_index = 148 rdev->pm.current_power_state_index; 149 break; 150 } else { 151 rdev->pm.requested_power_state_index = i; 152 break; 153 } 154 } 155 } else { 156 if (rdev->pm.current_power_state_index == 0) 157 rdev->pm.requested_power_state_index = 158 rdev->pm.num_power_states - 1; 159 else 160 rdev->pm.requested_power_state_index = 161 rdev->pm.current_power_state_index - 1; 162 } 163 } 164 rdev->pm.requested_clock_mode_index = 0; 165 /* don't use the power state if crtcs are active and no display flag is set */ 166 if ((rdev->pm.active_crtc_count > 0) && 167 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 168 clock_info[rdev->pm.requested_clock_mode_index].flags & 169 RADEON_PM_MODE_NO_DISPLAY)) { 170 rdev->pm.requested_power_state_index++; 171 } 172 break; 173 case DYNPM_ACTION_UPCLOCK: 174 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 175 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 176 rdev->pm.dynpm_can_upclock = false; 177 } else { 178 if (rdev->pm.active_crtc_count > 1) { 179 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 180 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 181 continue; 182 else if (i <= rdev->pm.current_power_state_index) { 183 rdev->pm.requested_power_state_index = 184 rdev->pm.current_power_state_index; 185 break; 186 } else { 187 rdev->pm.requested_power_state_index = i; 188 break; 189 } 190 } 191 } else 192 rdev->pm.requested_power_state_index = 193 rdev->pm.current_power_state_index + 1; 194 } 195 rdev->pm.requested_clock_mode_index = 0; 196 break; 197 case DYNPM_ACTION_DEFAULT: 198 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 199 rdev->pm.requested_clock_mode_index = 0; 200 rdev->pm.dynpm_can_upclock = false; 201 break; 202 case DYNPM_ACTION_NONE: 203 default: 204 DRM_ERROR("Requested mode for not defined action\n"); 205 return; 206 } 207 } else { 208 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 209 /* for now just select the first power state and switch between clock modes */ 210 /* power state array is low to high, default is first (0) */ 211 if (rdev->pm.active_crtc_count > 1) { 212 rdev->pm.requested_power_state_index = -1; 213 /* start at 1 as we don't want the default mode */ 214 for (i = 1; i < rdev->pm.num_power_states; i++) { 215 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 216 continue; 217 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 218 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 219 rdev->pm.requested_power_state_index = i; 220 break; 221 } 222 } 223 /* if nothing selected, grab the default state. */ 224 if (rdev->pm.requested_power_state_index == -1) 225 rdev->pm.requested_power_state_index = 0; 226 } else 227 rdev->pm.requested_power_state_index = 1; 228 229 switch (rdev->pm.dynpm_planned_action) { 230 case DYNPM_ACTION_MINIMUM: 231 rdev->pm.requested_clock_mode_index = 0; 232 rdev->pm.dynpm_can_downclock = false; 233 break; 234 case DYNPM_ACTION_DOWNCLOCK: 235 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 236 if (rdev->pm.current_clock_mode_index == 0) { 237 rdev->pm.requested_clock_mode_index = 0; 238 rdev->pm.dynpm_can_downclock = false; 239 } else 240 rdev->pm.requested_clock_mode_index = 241 rdev->pm.current_clock_mode_index - 1; 242 } else { 243 rdev->pm.requested_clock_mode_index = 0; 244 rdev->pm.dynpm_can_downclock = false; 245 } 246 /* don't use the power state if crtcs are active and no display flag is set */ 247 if ((rdev->pm.active_crtc_count > 0) && 248 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 249 clock_info[rdev->pm.requested_clock_mode_index].flags & 250 RADEON_PM_MODE_NO_DISPLAY)) { 251 rdev->pm.requested_clock_mode_index++; 252 } 253 break; 254 case DYNPM_ACTION_UPCLOCK: 255 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 256 if (rdev->pm.current_clock_mode_index == 257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 258 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 259 rdev->pm.dynpm_can_upclock = false; 260 } else 261 rdev->pm.requested_clock_mode_index = 262 rdev->pm.current_clock_mode_index + 1; 263 } else { 264 rdev->pm.requested_clock_mode_index = 265 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 266 rdev->pm.dynpm_can_upclock = false; 267 } 268 break; 269 case DYNPM_ACTION_DEFAULT: 270 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 271 rdev->pm.requested_clock_mode_index = 0; 272 rdev->pm.dynpm_can_upclock = false; 273 break; 274 case DYNPM_ACTION_NONE: 275 default: 276 DRM_ERROR("Requested mode for not defined action\n"); 277 return; 278 } 279 } 280 281 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 282 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 283 clock_info[rdev->pm.requested_clock_mode_index].sclk, 284 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 285 clock_info[rdev->pm.requested_clock_mode_index].mclk, 286 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 287 pcie_lanes); 288 } 289 290 void rs780_pm_init_profile(struct radeon_device *rdev) 291 { 292 if (rdev->pm.num_power_states == 2) { 293 /* default */ 294 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 298 /* low sh */ 299 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 303 /* mid sh */ 304 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 308 /* high sh */ 309 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 313 /* low mh */ 314 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 318 /* mid mh */ 319 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 323 /* high mh */ 324 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 328 } else if (rdev->pm.num_power_states == 3) { 329 /* default */ 330 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 331 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 334 /* low sh */ 335 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 339 /* mid sh */ 340 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 341 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 344 /* high sh */ 345 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 346 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 349 /* low mh */ 350 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 351 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 354 /* mid mh */ 355 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 356 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 359 /* high mh */ 360 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 361 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 364 } else { 365 /* default */ 366 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 370 /* low sh */ 371 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 372 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 375 /* mid sh */ 376 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 377 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 380 /* high sh */ 381 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 382 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 385 /* low mh */ 386 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 390 /* mid mh */ 391 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 392 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 395 /* high mh */ 396 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 397 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 400 } 401 } 402 403 void r600_pm_init_profile(struct radeon_device *rdev) 404 { 405 int idx; 406 407 if (rdev->family == CHIP_R600) { 408 /* XXX */ 409 /* default */ 410 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 411 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 414 /* low sh */ 415 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 416 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 419 /* mid sh */ 420 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 421 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 424 /* high sh */ 425 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 426 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 429 /* low mh */ 430 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 431 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 434 /* mid mh */ 435 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 436 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 439 /* high mh */ 440 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 441 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 444 } else { 445 if (rdev->pm.num_power_states < 4) { 446 /* default */ 447 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 451 /* low sh */ 452 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 453 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 456 /* mid sh */ 457 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 458 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 461 /* high sh */ 462 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 463 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 466 /* low mh */ 467 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 468 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 471 /* low mh */ 472 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 473 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 476 /* high mh */ 477 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 478 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 481 } else { 482 /* default */ 483 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 484 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 487 /* low sh */ 488 if (rdev->flags & RADEON_IS_MOBILITY) 489 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 490 else 491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 496 /* mid sh */ 497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 501 /* high sh */ 502 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 507 /* low mh */ 508 if (rdev->flags & RADEON_IS_MOBILITY) 509 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 510 else 511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 512 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 513 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 516 /* mid mh */ 517 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 518 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 521 /* high mh */ 522 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 523 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 524 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 527 } 528 } 529 } 530 531 void r600_pm_misc(struct radeon_device *rdev) 532 { 533 int req_ps_idx = rdev->pm.requested_power_state_index; 534 int req_cm_idx = rdev->pm.requested_clock_mode_index; 535 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 536 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 537 538 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 539 /* 0xff01 is a flag rather then an actual voltage */ 540 if (voltage->voltage == 0xff01) 541 return; 542 if (voltage->voltage != rdev->pm.current_vddc) { 543 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 544 rdev->pm.current_vddc = voltage->voltage; 545 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 546 } 547 } 548 } 549 550 bool r600_gui_idle(struct radeon_device *rdev) 551 { 552 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 553 return false; 554 else 555 return true; 556 } 557 558 /* hpd for digital panel detect/disconnect */ 559 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 560 { 561 bool connected = false; 562 563 if (ASIC_IS_DCE3(rdev)) { 564 switch (hpd) { 565 case RADEON_HPD_1: 566 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 567 connected = true; 568 break; 569 case RADEON_HPD_2: 570 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 571 connected = true; 572 break; 573 case RADEON_HPD_3: 574 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 575 connected = true; 576 break; 577 case RADEON_HPD_4: 578 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 579 connected = true; 580 break; 581 /* DCE 3.2 */ 582 case RADEON_HPD_5: 583 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 584 connected = true; 585 break; 586 case RADEON_HPD_6: 587 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 588 connected = true; 589 break; 590 default: 591 break; 592 } 593 } else { 594 switch (hpd) { 595 case RADEON_HPD_1: 596 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 597 connected = true; 598 break; 599 case RADEON_HPD_2: 600 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 601 connected = true; 602 break; 603 case RADEON_HPD_3: 604 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 605 connected = true; 606 break; 607 default: 608 break; 609 } 610 } 611 return connected; 612 } 613 614 void r600_hpd_set_polarity(struct radeon_device *rdev, 615 enum radeon_hpd_id hpd) 616 { 617 u32 tmp; 618 bool connected = r600_hpd_sense(rdev, hpd); 619 620 if (ASIC_IS_DCE3(rdev)) { 621 switch (hpd) { 622 case RADEON_HPD_1: 623 tmp = RREG32(DC_HPD1_INT_CONTROL); 624 if (connected) 625 tmp &= ~DC_HPDx_INT_POLARITY; 626 else 627 tmp |= DC_HPDx_INT_POLARITY; 628 WREG32(DC_HPD1_INT_CONTROL, tmp); 629 break; 630 case RADEON_HPD_2: 631 tmp = RREG32(DC_HPD2_INT_CONTROL); 632 if (connected) 633 tmp &= ~DC_HPDx_INT_POLARITY; 634 else 635 tmp |= DC_HPDx_INT_POLARITY; 636 WREG32(DC_HPD2_INT_CONTROL, tmp); 637 break; 638 case RADEON_HPD_3: 639 tmp = RREG32(DC_HPD3_INT_CONTROL); 640 if (connected) 641 tmp &= ~DC_HPDx_INT_POLARITY; 642 else 643 tmp |= DC_HPDx_INT_POLARITY; 644 WREG32(DC_HPD3_INT_CONTROL, tmp); 645 break; 646 case RADEON_HPD_4: 647 tmp = RREG32(DC_HPD4_INT_CONTROL); 648 if (connected) 649 tmp &= ~DC_HPDx_INT_POLARITY; 650 else 651 tmp |= DC_HPDx_INT_POLARITY; 652 WREG32(DC_HPD4_INT_CONTROL, tmp); 653 break; 654 case RADEON_HPD_5: 655 tmp = RREG32(DC_HPD5_INT_CONTROL); 656 if (connected) 657 tmp &= ~DC_HPDx_INT_POLARITY; 658 else 659 tmp |= DC_HPDx_INT_POLARITY; 660 WREG32(DC_HPD5_INT_CONTROL, tmp); 661 break; 662 /* DCE 3.2 */ 663 case RADEON_HPD_6: 664 tmp = RREG32(DC_HPD6_INT_CONTROL); 665 if (connected) 666 tmp &= ~DC_HPDx_INT_POLARITY; 667 else 668 tmp |= DC_HPDx_INT_POLARITY; 669 WREG32(DC_HPD6_INT_CONTROL, tmp); 670 break; 671 default: 672 break; 673 } 674 } else { 675 switch (hpd) { 676 case RADEON_HPD_1: 677 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 678 if (connected) 679 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 680 else 681 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 682 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 683 break; 684 case RADEON_HPD_2: 685 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 686 if (connected) 687 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 688 else 689 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 690 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 691 break; 692 case RADEON_HPD_3: 693 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 694 if (connected) 695 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 696 else 697 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 698 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 699 break; 700 default: 701 break; 702 } 703 } 704 } 705 706 void r600_hpd_init(struct radeon_device *rdev) 707 { 708 struct drm_device *dev = rdev->ddev; 709 struct drm_connector *connector; 710 unsigned enable = 0; 711 712 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 713 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 714 715 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 716 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 717 /* don't try to enable hpd on eDP or LVDS avoid breaking the 718 * aux dp channel on imac and help (but not completely fix) 719 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 720 */ 721 continue; 722 } 723 if (ASIC_IS_DCE3(rdev)) { 724 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 725 if (ASIC_IS_DCE32(rdev)) 726 tmp |= DC_HPDx_EN; 727 728 switch (radeon_connector->hpd.hpd) { 729 case RADEON_HPD_1: 730 WREG32(DC_HPD1_CONTROL, tmp); 731 break; 732 case RADEON_HPD_2: 733 WREG32(DC_HPD2_CONTROL, tmp); 734 break; 735 case RADEON_HPD_3: 736 WREG32(DC_HPD3_CONTROL, tmp); 737 break; 738 case RADEON_HPD_4: 739 WREG32(DC_HPD4_CONTROL, tmp); 740 break; 741 /* DCE 3.2 */ 742 case RADEON_HPD_5: 743 WREG32(DC_HPD5_CONTROL, tmp); 744 break; 745 case RADEON_HPD_6: 746 WREG32(DC_HPD6_CONTROL, tmp); 747 break; 748 default: 749 break; 750 } 751 } else { 752 switch (radeon_connector->hpd.hpd) { 753 case RADEON_HPD_1: 754 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 755 break; 756 case RADEON_HPD_2: 757 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 758 break; 759 case RADEON_HPD_3: 760 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 761 break; 762 default: 763 break; 764 } 765 } 766 enable |= 1 << radeon_connector->hpd.hpd; 767 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 768 } 769 radeon_irq_kms_enable_hpd(rdev, enable); 770 } 771 772 void r600_hpd_fini(struct radeon_device *rdev) 773 { 774 struct drm_device *dev = rdev->ddev; 775 struct drm_connector *connector; 776 unsigned disable = 0; 777 778 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 779 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 780 if (ASIC_IS_DCE3(rdev)) { 781 switch (radeon_connector->hpd.hpd) { 782 case RADEON_HPD_1: 783 WREG32(DC_HPD1_CONTROL, 0); 784 break; 785 case RADEON_HPD_2: 786 WREG32(DC_HPD2_CONTROL, 0); 787 break; 788 case RADEON_HPD_3: 789 WREG32(DC_HPD3_CONTROL, 0); 790 break; 791 case RADEON_HPD_4: 792 WREG32(DC_HPD4_CONTROL, 0); 793 break; 794 /* DCE 3.2 */ 795 case RADEON_HPD_5: 796 WREG32(DC_HPD5_CONTROL, 0); 797 break; 798 case RADEON_HPD_6: 799 WREG32(DC_HPD6_CONTROL, 0); 800 break; 801 default: 802 break; 803 } 804 } else { 805 switch (radeon_connector->hpd.hpd) { 806 case RADEON_HPD_1: 807 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 808 break; 809 case RADEON_HPD_2: 810 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 811 break; 812 case RADEON_HPD_3: 813 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 814 break; 815 default: 816 break; 817 } 818 } 819 disable |= 1 << radeon_connector->hpd.hpd; 820 } 821 radeon_irq_kms_disable_hpd(rdev, disable); 822 } 823 824 /* 825 * R600 PCIE GART 826 */ 827 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 828 { 829 unsigned i; 830 u32 tmp; 831 832 /* flush hdp cache so updates hit vram */ 833 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 834 !(rdev->flags & RADEON_IS_AGP)) { 835 volatile uint32_t *ptr = rdev->gart.ptr; 836 u32 tmp; 837 838 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 839 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 840 * This seems to cause problems on some AGP cards. Just use the old 841 * method for them. 842 */ 843 WREG32(HDP_DEBUG1, 0); 844 tmp = *ptr; 845 } else 846 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 847 848 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 849 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 850 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 851 for (i = 0; i < rdev->usec_timeout; i++) { 852 /* read MC_STATUS */ 853 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 854 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 855 if (tmp == 2) { 856 DRM_ERROR("[drm] r600 flush TLB failed\n"); 857 return; 858 } 859 if (tmp) { 860 return; 861 } 862 DRM_UDELAY(1); 863 } 864 } 865 866 int r600_pcie_gart_init(struct radeon_device *rdev) 867 { 868 int r; 869 870 if (rdev->gart.robj) { 871 DRM_ERROR("R600 PCIE GART already initialized\n"); 872 return 0; 873 } 874 /* Initialize common gart structure */ 875 r = radeon_gart_init(rdev); 876 if (r) 877 return r; 878 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 879 return radeon_gart_table_vram_alloc(rdev); 880 } 881 882 static int r600_pcie_gart_enable(struct radeon_device *rdev) 883 { 884 u32 tmp; 885 int r, i; 886 887 if (rdev->gart.robj == NULL) { 888 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 889 return -EINVAL; 890 } 891 r = radeon_gart_table_vram_pin(rdev); 892 if (r) 893 return r; 894 radeon_gart_restore(rdev); 895 896 /* Setup L2 cache */ 897 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 898 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 899 EFFECTIVE_L2_QUEUE_SIZE(7)); 900 WREG32(VM_L2_CNTL2, 0); 901 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 902 /* Setup TLB control */ 903 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 904 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 905 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 906 ENABLE_WAIT_L2_QUERY; 907 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 908 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 909 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 910 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 911 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 912 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 913 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 914 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 915 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 916 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 917 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 918 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 919 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 920 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 921 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 922 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 923 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 924 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 925 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 926 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 927 (u32)(rdev->dummy_page.addr >> 12)); 928 for (i = 1; i < 7; i++) 929 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 930 931 r600_pcie_gart_tlb_flush(rdev); 932 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 933 (unsigned)(rdev->mc.gtt_size >> 20), 934 (unsigned long long)rdev->gart.table_addr); 935 rdev->gart.ready = true; 936 return 0; 937 } 938 939 static void r600_pcie_gart_disable(struct radeon_device *rdev) 940 { 941 u32 tmp; 942 int i; 943 944 /* Disable all tables */ 945 for (i = 0; i < 7; i++) 946 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 947 948 /* Disable L2 cache */ 949 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 950 EFFECTIVE_L2_QUEUE_SIZE(7)); 951 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 952 /* Setup L1 TLB control */ 953 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 954 ENABLE_WAIT_L2_QUERY; 955 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 956 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 957 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 958 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 959 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 960 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 961 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 962 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 963 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 964 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 965 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 966 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 967 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 968 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 969 radeon_gart_table_vram_unpin(rdev); 970 } 971 972 static void r600_pcie_gart_fini(struct radeon_device *rdev) 973 { 974 radeon_gart_fini(rdev); 975 r600_pcie_gart_disable(rdev); 976 radeon_gart_table_vram_free(rdev); 977 } 978 979 static void r600_agp_enable(struct radeon_device *rdev) 980 { 981 u32 tmp; 982 int i; 983 984 /* Setup L2 cache */ 985 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 986 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 987 EFFECTIVE_L2_QUEUE_SIZE(7)); 988 WREG32(VM_L2_CNTL2, 0); 989 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 990 /* Setup TLB control */ 991 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 992 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 993 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 994 ENABLE_WAIT_L2_QUERY; 995 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 996 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 997 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 998 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 999 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1000 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1001 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1002 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1003 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1004 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1005 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1006 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1007 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1008 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1009 for (i = 0; i < 7; i++) 1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1011 } 1012 1013 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1014 { 1015 unsigned i; 1016 u32 tmp; 1017 1018 for (i = 0; i < rdev->usec_timeout; i++) { 1019 /* read MC_STATUS */ 1020 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1021 if (!tmp) 1022 return 0; 1023 DRM_UDELAY(1); 1024 } 1025 return -1; 1026 } 1027 1028 static void r600_mc_program(struct radeon_device *rdev) 1029 { 1030 struct rv515_mc_save save; 1031 u32 tmp; 1032 int i, j; 1033 1034 /* Initialize HDP */ 1035 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1036 WREG32((0x2c14 + j), 0x00000000); 1037 WREG32((0x2c18 + j), 0x00000000); 1038 WREG32((0x2c1c + j), 0x00000000); 1039 WREG32((0x2c20 + j), 0x00000000); 1040 WREG32((0x2c24 + j), 0x00000000); 1041 } 1042 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1043 1044 rv515_mc_stop(rdev, &save); 1045 if (r600_mc_wait_for_idle(rdev)) { 1046 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1047 } 1048 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1049 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1050 /* Update configuration */ 1051 if (rdev->flags & RADEON_IS_AGP) { 1052 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1053 /* VRAM before AGP */ 1054 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1055 rdev->mc.vram_start >> 12); 1056 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1057 rdev->mc.gtt_end >> 12); 1058 } else { 1059 /* VRAM after AGP */ 1060 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1061 rdev->mc.gtt_start >> 12); 1062 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1063 rdev->mc.vram_end >> 12); 1064 } 1065 } else { 1066 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1067 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1068 } 1069 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1070 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1071 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1072 WREG32(MC_VM_FB_LOCATION, tmp); 1073 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1074 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1075 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1076 if (rdev->flags & RADEON_IS_AGP) { 1077 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1078 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1079 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1080 } else { 1081 WREG32(MC_VM_AGP_BASE, 0); 1082 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1083 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1084 } 1085 if (r600_mc_wait_for_idle(rdev)) { 1086 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1087 } 1088 rv515_mc_resume(rdev, &save); 1089 /* we need to own VRAM, so turn off the VGA renderer here 1090 * to stop it overwriting our objects */ 1091 rv515_vga_render_disable(rdev); 1092 } 1093 1094 /** 1095 * r600_vram_gtt_location - try to find VRAM & GTT location 1096 * @rdev: radeon device structure holding all necessary informations 1097 * @mc: memory controller structure holding memory informations 1098 * 1099 * Function will place try to place VRAM at same place as in CPU (PCI) 1100 * address space as some GPU seems to have issue when we reprogram at 1101 * different address space. 1102 * 1103 * If there is not enough space to fit the unvisible VRAM after the 1104 * aperture then we limit the VRAM size to the aperture. 1105 * 1106 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1107 * them to be in one from GPU point of view so that we can program GPU to 1108 * catch access outside them (weird GPU policy see ??). 1109 * 1110 * This function will never fails, worst case are limiting VRAM or GTT. 1111 * 1112 * Note: GTT start, end, size should be initialized before calling this 1113 * function on AGP platform. 1114 */ 1115 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1116 { 1117 u64 size_bf, size_af; 1118 1119 if (mc->mc_vram_size > 0xE0000000) { 1120 /* leave room for at least 512M GTT */ 1121 dev_warn(rdev->dev, "limiting VRAM\n"); 1122 mc->real_vram_size = 0xE0000000; 1123 mc->mc_vram_size = 0xE0000000; 1124 } 1125 if (rdev->flags & RADEON_IS_AGP) { 1126 size_bf = mc->gtt_start; 1127 size_af = 0xFFFFFFFF - mc->gtt_end; 1128 if (size_bf > size_af) { 1129 if (mc->mc_vram_size > size_bf) { 1130 dev_warn(rdev->dev, "limiting VRAM\n"); 1131 mc->real_vram_size = size_bf; 1132 mc->mc_vram_size = size_bf; 1133 } 1134 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1135 } else { 1136 if (mc->mc_vram_size > size_af) { 1137 dev_warn(rdev->dev, "limiting VRAM\n"); 1138 mc->real_vram_size = size_af; 1139 mc->mc_vram_size = size_af; 1140 } 1141 mc->vram_start = mc->gtt_end + 1; 1142 } 1143 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1144 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1145 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, 1146 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); 1147 } else { 1148 u64 base = 0; 1149 if (rdev->flags & RADEON_IS_IGP) { 1150 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1151 base <<= 24; 1152 } 1153 radeon_vram_location(rdev, &rdev->mc, base); 1154 rdev->mc.gtt_base_align = 0; 1155 radeon_gtt_location(rdev, mc); 1156 } 1157 } 1158 1159 static int r600_mc_init(struct radeon_device *rdev) 1160 { 1161 u32 tmp; 1162 int chansize, numchan; 1163 1164 /* Get VRAM informations */ 1165 rdev->mc.vram_is_ddr = true; 1166 tmp = RREG32(RAMCFG); 1167 if (tmp & CHANSIZE_OVERRIDE) { 1168 chansize = 16; 1169 } else if (tmp & CHANSIZE_MASK) { 1170 chansize = 64; 1171 } else { 1172 chansize = 32; 1173 } 1174 tmp = RREG32(CHMAP); 1175 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1176 case 0: 1177 default: 1178 numchan = 1; 1179 break; 1180 case 1: 1181 numchan = 2; 1182 break; 1183 case 2: 1184 numchan = 4; 1185 break; 1186 case 3: 1187 numchan = 8; 1188 break; 1189 } 1190 rdev->mc.vram_width = numchan * chansize; 1191 /* Could aper size report 0 ? */ 1192 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1193 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1194 /* Setup GPU memory space */ 1195 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1196 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1197 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1198 r600_vram_gtt_location(rdev, &rdev->mc); 1199 1200 if (rdev->flags & RADEON_IS_IGP) { 1201 rs690_pm_info(rdev); 1202 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1203 } 1204 radeon_update_bandwidth_info(rdev); 1205 return 0; 1206 } 1207 1208 int r600_vram_scratch_init(struct radeon_device *rdev) 1209 { 1210 int r; 1211 void *vram_scratch_ptr_ptr; 1212 1213 if (rdev->vram_scratch.robj == NULL) { 1214 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1215 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1216 NULL, &rdev->vram_scratch.robj); 1217 if (r) { 1218 return r; 1219 } 1220 } 1221 1222 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1223 if (unlikely(r != 0)) { 1224 radeon_bo_unref(&rdev->vram_scratch.robj); 1225 return r; 1226 } 1227 r = radeon_bo_pin(rdev->vram_scratch.robj, 1228 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1229 if (r) { 1230 radeon_bo_unreserve(rdev->vram_scratch.robj); 1231 radeon_bo_unref(&rdev->vram_scratch.robj); 1232 return r; 1233 } 1234 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1235 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1236 vram_scratch_ptr_ptr); 1237 if (r) 1238 radeon_bo_unpin(rdev->vram_scratch.robj); 1239 radeon_bo_unreserve(rdev->vram_scratch.robj); 1240 if (r) 1241 radeon_bo_unref(&rdev->vram_scratch.robj); 1242 1243 return r; 1244 } 1245 1246 void r600_vram_scratch_fini(struct radeon_device *rdev) 1247 { 1248 int r; 1249 1250 if (rdev->vram_scratch.robj == NULL) { 1251 return; 1252 } 1253 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1254 if (likely(r == 0)) { 1255 radeon_bo_kunmap(rdev->vram_scratch.robj); 1256 radeon_bo_unpin(rdev->vram_scratch.robj); 1257 radeon_bo_unreserve(rdev->vram_scratch.robj); 1258 } 1259 radeon_bo_unref(&rdev->vram_scratch.robj); 1260 } 1261 1262 /* We doesn't check that the GPU really needs a reset we simply do the 1263 * reset, it's up to the caller to determine if the GPU needs one. We 1264 * might add an helper function to check that. 1265 */ 1266 static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) 1267 { 1268 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1269 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 1270 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 1271 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 1272 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 1273 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 1274 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 1275 S_008010_GUI_ACTIVE(1); 1276 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 1277 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 1278 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 1279 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 1280 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 1281 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 1282 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 1283 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 1284 u32 tmp; 1285 1286 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1287 return; 1288 1289 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1290 RREG32(R_008010_GRBM_STATUS)); 1291 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1292 RREG32(R_008014_GRBM_STATUS2)); 1293 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1294 RREG32(R_000E50_SRBM_STATUS)); 1295 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1296 RREG32(CP_STALLED_STAT1)); 1297 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1298 RREG32(CP_STALLED_STAT2)); 1299 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1300 RREG32(CP_BUSY_STAT)); 1301 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1302 RREG32(CP_STAT)); 1303 1304 /* Disable CP parsing/prefetching */ 1305 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1306 1307 /* Check if any of the rendering block is busy and reset it */ 1308 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1309 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1310 tmp = S_008020_SOFT_RESET_CR(1) | 1311 S_008020_SOFT_RESET_DB(1) | 1312 S_008020_SOFT_RESET_CB(1) | 1313 S_008020_SOFT_RESET_PA(1) | 1314 S_008020_SOFT_RESET_SC(1) | 1315 S_008020_SOFT_RESET_SMX(1) | 1316 S_008020_SOFT_RESET_SPI(1) | 1317 S_008020_SOFT_RESET_SX(1) | 1318 S_008020_SOFT_RESET_SH(1) | 1319 S_008020_SOFT_RESET_TC(1) | 1320 S_008020_SOFT_RESET_TA(1) | 1321 S_008020_SOFT_RESET_VC(1) | 1322 S_008020_SOFT_RESET_VGT(1); 1323 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1325 RREG32(R_008020_GRBM_SOFT_RESET); 1326 DRM_MDELAY(15); 1327 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1328 } 1329 /* Reset CP (we always reset CP) */ 1330 tmp = S_008020_SOFT_RESET_CP(1); 1331 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1332 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1333 RREG32(R_008020_GRBM_SOFT_RESET); 1334 DRM_MDELAY(15); 1335 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1336 1337 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1338 RREG32(R_008010_GRBM_STATUS)); 1339 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1340 RREG32(R_008014_GRBM_STATUS2)); 1341 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1342 RREG32(R_000E50_SRBM_STATUS)); 1343 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1344 RREG32(CP_STALLED_STAT1)); 1345 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1346 RREG32(CP_STALLED_STAT2)); 1347 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1348 RREG32(CP_BUSY_STAT)); 1349 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1350 RREG32(CP_STAT)); 1351 1352 } 1353 1354 static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) 1355 { 1356 u32 tmp; 1357 1358 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1359 return; 1360 1361 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1362 RREG32(DMA_STATUS_REG)); 1363 1364 /* Disable DMA */ 1365 tmp = RREG32(DMA_RB_CNTL); 1366 tmp &= ~DMA_RB_ENABLE; 1367 WREG32(DMA_RB_CNTL, tmp); 1368 1369 /* Reset dma */ 1370 if (rdev->family >= CHIP_RV770) 1371 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 1372 else 1373 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 1374 RREG32(SRBM_SOFT_RESET); 1375 DRM_UDELAY(50); 1376 WREG32(SRBM_SOFT_RESET, 0); 1377 1378 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1379 RREG32(DMA_STATUS_REG)); 1380 } 1381 1382 static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1383 { 1384 struct rv515_mc_save save; 1385 1386 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1387 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 1388 1389 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1390 reset_mask &= ~RADEON_RESET_DMA; 1391 1392 if (reset_mask == 0) 1393 return 0; 1394 1395 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1396 1397 rv515_mc_stop(rdev, &save); 1398 if (r600_mc_wait_for_idle(rdev)) { 1399 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1400 } 1401 1402 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 1403 r600_gpu_soft_reset_gfx(rdev); 1404 1405 if (reset_mask & RADEON_RESET_DMA) 1406 r600_gpu_soft_reset_dma(rdev); 1407 1408 /* Wait a little for things to settle down */ 1409 DRM_MDELAY(1); 1410 1411 rv515_mc_resume(rdev, &save); 1412 return 0; 1413 } 1414 1415 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1416 { 1417 u32 srbm_status; 1418 u32 grbm_status; 1419 u32 grbm_status2; 1420 1421 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1422 grbm_status = RREG32(R_008010_GRBM_STATUS); 1423 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1424 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1425 radeon_ring_lockup_update(ring); 1426 return false; 1427 } 1428 /* force CP activities */ 1429 radeon_ring_force_activity(rdev, ring); 1430 return radeon_ring_test_lockup(rdev, ring); 1431 } 1432 1433 /** 1434 * r600_dma_is_lockup - Check if the DMA engine is locked up 1435 * 1436 * @rdev: radeon_device pointer 1437 * @ring: radeon_ring structure holding ring information 1438 * 1439 * Check if the async DMA engine is locked up (r6xx-evergreen). 1440 * Returns true if the engine appears to be locked up, false if not. 1441 */ 1442 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1443 { 1444 u32 dma_status_reg; 1445 1446 dma_status_reg = RREG32(DMA_STATUS_REG); 1447 if (dma_status_reg & DMA_IDLE) { 1448 radeon_ring_lockup_update(ring); 1449 return false; 1450 } 1451 /* force ring activities */ 1452 radeon_ring_force_activity(rdev, ring); 1453 return radeon_ring_test_lockup(rdev, ring); 1454 } 1455 1456 int r600_asic_reset(struct radeon_device *rdev) 1457 { 1458 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 1459 RADEON_RESET_COMPUTE | 1460 RADEON_RESET_DMA)); 1461 } 1462 1463 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1464 u32 tiling_pipe_num, 1465 u32 max_rb_num, 1466 u32 total_max_rb_num, 1467 u32 disabled_rb_mask) 1468 { 1469 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1470 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1471 u32 data = 0, mask = 1 << (max_rb_num - 1); 1472 unsigned i, j; 1473 1474 /* mask out the RBs that don't exist on that asic */ 1475 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1476 /* make sure at least one RB is available */ 1477 if ((tmp & 0xff) != 0xff) 1478 disabled_rb_mask = tmp; 1479 1480 rendering_pipe_num = 1 << tiling_pipe_num; 1481 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1482 KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num")); 1483 1484 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1485 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1486 1487 if (rdev->family <= CHIP_RV740) { 1488 /* r6xx/r7xx */ 1489 rb_num_width = 2; 1490 } else { 1491 /* eg+ */ 1492 rb_num_width = 4; 1493 } 1494 1495 for (i = 0; i < max_rb_num; i++) { 1496 if (!(mask & disabled_rb_mask)) { 1497 for (j = 0; j < pipe_rb_ratio; j++) { 1498 data <<= rb_num_width; 1499 data |= max_rb_num - i - 1; 1500 } 1501 if (pipe_rb_remain) { 1502 data <<= rb_num_width; 1503 data |= max_rb_num - i - 1; 1504 pipe_rb_remain--; 1505 } 1506 } 1507 mask >>= 1; 1508 } 1509 1510 return data; 1511 } 1512 1513 int r600_count_pipe_bits(uint32_t val) 1514 { 1515 return hweight32(val); 1516 } 1517 1518 static void r600_gpu_init(struct radeon_device *rdev) 1519 { 1520 u32 tiling_config; 1521 u32 ramcfg; 1522 u32 cc_rb_backend_disable; 1523 u32 cc_gc_shader_pipe_config; 1524 u32 tmp; 1525 int i, j; 1526 u32 sq_config; 1527 u32 sq_gpr_resource_mgmt_1 = 0; 1528 u32 sq_gpr_resource_mgmt_2 = 0; 1529 u32 sq_thread_resource_mgmt = 0; 1530 u32 sq_stack_resource_mgmt_1 = 0; 1531 u32 sq_stack_resource_mgmt_2 = 0; 1532 u32 disabled_rb_mask; 1533 1534 rdev->config.r600.tiling_group_size = 256; 1535 switch (rdev->family) { 1536 case CHIP_R600: 1537 rdev->config.r600.max_pipes = 4; 1538 rdev->config.r600.max_tile_pipes = 8; 1539 rdev->config.r600.max_simds = 4; 1540 rdev->config.r600.max_backends = 4; 1541 rdev->config.r600.max_gprs = 256; 1542 rdev->config.r600.max_threads = 192; 1543 rdev->config.r600.max_stack_entries = 256; 1544 rdev->config.r600.max_hw_contexts = 8; 1545 rdev->config.r600.max_gs_threads = 16; 1546 rdev->config.r600.sx_max_export_size = 128; 1547 rdev->config.r600.sx_max_export_pos_size = 16; 1548 rdev->config.r600.sx_max_export_smx_size = 128; 1549 rdev->config.r600.sq_num_cf_insts = 2; 1550 break; 1551 case CHIP_RV630: 1552 case CHIP_RV635: 1553 rdev->config.r600.max_pipes = 2; 1554 rdev->config.r600.max_tile_pipes = 2; 1555 rdev->config.r600.max_simds = 3; 1556 rdev->config.r600.max_backends = 1; 1557 rdev->config.r600.max_gprs = 128; 1558 rdev->config.r600.max_threads = 192; 1559 rdev->config.r600.max_stack_entries = 128; 1560 rdev->config.r600.max_hw_contexts = 8; 1561 rdev->config.r600.max_gs_threads = 4; 1562 rdev->config.r600.sx_max_export_size = 128; 1563 rdev->config.r600.sx_max_export_pos_size = 16; 1564 rdev->config.r600.sx_max_export_smx_size = 128; 1565 rdev->config.r600.sq_num_cf_insts = 2; 1566 break; 1567 case CHIP_RV610: 1568 case CHIP_RV620: 1569 case CHIP_RS780: 1570 case CHIP_RS880: 1571 rdev->config.r600.max_pipes = 1; 1572 rdev->config.r600.max_tile_pipes = 1; 1573 rdev->config.r600.max_simds = 2; 1574 rdev->config.r600.max_backends = 1; 1575 rdev->config.r600.max_gprs = 128; 1576 rdev->config.r600.max_threads = 192; 1577 rdev->config.r600.max_stack_entries = 128; 1578 rdev->config.r600.max_hw_contexts = 4; 1579 rdev->config.r600.max_gs_threads = 4; 1580 rdev->config.r600.sx_max_export_size = 128; 1581 rdev->config.r600.sx_max_export_pos_size = 16; 1582 rdev->config.r600.sx_max_export_smx_size = 128; 1583 rdev->config.r600.sq_num_cf_insts = 1; 1584 break; 1585 case CHIP_RV670: 1586 rdev->config.r600.max_pipes = 4; 1587 rdev->config.r600.max_tile_pipes = 4; 1588 rdev->config.r600.max_simds = 4; 1589 rdev->config.r600.max_backends = 4; 1590 rdev->config.r600.max_gprs = 192; 1591 rdev->config.r600.max_threads = 192; 1592 rdev->config.r600.max_stack_entries = 256; 1593 rdev->config.r600.max_hw_contexts = 8; 1594 rdev->config.r600.max_gs_threads = 16; 1595 rdev->config.r600.sx_max_export_size = 128; 1596 rdev->config.r600.sx_max_export_pos_size = 16; 1597 rdev->config.r600.sx_max_export_smx_size = 128; 1598 rdev->config.r600.sq_num_cf_insts = 2; 1599 break; 1600 default: 1601 break; 1602 } 1603 1604 /* Initialize HDP */ 1605 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1606 WREG32((0x2c14 + j), 0x00000000); 1607 WREG32((0x2c18 + j), 0x00000000); 1608 WREG32((0x2c1c + j), 0x00000000); 1609 WREG32((0x2c20 + j), 0x00000000); 1610 WREG32((0x2c24 + j), 0x00000000); 1611 } 1612 1613 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1614 1615 /* Setup tiling */ 1616 tiling_config = 0; 1617 ramcfg = RREG32(RAMCFG); 1618 switch (rdev->config.r600.max_tile_pipes) { 1619 case 1: 1620 tiling_config |= PIPE_TILING(0); 1621 break; 1622 case 2: 1623 tiling_config |= PIPE_TILING(1); 1624 break; 1625 case 4: 1626 tiling_config |= PIPE_TILING(2); 1627 break; 1628 case 8: 1629 tiling_config |= PIPE_TILING(3); 1630 break; 1631 default: 1632 break; 1633 } 1634 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1635 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1636 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1637 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1638 1639 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1640 if (tmp > 3) { 1641 tiling_config |= ROW_TILING(3); 1642 tiling_config |= SAMPLE_SPLIT(3); 1643 } else { 1644 tiling_config |= ROW_TILING(tmp); 1645 tiling_config |= SAMPLE_SPLIT(tmp); 1646 } 1647 tiling_config |= BANK_SWAPS(1); 1648 1649 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1650 tmp = R6XX_MAX_BACKENDS - 1651 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1652 if (tmp < rdev->config.r600.max_backends) { 1653 rdev->config.r600.max_backends = tmp; 1654 } 1655 1656 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1657 tmp = R6XX_MAX_PIPES - 1658 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1659 if (tmp < rdev->config.r600.max_pipes) { 1660 rdev->config.r600.max_pipes = tmp; 1661 } 1662 tmp = R6XX_MAX_SIMDS - 1663 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1664 if (tmp < rdev->config.r600.max_simds) { 1665 rdev->config.r600.max_simds = tmp; 1666 } 1667 1668 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1669 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1670 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1671 R6XX_MAX_BACKENDS, disabled_rb_mask); 1672 tiling_config |= tmp << 16; 1673 rdev->config.r600.backend_map = tmp; 1674 1675 rdev->config.r600.tile_config = tiling_config; 1676 WREG32(GB_TILING_CONFIG, tiling_config); 1677 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1678 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1679 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1680 1681 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1682 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1683 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1684 1685 /* Setup some CP states */ 1686 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1687 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1688 1689 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1690 SYNC_WALKER | SYNC_ALIGNER)); 1691 /* Setup various GPU states */ 1692 if (rdev->family == CHIP_RV670) 1693 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1694 1695 tmp = RREG32(SX_DEBUG_1); 1696 tmp |= SMX_EVENT_RELEASE; 1697 if ((rdev->family > CHIP_R600)) 1698 tmp |= ENABLE_NEW_SMX_ADDRESS; 1699 WREG32(SX_DEBUG_1, tmp); 1700 1701 if (((rdev->family) == CHIP_R600) || 1702 ((rdev->family) == CHIP_RV630) || 1703 ((rdev->family) == CHIP_RV610) || 1704 ((rdev->family) == CHIP_RV620) || 1705 ((rdev->family) == CHIP_RS780) || 1706 ((rdev->family) == CHIP_RS880)) { 1707 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1708 } else { 1709 WREG32(DB_DEBUG, 0); 1710 } 1711 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1712 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1713 1714 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1715 WREG32(VGT_NUM_INSTANCES, 0); 1716 1717 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1718 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1719 1720 tmp = RREG32(SQ_MS_FIFO_SIZES); 1721 if (((rdev->family) == CHIP_RV610) || 1722 ((rdev->family) == CHIP_RV620) || 1723 ((rdev->family) == CHIP_RS780) || 1724 ((rdev->family) == CHIP_RS880)) { 1725 tmp = (CACHE_FIFO_SIZE(0xa) | 1726 FETCH_FIFO_HIWATER(0xa) | 1727 DONE_FIFO_HIWATER(0xe0) | 1728 ALU_UPDATE_FIFO_HIWATER(0x8)); 1729 } else if (((rdev->family) == CHIP_R600) || 1730 ((rdev->family) == CHIP_RV630)) { 1731 tmp &= ~DONE_FIFO_HIWATER(0xff); 1732 tmp |= DONE_FIFO_HIWATER(0x4); 1733 } 1734 WREG32(SQ_MS_FIFO_SIZES, tmp); 1735 1736 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1737 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1738 */ 1739 sq_config = RREG32(SQ_CONFIG); 1740 sq_config &= ~(PS_PRIO(3) | 1741 VS_PRIO(3) | 1742 GS_PRIO(3) | 1743 ES_PRIO(3)); 1744 sq_config |= (DX9_CONSTS | 1745 VC_ENABLE | 1746 PS_PRIO(0) | 1747 VS_PRIO(1) | 1748 GS_PRIO(2) | 1749 ES_PRIO(3)); 1750 1751 if ((rdev->family) == CHIP_R600) { 1752 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1753 NUM_VS_GPRS(124) | 1754 NUM_CLAUSE_TEMP_GPRS(4)); 1755 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1756 NUM_ES_GPRS(0)); 1757 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1758 NUM_VS_THREADS(48) | 1759 NUM_GS_THREADS(4) | 1760 NUM_ES_THREADS(4)); 1761 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1762 NUM_VS_STACK_ENTRIES(128)); 1763 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1764 NUM_ES_STACK_ENTRIES(0)); 1765 } else if (((rdev->family) == CHIP_RV610) || 1766 ((rdev->family) == CHIP_RV620) || 1767 ((rdev->family) == CHIP_RS780) || 1768 ((rdev->family) == CHIP_RS880)) { 1769 /* no vertex cache */ 1770 sq_config &= ~VC_ENABLE; 1771 1772 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1773 NUM_VS_GPRS(44) | 1774 NUM_CLAUSE_TEMP_GPRS(2)); 1775 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1776 NUM_ES_GPRS(17)); 1777 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1778 NUM_VS_THREADS(78) | 1779 NUM_GS_THREADS(4) | 1780 NUM_ES_THREADS(31)); 1781 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1782 NUM_VS_STACK_ENTRIES(40)); 1783 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1784 NUM_ES_STACK_ENTRIES(16)); 1785 } else if (((rdev->family) == CHIP_RV630) || 1786 ((rdev->family) == CHIP_RV635)) { 1787 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1788 NUM_VS_GPRS(44) | 1789 NUM_CLAUSE_TEMP_GPRS(2)); 1790 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1791 NUM_ES_GPRS(18)); 1792 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1793 NUM_VS_THREADS(78) | 1794 NUM_GS_THREADS(4) | 1795 NUM_ES_THREADS(31)); 1796 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1797 NUM_VS_STACK_ENTRIES(40)); 1798 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1799 NUM_ES_STACK_ENTRIES(16)); 1800 } else if ((rdev->family) == CHIP_RV670) { 1801 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1802 NUM_VS_GPRS(44) | 1803 NUM_CLAUSE_TEMP_GPRS(2)); 1804 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1805 NUM_ES_GPRS(17)); 1806 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1807 NUM_VS_THREADS(78) | 1808 NUM_GS_THREADS(4) | 1809 NUM_ES_THREADS(31)); 1810 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1811 NUM_VS_STACK_ENTRIES(64)); 1812 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1813 NUM_ES_STACK_ENTRIES(64)); 1814 } 1815 1816 WREG32(SQ_CONFIG, sq_config); 1817 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1818 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1819 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1820 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1821 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1822 1823 if (((rdev->family) == CHIP_RV610) || 1824 ((rdev->family) == CHIP_RV620) || 1825 ((rdev->family) == CHIP_RS780) || 1826 ((rdev->family) == CHIP_RS880)) { 1827 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1828 } else { 1829 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1830 } 1831 1832 /* More default values. 2D/3D driver should adjust as needed */ 1833 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1834 S1_X(0x4) | S1_Y(0xc))); 1835 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1836 S1_X(0x2) | S1_Y(0x2) | 1837 S2_X(0xa) | S2_Y(0x6) | 1838 S3_X(0x6) | S3_Y(0xa))); 1839 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1840 S1_X(0x4) | S1_Y(0xc) | 1841 S2_X(0x1) | S2_Y(0x6) | 1842 S3_X(0xa) | S3_Y(0xe))); 1843 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1844 S5_X(0x0) | S5_Y(0x0) | 1845 S6_X(0xb) | S6_Y(0x4) | 1846 S7_X(0x7) | S7_Y(0x8))); 1847 1848 WREG32(VGT_STRMOUT_EN, 0); 1849 tmp = rdev->config.r600.max_pipes * 16; 1850 switch (rdev->family) { 1851 case CHIP_RV610: 1852 case CHIP_RV620: 1853 case CHIP_RS780: 1854 case CHIP_RS880: 1855 tmp += 32; 1856 break; 1857 case CHIP_RV670: 1858 tmp += 128; 1859 break; 1860 default: 1861 break; 1862 } 1863 if (tmp > 256) { 1864 tmp = 256; 1865 } 1866 WREG32(VGT_ES_PER_GS, 128); 1867 WREG32(VGT_GS_PER_ES, tmp); 1868 WREG32(VGT_GS_PER_VS, 2); 1869 WREG32(VGT_GS_VERTEX_REUSE, 16); 1870 1871 /* more default values. 2D/3D driver should adjust as needed */ 1872 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1873 WREG32(VGT_STRMOUT_EN, 0); 1874 WREG32(SX_MISC, 0); 1875 WREG32(PA_SC_MODE_CNTL, 0); 1876 WREG32(PA_SC_AA_CONFIG, 0); 1877 WREG32(PA_SC_LINE_STIPPLE, 0); 1878 WREG32(SPI_INPUT_Z, 0); 1879 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1880 WREG32(CB_COLOR7_FRAG, 0); 1881 1882 /* Clear render buffer base addresses */ 1883 WREG32(CB_COLOR0_BASE, 0); 1884 WREG32(CB_COLOR1_BASE, 0); 1885 WREG32(CB_COLOR2_BASE, 0); 1886 WREG32(CB_COLOR3_BASE, 0); 1887 WREG32(CB_COLOR4_BASE, 0); 1888 WREG32(CB_COLOR5_BASE, 0); 1889 WREG32(CB_COLOR6_BASE, 0); 1890 WREG32(CB_COLOR7_BASE, 0); 1891 WREG32(CB_COLOR7_FRAG, 0); 1892 1893 switch (rdev->family) { 1894 case CHIP_RV610: 1895 case CHIP_RV620: 1896 case CHIP_RS780: 1897 case CHIP_RS880: 1898 tmp = TC_L2_SIZE(8); 1899 break; 1900 case CHIP_RV630: 1901 case CHIP_RV635: 1902 tmp = TC_L2_SIZE(4); 1903 break; 1904 case CHIP_R600: 1905 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1906 break; 1907 default: 1908 tmp = TC_L2_SIZE(0); 1909 break; 1910 } 1911 WREG32(TC_CNTL, tmp); 1912 1913 tmp = RREG32(HDP_HOST_PATH_CNTL); 1914 WREG32(HDP_HOST_PATH_CNTL, tmp); 1915 1916 tmp = RREG32(ARB_POP); 1917 tmp |= ENABLE_TC128; 1918 WREG32(ARB_POP, tmp); 1919 1920 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1921 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1922 NUM_CLIP_SEQ(3))); 1923 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1924 WREG32(VC_ENHANCE, 0); 1925 } 1926 1927 1928 /* 1929 * Indirect registers accessor 1930 */ 1931 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1932 { 1933 u32 r; 1934 1935 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1936 (void)RREG32(PCIE_PORT_INDEX); 1937 r = RREG32(PCIE_PORT_DATA); 1938 return r; 1939 } 1940 1941 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1942 { 1943 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1944 (void)RREG32(PCIE_PORT_INDEX); 1945 WREG32(PCIE_PORT_DATA, (v)); 1946 (void)RREG32(PCIE_PORT_DATA); 1947 } 1948 1949 /* 1950 * CP & Ring 1951 */ 1952 void r600_cp_stop(struct radeon_device *rdev) 1953 { 1954 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1955 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1956 WREG32(SCRATCH_UMSK, 0); 1957 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1958 } 1959 1960 int r600_init_microcode(struct radeon_device *rdev) 1961 { 1962 const char *chip_name; 1963 const char *rlc_chip_name; 1964 size_t pfp_req_size, me_req_size, rlc_req_size; 1965 char fw_name[30]; 1966 int err; 1967 1968 DRM_DEBUG("\n"); 1969 1970 switch (rdev->family) { 1971 case CHIP_R600: 1972 chip_name = "R600"; 1973 rlc_chip_name = "R600"; 1974 break; 1975 case CHIP_RV610: 1976 chip_name = "RV610"; 1977 rlc_chip_name = "R600"; 1978 break; 1979 case CHIP_RV630: 1980 chip_name = "RV630"; 1981 rlc_chip_name = "R600"; 1982 break; 1983 case CHIP_RV620: 1984 chip_name = "RV620"; 1985 rlc_chip_name = "R600"; 1986 break; 1987 case CHIP_RV635: 1988 chip_name = "RV635"; 1989 rlc_chip_name = "R600"; 1990 break; 1991 case CHIP_RV670: 1992 chip_name = "RV670"; 1993 rlc_chip_name = "R600"; 1994 break; 1995 case CHIP_RS780: 1996 case CHIP_RS880: 1997 chip_name = "RS780"; 1998 rlc_chip_name = "R600"; 1999 break; 2000 case CHIP_RV770: 2001 chip_name = "RV770"; 2002 rlc_chip_name = "R700"; 2003 break; 2004 case CHIP_RV730: 2005 case CHIP_RV740: 2006 chip_name = "RV730"; 2007 rlc_chip_name = "R700"; 2008 break; 2009 case CHIP_RV710: 2010 chip_name = "RV710"; 2011 rlc_chip_name = "R700"; 2012 break; 2013 case CHIP_CEDAR: 2014 chip_name = "CEDAR"; 2015 rlc_chip_name = "CEDAR"; 2016 break; 2017 case CHIP_REDWOOD: 2018 chip_name = "REDWOOD"; 2019 rlc_chip_name = "REDWOOD"; 2020 break; 2021 case CHIP_JUNIPER: 2022 chip_name = "JUNIPER"; 2023 rlc_chip_name = "JUNIPER"; 2024 break; 2025 case CHIP_CYPRESS: 2026 case CHIP_HEMLOCK: 2027 chip_name = "CYPRESS"; 2028 rlc_chip_name = "CYPRESS"; 2029 break; 2030 case CHIP_PALM: 2031 chip_name = "PALM"; 2032 rlc_chip_name = "SUMO"; 2033 break; 2034 case CHIP_SUMO: 2035 chip_name = "SUMO"; 2036 rlc_chip_name = "SUMO"; 2037 break; 2038 case CHIP_SUMO2: 2039 chip_name = "SUMO2"; 2040 rlc_chip_name = "SUMO"; 2041 break; 2042 default: panic("%s: Unsupported family %d", __func__, rdev->family); 2043 } 2044 2045 if (rdev->family >= CHIP_CEDAR) { 2046 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2047 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2048 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2049 } else if (rdev->family >= CHIP_RV770) { 2050 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2051 me_req_size = R700_PM4_UCODE_SIZE * 4; 2052 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2053 } else { 2054 pfp_req_size = PFP_UCODE_SIZE * 4; 2055 me_req_size = PM4_UCODE_SIZE * 12; 2056 rlc_req_size = RLC_UCODE_SIZE * 4; 2057 } 2058 2059 DRM_INFO("Loading %s Microcode\n", chip_name); 2060 err = 0; 2061 2062 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2063 rdev->pfp_fw = firmware_get(fw_name); 2064 if (rdev->pfp_fw == NULL) { 2065 err = -ENOENT; 2066 goto out; 2067 } 2068 if (rdev->pfp_fw->datasize != pfp_req_size) { 2069 DRM_ERROR( 2070 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2071 rdev->pfp_fw->datasize, fw_name); 2072 err = -EINVAL; 2073 goto out; 2074 } 2075 2076 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2077 rdev->me_fw = firmware_get(fw_name); 2078 if (rdev->me_fw == NULL) { 2079 err = -ENOENT; 2080 goto out; 2081 } 2082 if (rdev->me_fw->datasize != me_req_size) { 2083 DRM_ERROR( 2084 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2085 rdev->me_fw->datasize, fw_name); 2086 err = -EINVAL; 2087 } 2088 2089 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", 2090 rlc_chip_name); 2091 rdev->rlc_fw = firmware_get(fw_name); 2092 if (rdev->rlc_fw == NULL) { 2093 err = -ENOENT; 2094 goto out; 2095 } 2096 if (rdev->rlc_fw->datasize != rlc_req_size) { 2097 DRM_ERROR( 2098 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2099 rdev->rlc_fw->datasize, fw_name); 2100 err = -EINVAL; 2101 } 2102 2103 out: 2104 if (err) { 2105 if (err != -EINVAL) 2106 DRM_ERROR( 2107 "r600_cp: Failed to load firmware \"%s\"\n", 2108 fw_name); 2109 if (rdev->pfp_fw != NULL) { 2110 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 2111 rdev->pfp_fw = NULL; 2112 } 2113 if (rdev->me_fw != NULL) { 2114 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 2115 rdev->me_fw = NULL; 2116 } 2117 if (rdev->rlc_fw != NULL) { 2118 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 2119 rdev->rlc_fw = NULL; 2120 } 2121 } 2122 return err; 2123 } 2124 2125 /** 2126 * r600_fini_microcode - drop the firmwares image references 2127 * 2128 * @rdev: radeon_device pointer 2129 * 2130 * Drop the pfp, me and rlc firmwares image references. 2131 * Called at driver shutdown. 2132 */ 2133 void r600_fini_microcode(struct radeon_device *rdev) 2134 { 2135 2136 if (rdev->pfp_fw != NULL) { 2137 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 2138 rdev->pfp_fw = NULL; 2139 } 2140 2141 if (rdev->me_fw != NULL) { 2142 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 2143 rdev->me_fw = NULL; 2144 } 2145 2146 if (rdev->rlc_fw != NULL) { 2147 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 2148 rdev->rlc_fw = NULL; 2149 } 2150 } 2151 2152 static int r600_cp_load_microcode(struct radeon_device *rdev) 2153 { 2154 const __be32 *fw_data; 2155 int i; 2156 2157 if (!rdev->me_fw || !rdev->pfp_fw) 2158 return -EINVAL; 2159 2160 r600_cp_stop(rdev); 2161 2162 WREG32(CP_RB_CNTL, 2163 #ifdef __BIG_ENDIAN 2164 BUF_SWAP_32BIT | 2165 #endif 2166 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2167 2168 /* Reset cp */ 2169 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2170 RREG32(GRBM_SOFT_RESET); 2171 DRM_MDELAY(15); 2172 WREG32(GRBM_SOFT_RESET, 0); 2173 2174 WREG32(CP_ME_RAM_WADDR, 0); 2175 2176 fw_data = (const __be32 *)rdev->me_fw->data; 2177 WREG32(CP_ME_RAM_WADDR, 0); 2178 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2179 WREG32(CP_ME_RAM_DATA, 2180 be32_to_cpup(fw_data++)); 2181 2182 fw_data = (const __be32 *)rdev->pfp_fw->data; 2183 WREG32(CP_PFP_UCODE_ADDR, 0); 2184 for (i = 0; i < PFP_UCODE_SIZE; i++) 2185 WREG32(CP_PFP_UCODE_DATA, 2186 be32_to_cpup(fw_data++)); 2187 2188 WREG32(CP_PFP_UCODE_ADDR, 0); 2189 WREG32(CP_ME_RAM_WADDR, 0); 2190 WREG32(CP_ME_RAM_RADDR, 0); 2191 return 0; 2192 } 2193 2194 int r600_cp_start(struct radeon_device *rdev) 2195 { 2196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2197 int r; 2198 uint32_t cp_me; 2199 2200 r = radeon_ring_lock(rdev, ring, 7); 2201 if (r) { 2202 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2203 return r; 2204 } 2205 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2206 radeon_ring_write(ring, 0x1); 2207 if (rdev->family >= CHIP_RV770) { 2208 radeon_ring_write(ring, 0x0); 2209 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2210 } else { 2211 radeon_ring_write(ring, 0x3); 2212 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2213 } 2214 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2215 radeon_ring_write(ring, 0); 2216 radeon_ring_write(ring, 0); 2217 radeon_ring_unlock_commit(rdev, ring); 2218 2219 cp_me = 0xff; 2220 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2221 return 0; 2222 } 2223 2224 int r600_cp_resume(struct radeon_device *rdev) 2225 { 2226 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2227 u32 tmp; 2228 u32 rb_bufsz; 2229 int r; 2230 2231 /* Reset cp */ 2232 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2233 RREG32(GRBM_SOFT_RESET); 2234 DRM_MDELAY(15); 2235 WREG32(GRBM_SOFT_RESET, 0); 2236 2237 /* Set ring buffer size */ 2238 rb_bufsz = drm_order(ring->ring_size / 8); 2239 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2240 #ifdef __BIG_ENDIAN 2241 tmp |= BUF_SWAP_32BIT; 2242 #endif 2243 WREG32(CP_RB_CNTL, tmp); 2244 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2245 2246 /* Set the write pointer delay */ 2247 WREG32(CP_RB_WPTR_DELAY, 0); 2248 2249 /* Initialize the ring buffer's read and write pointers */ 2250 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2251 WREG32(CP_RB_RPTR_WR, 0); 2252 ring->wptr = 0; 2253 WREG32(CP_RB_WPTR, ring->wptr); 2254 2255 /* set the wb address whether it's enabled or not */ 2256 WREG32(CP_RB_RPTR_ADDR, 2257 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2258 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2259 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2260 2261 if (rdev->wb.enabled) 2262 WREG32(SCRATCH_UMSK, 0xff); 2263 else { 2264 tmp |= RB_NO_UPDATE; 2265 WREG32(SCRATCH_UMSK, 0); 2266 } 2267 2268 DRM_MDELAY(1); 2269 WREG32(CP_RB_CNTL, tmp); 2270 2271 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2272 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2273 2274 ring->rptr = RREG32(CP_RB_RPTR); 2275 2276 r600_cp_start(rdev); 2277 ring->ready = true; 2278 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2279 if (r) { 2280 ring->ready = false; 2281 return r; 2282 } 2283 return 0; 2284 } 2285 2286 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2287 { 2288 u32 rb_bufsz; 2289 int r; 2290 2291 /* Align ring size */ 2292 rb_bufsz = drm_order(ring_size / 8); 2293 ring_size = (1 << (rb_bufsz + 1)) * 4; 2294 ring->ring_size = ring_size; 2295 ring->align_mask = 16 - 1; 2296 2297 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2298 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2299 if (r) { 2300 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2301 ring->rptr_save_reg = 0; 2302 } 2303 } 2304 } 2305 2306 void r600_cp_fini(struct radeon_device *rdev) 2307 { 2308 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2309 r600_cp_stop(rdev); 2310 radeon_ring_fini(rdev, ring); 2311 radeon_scratch_free(rdev, ring->rptr_save_reg); 2312 } 2313 2314 /* 2315 * DMA 2316 * Starting with R600, the GPU has an asynchronous 2317 * DMA engine. The programming model is very similar 2318 * to the 3D engine (ring buffer, IBs, etc.), but the 2319 * DMA controller has it's own packet format that is 2320 * different form the PM4 format used by the 3D engine. 2321 * It supports copying data, writing embedded data, 2322 * solid fills, and a number of other things. It also 2323 * has support for tiling/detiling of buffers. 2324 */ 2325 /** 2326 * r600_dma_stop - stop the async dma engine 2327 * 2328 * @rdev: radeon_device pointer 2329 * 2330 * Stop the async dma engine (r6xx-evergreen). 2331 */ 2332 void r600_dma_stop(struct radeon_device *rdev) 2333 { 2334 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2335 2336 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2337 2338 rb_cntl &= ~DMA_RB_ENABLE; 2339 WREG32(DMA_RB_CNTL, rb_cntl); 2340 2341 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2342 } 2343 2344 /** 2345 * r600_dma_resume - setup and start the async dma engine 2346 * 2347 * @rdev: radeon_device pointer 2348 * 2349 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2350 * Returns 0 for success, error for failure. 2351 */ 2352 int r600_dma_resume(struct radeon_device *rdev) 2353 { 2354 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2355 u32 rb_cntl, dma_cntl, ib_cntl; 2356 u32 rb_bufsz; 2357 int r; 2358 2359 /* Reset dma */ 2360 if (rdev->family >= CHIP_RV770) 2361 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2362 else 2363 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2364 RREG32(SRBM_SOFT_RESET); 2365 DRM_UDELAY(50); 2366 WREG32(SRBM_SOFT_RESET, 0); 2367 2368 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2369 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2370 2371 /* Set ring buffer size in dwords */ 2372 rb_bufsz = drm_order(ring->ring_size / 4); 2373 rb_cntl = rb_bufsz << 1; 2374 #ifdef __BIG_ENDIAN 2375 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2376 #endif 2377 WREG32(DMA_RB_CNTL, rb_cntl); 2378 2379 /* Initialize the ring buffer's read and write pointers */ 2380 WREG32(DMA_RB_RPTR, 0); 2381 WREG32(DMA_RB_WPTR, 0); 2382 2383 /* set the wb address whether it's enabled or not */ 2384 WREG32(DMA_RB_RPTR_ADDR_HI, 2385 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2386 WREG32(DMA_RB_RPTR_ADDR_LO, 2387 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2388 2389 if (rdev->wb.enabled) 2390 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2391 2392 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2393 2394 /* enable DMA IBs */ 2395 ib_cntl = DMA_IB_ENABLE; 2396 #ifdef __BIG_ENDIAN 2397 ib_cntl |= DMA_IB_SWAP_ENABLE; 2398 #endif 2399 WREG32(DMA_IB_CNTL, ib_cntl); 2400 2401 dma_cntl = RREG32(DMA_CNTL); 2402 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2403 WREG32(DMA_CNTL, dma_cntl); 2404 2405 if (rdev->family >= CHIP_RV770) 2406 WREG32(DMA_MODE, 1); 2407 2408 ring->wptr = 0; 2409 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2410 2411 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2412 2413 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2414 2415 ring->ready = true; 2416 2417 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2418 if (r) { 2419 ring->ready = false; 2420 return r; 2421 } 2422 2423 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2424 2425 return 0; 2426 } 2427 2428 /** 2429 * r600_dma_fini - tear down the async dma engine 2430 * 2431 * @rdev: radeon_device pointer 2432 * 2433 * Stop the async dma engine and free the ring (r6xx-evergreen). 2434 */ 2435 void r600_dma_fini(struct radeon_device *rdev) 2436 { 2437 r600_dma_stop(rdev); 2438 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2439 } 2440 2441 /* 2442 * GPU scratch registers helpers function. 2443 */ 2444 void r600_scratch_init(struct radeon_device *rdev) 2445 { 2446 int i; 2447 2448 rdev->scratch.num_reg = 7; 2449 rdev->scratch.reg_base = SCRATCH_REG0; 2450 for (i = 0; i < rdev->scratch.num_reg; i++) { 2451 rdev->scratch.free[i] = true; 2452 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2453 } 2454 } 2455 2456 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2457 { 2458 uint32_t scratch; 2459 uint32_t tmp = 0; 2460 unsigned i; 2461 int r; 2462 2463 r = radeon_scratch_get(rdev, &scratch); 2464 if (r) { 2465 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2466 return r; 2467 } 2468 WREG32(scratch, 0xCAFEDEAD); 2469 r = radeon_ring_lock(rdev, ring, 3); 2470 if (r) { 2471 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2472 radeon_scratch_free(rdev, scratch); 2473 return r; 2474 } 2475 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2476 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2477 radeon_ring_write(ring, 0xDEADBEEF); 2478 radeon_ring_unlock_commit(rdev, ring); 2479 for (i = 0; i < rdev->usec_timeout; i++) { 2480 tmp = RREG32(scratch); 2481 if (tmp == 0xDEADBEEF) 2482 break; 2483 DRM_UDELAY(1); 2484 } 2485 if (i < rdev->usec_timeout) { 2486 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2487 } else { 2488 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2489 ring->idx, scratch, tmp); 2490 r = -EINVAL; 2491 } 2492 radeon_scratch_free(rdev, scratch); 2493 return r; 2494 } 2495 2496 /** 2497 * r600_dma_ring_test - simple async dma engine test 2498 * 2499 * @rdev: radeon_device pointer 2500 * @ring: radeon_ring structure holding ring information 2501 * 2502 * Test the DMA engine by writing using it to write an 2503 * value to memory. (r6xx-SI). 2504 * Returns 0 for success, error for failure. 2505 */ 2506 int r600_dma_ring_test(struct radeon_device *rdev, 2507 struct radeon_ring *ring) 2508 { 2509 unsigned i; 2510 int r; 2511 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 2512 u32 tmp; 2513 2514 if (!ptr) { 2515 DRM_ERROR("invalid vram scratch pointer\n"); 2516 return -EINVAL; 2517 } 2518 2519 tmp = 0xCAFEDEAD; 2520 *ptr = tmp; 2521 2522 r = radeon_ring_lock(rdev, ring, 4); 2523 if (r) { 2524 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2525 return r; 2526 } 2527 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2528 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2529 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2530 radeon_ring_write(ring, 0xDEADBEEF); 2531 radeon_ring_unlock_commit(rdev, ring); 2532 2533 for (i = 0; i < rdev->usec_timeout; i++) { 2534 tmp = *ptr; 2535 if (tmp == 0xDEADBEEF) 2536 break; 2537 DRM_UDELAY(1); 2538 } 2539 2540 if (i < rdev->usec_timeout) { 2541 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2542 } else { 2543 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2544 ring->idx, tmp); 2545 r = -EINVAL; 2546 } 2547 return r; 2548 } 2549 2550 /* 2551 * CP fences/semaphores 2552 */ 2553 2554 void r600_fence_ring_emit(struct radeon_device *rdev, 2555 struct radeon_fence *fence) 2556 { 2557 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2558 2559 if (rdev->wb.use_event) { 2560 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2561 /* flush read cache over gart */ 2562 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2563 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2564 PACKET3_VC_ACTION_ENA | 2565 PACKET3_SH_ACTION_ENA); 2566 radeon_ring_write(ring, 0xFFFFFFFF); 2567 radeon_ring_write(ring, 0); 2568 radeon_ring_write(ring, 10); /* poll interval */ 2569 /* EVENT_WRITE_EOP - flush caches, send int */ 2570 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2571 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2572 radeon_ring_write(ring, addr & 0xffffffff); 2573 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2574 radeon_ring_write(ring, fence->seq); 2575 radeon_ring_write(ring, 0); 2576 } else { 2577 /* flush read cache over gart */ 2578 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2579 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2580 PACKET3_VC_ACTION_ENA | 2581 PACKET3_SH_ACTION_ENA); 2582 radeon_ring_write(ring, 0xFFFFFFFF); 2583 radeon_ring_write(ring, 0); 2584 radeon_ring_write(ring, 10); /* poll interval */ 2585 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2586 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2587 /* wait for 3D idle clean */ 2588 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2589 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2590 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2591 /* Emit fence sequence & fire IRQ */ 2592 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2593 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2594 radeon_ring_write(ring, fence->seq); 2595 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2596 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2597 radeon_ring_write(ring, RB_INT_STAT); 2598 } 2599 } 2600 2601 void r600_semaphore_ring_emit(struct radeon_device *rdev, 2602 struct radeon_ring *ring, 2603 struct radeon_semaphore *semaphore, 2604 bool emit_wait) 2605 { 2606 uint64_t addr = semaphore->gpu_addr; 2607 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2608 2609 if (rdev->family < CHIP_CAYMAN) 2610 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2611 2612 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2613 radeon_ring_write(ring, addr & 0xffffffff); 2614 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2615 } 2616 2617 /* 2618 * DMA fences/semaphores 2619 */ 2620 2621 /** 2622 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 2623 * 2624 * @rdev: radeon_device pointer 2625 * @fence: radeon fence object 2626 * 2627 * Add a DMA fence packet to the ring to write 2628 * the fence seq number and DMA trap packet to generate 2629 * an interrupt if needed (r6xx-r7xx). 2630 */ 2631 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 2632 struct radeon_fence *fence) 2633 { 2634 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2635 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2636 2637 /* write the fence */ 2638 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 2639 radeon_ring_write(ring, addr & 0xfffffffc); 2640 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 2641 radeon_ring_write(ring, lower_32_bits(fence->seq)); 2642 /* generate an interrupt */ 2643 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 2644 } 2645 2646 /** 2647 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 2648 * 2649 * @rdev: radeon_device pointer 2650 * @ring: radeon_ring structure holding ring information 2651 * @semaphore: radeon semaphore object 2652 * @emit_wait: wait or signal semaphore 2653 * 2654 * Add a DMA semaphore packet to the ring wait on or signal 2655 * other rings (r6xx-SI). 2656 */ 2657 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 2658 struct radeon_ring *ring, 2659 struct radeon_semaphore *semaphore, 2660 bool emit_wait) 2661 { 2662 u64 addr = semaphore->gpu_addr; 2663 u32 s = emit_wait ? 0 : 1; 2664 2665 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 2666 radeon_ring_write(ring, addr & 0xfffffffc); 2667 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 2668 } 2669 2670 int r600_copy_blit(struct radeon_device *rdev, 2671 uint64_t src_offset, 2672 uint64_t dst_offset, 2673 unsigned num_gpu_pages, 2674 struct radeon_fence **fence) 2675 { 2676 struct radeon_semaphore *sem = NULL; 2677 struct radeon_sa_bo *vb = NULL; 2678 int r; 2679 2680 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 2681 if (r) { 2682 return r; 2683 } 2684 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 2685 r600_blit_done_copy(rdev, fence, vb, sem); 2686 return 0; 2687 } 2688 2689 /** 2690 * r600_copy_dma - copy pages using the DMA engine 2691 * 2692 * @rdev: radeon_device pointer 2693 * @src_offset: src GPU address 2694 * @dst_offset: dst GPU address 2695 * @num_gpu_pages: number of GPU pages to xfer 2696 * @fence: radeon fence object 2697 * 2698 * Copy GPU paging using the DMA engine (r6xx). 2699 * Used by the radeon ttm implementation to move pages if 2700 * registered as the asic copy callback. 2701 */ 2702 int r600_copy_dma(struct radeon_device *rdev, 2703 uint64_t src_offset, uint64_t dst_offset, 2704 unsigned num_gpu_pages, 2705 struct radeon_fence **fence) 2706 { 2707 struct radeon_semaphore *sem = NULL; 2708 int ring_index = rdev->asic->copy.dma_ring_index; 2709 struct radeon_ring *ring = &rdev->ring[ring_index]; 2710 u32 size_in_dw, cur_size_in_dw; 2711 int i, num_loops; 2712 int r = 0; 2713 2714 r = radeon_semaphore_create(rdev, &sem); 2715 if (r) { 2716 DRM_ERROR("radeon: moving bo (%d).\n", r); 2717 return r; 2718 } 2719 2720 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 2721 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 2722 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 2723 if (r) { 2724 DRM_ERROR("radeon: moving bo (%d).\n", r); 2725 radeon_semaphore_free(rdev, &sem, NULL); 2726 return r; 2727 } 2728 2729 if (radeon_fence_need_sync(*fence, ring->idx)) { 2730 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 2731 ring->idx); 2732 radeon_fence_note_sync(*fence, ring->idx); 2733 } else { 2734 radeon_semaphore_free(rdev, &sem, NULL); 2735 } 2736 2737 for (i = 0; i < num_loops; i++) { 2738 cur_size_in_dw = size_in_dw; 2739 if (cur_size_in_dw > 0xFFFE) 2740 cur_size_in_dw = 0xFFFE; 2741 size_in_dw -= cur_size_in_dw; 2742 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 2743 radeon_ring_write(ring, dst_offset & 0xfffffffc); 2744 radeon_ring_write(ring, src_offset & 0xfffffffc); 2745 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 2746 (upper_32_bits(src_offset) & 0xff))); 2747 src_offset += cur_size_in_dw * 4; 2748 dst_offset += cur_size_in_dw * 4; 2749 } 2750 2751 r = radeon_fence_emit(rdev, fence, ring->idx); 2752 if (r) { 2753 radeon_ring_unlock_undo(rdev, ring); 2754 return r; 2755 } 2756 2757 radeon_ring_unlock_commit(rdev, ring); 2758 radeon_semaphore_free(rdev, &sem, *fence); 2759 2760 return r; 2761 } 2762 2763 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2764 uint32_t tiling_flags, uint32_t pitch, 2765 uint32_t offset, uint32_t obj_size) 2766 { 2767 /* FIXME: implement */ 2768 return 0; 2769 } 2770 2771 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2772 { 2773 /* FIXME: implement */ 2774 } 2775 2776 static int r600_startup(struct radeon_device *rdev) 2777 { 2778 struct radeon_ring *ring; 2779 int r; 2780 2781 /* enable pcie gen2 link */ 2782 r600_pcie_gen2_enable(rdev); 2783 2784 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2785 r = r600_init_microcode(rdev); 2786 if (r) { 2787 DRM_ERROR("Failed to load firmware!\n"); 2788 return r; 2789 } 2790 } 2791 2792 r = r600_vram_scratch_init(rdev); 2793 if (r) 2794 return r; 2795 2796 r600_mc_program(rdev); 2797 if (rdev->flags & RADEON_IS_AGP) { 2798 r600_agp_enable(rdev); 2799 } else { 2800 r = r600_pcie_gart_enable(rdev); 2801 if (r) 2802 return r; 2803 } 2804 r600_gpu_init(rdev); 2805 r = r600_blit_init(rdev); 2806 if (r) { 2807 r600_blit_fini(rdev); 2808 rdev->asic->copy.copy = NULL; 2809 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2810 } 2811 2812 /* allocate wb buffer */ 2813 r = radeon_wb_init(rdev); 2814 if (r) 2815 return r; 2816 2817 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2818 if (r) { 2819 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2820 return r; 2821 } 2822 2823 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2824 if (r) { 2825 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2826 return r; 2827 } 2828 2829 /* Enable IRQ */ 2830 r = r600_irq_init(rdev); 2831 if (r) { 2832 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2833 radeon_irq_kms_fini(rdev); 2834 return r; 2835 } 2836 r600_irq_set(rdev); 2837 2838 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2839 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2840 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 2841 0, 0xfffff, RADEON_CP_PACKET2); 2842 if (r) 2843 return r; 2844 2845 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2846 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2847 DMA_RB_RPTR, DMA_RB_WPTR, 2848 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2849 if (r) 2850 return r; 2851 2852 r = r600_cp_load_microcode(rdev); 2853 if (r) 2854 return r; 2855 r = r600_cp_resume(rdev); 2856 if (r) 2857 return r; 2858 2859 r = r600_dma_resume(rdev); 2860 if (r) 2861 return r; 2862 2863 r = radeon_ib_pool_init(rdev); 2864 if (r) { 2865 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2866 return r; 2867 } 2868 2869 r = r600_audio_init(rdev); 2870 if (r) { 2871 DRM_ERROR("radeon: audio init failed\n"); 2872 return r; 2873 } 2874 2875 return 0; 2876 } 2877 2878 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2879 { 2880 uint32_t temp; 2881 2882 temp = RREG32(CONFIG_CNTL); 2883 if (state == false) { 2884 temp &= ~(1<<0); 2885 temp |= (1<<1); 2886 } else { 2887 temp &= ~(1<<1); 2888 } 2889 WREG32(CONFIG_CNTL, temp); 2890 } 2891 2892 int r600_resume(struct radeon_device *rdev) 2893 { 2894 int r; 2895 2896 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2897 * posting will perform necessary task to bring back GPU into good 2898 * shape. 2899 */ 2900 /* post card */ 2901 atom_asic_init(rdev->mode_info.atom_context); 2902 2903 rdev->accel_working = true; 2904 r = r600_startup(rdev); 2905 if (r) { 2906 DRM_ERROR("r600 startup failed on resume\n"); 2907 rdev->accel_working = false; 2908 return r; 2909 } 2910 2911 return r; 2912 } 2913 2914 int r600_suspend(struct radeon_device *rdev) 2915 { 2916 r600_audio_fini(rdev); 2917 r600_cp_stop(rdev); 2918 r600_dma_stop(rdev); 2919 r600_irq_suspend(rdev); 2920 radeon_wb_disable(rdev); 2921 r600_pcie_gart_disable(rdev); 2922 2923 return 0; 2924 } 2925 2926 /* Plan is to move initialization in that function and use 2927 * helper function so that radeon_device_init pretty much 2928 * do nothing more than calling asic specific function. This 2929 * should also allow to remove a bunch of callback function 2930 * like vram_info. 2931 */ 2932 int r600_init(struct radeon_device *rdev) 2933 { 2934 int r; 2935 2936 if (r600_debugfs_mc_info_init(rdev)) { 2937 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2938 } 2939 /* Read BIOS */ 2940 if (!radeon_get_bios(rdev)) { 2941 if (ASIC_IS_AVIVO(rdev)) 2942 return -EINVAL; 2943 } 2944 /* Must be an ATOMBIOS */ 2945 if (!rdev->is_atom_bios) { 2946 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2947 return -EINVAL; 2948 } 2949 r = radeon_atombios_init(rdev); 2950 if (r) 2951 return r; 2952 /* Post card if necessary */ 2953 if (!radeon_card_posted(rdev)) { 2954 if (!rdev->bios) { 2955 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2956 return -EINVAL; 2957 } 2958 DRM_INFO("GPU not posted. posting now...\n"); 2959 atom_asic_init(rdev->mode_info.atom_context); 2960 } 2961 /* Initialize scratch registers */ 2962 r600_scratch_init(rdev); 2963 /* Initialize surface registers */ 2964 radeon_surface_init(rdev); 2965 /* Initialize clocks */ 2966 radeon_get_clock_info(rdev->ddev); 2967 /* Fence driver */ 2968 r = radeon_fence_driver_init(rdev); 2969 if (r) 2970 return r; 2971 if (rdev->flags & RADEON_IS_AGP) { 2972 r = radeon_agp_init(rdev); 2973 if (r) 2974 radeon_agp_disable(rdev); 2975 } 2976 r = r600_mc_init(rdev); 2977 if (r) 2978 return r; 2979 /* Memory manager */ 2980 r = radeon_bo_init(rdev); 2981 if (r) 2982 return r; 2983 2984 r = radeon_irq_kms_init(rdev); 2985 if (r) 2986 return r; 2987 2988 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 2989 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 2990 2991 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2992 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2993 2994 rdev->ih.ring_obj = NULL; 2995 r600_ih_ring_init(rdev, 64 * 1024); 2996 2997 r = r600_pcie_gart_init(rdev); 2998 if (r) 2999 return r; 3000 3001 rdev->accel_working = true; 3002 r = r600_startup(rdev); 3003 if (r) { 3004 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3005 r600_cp_fini(rdev); 3006 r600_dma_fini(rdev); 3007 r600_irq_fini(rdev); 3008 radeon_wb_fini(rdev); 3009 radeon_ib_pool_fini(rdev); 3010 radeon_irq_kms_fini(rdev); 3011 r600_pcie_gart_fini(rdev); 3012 rdev->accel_working = false; 3013 } 3014 3015 return 0; 3016 } 3017 3018 void r600_fini(struct radeon_device *rdev) 3019 { 3020 r600_audio_fini(rdev); 3021 r600_blit_fini(rdev); 3022 r600_cp_fini(rdev); 3023 r600_dma_fini(rdev); 3024 r600_irq_fini(rdev); 3025 radeon_wb_fini(rdev); 3026 radeon_ib_pool_fini(rdev); 3027 radeon_irq_kms_fini(rdev); 3028 r600_pcie_gart_fini(rdev); 3029 r600_vram_scratch_fini(rdev); 3030 radeon_agp_fini(rdev); 3031 radeon_gem_fini(rdev); 3032 radeon_fence_driver_fini(rdev); 3033 radeon_bo_fini(rdev); 3034 radeon_atombios_fini(rdev); 3035 r600_fini_microcode(rdev); 3036 drm_free(rdev->bios, DRM_MEM_DRIVER); 3037 rdev->bios = NULL; 3038 } 3039 3040 3041 /* 3042 * CS stuff 3043 */ 3044 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3045 { 3046 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3047 u32 next_rptr; 3048 3049 if (ring->rptr_save_reg) { 3050 next_rptr = ring->wptr + 3 + 4; 3051 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3052 radeon_ring_write(ring, ((ring->rptr_save_reg - 3053 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3054 radeon_ring_write(ring, next_rptr); 3055 } else if (rdev->wb.enabled) { 3056 next_rptr = ring->wptr + 5 + 4; 3057 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3058 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3059 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3060 radeon_ring_write(ring, next_rptr); 3061 radeon_ring_write(ring, 0); 3062 } 3063 3064 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3065 radeon_ring_write(ring, 3066 #ifdef __BIG_ENDIAN 3067 (2 << 0) | 3068 #endif 3069 (ib->gpu_addr & 0xFFFFFFFC)); 3070 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3071 radeon_ring_write(ring, ib->length_dw); 3072 } 3073 3074 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3075 { 3076 struct radeon_ib ib; 3077 uint32_t scratch; 3078 uint32_t tmp = 0; 3079 unsigned i; 3080 int r; 3081 3082 r = radeon_scratch_get(rdev, &scratch); 3083 if (r) { 3084 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3085 return r; 3086 } 3087 WREG32(scratch, 0xCAFEDEAD); 3088 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3089 if (r) { 3090 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3091 goto free_scratch; 3092 } 3093 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3094 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3095 ib.ptr[2] = 0xDEADBEEF; 3096 ib.length_dw = 3; 3097 r = radeon_ib_schedule(rdev, &ib, NULL); 3098 if (r) { 3099 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3100 goto free_ib; 3101 } 3102 r = radeon_fence_wait(ib.fence, false); 3103 if (r) { 3104 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3105 goto free_ib; 3106 } 3107 for (i = 0; i < rdev->usec_timeout; i++) { 3108 tmp = RREG32(scratch); 3109 if (tmp == 0xDEADBEEF) 3110 break; 3111 DRM_UDELAY(1); 3112 } 3113 if (i < rdev->usec_timeout) { 3114 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3115 } else { 3116 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3117 scratch, tmp); 3118 r = -EINVAL; 3119 } 3120 free_ib: 3121 radeon_ib_free(rdev, &ib); 3122 free_scratch: 3123 radeon_scratch_free(rdev, scratch); 3124 return r; 3125 } 3126 3127 /** 3128 * r600_dma_ib_test - test an IB on the DMA engine 3129 * 3130 * @rdev: radeon_device pointer 3131 * @ring: radeon_ring structure holding ring information 3132 * 3133 * Test a simple IB in the DMA ring (r6xx-SI). 3134 * Returns 0 on success, error on failure. 3135 */ 3136 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3137 { 3138 struct radeon_ib ib; 3139 unsigned i; 3140 int r; 3141 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 3142 u32 tmp = 0; 3143 3144 if (!ptr) { 3145 DRM_ERROR("invalid vram scratch pointer\n"); 3146 return -EINVAL; 3147 } 3148 3149 tmp = 0xCAFEDEAD; 3150 *ptr = tmp; 3151 3152 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3153 if (r) { 3154 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3155 return r; 3156 } 3157 3158 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3159 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3160 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3161 ib.ptr[3] = 0xDEADBEEF; 3162 ib.length_dw = 4; 3163 3164 r = radeon_ib_schedule(rdev, &ib, NULL); 3165 if (r) { 3166 radeon_ib_free(rdev, &ib); 3167 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3168 return r; 3169 } 3170 r = radeon_fence_wait(ib.fence, false); 3171 if (r) { 3172 radeon_ib_free(rdev, &ib); 3173 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3174 return r; 3175 } 3176 for (i = 0; i < rdev->usec_timeout; i++) { 3177 tmp = *ptr; 3178 if (tmp == 0xDEADBEEF) 3179 break; 3180 DRM_UDELAY(1); 3181 } 3182 if (i < rdev->usec_timeout) { 3183 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3184 } else { 3185 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3186 r = -EINVAL; 3187 } 3188 radeon_ib_free(rdev, &ib); 3189 return r; 3190 } 3191 3192 /** 3193 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3194 * 3195 * @rdev: radeon_device pointer 3196 * @ib: IB object to schedule 3197 * 3198 * Schedule an IB in the DMA ring (r6xx-r7xx). 3199 */ 3200 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3201 { 3202 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3203 3204 if (rdev->wb.enabled) { 3205 u32 next_rptr = ring->wptr + 4; 3206 while ((next_rptr & 7) != 5) 3207 next_rptr++; 3208 next_rptr += 3; 3209 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3210 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3211 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3212 radeon_ring_write(ring, next_rptr); 3213 } 3214 3215 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3216 * Pad as necessary with NOPs. 3217 */ 3218 while ((ring->wptr & 7) != 5) 3219 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3220 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3221 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3222 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3223 3224 } 3225 3226 /* 3227 * Interrupts 3228 * 3229 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3230 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3231 * writing to the ring and the GPU consuming, the GPU writes to the ring 3232 * and host consumes. As the host irq handler processes interrupts, it 3233 * increments the rptr. When the rptr catches up with the wptr, all the 3234 * current interrupts have been processed. 3235 */ 3236 3237 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3238 { 3239 u32 rb_bufsz; 3240 3241 /* Align ring size */ 3242 rb_bufsz = drm_order(ring_size / 4); 3243 ring_size = (1 << rb_bufsz) * 4; 3244 rdev->ih.ring_size = ring_size; 3245 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3246 rdev->ih.rptr = 0; 3247 } 3248 3249 int r600_ih_ring_alloc(struct radeon_device *rdev) 3250 { 3251 int r; 3252 void *ring_ptr; 3253 3254 /* Allocate ring buffer */ 3255 if (rdev->ih.ring_obj == NULL) { 3256 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3257 PAGE_SIZE, true, 3258 RADEON_GEM_DOMAIN_GTT, 3259 NULL, &rdev->ih.ring_obj); 3260 if (r) { 3261 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3262 return r; 3263 } 3264 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3265 if (unlikely(r != 0)) { 3266 radeon_bo_unref(&rdev->ih.ring_obj); 3267 return r; 3268 } 3269 r = radeon_bo_pin(rdev->ih.ring_obj, 3270 RADEON_GEM_DOMAIN_GTT, 3271 &rdev->ih.gpu_addr); 3272 if (r) { 3273 radeon_bo_unreserve(rdev->ih.ring_obj); 3274 radeon_bo_unref(&rdev->ih.ring_obj); 3275 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3276 return r; 3277 } 3278 ring_ptr = &rdev->ih.ring; 3279 r = radeon_bo_kmap(rdev->ih.ring_obj, 3280 ring_ptr); 3281 if (r) 3282 radeon_bo_unpin(rdev->ih.ring_obj); 3283 radeon_bo_unreserve(rdev->ih.ring_obj); 3284 if (r) { 3285 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3286 radeon_bo_unref(&rdev->ih.ring_obj); 3287 return r; 3288 } 3289 } 3290 return 0; 3291 } 3292 3293 void r600_ih_ring_fini(struct radeon_device *rdev) 3294 { 3295 int r; 3296 if (rdev->ih.ring_obj) { 3297 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3298 if (likely(r == 0)) { 3299 radeon_bo_kunmap(rdev->ih.ring_obj); 3300 radeon_bo_unpin(rdev->ih.ring_obj); 3301 radeon_bo_unreserve(rdev->ih.ring_obj); 3302 } 3303 radeon_bo_unref(&rdev->ih.ring_obj); 3304 rdev->ih.ring = NULL; 3305 rdev->ih.ring_obj = NULL; 3306 } 3307 } 3308 3309 void r600_rlc_stop(struct radeon_device *rdev) 3310 { 3311 3312 if ((rdev->family >= CHIP_RV770) && 3313 (rdev->family <= CHIP_RV740)) { 3314 /* r7xx asics need to soft reset RLC before halting */ 3315 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3316 RREG32(SRBM_SOFT_RESET); 3317 DRM_MDELAY(15); 3318 WREG32(SRBM_SOFT_RESET, 0); 3319 RREG32(SRBM_SOFT_RESET); 3320 } 3321 3322 WREG32(RLC_CNTL, 0); 3323 } 3324 3325 static void r600_rlc_start(struct radeon_device *rdev) 3326 { 3327 WREG32(RLC_CNTL, RLC_ENABLE); 3328 } 3329 3330 static int r600_rlc_init(struct radeon_device *rdev) 3331 { 3332 u32 i; 3333 const __be32 *fw_data; 3334 3335 if (!rdev->rlc_fw) 3336 return -EINVAL; 3337 3338 r600_rlc_stop(rdev); 3339 3340 WREG32(RLC_HB_CNTL, 0); 3341 3342 if (rdev->family == CHIP_ARUBA) { 3343 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3344 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3345 } 3346 if (rdev->family <= CHIP_CAYMAN) { 3347 WREG32(RLC_HB_BASE, 0); 3348 WREG32(RLC_HB_RPTR, 0); 3349 WREG32(RLC_HB_WPTR, 0); 3350 } 3351 if (rdev->family <= CHIP_CAICOS) { 3352 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3353 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3354 } 3355 WREG32(RLC_MC_CNTL, 0); 3356 WREG32(RLC_UCODE_CNTL, 0); 3357 3358 fw_data = (const __be32 *)rdev->rlc_fw->data; 3359 if (rdev->family >= CHIP_ARUBA) { 3360 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { 3361 WREG32(RLC_UCODE_ADDR, i); 3362 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3363 } 3364 } else if (rdev->family >= CHIP_CAYMAN) { 3365 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 3366 WREG32(RLC_UCODE_ADDR, i); 3367 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3368 } 3369 } else if (rdev->family >= CHIP_CEDAR) { 3370 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 3371 WREG32(RLC_UCODE_ADDR, i); 3372 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3373 } 3374 } else if (rdev->family >= CHIP_RV770) { 3375 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3376 WREG32(RLC_UCODE_ADDR, i); 3377 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3378 } 3379 } else { 3380 for (i = 0; i < RLC_UCODE_SIZE; i++) { 3381 WREG32(RLC_UCODE_ADDR, i); 3382 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3383 } 3384 } 3385 WREG32(RLC_UCODE_ADDR, 0); 3386 3387 r600_rlc_start(rdev); 3388 3389 return 0; 3390 } 3391 3392 static void r600_enable_interrupts(struct radeon_device *rdev) 3393 { 3394 u32 ih_cntl = RREG32(IH_CNTL); 3395 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3396 3397 ih_cntl |= ENABLE_INTR; 3398 ih_rb_cntl |= IH_RB_ENABLE; 3399 WREG32(IH_CNTL, ih_cntl); 3400 WREG32(IH_RB_CNTL, ih_rb_cntl); 3401 rdev->ih.enabled = true; 3402 } 3403 3404 void r600_disable_interrupts(struct radeon_device *rdev) 3405 { 3406 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3407 u32 ih_cntl = RREG32(IH_CNTL); 3408 3409 ih_rb_cntl &= ~IH_RB_ENABLE; 3410 ih_cntl &= ~ENABLE_INTR; 3411 WREG32(IH_RB_CNTL, ih_rb_cntl); 3412 WREG32(IH_CNTL, ih_cntl); 3413 /* set rptr, wptr to 0 */ 3414 WREG32(IH_RB_RPTR, 0); 3415 WREG32(IH_RB_WPTR, 0); 3416 rdev->ih.enabled = false; 3417 rdev->ih.rptr = 0; 3418 } 3419 3420 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3421 { 3422 u32 tmp; 3423 3424 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3425 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3426 WREG32(DMA_CNTL, tmp); 3427 WREG32(GRBM_INT_CNTL, 0); 3428 WREG32(DxMODE_INT_MASK, 0); 3429 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3430 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3431 if (ASIC_IS_DCE3(rdev)) { 3432 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3433 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3434 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3435 WREG32(DC_HPD1_INT_CONTROL, tmp); 3436 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3437 WREG32(DC_HPD2_INT_CONTROL, tmp); 3438 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3439 WREG32(DC_HPD3_INT_CONTROL, tmp); 3440 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3441 WREG32(DC_HPD4_INT_CONTROL, tmp); 3442 if (ASIC_IS_DCE32(rdev)) { 3443 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3444 WREG32(DC_HPD5_INT_CONTROL, tmp); 3445 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3446 WREG32(DC_HPD6_INT_CONTROL, tmp); 3447 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3448 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3449 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3450 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3451 } else { 3452 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3453 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3454 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3455 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3456 } 3457 } else { 3458 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3459 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3460 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3461 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3462 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3463 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3464 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3465 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3466 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3467 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3468 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3469 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3470 } 3471 } 3472 3473 int r600_irq_init(struct radeon_device *rdev) 3474 { 3475 int ret = 0; 3476 int rb_bufsz; 3477 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3478 3479 /* allocate ring */ 3480 ret = r600_ih_ring_alloc(rdev); 3481 if (ret) 3482 return ret; 3483 3484 /* disable irqs */ 3485 r600_disable_interrupts(rdev); 3486 3487 /* init rlc */ 3488 ret = r600_rlc_init(rdev); 3489 if (ret) { 3490 r600_ih_ring_fini(rdev); 3491 return ret; 3492 } 3493 3494 /* setup interrupt control */ 3495 /* set dummy read address to ring address */ 3496 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3497 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3498 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3499 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3500 */ 3501 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3502 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3503 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3504 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3505 3506 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3507 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3508 3509 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3510 IH_WPTR_OVERFLOW_CLEAR | 3511 (rb_bufsz << 1)); 3512 3513 if (rdev->wb.enabled) 3514 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3515 3516 /* set the writeback address whether it's enabled or not */ 3517 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3518 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3519 3520 WREG32(IH_RB_CNTL, ih_rb_cntl); 3521 3522 /* set rptr, wptr to 0 */ 3523 WREG32(IH_RB_RPTR, 0); 3524 WREG32(IH_RB_WPTR, 0); 3525 3526 /* Default settings for IH_CNTL (disabled at first) */ 3527 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3528 /* RPTR_REARM only works if msi's are enabled */ 3529 if (rdev->msi_enabled) 3530 ih_cntl |= RPTR_REARM; 3531 WREG32(IH_CNTL, ih_cntl); 3532 3533 /* force the active interrupt state to all disabled */ 3534 if (rdev->family >= CHIP_CEDAR) 3535 evergreen_disable_interrupt_state(rdev); 3536 else 3537 r600_disable_interrupt_state(rdev); 3538 3539 /* at this point everything should be setup correctly to enable master */ 3540 pci_enable_busmaster(rdev->dev); 3541 3542 /* enable irqs */ 3543 r600_enable_interrupts(rdev); 3544 3545 return ret; 3546 } 3547 3548 void r600_irq_suspend(struct radeon_device *rdev) 3549 { 3550 r600_irq_disable(rdev); 3551 r600_rlc_stop(rdev); 3552 } 3553 3554 void r600_irq_fini(struct radeon_device *rdev) 3555 { 3556 r600_irq_suspend(rdev); 3557 r600_ih_ring_fini(rdev); 3558 } 3559 3560 int r600_irq_set(struct radeon_device *rdev) 3561 { 3562 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3563 u32 mode_int = 0; 3564 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3565 u32 grbm_int_cntl = 0; 3566 u32 hdmi0, hdmi1; 3567 u32 d1grph = 0, d2grph = 0; 3568 u32 dma_cntl; 3569 3570 if (!rdev->irq.installed) { 3571 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 3572 return -EINVAL; 3573 } 3574 /* don't enable anything if the ih is disabled */ 3575 if (!rdev->ih.enabled) { 3576 r600_disable_interrupts(rdev); 3577 /* force the active interrupt state to all disabled */ 3578 r600_disable_interrupt_state(rdev); 3579 return 0; 3580 } 3581 3582 if (ASIC_IS_DCE3(rdev)) { 3583 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3584 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3585 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3586 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3587 if (ASIC_IS_DCE32(rdev)) { 3588 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3589 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3590 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3591 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3592 } else { 3593 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3594 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3595 } 3596 } else { 3597 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3598 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3599 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3600 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3601 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3602 } 3603 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3604 3605 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3606 DRM_DEBUG("r600_irq_set: sw int\n"); 3607 cp_int_cntl |= RB_INT_ENABLE; 3608 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3609 } 3610 3611 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3612 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3613 dma_cntl |= TRAP_ENABLE; 3614 } 3615 3616 if (rdev->irq.crtc_vblank_int[0] || 3617 atomic_read(&rdev->irq.pflip[0])) { 3618 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3619 mode_int |= D1MODE_VBLANK_INT_MASK; 3620 } 3621 if (rdev->irq.crtc_vblank_int[1] || 3622 atomic_read(&rdev->irq.pflip[1])) { 3623 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3624 mode_int |= D2MODE_VBLANK_INT_MASK; 3625 } 3626 if (rdev->irq.hpd[0]) { 3627 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3628 hpd1 |= DC_HPDx_INT_EN; 3629 } 3630 if (rdev->irq.hpd[1]) { 3631 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3632 hpd2 |= DC_HPDx_INT_EN; 3633 } 3634 if (rdev->irq.hpd[2]) { 3635 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3636 hpd3 |= DC_HPDx_INT_EN; 3637 } 3638 if (rdev->irq.hpd[3]) { 3639 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3640 hpd4 |= DC_HPDx_INT_EN; 3641 } 3642 if (rdev->irq.hpd[4]) { 3643 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3644 hpd5 |= DC_HPDx_INT_EN; 3645 } 3646 if (rdev->irq.hpd[5]) { 3647 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3648 hpd6 |= DC_HPDx_INT_EN; 3649 } 3650 if (rdev->irq.afmt[0]) { 3651 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3652 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3653 } 3654 if (rdev->irq.afmt[1]) { 3655 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3656 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3657 } 3658 3659 WREG32(CP_INT_CNTL, cp_int_cntl); 3660 WREG32(DMA_CNTL, dma_cntl); 3661 WREG32(DxMODE_INT_MASK, mode_int); 3662 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3663 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3664 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3665 if (ASIC_IS_DCE3(rdev)) { 3666 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3667 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3668 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3669 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3670 if (ASIC_IS_DCE32(rdev)) { 3671 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3672 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3673 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3674 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3675 } else { 3676 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3677 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3678 } 3679 } else { 3680 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3681 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3682 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3683 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3684 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3685 } 3686 3687 return 0; 3688 } 3689 3690 static void r600_irq_ack(struct radeon_device *rdev) 3691 { 3692 u32 tmp; 3693 3694 if (ASIC_IS_DCE3(rdev)) { 3695 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3696 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3697 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3698 if (ASIC_IS_DCE32(rdev)) { 3699 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3700 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3701 } else { 3702 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3703 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3704 } 3705 } else { 3706 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3707 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3708 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3709 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3710 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3711 } 3712 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3713 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3714 3715 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3716 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3717 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3718 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3719 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3720 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3721 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3722 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3723 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3724 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3725 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3726 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3727 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3728 if (ASIC_IS_DCE3(rdev)) { 3729 tmp = RREG32(DC_HPD1_INT_CONTROL); 3730 tmp |= DC_HPDx_INT_ACK; 3731 WREG32(DC_HPD1_INT_CONTROL, tmp); 3732 } else { 3733 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3734 tmp |= DC_HPDx_INT_ACK; 3735 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3736 } 3737 } 3738 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3739 if (ASIC_IS_DCE3(rdev)) { 3740 tmp = RREG32(DC_HPD2_INT_CONTROL); 3741 tmp |= DC_HPDx_INT_ACK; 3742 WREG32(DC_HPD2_INT_CONTROL, tmp); 3743 } else { 3744 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3745 tmp |= DC_HPDx_INT_ACK; 3746 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3747 } 3748 } 3749 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3750 if (ASIC_IS_DCE3(rdev)) { 3751 tmp = RREG32(DC_HPD3_INT_CONTROL); 3752 tmp |= DC_HPDx_INT_ACK; 3753 WREG32(DC_HPD3_INT_CONTROL, tmp); 3754 } else { 3755 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3756 tmp |= DC_HPDx_INT_ACK; 3757 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3758 } 3759 } 3760 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3761 tmp = RREG32(DC_HPD4_INT_CONTROL); 3762 tmp |= DC_HPDx_INT_ACK; 3763 WREG32(DC_HPD4_INT_CONTROL, tmp); 3764 } 3765 if (ASIC_IS_DCE32(rdev)) { 3766 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3767 tmp = RREG32(DC_HPD5_INT_CONTROL); 3768 tmp |= DC_HPDx_INT_ACK; 3769 WREG32(DC_HPD5_INT_CONTROL, tmp); 3770 } 3771 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3772 tmp = RREG32(DC_HPD5_INT_CONTROL); 3773 tmp |= DC_HPDx_INT_ACK; 3774 WREG32(DC_HPD6_INT_CONTROL, tmp); 3775 } 3776 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3777 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3778 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3779 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3780 } 3781 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3782 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3783 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3784 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3785 } 3786 } else { 3787 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3788 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3789 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3790 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3791 } 3792 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3793 if (ASIC_IS_DCE3(rdev)) { 3794 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3795 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3796 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3797 } else { 3798 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3799 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3800 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3801 } 3802 } 3803 } 3804 } 3805 3806 void r600_irq_disable(struct radeon_device *rdev) 3807 { 3808 r600_disable_interrupts(rdev); 3809 /* Wait and acknowledge irq */ 3810 DRM_MDELAY(1); 3811 r600_irq_ack(rdev); 3812 r600_disable_interrupt_state(rdev); 3813 } 3814 3815 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3816 { 3817 u32 wptr, tmp; 3818 3819 if (rdev->wb.enabled) 3820 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3821 else 3822 wptr = RREG32(IH_RB_WPTR); 3823 3824 if (wptr & RB_OVERFLOW) { 3825 /* When a ring buffer overflow happen start parsing interrupt 3826 * from the last not overwritten vector (wptr + 16). Hopefully 3827 * this should allow us to catchup. 3828 */ 3829 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3830 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3831 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3832 tmp = RREG32(IH_RB_CNTL); 3833 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3834 WREG32(IH_RB_CNTL, tmp); 3835 } 3836 return (wptr & rdev->ih.ptr_mask); 3837 } 3838 3839 /* r600 IV Ring 3840 * Each IV ring entry is 128 bits: 3841 * [7:0] - interrupt source id 3842 * [31:8] - reserved 3843 * [59:32] - interrupt source data 3844 * [127:60] - reserved 3845 * 3846 * The basic interrupt vector entries 3847 * are decoded as follows: 3848 * src_id src_data description 3849 * 1 0 D1 Vblank 3850 * 1 1 D1 Vline 3851 * 5 0 D2 Vblank 3852 * 5 1 D2 Vline 3853 * 19 0 FP Hot plug detection A 3854 * 19 1 FP Hot plug detection B 3855 * 19 2 DAC A auto-detection 3856 * 19 3 DAC B auto-detection 3857 * 21 4 HDMI block A 3858 * 21 5 HDMI block B 3859 * 176 - CP_INT RB 3860 * 177 - CP_INT IB1 3861 * 178 - CP_INT IB2 3862 * 181 - EOP Interrupt 3863 * 233 - GUI Idle 3864 * 3865 * Note, these are based on r600 and may need to be 3866 * adjusted or added to on newer asics 3867 */ 3868 3869 irqreturn_t r600_irq_process(struct radeon_device *rdev) 3870 { 3871 u32 wptr; 3872 u32 rptr; 3873 u32 src_id, src_data; 3874 u32 ring_index; 3875 bool queue_hotplug = false; 3876 bool queue_hdmi = false; 3877 3878 if (!rdev->ih.enabled || rdev->shutdown) 3879 return IRQ_NONE; 3880 3881 /* No MSIs, need a dummy read to flush PCI DMAs */ 3882 if (!rdev->msi_enabled) 3883 RREG32(IH_RB_WPTR); 3884 3885 wptr = r600_get_ih_wptr(rdev); 3886 3887 restart_ih: 3888 /* is somebody else already processing irqs? */ 3889 if (atomic_xchg(&rdev->ih.lock, 1)) 3890 return IRQ_NONE; 3891 3892 rptr = rdev->ih.rptr; 3893 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3894 3895 /* Order reading of wptr vs. reading of IH ring data */ 3896 cpu_lfence(); 3897 3898 /* display interrupts */ 3899 r600_irq_ack(rdev); 3900 3901 while (rptr != wptr) { 3902 /* wptr/rptr are in bytes! */ 3903 ring_index = rptr / 4; 3904 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3905 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3906 3907 switch (src_id) { 3908 case 1: /* D1 vblank/vline */ 3909 switch (src_data) { 3910 case 0: /* D1 vblank */ 3911 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3912 if (rdev->irq.crtc_vblank_int[0]) { 3913 drm_handle_vblank(rdev->ddev, 0); 3914 rdev->pm.vblank_sync = true; 3915 DRM_WAKEUP(&rdev->irq.vblank_queue); 3916 } 3917 if (atomic_read(&rdev->irq.pflip[0])) 3918 radeon_crtc_handle_flip(rdev, 0); 3919 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3920 DRM_DEBUG("IH: D1 vblank\n"); 3921 } 3922 break; 3923 case 1: /* D1 vline */ 3924 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3925 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3926 DRM_DEBUG("IH: D1 vline\n"); 3927 } 3928 break; 3929 default: 3930 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3931 break; 3932 } 3933 break; 3934 case 5: /* D2 vblank/vline */ 3935 switch (src_data) { 3936 case 0: /* D2 vblank */ 3937 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3938 if (rdev->irq.crtc_vblank_int[1]) { 3939 drm_handle_vblank(rdev->ddev, 1); 3940 rdev->pm.vblank_sync = true; 3941 DRM_WAKEUP(&rdev->irq.vblank_queue); 3942 } 3943 if (atomic_read(&rdev->irq.pflip[1])) 3944 radeon_crtc_handle_flip(rdev, 1); 3945 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3946 DRM_DEBUG("IH: D2 vblank\n"); 3947 } 3948 break; 3949 case 1: /* D1 vline */ 3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3951 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3952 DRM_DEBUG("IH: D2 vline\n"); 3953 } 3954 break; 3955 default: 3956 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3957 break; 3958 } 3959 break; 3960 case 19: /* HPD/DAC hotplug */ 3961 switch (src_data) { 3962 case 0: 3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3964 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3965 queue_hotplug = true; 3966 DRM_DEBUG("IH: HPD1\n"); 3967 } 3968 break; 3969 case 1: 3970 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3971 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3972 queue_hotplug = true; 3973 DRM_DEBUG("IH: HPD2\n"); 3974 } 3975 break; 3976 case 4: 3977 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3978 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3979 queue_hotplug = true; 3980 DRM_DEBUG("IH: HPD3\n"); 3981 } 3982 break; 3983 case 5: 3984 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3985 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3986 queue_hotplug = true; 3987 DRM_DEBUG("IH: HPD4\n"); 3988 } 3989 break; 3990 case 10: 3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3992 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 3993 queue_hotplug = true; 3994 DRM_DEBUG("IH: HPD5\n"); 3995 } 3996 break; 3997 case 12: 3998 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3999 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4000 queue_hotplug = true; 4001 DRM_DEBUG("IH: HPD6\n"); 4002 } 4003 break; 4004 default: 4005 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4006 break; 4007 } 4008 break; 4009 case 21: /* hdmi */ 4010 switch (src_data) { 4011 case 4: 4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4013 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4014 queue_hdmi = true; 4015 DRM_DEBUG("IH: HDMI0\n"); 4016 } 4017 break; 4018 case 5: 4019 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4020 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4021 queue_hdmi = true; 4022 DRM_DEBUG("IH: HDMI1\n"); 4023 } 4024 break; 4025 default: 4026 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4027 break; 4028 } 4029 break; 4030 case 176: /* CP_INT in ring buffer */ 4031 case 177: /* CP_INT in IB1 */ 4032 case 178: /* CP_INT in IB2 */ 4033 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4034 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4035 break; 4036 case 181: /* CP EOP event */ 4037 DRM_DEBUG("IH: CP EOP\n"); 4038 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4039 break; 4040 case 224: /* DMA trap event */ 4041 DRM_DEBUG("IH: DMA trap\n"); 4042 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4043 break; 4044 case 233: /* GUI IDLE */ 4045 DRM_DEBUG("IH: GUI idle\n"); 4046 break; 4047 default: 4048 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4049 break; 4050 } 4051 4052 /* wptr/rptr are in bytes! */ 4053 rptr += 16; 4054 rptr &= rdev->ih.ptr_mask; 4055 } 4056 if (queue_hotplug) 4057 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 4058 if (queue_hdmi) 4059 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 4060 rdev->ih.rptr = rptr; 4061 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4062 atomic_set(&rdev->ih.lock, 0); 4063 4064 /* make sure wptr hasn't changed while processing */ 4065 wptr = r600_get_ih_wptr(rdev); 4066 if (wptr != rptr) 4067 goto restart_ih; 4068 4069 return IRQ_HANDLED; 4070 } 4071 4072 /* 4073 * Debugfs info 4074 */ 4075 #if defined(CONFIG_DEBUG_FS) 4076 4077 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4078 { 4079 struct drm_info_node *node = (struct drm_info_node *) m->private; 4080 struct drm_device *dev = node->minor->dev; 4081 struct radeon_device *rdev = dev->dev_private; 4082 4083 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4084 DREG32_SYS(m, rdev, VM_L2_STATUS); 4085 return 0; 4086 } 4087 4088 static struct drm_info_list r600_mc_info_list[] = { 4089 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4090 }; 4091 #endif 4092 4093 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4094 { 4095 #if defined(CONFIG_DEBUG_FS) 4096 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4097 #else 4098 return 0; 4099 #endif 4100 } 4101 4102 /** 4103 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4104 * rdev: radeon device structure 4105 * bo: buffer object struct which userspace is waiting for idle 4106 * 4107 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4108 * through ring buffer, this leads to corruption in rendering, see 4109 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4110 * directly perform HDP flush by writing register through MMIO. 4111 */ 4112 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4113 { 4114 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4115 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4116 * This seems to cause problems on some AGP cards. Just use the old 4117 * method for them. 4118 */ 4119 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4120 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4121 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4122 u32 tmp; 4123 4124 WREG32(HDP_DEBUG1, 0); 4125 tmp = *ptr; 4126 } else 4127 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4128 } 4129 4130 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4131 { 4132 u32 link_width_cntl, mask, target_reg; 4133 4134 if (rdev->flags & RADEON_IS_IGP) 4135 return; 4136 4137 if (!(rdev->flags & RADEON_IS_PCIE)) 4138 return; 4139 4140 /* x2 cards have a special sequence */ 4141 if (ASIC_IS_X2(rdev)) 4142 return; 4143 4144 /* FIXME wait for idle */ 4145 4146 switch (lanes) { 4147 case 0: 4148 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4149 break; 4150 case 1: 4151 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4152 break; 4153 case 2: 4154 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4155 break; 4156 case 4: 4157 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4158 break; 4159 case 8: 4160 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4161 break; 4162 case 12: 4163 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4164 break; 4165 case 16: 4166 default: 4167 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4168 break; 4169 } 4170 4171 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4172 4173 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 4174 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 4175 return; 4176 4177 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 4178 return; 4179 4180 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4181 RADEON_PCIE_LC_RECONFIG_NOW | 4182 R600_PCIE_LC_RENEGOTIATE_EN | 4183 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4184 link_width_cntl |= mask; 4185 4186 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4187 4188 /* some northbridges can renegotiate the link rather than requiring 4189 * a complete re-config. 4190 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 4191 */ 4192 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 4193 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 4194 else 4195 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 4196 4197 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 4198 RADEON_PCIE_LC_RECONFIG_NOW)); 4199 4200 if (rdev->family >= CHIP_RV770) 4201 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 4202 else 4203 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 4204 4205 /* wait for lane set to complete */ 4206 link_width_cntl = RREG32(target_reg); 4207 while (link_width_cntl == 0xffffffff) 4208 link_width_cntl = RREG32(target_reg); 4209 4210 } 4211 4212 int r600_get_pcie_lanes(struct radeon_device *rdev) 4213 { 4214 u32 link_width_cntl; 4215 4216 if (rdev->flags & RADEON_IS_IGP) 4217 return 0; 4218 4219 if (!(rdev->flags & RADEON_IS_PCIE)) 4220 return 0; 4221 4222 /* x2 cards have a special sequence */ 4223 if (ASIC_IS_X2(rdev)) 4224 return 0; 4225 4226 /* FIXME wait for idle */ 4227 4228 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4229 4230 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4231 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4232 return 0; 4233 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4234 return 1; 4235 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4236 return 2; 4237 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4238 return 4; 4239 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4240 return 8; 4241 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4242 default: 4243 return 16; 4244 } 4245 } 4246 4247 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4248 { 4249 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4250 u16 link_cntl2; 4251 u32 mask; 4252 int ret; 4253 4254 if (radeon_pcie_gen2 == 0) 4255 return; 4256 4257 if (rdev->flags & RADEON_IS_IGP) 4258 return; 4259 4260 if (!(rdev->flags & RADEON_IS_PCIE)) 4261 return; 4262 4263 /* x2 cards have a special sequence */ 4264 if (ASIC_IS_X2(rdev)) 4265 return; 4266 4267 /* only RV6xx+ chips are supported */ 4268 if (rdev->family <= CHIP_R600) 4269 return; 4270 4271 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4272 if (ret != 0) 4273 return; 4274 4275 if (!(mask & DRM_PCIE_SPEED_50)) 4276 return; 4277 4278 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4279 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4280 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4281 return; 4282 } 4283 4284 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4285 4286 /* 55 nm r6xx asics */ 4287 if ((rdev->family == CHIP_RV670) || 4288 (rdev->family == CHIP_RV620) || 4289 (rdev->family == CHIP_RV635)) { 4290 /* advertise upconfig capability */ 4291 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4292 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4293 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4294 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4295 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4296 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4297 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4298 LC_RECONFIG_ARC_MISSING_ESCAPE); 4299 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4300 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4301 } else { 4302 link_width_cntl |= LC_UPCONFIGURE_DIS; 4303 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4304 } 4305 } 4306 4307 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4308 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4309 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4310 4311 /* 55 nm r6xx asics */ 4312 if ((rdev->family == CHIP_RV670) || 4313 (rdev->family == CHIP_RV620) || 4314 (rdev->family == CHIP_RV635)) { 4315 WREG32(MM_CFGREGS_CNTL, 0x8); 4316 link_cntl2 = RREG32(0x4088); 4317 WREG32(MM_CFGREGS_CNTL, 0); 4318 /* not supported yet */ 4319 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4320 return; 4321 } 4322 4323 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4324 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4325 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4326 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4327 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4328 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4329 4330 tmp = RREG32(0x541c); 4331 WREG32(0x541c, tmp | 0x8); 4332 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4333 link_cntl2 = RREG16(0x4088); 4334 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4335 link_cntl2 |= 0x2; 4336 WREG16(0x4088, link_cntl2); 4337 WREG32(MM_CFGREGS_CNTL, 0); 4338 4339 if ((rdev->family == CHIP_RV670) || 4340 (rdev->family == CHIP_RV620) || 4341 (rdev->family == CHIP_RV635)) { 4342 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4343 training_cntl &= ~LC_POINT_7_PLUS_EN; 4344 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4345 } else { 4346 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4347 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4348 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4349 } 4350 4351 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4352 speed_cntl |= LC_GEN2_EN_STRAP; 4353 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4354 4355 } else { 4356 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4357 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4358 if (1) 4359 link_width_cntl |= LC_UPCONFIGURE_DIS; 4360 else 4361 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4362 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4363 } 4364 } 4365 4366 /** 4367 * r600_get_gpu_clock - return GPU clock counter snapshot 4368 * 4369 * @rdev: radeon_device pointer 4370 * 4371 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4372 * Returns the 64 bit clock counter snapshot. 4373 */ 4374 uint64_t r600_get_gpu_clock(struct radeon_device *rdev) 4375 { 4376 uint64_t clock; 4377 4378 spin_lock(&rdev->gpu_clock_mutex); 4379 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4380 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4381 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4382 spin_unlock(&rdev->gpu_clock_mutex); 4383 return clock; 4384 } 4385